Display device and mobile electronic device including the same

Abstract

A display device and a mobile electronic device including the same are provided. The display device includes: a driving element layer on a substrate; a wiring layer on the driving element layer and including a power supply wiring; and a light emitting element layer disposed on the wiring layer. The light emitting element layer includes: a pixel defining layer defining a plurality of openings for a plurality of pixels; a first electrode in each of the openings; a heating wiring on the pixel defining layer around each opening; a connection electrode connecting the heating wiring and the power supply wiring by extending through contact holes of the wiring layer and the pixel defining layer; an intermediate layer covering the first electrode in the plurality of pixels and the pixel defining layer between the plurality of pixels and including a disconnection portion adjacent to the heating wiring on the pixel defining layer; and a second electrode continuously arranged on the intermediate layer in the plurality of openings for the plurality of pixels and between the plurality of pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0092548, filed in the Korean Intellectual Property Office on July 17, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a mobile electronic device including the display device. Background Art

[0004] Wearable devices that produce a focal point at a short distance in front of the user's eyes are being developed in the form of glasses or helmets. For example, the wearable device may be a head-mounted display (HMD) or augmented reality (AR) glasses. Such a wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0005] Wearable devices such as HMDs or AR glasses need to have a display specification of at least 2000 pixels per inch (PPI) so that users can use them for a long time without feeling dizzy. To this end, organic light emitting diode on silicon (OLEDoS) technology is proposed as a small high-resolution organic light emitting display device. OLEDoS is a technology for placing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0006] Since the distance between pixels is reduced in the display panel to which the OLEDoS technology is applied, an unexpected leakage current may be generated between adjacent pixels. The leakage current may be generated by a conductive layer arranged in an intermediate layer between a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode). It is known that the leakage current is the cause of color crosstalk between adjacent pixels. Summary of the invention

[0007] Aspects of the present disclosure provide a display device and a mobile electronic device including the display device in which at least a portion of an intermediate layer disposed between a pixel electrode and a common electrode is disconnected between adjacent pixels to prevent leakage current and color crosstalk.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment of the present disclosure, a display device may include: a substrate; a driving element layer arranged on the substrate; a wiring layer arranged on the driving element layer and including a power wiring; and a light-emitting element layer arranged on the wiring layer. The light-emitting element layer may include: a pixel defining layer defining a plurality of openings for a plurality of pixels; a first electrode arranged in each of the plurality of openings for the plurality of pixels; a heating wiring arranged on the pixel defining layer around each opening; a connecting electrode connecting the heating wiring and the power wiring through a contact hole extending through at least a portion of the wiring layer and the pixel defining layer; an intermediate layer covering the first electrode in each of the plurality of pixels and the pixel defining layer between the plurality of pixels, and including a disconnected portion adjacent to the heating wiring on the pixel defining layer; and a second electrode continuously arranged on the intermediate layer in the plurality of openings for the plurality of pixels and between the plurality of pixels.

[0010] The disconnected portion of the intermediate layer and the second electrode covering the disconnected portion of the intermediate layer may be arranged on a pixel defining layer between a plurality of pixels, the disconnected portion of the intermediate layer is disconnected from a pixel portion of the intermediate layer arranged in a plurality of openings of the pixel defining layer, and the second electrode is continuously arranged on the disconnected portion of the intermediate layer and the pixel portion.

[0011] The plurality of pixels may include a first pixel and a second pixel, and the plurality of openings may include a first opening of the first pixel and a second opening of the second pixel. A first heating wiring around the first opening and a second heating wiring around the second opening may be spaced apart at a predetermined interval on the pixel defining layer between the plurality of pixels.

[0012] The disconnected portion of the intermediate layer may be arranged between the first heating wiring and the second heating wiring.

[0013] The power wiring may include a first power wiring that drives a first heating wiring and a second power wiring that drives a second heating wiring, the first heating wiring being electrically connected to the first power wiring via a first connecting electrode extending through the pixel defining layer, and the second heating wiring being electrically connected to the second power wiring via a second connecting electrode extending through the pixel defining layer.

[0014] The first power wiring and the second power wiring may be spaced apart at a predetermined interval on the wiring layer and driven independently.

[0015] The first power wiring and the second power wiring may be connected as one power wiring on the wiring layer, and a pair of heating wirings surrounding each of a plurality of adjacent pixels are electrically connected to the one power wiring.

[0016] The first metal forming the heating wiring, the second metal forming the connection electrode, and the third metal forming the power supply wiring are different metals.

[0017] The resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal.

[0018] The intermediate layer may include one or more conductive layers having a disconnected portion adjacent to the heating wiring, and the conductive layer may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, a charge generation layer CGL, and a P-doped layer PHIL.

[0019] The heating wiring surrounds each opening and may include an opening slit region that is open in a particular lateral direction.

[0020] The intermediate layer and the second electrode may be continuously arranged around the opening slit region.

[0021] According to an embodiment of the present disclosure, a mobile electronic device may include a display panel. The display panel may include: a substrate; a driving element layer, the driving element layer is arranged on the substrate; a wiring layer, the wiring layer is arranged on the driving element layer and includes a power wiring; and a light-emitting element layer, the light-emitting element layer is arranged on the wiring layer. The light-emitting element layer may include: a pixel defining layer, the pixel defining layer defines a plurality of openings for a plurality of pixels; a first electrode, the first electrode is arranged in each of the plurality of openings; a heating wiring, the heating wiring is arranged on the pixel defining layer around each opening; a connecting electrode, the connecting electrode connects the heating wiring and the power wiring through a contact hole extending through at least a portion of the wiring layer and the pixel defining layer; an intermediate layer, the intermediate layer covers the first electrode in each of the plurality of pixels and the pixel defining layer between the plurality of pixels, and includes a disconnected portion adjacent to the heating wiring on the pixel defining layer; and a second electrode, the second electrode is continuously arranged on the intermediate layer in the plurality of openings for the plurality of pixels and between the plurality of pixels.

[0022] The disconnected portion of the intermediate layer and the second electrode covering the disconnected portion of the intermediate layer may be arranged on a pixel defining layer between a plurality of pixels, the disconnected portion of the intermediate layer is disconnected from a pixel portion of the intermediate layer arranged in a plurality of openings of the pixel defining layer, and the second electrode is continuously arranged on the disconnected portion of the intermediate layer and the pixel portion.

[0023] In the case where the plurality of openings include a first opening for a first pixel and a second opening for a second pixel, a first heating wiring around the first opening and a second heating wiring around the second opening may be spaced apart at predetermined intervals on the pixel defining layer between the plurality of pixels.

[0024] The disconnected portion of the intermediate layer may be arranged between the first heating wiring and the second heating wiring.

[0025] The power wiring may include a first power wiring that drives a first heating wiring and a second power wiring that drives a second heating wiring, the first heating wiring being electrically connected to the first power wiring via a first connecting electrode extending through the pixel defining layer, and the second heating wiring being electrically connected to the second power wiring via a second connecting electrode extending through the pixel defining layer.

[0026] The first power wiring and the second power wiring may be spaced apart at a predetermined interval on the wiring layer and driven independently.

[0027] The first power wiring and the second power wiring may be connected as one power wiring on the wiring layer, and a pair of heating wirings surrounding each of a plurality of adjacent pixels are electrically connected to the one power wiring.

[0028] The first metal forming the heating wiring, the second metal forming the connection electrode and the third metal forming the power wiring may be different metals, and the resistance of the first metal is greater than that of the second metal, and the resistance of the second metal is greater than that of the third metal.

[0029] In the display device and the mobile electronic device including the display device according to the embodiment, at least a portion of the intermediate layer disposed between the pixel electrode and the common electrode may be disconnected between adjacent pixels, thereby preventing leakage current and color crosstalk.

[0030] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a perspective view of a display device according to an embodiment;

[0033] Figure 2 is a plan view of a display panel according to an embodiment;

[0034] Figure 3 is a block diagram of a configuration of a display device according to an embodiment;

[0035] Figure 4 is a circuit diagram of a pixel of a display device according to an embodiment;

[0036] Figure 5is a schematic cross-sectional view of a portion of a display panel of a display device according to an embodiment;

[0037] Figure 6 is a cross-sectional view schematically illustrating a stacked structure of a light emitting element according to an embodiment;

[0038] Figure 7 is a cross-sectional view schematically illustrating a stacked structure of a light emitting element according to an embodiment;

[0039] Figure 8 is a schematic plan view of a portion of a display area of ​​a display panel according to an embodiment; Fig. 9 The diagram shows Figure 8 The heat driving pad unit shown in FIG. 1 is arranged on the outer edge of the cutting area;

[0040] Fig.10 It is a schematic diagram Figure 8 and Fig. 9 A cross-sectional view of the cross-sectional structure of adjacent pixels shown in FIG.

[0041] Fig.11 The diagram shows Fig.10 An embodiment in which the first power supply wiring and the second power supply wiring are combined into one wiring;

[0042] Fig.12 It is a graphic manufacturing Fig.10 A flow chart of a method for displaying a panel as shown in FIG.

[0043] Figures 13 to 16 are cross-sectional views sequentially illustrating a method of manufacturing a display panel according to an embodiment;

[0044] Fig.17 The diagram shows Figure 8 The heating wiring illustrated in FIG. 1 includes an embodiment in which an open slit region is provided in a specific lateral direction of each pixel;

[0045] Fig.18 It is a graphic manufacturing Fig.17 A flowchart of a method for displaying a panel as shown in FIG.

[0046] Figures 19 to 22 are cross-sectional views sequentially illustrating a method of manufacturing a display panel according to an embodiment; and

[0047] Fig.23 is an exemplary view of a wearable device including a display device according to an embodiment. DETAILED DESCRIPTION

[0048] The inventive concept will now be described more fully below with reference to the accompanying drawings in which embodiments of the invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0049] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification. As used herein, "some" and "at least one" mean a range between one and all, inclusive.

[0050] It will be understood that although the order terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited to any order of these terms. These terms are used to distinguish one element from another element and may be interchangeable. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0051] The features of each of the various embodiments of the present disclosure may be combined with each other in part or in whole, and may technically interact with each other differently, and the corresponding embodiments may be implemented independently of each other, or may be implemented together in association with each other.

[0052] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0054] Reference Figure 1 The display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers. For example, the display device 10 may be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For example, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0055] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having short sides in the first direction DR1 and long sides in the second direction DR2. Alternatively, the display device 10 may have a planar shape similar to a quadrilateral having long sides in the first direction DR1 and short sides in the second direction DR2. Figure 1 , DR3 represents a normal direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. Each corner where the short side intersects the long side may be rounded with a predetermined curvature, or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0056] The display device 10 may include a display panel 110 , a circuit board 120 , and a power supply unit 130 .

[0057] The display panel 110 is formed using a semiconductor wafer substrate (see Figure 2 ) as a display panel 110 as a base substrate. The display panel 110 may include a main area MA and a sub-area SBA.

[0058] The main area MA may include a display area DA and a non-display area NDA. The display area DA includes pixels PX that display an image (see Figure 3 ), the non-display area NDA is arranged around the display area DA. The non-display area NDA may be an area outside the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 110 may include a pixel driving circuit PC including a switching element (see Figure 4 ) and the light-emitting element LEL as a self-luminous element (see Figure 5 ).

[0059] The light emitting element LEL may include, but is not limited to, at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode.

[0060] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 110. The non-display area NDA may include fan-out lines (not shown) extending from lines (e.g., gate lines, data lines, and emission control lines) of the display area DA, and a display pad unit (not shown) connecting the fan-out lines and the display driving circuit 210.

[0061] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a main pad unit connected to the circuit board 120. Alternatively, the sub-area SBA may be omitted, and the main pad unit may be disposed in the non-display area NDA.

[0062] The circuit board 120 may be attached to the main pad unit of the display panel 110 using an anisotropic conductive film (ACF). Leads of the circuit board 120 may be electrically connected to the main pad unit of the display panel 110. The circuit board 120 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0063] The power supply unit 130 may be disposed on the circuit board 120 to supply a power supply voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 may generate a driving voltage and supply the driving voltage to the driving voltage line. For example, the driving voltage may include a high potential voltage ( Figure 4 The first driving voltage ELVDD), the low potential voltage ( Figure 4 The second driving voltage ELVSS) and the initialization voltage VINT (see Figure 4 ).

[0064] Figure 2 is a plan view of a display panel 110 according to an embodiment.

[0065] Reference Figure 2 , the display panel 110 may be an organic light emitting diode on silicon (OLEDoS) panel using a semiconductor wafer substrate as a base substrate. For example, the display panel 110 may include a substrate 200, and the substrate 200 may be a semiconductor wafer substrate. In this document, the substrate 200 may be, but is not necessarily, referred to as a "semiconductor substrate", "semiconductor wafer substrate" or "wafer".

[0066] According to an embodiment, the pixel driving circuit PC (see Figure 4 ) and a display driving circuit 210 for controlling the pixel driving circuit PC may be arranged on the front surface 201 of the substrate 200. The pixel driving circuit PC is arranged to be connected to the pixels PX in the display area DA (see Figure 3 ) of the light-emitting element LEL (see Figure 5 The display driving circuit 210 is arranged in the non-display area NDA and drives the pixel driving circuit PC.

[0067] Pixel drive circuit PC (see Figure 4 ) and the display driving circuit 210 may be formed on a driving element layer 501 disposed on the front surface 201 of the substrate 200 (see Figure 5). The driving element layer 501 may include, for example, an N-type metal oxide semiconductor field effect transistor (MOSFET) and / or a P-type MOSFET. In this document, the driving element layer 501 (see Figure 5 ) may but need not necessarily be referred to as a “MOSFET layer”, “CMOS layer”, “transistor layer” or “backplane layer”.

[0068] Figure 3 is a block diagram showing a configuration of a display device 10 according to an embodiment.

[0069] Reference Figure 3 , the display device 10 includes a display driving circuit 210 embedded in the display panel 110. The display driving circuit 210 is formed in a driving element layer 501 arranged on the front surface of the substrate 200. Such a display driving circuit 210 may include a timing controller 310, a gate driver 320, an emission control driver 330, and a data driver 340, but the present disclosure is not limited thereto. Although not shown, the display driving circuit 210 may also include a memory (e.g., OTP), an interface circuit (e.g., I / F), an image processing circuit (e.g., logic), and / or a gamma processing circuit.

[0070] The display area DA of the display panel 110 includes a plurality of pixels PX arranged in a matrix form. Each of the plurality of pixels PX may be connected to a first driving voltage line VDL, a second driving voltage line VSL, a gate line GL, an emission control line EML, an initialization line VIL, and a data line DL.

[0071] The first driving voltage line VDL is supplied with a first driving voltage ELVDD (see FIG. Figure 4 ) is supplied to the pixel PX. The second driving voltage line VSL is supplied with the second driving voltage ELVSS (see FIG. 1 ) input from the power supply unit 130. Figure 4 ) is supplied to the pixel PX. The gate line GL receives the gate signals GI and GW (see Figure 4 ) is supplied to the pixel PX. The emission control line EML supplies the emission control signal EM input from the emission control driver 330 to the pixel PX. The initialization line VIL supplies the initialization voltage VINT (see Figure 4 ) is supplied to the pixel PX. The data line DL receives the analog data voltage Vdat (see Figure 4 ) is supplied to the pixel PX.

[0072] The first driving voltage ELVDD may be a high potential voltage, and the second driving voltage ELVSS may be a low potential voltage. For example, the first driving voltage ELVDD may have a potential higher than that of the second driving voltage ELVSS. For each frame, the initialization voltage VINT (see Figure 4 ) may have a pixel driving circuit PC (see Figure 4 ) initialization potential.

[0073] Figure 3 One gate line GL illustrated in FIG. 5 may include a first gate line GWL and a second gate line GIL, but the present disclosure is not limited thereto.

[0074] Each of the plurality of pixels PX may include a light emitting element LEL (see Figure 4 ), and may include a plurality of transistors and at least one capacitor as a pixel driving circuit PC for driving the light emitting element LEL (see Figure 4 ).

[0075] The timing controller 310 may receive a data signal DATA and a timing signal from the circuit board 120. The timing controller 310 may generate a data control signal DCS based on the timing signal, and use the data control signal DCS to control the operation timing of the data driver 340. The timing controller 310 may generate a gate control signal GCS based on the timing signal, and use the gate control signal GCS to control the operation timing of the gate driver 320. The timing controller 310 may generate an emission control signal ECS based on the timing signal, and control the operation timing of the emission control driver 330 based on the emission control signal ECS.

[0076] The data driver 340 may convert the data signal DATA into an analog data voltage Vdat and supply the analog data voltage Vdat to the pixel PX through the data line DL. The gate signals GI and GW of the gate driver 320 may select the pixel PX to which the analog data voltage Vdat is to be supplied, and the selected pixel PX may receive the analog data voltage Vdat through the data line DL.

[0077] The power supply unit 130 may be disposed on the circuit board 120 to supply a power supply voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 generates a driving voltage and supplies the driving voltage to the first driving voltage line VDL or the second driving voltage line VSL. The power supply unit 130 may generate a common voltage and supply the common voltage to the second electrode (e.g., Figure 5 The second electrode CAE).

[0078] The gate driver 320 can transmit gate signals GI and GW (see Figure 4 ) is supplied to the pixel PX.

[0079] The emission control driver 330 can transmit the emission control signal EM (see Figure 4 ) is supplied to the pixel PX.

[0080] Figure 4 is a circuit diagram of a pixel PX of the display device 10 according to the embodiment.

[0081] Reference Figure 4 , the pixel PX may include a light emitting element LEL (e.g., an organic light emitting diode) and a pixel driving circuit PC connected to the light emitting element LEL as a display element. The pixel driving circuit PC may include first to fourth transistors T1 to T4 and a first capacitor C1, but the present disclosure is not limited thereto. The first to fourth transistors T1 to T4 may be implemented as N-type MOSFETs and / or P-type MOSFETs. Although Figure 4 The first to fourth transistors T1 to T4 are illustrated as P-type MOSFETs, but the present disclosure is not limited thereto.

[0082] The first transistor T1 may be a driving transistor in which the magnitude of the source-drain current is determined according to the gate-source voltage, and each of the second to fourth transistors T2 to T4 may be a switching transistor turned on / off according to the gate-source voltage or substantially the gate voltage.

[0083] The first transistor T1 includes a gate connected to the first node N1, a source connected to the second node N2, and a drain connected to the third node N3. The first transistor T1 is turned on or off based on the voltage level of the first node N1. The turned-on first transistor T1 connects the second node N2 and the third node N3. The second node N2 is a node connected to the source of the third transistor T3 and is supplied with the first driving voltage ELVDD when the third transistor T3 is turned on in response to the emission control signal EM. The third node N3 is a first electrode ANE of the light emitting element LEL (see Figure 5 ) and a node to which the drain of the fourth transistor T4 is connected. The third node N3 is a node to which the initialization voltage VINT is supplied when the fourth transistor T4 is turned on in response to the second gate signal GI.

[0084] The second transistor T2 includes a gate connected to the first gate line GWL, a source connected to the data line DL, and a drain connected to the first node N1. The second transistor T2 is turned on in response to the first gate signal GW supplied from the first gate line GWL. The turned-on second transistor T2 supplies the analog data voltage Vdat supplied from the data line DL to the first node N1.

[0085] The third transistor T3 includes a gate connected to the emission control line EML, a source connected to the first driving voltage line VDL to which the first driving voltage ELVDD is supplied, and a drain connected to the second node N2. The third transistor T3 is turned on in response to the emission control signal EM supplied from the emission control line EML. The turned-on third transistor T3 supplies the first driving voltage ELVDD to the second node N2.

[0086] The fourth transistor T4 includes a gate connected to the second gate line GIL, a source connected to the initialization line VIL to which the initialization voltage VINT is supplied, and a drain connected to the third node N3. The fourth transistor T4 is turned on in response to the second gate signal GI supplied from the second gate line GIL. The turned-on fourth transistor T4 supplies the initialization voltage VINT to the third node N3.

[0087] The first capacitor C1 is disposed between the first node N1 and the second node N2. The first capacitor C1 is used to store the analog data voltage Vdat input through the second transistor T2.

[0088] The light emitting element LEL may include a first electrode (eg, Figure 5 A first electrode ANE), a second electrode facing the first electrode (eg, Figure 5 A second electrode CAE) and an intermediate layer (eg, Figure 5 The middle layer ML may include an organic light emitting layer. The second electrode may receive a second driving voltage ELVSS. The second electrode may be connected to a second driving voltage line VSL that transmits the second driving voltage ELVSS. The second electrode may be connected to a plurality of pixels PX.

[0089] Figure 5 is a schematic cross-sectional view of a portion of a display panel 110 of a display device 10 according to an embodiment. For example, Figure 5 A stack structure of each of the non-display area NDA and the display area DA of the display panel 110 according to an embodiment is schematically illustrated.

[0090] In reference Figure 5 In the description of , the expression "on" may mean a third direction DR3, and the front surface of the substrate 200 faces the third direction DR3. The front surface of the substrate 200 may refer to a direction in which each light emitting element LEL arranged in the display area DA emits light for displaying an image.

[0091] Reference Figure 5 , the display panel 110 according to the embodiment may include a substrate 200, and the substrate 200 may be a semiconductor wafer substrate.

[0092] A driving element layer 501 including a display driving circuit 210 and a pixel driving circuit PC, at least one wiring layer 502, a light emitting element layer 503 including a light emitting element LEL, an encapsulation layer 504 covering the light emitting element LEL, a color filter layer 505 including a color filter CF, a light control layer 506 including a refractive layer MLA, and a covering layer 507 including a covering member CV may be sequentially stacked on the front surface of the substrate 200. At least one of the light emitting element layer 503, the encapsulation layer 504, the color filter layer 505, the light control layer 506, and the covering layer 507 may not be arranged in the non-display area NDA.

[0093] The substrate 200 may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The substrate 200 may be a substrate 200 doped with first type impurities.

[0094] A driving element layer 501 including an N-type MOSFET and / or a P-type MOSFET is arranged on a substrate 200. The first type impurity may be a P-type impurity, and the second type impurity may be an N-type impurity. Alternatively, the first type impurity may be an N-type impurity, and the second type impurity may be a P-type impurity.

[0095] In this document, an N-type MOSFET MOS included in the driving element layer 501 will be described as an example. The N-type MOSFET MOS may include a well region W1 doped with N-type impurities in a substrate 200 doped with P-type impurities.

[0096] The well region W1 may include a first low-concentration impurity region LDD1 and a second low-concentration impurity region LDD2 having an impurity concentration relatively lower than that of other portions. The first low-concentration impurity region LDD1 may define a source region S1, and the second low-concentration impurity region LDD2 may define a drain region D1. A source electrode SE of an N-type MOSFET MOS may be connected to the source region S1, and a drain electrode DE of the N-type MOSFET MOS may be connected to the drain region D1.

[0097] A channel CH is defined between the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2 to overlap the gate G1. An oxide layer (not shown) as an insulating layer may be disposed between the gate G1 and the well region W1.

[0098] N-type MOSFET MOS constitutes the display driving circuit 210 (see Figure 2 ), and the display driving circuit 210 is arranged in the non-display area NDA of the display panel 110. In addition, the N-type MOSFET MOS constitutes a transistor ( Figure 4The first transistor T1 to the fourth transistor T4 are provided, and the pixel driving circuit PC is arranged in the display area DA of the display panel 110. That is, each pixel driving circuit PC is a circuit including a combination of N-type MOSFET MOS arranged in the driving element layer 501 to correspond to the display area DA. In addition, the display driving circuit 210 is a circuit including a combination of N-type MOSFET MOS arranged in the driving element layer 501 to correspond to the non-display area NDA. For the convenience of description, Figure 5 Any one N-type MOSFET MOS of the pixel driving circuit PC arranged in the display area DA of the display panel 110 is illustrated as an example.

[0099] At least one wiring layer 502 is arranged on the driving element layer 501. At least one wiring layer 502 includes an insulating layer VIA sequentially stacked on the driving element layer 501 and a connection electrode CE and a wiring (not shown) connected to the N-type MOSFET MOS through a contact hole CT1 that at least partially penetrates the insulating layer VIA. That is, the wiring layer 502 includes a connection electrode CE and a connection wiring for connecting the N-type MOSFET MOS of the driving element layer 501 to each other and an insulating layer VIA for insulating them from each other. In addition, the wiring layer 502 may include a plurality of signal wirings and a plurality of power wirings for driving the display panel 110.

[0100] Figure 5 The connection electrode CE illustrated in FIG. 5 connects an N-type MOSFET MOS corresponding to the pixel driving circuit PC among a plurality of N-type MOSFET MOS arranged in the driving element layer 501 to the light emitting element LEL arranged on the wiring layer 502 in a vertical direction. Here, the vertical direction means a normal direction of the display panel 110 (i.e., a third direction DR3).

[0101] The wiring (not shown) arranged in the wiring layer 502 includes lines (eg, Figure 3 The wiring arranged in the wiring layer 502 also includes lines connected to the pixel driving circuit PC (for example, Figure 3 A fan-out line (not shown) extending from the gate line GL, the data line DL, and the emission control line EML and arranged in the non-display area NDA.

[0102] The wiring layer 502 may include a plurality of pad electrodes arranged to correspond to the non-display area NDA. The plurality of pad electrodes include a first gate pad PD1 to which the first gate line GWL is connected, a second gate pad PD2 to which the second gate line GIL is connected, an initialization pad PD3 to which the initialization line VIL is connected, an emission pad PD4 to which the emission control line EML is connected, a data pad PD5 to which the data line DL is connected, a first drive voltage pad PD6 to which the first drive voltage line VDL is connected, and a second drive voltage pad PD7 to which the second drive voltage line VSL is connected. However, Figure 5 The pad electrodes illustrated in FIG. 1 are examples, and the present disclosure is not limited thereto.

[0103] A planarization layer FL including an organic layer may be disposed on the uppermost layer among the plurality of insulating layers VIA included in the wiring layer 502 .

[0104] A pixel defining layer PDL defining a plurality of pixels PX and a light emitting element layer 503 including a light emitting element LEL may be arranged on the wiring layer 502. The light emitting element LEL includes a first electrode ANE connected to an N-type MOSFET MOS included in the pixel driving circuit PC through a contact hole CT2 and a connection electrode CE, an intermediate layer ML arranged on the first electrode ANE, and a second electrode CAE arranged on the intermediate layer ML. The pixel defining layer PDL includes openings OP (see FIG. 1 ) corresponding to the pixels PX, respectively. Figure 8 ), and a portion of the first electrode ANE of the light emitting element LEL may be exposed in each opening OP.

[0105] The middle layer ML may include a hole injection layer HIL, a hole transport layer HTL, a light emitting layer, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. For example, the light emitting element LEL may be an RGB type light emitting element LEL that emits a first color of light (e.g., red light) in a first pixel PX1 (e.g., a red pixel), emits a second color of light (e.g., green light) in a second pixel PX2 (e.g., a green pixel), and emits a third color of light (e.g., blue light) in a third pixel PX3 (e.g., a blue pixel). Alternatively, the light emitting element LEL may be a white OLED (WOLED) type light emitting element LEL that emits white light in all of the first pixel PX1 (e.g., a red pixel), the second pixel PX2 (e.g., a green pixel), and the third pixel PX3 (e.g., a blue pixel).

[0106] The stack structure of the organic material included in the middle layer ML may differ depending on whether the light emitting element LEL is an RGB type or a WOLED type, but the present disclosure is not limited thereto.

[0107] A heating wiring 810 is arranged on the pixel defining layer PDL, and the heating wiring 810 disconnects the middle layer ML of the light emitting element LEL between adjacent pixels PX during the process. The disconnection of the middle layer ML occurs in the process of applying a driving voltage (or a driving current) to the heating wiring 810. The process of applying the driving voltage (or a driving current) to the heating wiring 810 may be performed after the middle layer ML is deposited. As will be described later, the process of applying the driving voltage (or a driving current) to the heating wiring 810 may be performed before the process of depositing the second electrode CAE or after the process of depositing the second electrode CAE.

[0108] According to an embodiment, the heating wiring 810 is electrically connected to the power supply wiring 830 provided on the wiring layer through the connection electrode 820 vertically penetrating the pixel defining layer PDL (see Figure 8 ). The heating wiring 810 is configured to receive a driving voltage (or a driving current) through the power wiring 830 and the connection electrode 820, and generate heat in response to the received driving voltage (or driving current). The temperature of the heating wiring 810 can be increased to a high temperature of about 400° C. or higher by the received driving voltage (or driving current), and the intermediate layer ML deposited on and around the heating wiring 810 can be removed by the high temperature.

[0109] In an embodiment, the intermediate layer ML of the light emitting element LEL may be disconnected between adjacent pixels PX, thereby preventing leakage current between adjacent pixels PX and preventing color crosstalk. Therefore, the intermediate layer ML includes a disconnected portion and a pixel portion located between the pixels PX, and the pixel portion is substantially on the first electrode ANE. Color crosstalk refers to a phenomenon in which, when a blue pixel emits blue light, a red pixel (e.g., a first pixel PX1) adjacent to a blue pixel (e.g., a third pixel PX3) is unintentionally turned on. Color crosstalk occurs due to leakage current and may occur when a blue pixel and a red pixel having a large voltage difference driving the pixel PX are adjacent to each other. For example, leakage current is a phenomenon in which, when a driving current is supplied to the light emitting element LEL of the blue pixel to turn on the blue pixel, a portion of the driving current is sent to the red pixel (e.g., the first pixel PX1) through some conductive layers of the intermediate layer ML. When a leakage current is generated, the red pixel may be turned on unintentionally together with the blue pixel.

[0110] An encapsulation layer 504 including at least one organic encapsulation layer and at least one inorganic encapsulation layer may be disposed on the light emitting element layer 503. For example, the encapsulation layer 504 may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3, but the present disclosure is not limited thereto.

[0111] A color filter layer 505 including a color filter CF may be disposed on the encapsulation layer 504. The color filter CF may include a first color filter CF1 transmitting red light, a second color filter CF2 transmitting green light, or a third color filter CF3 transmitting blue light, but the present disclosure is not limited thereto. When the light emitting element LEL of the light emitting element layer 503 is a WOLED type light emitting element LEL, the color filter layer 505 may be provided. If the light emitting element LEL of the light emitting element layer 503 is an RGB type light emitting element LEL that directly emits red light, green light, or blue light, the color filter layer 505 may be omitted.

[0112] The light control layer 506 including the refraction layer MLA is disposed on the color filter layer 505. The refraction layer MLA may refract light emitted from the light emitting element layer 503 and propagating in a normal direction of the display panel 110. The refraction layer MLA may include a micro lens array.

[0113] A cover layer 507 serving as a cover of the display panel 110 may be disposed on the light control layer 506. The cover layer 507 may include a cover member CV made of glass, but the present disclosure is not limited thereto. The cover layer 507 may include, for example, a protective film.

[0114] Figure 6 is a cross-sectional view schematically illustrating a stacked structure of a light emitting element LEL according to an embodiment. For example, Figure 6 The diagram shows a stacked structure of the intermediate layer ML when the light emitting element LEL of the light emitting element layer 503 is a WOLED type light emitting element LEL.

[0115] Reference Figure 6 According to an embodiment, the display panel 110 may include a plurality of pixels PX, the plurality of pixels PX including a first pixel PX1 for displaying a first color (e.g., red), a second pixel PX2 for displaying a second color (e.g., green), and a third pixel PX3 for displaying a third color (e.g., blue).

[0116] The light emitting element LEL arranged in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 emits white light. The display panel 110 displays the first color, the second color, and the third color using color filters. For example, the white light emitted from the first pixel PX1 passes through the first color filter CF1 to display the first color, the white light emitted from the second pixel PX2 passes through the second color filter CF2 to display the second color, and the white light emitted from the third pixel PX3 passes through the third color filter CF3 to display the third color.

[0117] A first electrode ANE (eg, a pixel electrode or an anode) is disposed in each of the first, second, and third pixels PX1, PX2, and PX3. An intermediate layer ML and a second electrode CAE are disposed on the first electrode ANE of each of the first, second, and third pixels PX1, PX2, and PX3.

[0118] The middle layer ML and the second electrode CAE may be a common layer shared among the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 and continuous in at least some regions between the pixels PX.

[0119] The middle layer ML may include a first emission unit EU1, a charge generation layer CGL, a second emission unit EU2, a charge generation layer CGL, and a third emission unit EU3 sequentially stacked on the first electrode ANE of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, but the present disclosure is not necessarily limited thereto. That is, the stacking order and structure of the middle layer ML can be variously changed.

[0120] The first emission unit EU1 may include a hole injection layer HIL or a P-doped layer PHIL doped with a P-type semiconductor, a blue light emitting layer BEML, and an electron transport layer ETL. The second emission unit EU2 may include a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL. The third emission unit EU3 may include a hole transport layer HTL, a red light emitting layer REML, and an electron transport layer ETL.

[0121] The charge generation layer CGL is disposed between the first emission unit EU1 and the second emission unit EU2. In addition, the charge generation layer CGL may be disposed between the second emission unit EU2 and the third emission unit EU3. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer.

[0122] The second electrode CAE is disposed on the third emission unit EU3. The second electrode CAE may be a common layer shared among the first pixel PX1, the second pixel PX2, and the third pixel PX3 and continuous in at least some regions between the pixels PX.

[0123] A capping layer CPL may be disposed on the second electrode CAE. Although not shown, the encapsulation layer 504 (see Figure 5 ) may be disposed on the capping layer CPL, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the encapsulation layer 504. The capping layer CPL may improve light emitting efficiency by the principle of constructive interference.

[0124] In the display panel 110 according to the present embodiment, since the intermediate layer ML disposed between the first electrode ANE and the second electrode CAE is shared by the first pixel PX1, the second pixel PX2, and the third pixel PX3 and is continuous in at least some regions between the pixels PX, leakage current may be generated. Figure 6 As shown by arrows 601 in FIG. 8 , leakage current may flow between adjacent pixels PX through the conductive layer included in the middle layer ML.

[0125] The display panel 110 according to an embodiment includes a heating wiring 810 in a region between a plurality of pixels PX to prevent leakage current. For example, the heating wiring 810 is arranged on a pixel defining layer PDL between adjacent pixels PX. The heating wiring 810 arranged between adjacent pixels PX is driven before or after a process of depositing the second electrode CAE. When the heating wiring 810 is driven, high-temperature heat is generated, and the generated high-temperature heat causes some conductive layers included in the intermediate layer ML to be disconnected to form a disconnected portion. In the present disclosure, since some conductive layers included in the intermediate layer ML are disconnected around the heating wiring 810 between adjacent pixels PX, as shown in FIG. Figure 6 As shown by the solid line 602 in FIG. 8 , leakage current and color crosstalk can be prevented.

[0126] Figure 7 is a cross-sectional view schematically illustrating a stacked structure of a light emitting element LEL according to an embodiment. For example, Figure 7 The stacked structure of the middle layer ML is illustrated when the light emitting element LEL of the light emitting element layer 503 is an RGB type light emitting element LEL that directly emits red light in the first pixel PX1 , green light in the second pixel PX2 , and blue light in the third pixel PX3 .

[0127] Reference Figure 7 According to an embodiment, the display panel 110 may include a plurality of pixels PX, the plurality of pixels PX including a first pixel PX1 for displaying a first color (e.g., red), a second pixel PX2 for displaying a second color (e.g., green), and a third pixel PX3 for displaying a third color (e.g., blue).

[0128] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may directly emit light of a designated color. For example, the light emitting element LEL in the first pixel PX1 may include a red light emitting layer REML to emit red light from the first emission region, the light emitting element LEL in the second pixel PX2 may include a green light emitting layer GEML to emit green light from the second emission region, and the light emitting element LEL in the third pixel PX3 may include a blue light emitting layer BEML to emit blue light from the third emission region. Here, the first emission region is a region where the first electrode ANE provided in the first pixel PX1 is covered by the intermediate layer ML, the second emission region is a region where the first electrode ANE provided in the second pixel PX2 is covered by the intermediate layer ML, and the third emission region is a region where the first electrode ANE provided in the third pixel PX3 is covered by the intermediate layer ML.

[0129] A first electrode ANE (e.g., a pixel electrode or an anode) is disposed in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. An intermediate layer ML and a second electrode CAE are disposed on the first electrode ANE of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. A first common layer CL1 (e.g., a lower common layer), a light emitting layer, and a second common layer CL2 (e.g., an upper common layer) are disposed in the intermediate layer ML, and the second electrode CAE is disposed on the intermediate layer ML.

[0130] The first common layer CL1, the second common layer CL2, and the second electrode CAE may be common layers shared by the first pixel PX1, the second pixel PX2, and the third pixel PX3 and continuous in some areas between the pixels PX. On the other hand, different light-emitting layers may be arranged in the first pixel PX1, the second pixel PX2, and the third pixel PX3 between the first common layer CL1 and the second common layer CL2, respectively. For example, a red light-emitting layer REML may be arranged in the first pixel PX1, a green light-emitting layer GEML may be arranged in the second pixel PX2, and a blue light-emitting layer BEML may be arranged in the third pixel PX3. The red light-emitting layer REML, the green light-emitting layer GEML, and the blue light-emitting layer BEML may be disconnected at the boundary of each pixel PX.

[0131] The first common layer CL1 may be a layer disposed below the red light emitting layer REML, the green light emitting layer GEML, and the blue light emitting layer BEML, and may include a hole injection layer HIL or a P-doped layer PHIL doped with a P-type semiconductor and a hole transport layer HTL. However, the present disclosure is not limited thereto. For example, the first common layer CL1 may include at least one hole injection layer HIL and at least one hole transport layer HTL.

[0132] The second common layer CL2 may be a layer disposed on the red light emitting layer REML, the green light emitting layer GEML, and the blue light emitting layer BEML, and may include an electron transport layer ETL and an electron injection layer EIL. However, the present disclosure is not limited thereto. For example, the second common layer CL2 may include at least one electron transport layer ETL and at least one electron injection layer EIL.

[0133] The capping layer CPL may be disposed on the second electrode CAE. The capping layer CPL may improve light emitting efficiency through the principle of constructive interference.

[0134] and Figure 6 The implementation methods are different. Figure 7 An embodiment does not include a color filter.

[0135] like Figure 6 As in the embodiment of Figure 7 In the display panel 110 of the embodiment illustrated in FIG. 1 , the first common layer CL1 and the second common layer CL2 disposed between the first electrode ANE and the second electrode CAE are shared between the first pixel PX1, the second pixel PX2, and the third pixel PX3, and are continuous in some areas between the pixels PX. Therefore, leakage current may be generated through the first common layer CL1 and the second common layer CL2. Figure 7 As indicated by arrows 701 in FIG. 7 , a leakage current may flow between adjacent pixels PX through the conductive layers included in the first common layer CL1 and the second common layer CL2 .

[0136] The display panel 110 according to the embodiment of the present disclosure includes a heating wiring 810 in a region between a plurality of pixels PX to prevent leakage current, and disconnects some conductive layers included in the middle layer ML using the heating wiring 810. In the present disclosure, since some conductive layers included in the middle layer ML are disconnected around the heating wiring 810 between adjacent pixels PX, as shown in FIG. Figure 7 In the present document, some conductive layers of the middle layer ML disconnected around the heating wiring 810 may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0137] Figure 8 is a schematic plan view of a portion of a display area of ​​a display panel 110 according to an embodiment. For example, Figure 8 2 may be a plan view illustrating a portion of the display panel 110 viewed in a normal direction perpendicular to an upper surface of the display panel 110 (or the substrate 200 ).

[0138] Reference Figure 8, the display panel 110 includes a plurality of pixels PX including a first pixel PX1, a second pixel PX2, and a third pixel PX3. The plurality of pixels PX are arranged in a matrix form in a display area DA of the display panel 110. For example, the first pixel PX1 and the second pixel PX2 may be alternately arranged in each of the odd rows R1 and the odd rows R3 in which the plurality of pixels PX are arranged, and the second pixel PX2 and the third pixel PX3 may be alternately arranged in each of the even rows R2. In addition, the first pixel PX1 arranged in the odd rows R1 and the odd rows R3 and the third pixel PX3 arranged in the even rows R2 are arranged adjacent to each other in a column direction (i.e., a vertical direction), and the second pixel PX2 arranged in the odd rows R1 and the odd rows R3 and the second pixel PX2 arranged in the even rows R2 are arranged adjacent to each other in a column direction (i.e., a vertical direction). Figure 8 Some of the first pixel PX1, the second pixel PX2, and the third pixel PX3 illustrated in FIG. 4 may be replaced by a fourth pixel (not illustrated) displaying white light. Figure 8 The arrangement of the plurality of pixels PX illustrated in FIG. 1 is an example, and the present disclosure is not limited thereto.

[0139] exist Figure 8 , solid lines indicating regions of the first pixel PX1, the second pixel PX2, and the third pixel PX3 indicate openings OP (eg, Figure 8 For example, the first pixel PX1 may be defined in the first opening 801 of the pixel defining layer PDL, the second pixel PX2 may be defined in the second opening 802 of the pixel defining layer PDL, and the third pixel PX3 may be defined in the third opening 803 of the pixel defining layer PDL. Figure 8 , the area outside the solid line may be interpreted as an area in which the pixel defining layer PDL is substantially disposed.

[0140] According to an embodiment, the heating wiring 810 may be arranged between a plurality of pixels PX. The heating wiring 810 is arranged on the pixel defining layer PDL and surrounds each opening OP of the pixel defining layer PDL. For example, the first heating wiring 811 is arranged around the first opening 801 corresponding to each of the plurality of first pixels PX1 and surrounds the first opening 801. The second heating wiring 812 is arranged around the second opening 802 corresponding to each of the plurality of second pixels PX2 and surrounds the second opening 802. Similarly, the heating wiring 810 may surround the third opening 803 corresponding to each of the plurality of third pixels PX3.

[0141] According to an embodiment, a plurality of heating wirings 810 may be driven independently of each other. A plurality of heating wirings 810 may be provided around the opening OP, respectively, and may be electrically connected to the power wiring 830 through the contact hole CT810. For example, the first heating wiring 811 surrounding the first opening 801 may be electrically connected to the power wiring 830 through the first contact hole CT811. The second heating wiring 812 surrounding the second opening 802 may be electrically connected to the power wiring 830 through the second contact hole CT812. Such contact holes CT810 may be arranged in a region surrounding each opening OP, and the positions of the contact holes CT810 are not limited to those of the illustrated examples.

[0142] According to an embodiment, the power wiring 830 may be arranged in a grid shape on the wiring layer 502 positioned below the light emitting element layer 503, and a driving voltage (or a driving current) is supplied to the heating wiring 810 through the contact hole CT810. Such a power wiring 830 may be positioned at a position corresponding to the reference Figure 5 Any one of the plurality of connection electrodes 820 of the wiring layer 502 is depicted on the same layer.

[0143] According to an embodiment, the power wiring 830 may extend to the non-display area NDA and be connected to the power pad 840. The power pad 840 may be arranged in the non-display area NDA, and may include a single power pad 840 or a plurality of power pads 840. That is, in the illustrated example, a plurality of power pads 840 are described as being arranged in the non-display area NDA, but a single power pad 840 may also be arranged in one area of ​​the non-display area NDA. The power pad 840 may be used to apply a driving voltage (or a driving current) to the power wiring 830. The driving voltage (or a driving current) supplied to the power wiring 830 may be provided to each heating wiring 810 arranged on the pixel defining layer PDL through the contact hole CT810.

[0144] According to an embodiment, the power wiring 830 may be, for example, a wiring for a low potential voltage (a second driving voltage ELVSS (see Figure 4 )). For example, the low potential voltage supply wiring may be used to supply a driving voltage (or a driving current) to the heating wiring 810 during the manufacturing process of the display panel 110. The low potential voltage supply wiring may be used as a supply wiring for supplying a low potential voltage (a second driving voltage ELVSS (see FIG. 1 )) after the manufacturing of the display panel 110 is completed. Figure 4 ))'s wiring.

[0145] Although not shown, each heating wiring 810 can be connected to ground through a dummy contact hole (not shown) to form a current path. For example, a driving voltage (or driving current) input to each heating wiring 810 through a power wiring 830 can form a current path flowing to the outside through the dummy contact hole. To this end, the present disclosure may also include a dummy contact hole (not shown) and a connecting electrode 820 that connects a ground wiring (not shown) and a ground of the heating wiring 810 through the dummy contact hole.

[0146] Fig. 9 The diagram shows Figure 8 In the embodiment shown in FIG. 1 , the thermal driving pad unit is arranged on the outer edge of the cutting area. Fig. 9 In the following description of the implementation method of Figure 8 The description of the implementation method of the invention is repeated, and the description will focus on Fig. 9 The implementation method and Figure 8 The differences between the implementations of

[0147] Fig. 9 The implementation method and Figure 8 The difference between the embodiments of is that the display panel 110 does not include the power pad 840. The power pad 840 may be arranged outside the display panel 110, for example, on a mother substrate (not shown) used to manufacture the display panel 110. After performing a cutting process of cutting each of the plurality of display panels 110 from the mother substrate, the power pad 840 may not be included in the non-display area NDA of each display panel 110. Therefore, the power pad 840 may not be arranged in the non-display area NDA of the display panel 110 manufactured as a single piece after the cutting process. Fig. 9 , arrows 901 indicate cutting lines for cutting each display panel 110 from a mother substrate including the display panel 110 .

[0148] Fig.10 It is a schematic diagram Figure 8 and Fig. 9 FIG. 4 is a cross-sectional view of the cross-sectional structure of adjacent pixels PX (eg, a first pixel PX1 and a second pixel PX2 ). Fig.11 The diagram shows Fig.10 The first power supply wiring 831 and the second power supply wiring 832 shown in the figure are combined into one wiring. For example, Fig.10 and Fig.11 Can be along Figure 8 1 is a cross-sectional view of the light emitting element layer 503 of the display panel 110 taken along line AA′.

[0149] Reference Fig.10, the pixel defining layer PDL is arranged on the wiring layer to separate adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). In the illustrated example, the pixel defining layer PDL separates the first pixel PX1 and the second pixel PX2 adjacent to each other. For example, the first electrode ANE of the first pixel PX1 is arranged in the first opening 801 of the pixel defining layer PDL, and the first electrode ANE of the second pixel PX2 is arranged in the second opening 802. The pixel defining layer PDL is arranged between the first opening 801 and the second opening 802.

[0150] The intermediate layer ML is arranged on the first electrode ANE in the opening OP (the first opening 801 and the second opening 802) of the first pixel PX1 and the second pixel PX2. The intermediate layer ML arranged on the first electrode ANE in the opening OP (the first opening 801 and the second opening 802) of the adjacent pixel PX (for example, the first pixel PX1 and the second pixel PX2) may extend onto the upper surface of the pixel defining layer PDL, but may be disconnected on and / or around the heating wiring 810 on the pixel defining layer PDL. That is, the intermediate layer ML covers the first electrode ANE in the opening OP (the first opening 801 and the second opening 802) of the adjacent pixel PX (for example, the first pixel PX1 and the second pixel PX2) and extends onto the upper surface of the pixel defining layer PDL, but may be disconnected on the pixel defining layer PDL between the adjacent pixels PX (for example, the first pixel PX1 and the second pixel PX2) by the heating wiring 810.

[0151] The disconnection of the middle layer ML described in this document can be explained as follows. The middle layer ML includes Figure 6 and Figure 7 The multiple layers described, and all layers may be disconnected on the heating wiring 810 (or around the heating wiring 810). However, the present disclosure is not limited thereto. For example, some conductive layers among the multiple layers included in the middle layer ML may be disconnected on the heating wiring 810 (or around the heating wiring 810). In this case, some conductive layers may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, a charge generation layer CGL, and a P-doped layer PHIL.

[0152] The second electrode CAE is arranged on the middle layer ML in the opening OP (the first opening 801 and the second opening 802) of the first pixel PX1 and the second pixel PX2. The second electrode CAE arranged on the middle layer ML in the opening OP (the first opening 801 and the second opening 802) of the first pixel PX1 and the second pixel PX2 extends onto the pixel defining layer PDL to cover the middle layer ML and the heating wiring 810 exposed during the process of removing the middle layer ML. Therefore, the second electrode CAE is continuous while covering the middle layer ML in the opening OP of the pixel defining layer PDL and covering the middle layer ML and the heating wiring 810 between the adjacent pixels PX (for example, the first pixel PX1 and the second pixel PX2).

[0153] As described above, the second electrode CAE is shared between the plurality of pixels PX and is continuously arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). In contrast, the middle layer ML is shared between the plurality of pixels PX but is disconnected between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2) by the heating wiring 810.

[0154] The continuous connection of the second electrode CAE and the disconnection of the middle layer ML will now be described in more detail.

[0155] According to an embodiment, a heating wiring 810 surrounding each of a plurality of openings OP (a first opening 801 and a second opening 802) is arranged on a pixel defining layer PDL arranged between adjacent pixels PX (e.g., a first pixel PX1 and a second pixel PX2). A first portion ML1 of an intermediate layer ML and a second portion CAE1 of a second electrode CAE covering the first portion ML1 of the intermediate layer ML are arranged on the pixel defining layer PDL having the heating wiring 810. Here, the first portion ML1 of the intermediate layer ML is disconnected from a third portion ML2 of the intermediate layer ML arranged in the opening OP (the first opening 801 and the second opening 802) of the pixel defining layer PDL around the heating wiring 810. On the other hand, the second portion CAE1 of the second electrode CAE is continuously connected to the fourth portion CAE2 without being disconnected from the fourth portion CAE2 of the second electrode CAE arranged in the opening OP (the first opening 801 and the second opening 802) of the pixel defining layer PDL around the heating wiring 810. Here, the fourth portion CAE2 of the second electrode CAE arranged in the opening OP (the first opening 801 and the second opening 802 ) is a portion covering the third portion ML2 of the middle layer ML arranged in the opening OP (the first opening 801 and the second opening 802 ).

[0156] Since the heating wiring 810 surrounds each of the plurality of openings OP (the first opening 801 and the second opening 802) of the pixel defining layer PDL, the first heating wiring 811 and the second heating wiring 812 may be arranged separately from each other on the pixel defining layer PDL arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). For example, the first heating wiring 811 surrounding the first opening 801 of the first pixel PX1 and the second heating wiring 812 surrounding the second opening 802 of the second pixel PX2 may be arranged on the pixel defining layer PDL arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). In addition, the first heating wiring 811 and the second heating wiring 812 may be spaced apart by a predetermined distance on the pixel defining layer PDL arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the intermediate layer ML on the pixel defining layer PDL disconnected from each pixel PX may be substantially arranged between the first heating wiring 811 and the second heating wiring 812. For example, the first portion ML1 of the middle layer ML disconnected from the third portion ML2 of the middle layer ML arranged in the opening OP (the first opening 801 and the second opening 802 ) of the pixel defining layer PDL is arranged between the first heating wiring 811 and the second heating wiring 812 .

[0157] According to an embodiment, the power wiring 830 may independently drive the first and second heating wirings 811 and 812 surrounding the adjacent first and second pixels PX1 and PX2, respectively. The power wiring 830 and the heating wiring 810 may be provided in a one-to-one correspondence.

[0158] For example, the power wiring 830 may include a first power wiring 831 driving the first heating wiring 811 and a second power wiring 832 driving the second heating wiring 812. The first heating wiring 811 may be electrically connected to the first power wiring 831 by filling the first connection electrode 821 of the first contact hole CT811 penetrating the pixel defining layer PDL. The second heating wiring 812 may be electrically connected to the second power wiring 832 by filling the second connection electrode 822 of the second contact hole CT812 penetrating the pixel defining layer PDL. The first power wiring 831 and the second power wiring 832 may be arranged at intervals in the wiring layer 502 and may be driven independently. Although not shown, each of the first power wiring 831 and the second power wiring 832 may be arranged on a different layer included in the wiring layer 502.

[0159] In order to disconnect the middle layer ML by applying a driving voltage (or driving current) to the heating wiring 810, it is necessary to heat the heating wiring 810 to a high temperature of about 400°C or higher. To this end, it is necessary to design the resistance of the heating wiring 810 to be relatively high. According to an embodiment, the first metal forming the heating wiring 810, the second metal forming the connecting electrode 820, and the third metal forming the power wiring 830 may be different metals. Here, the resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal. That is, the resistance of the heating wiring 810 may be greater than the resistance of the connecting electrode 820, and the resistance of the connecting electrode 820 may be greater than the resistance of the power wiring 830.

[0160] at the same time, Fig.11 The implementation method and Fig.10 The difference between the embodiments of the present invention is that the first power wiring 831 and the second power wiring 832 are merged into one power wiring 830. For example, a pair of heating wirings 810 surrounding each of adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2) can be electrically connected to one power wiring 830 through a contact hole CT810. The present disclosure can use one power wiring 830 to drive at least two heating wirings 810 arranged adjacent to each other as a group, thereby reducing the number of power wirings 830 and power pads 840. Fig.11 , one power wiring 830 drives (ie, supplies a driving voltage to) two heating wirings 810 arranged adjacent to each other as a group. However, this is only one embodiment, and one power wiring 830 may drive two or more heating wirings 810 arranged adjacent to each other as a group.

[0161] Fig.12 It is a graphic manufacturing Fig.10 Flowchart of a method for displaying panel 110 is illustrated in FIG. Figures 13 to 16 are cross-sectional views sequentially illustrating a method of manufacturing the display panel 110 according to an embodiment.

[0162] Now refer to Figures 12 to 16 A method of manufacturing the display panel 110 according to an embodiment is described. The following description focuses on the process of manufacturing the display panel 110. Additional processes for forming the elements described herein may be performed before or after each operation described below. In addition, a conventional process for manufacturing the display panel 110 may be additionally performed before or after each operation described below.

[0163] Reference Fig.12 In operation 1210, a driving element layer 501 may be formed on the substrate 200. The driving element layer 501 may include a reference Figure 5The driving element layer 501 may include a display driving circuit 210 (see Figure 2 ) and pixel driving circuit PC.

[0164] Reference Fig.12 and Fig.13 In operation 1220, a wiring layer 502 may be formed on the driving element layer 501. The wiring layer 502 may include a plurality of insulating layers VIA sequentially stacked on the driving element layer 501, a connection electrode CE at least partially extending through the plurality of insulating layers VIA, and a plurality of wirings. The wiring layer 502 may include a power wiring 830 for supplying a driving voltage (or a driving current) to the heating wiring 810. The power wiring 830 may be, for example, a low potential voltage (a second driving voltage ELVSS (see Figure 4 ))'s supply wiring.

[0165] Reference Fig.12 and Fig.13 In operation 1230, a first electrode ANE of each pixel PX and a pixel defining layer PDL defining the pixel PX may be formed on the wiring layer 502. The first electrode ANE of each pixel PX may be exposed through an opening OP of the pixel defining layer PDL during the process. Both ends of each first electrode ANE may be covered by the pixel defining layer PDL.

[0166] Reference Fig.12 and Fig.13 In operation 1240, a contact hole CT810 extending through the pixel defining layer PDL and at least a portion of the insulating layer VIA of the wiring layer 502 is formed, and a connection electrode 820 electrically connected to the power wiring 830 of the wiring layer 502 is formed by filling the contact hole CT810. Then, a heating wiring 810 may be formed on the pixel defining layer PDL to cover the connection electrode 820 and surround each opening OP of the pixel defining layer PDL. Here, the first metal forming the heating wiring 810, the second metal forming the connection electrode 820, and the third metal forming the power wiring 830 may be different metals. Here, the resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal. That is, the resistance of the heating wiring 810 may be greater than the resistance of the connection electrode 820, and the resistance of the connection electrode 820 may be greater than the resistance of the power wiring 830.

[0167] Reference Fig.12 and Fig.14In operation 1250, the middle layer ML may be deposited. For example, by using an opening mask (not shown), the middle layer ML may be deposited not only in the opening OP of the pixel defining layer PDL but also on the pixel defining layer PDL between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the middle layer ML may cover the first electrode ANE in each opening OP of the pixel defining layer PDL and the heating wiring 810 disposed on the pixel defining layer PDL.

[0168] Reference Fig.12 and Fig.15 In operation 1260, the heating wiring 810 may be used to remove all or at least a portion of the intermediate layer ML disposed between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). To this end, a driving voltage (or a driving current) may be applied to the power supply pad 840, and the driving voltage (or a driving current) applied to the power supply pad 840 may be supplied to each heating wiring 810 passing through the power supply wiring 830 and the connection electrode 820. The heating wiring 810 is heated to a high temperature of about 400° C. or higher by the driving voltage (or the driving current). Due to the high temperature of the heating wiring 810, all or at least a portion of the intermediate layer ML deposited on the heating wiring 810 may be removed.

[0169] Reference Fig.12 and Fig.16 , in operation 1270, the second electrode CAE may be deposited. For example, by using an open mask, the second electrode CAE may be deposited not only in the opening OP of the pixel defining layer PDL, but also on the pixel defining layer PDL arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the second electrode CAE may cover the middle layer ML in each opening OP of the pixel defining layer PDL, and cover the middle layer ML and the heating wiring 810 arranged on the pixel defining layer PDL.

[0170] In reference Figures 12 to 16 In the method of manufacturing the display panel 110 described above, before the operation of depositing the second electrode CAE, a process of removing all or part of the middle layer ML using the heating wiring 810 is performed. However, the present disclosure is not limited thereto. For example, the process of removing all or part of the middle layer ML using the heating wiring 810 may also be performed after the operation of depositing the second electrode CAE.

[0171] Now refer to Figures 17 to 22 A method of performing a process of removing all or part of the middle layer ML using the heating wiring 810 after an operation of depositing the second electrode CAE and a display panel 110 manufactured using the method are described.

[0172] Fig.17The diagram shows Figure 8 The heating wiring 810 illustrated in FIG. 8 includes an embodiment of an open slit area OA in a specific lateral direction of each pixel PX. Fig.17 In the following description of the implementation method of Fig.10 The description of the implementation method of the invention is repeated, and the description will focus on Fig.17 The implementation method and Fig.10 The differences between the implementations of

[0173] Fig.17 The implementation method and Fig.10 The embodiment of the present invention is different in that the heating wiring 810 includes an open slit area OA, but does not completely surround each opening OP of the pixel defining layer PDL. For example, when viewed in a normal direction perpendicular to the upper surface of the substrate 200, the heating wiring 810 may surround each opening OP of the pixel defining layer PDL, but may include an open slit area OA that is open in a specific lateral direction. In the illustrated example, the open slit area OA is positioned in the first lateral direction of each pixel PX (for example, Fig.17 On the upper side of the figure), but the present disclosure is not limited to this.

[0174] According to an embodiment, the opening slit area OA may be defined as an area in which the heating wiring 810 is not arranged. Since the heating wiring 810 is not arranged in the opening slit area OA, the intermediate layer ML and the second electrode CAE of the light emitting element LEL may be continuous in the opening slit area OA without being disconnected. For example, the intermediate layer ML positioned outside each heating wiring 810 may be electrically connected to the intermediate layer ML positioned inside each heating wiring 810 (e.g., each opening OP of the pixel defining layer PDL) through the opening slit area OA. Similarly, the second electrode CAE positioned outside each heating wiring 810 may be electrically connected to the second electrode CAE positioned inside each heating wiring 810 (e.g., each opening OP of the pixel defining layer PDL) through the opening slit area OA. Therefore, the intermediate layer ML and the second electrode CAE may be continuous in the opening slit area OA without being disconnected.

[0175] Fig.18 It is a graphic manufacturing Fig.17 Flowchart of a method for displaying panel 110 is illustrated in FIG. Figures 19 to 22 are cross-sectional views sequentially illustrating a method of manufacturing the display panel 110 according to an embodiment.

[0176] Now refer to Figures 18 to 22A method of manufacturing the display panel 110 according to an embodiment is described. The following description focuses on the process of manufacturing the display panel 110. The additional process for forming the elements described in this document may be performed before or after each operation described below. In addition, the conventional process of manufacturing the display panel 110 may be additionally performed before or after each operation described below.

[0177] Reference Fig.18 In operation 1810, a driving element layer 501 may be formed on the substrate 200. The driving element layer 501 may include a reference Figure 5 The driving element layer 501 may include a display driving circuit 210 (see Figure 2 ) and pixel driving circuit PC. Operation 1810 is similar to reference Fig.12 The described operations 1210 are substantially the same.

[0178] Reference Fig.18 and Fig.19 In operation 1820, a wiring layer 502 may be formed on the driving element layer 501. The wiring layer 502 may include a plurality of insulating layers VIA sequentially stacked on the driving element layer 501, a connection electrode CE at least partially penetrating the plurality of insulating layers VIA, and a plurality of wirings. The wiring layer 502 may include a power wiring 830 for supplying a driving voltage (or a driving current) to the heating wiring 810. The power wiring 830 may be, for example, a low potential voltage (a second driving voltage ELVSS (see Figure 4 Operation 1820 and reference Fig.12 The described operation 1220 is substantially the same.

[0179] Reference Fig.18 and Fig.19 In operation 1830, a first electrode ANE of each pixel PX and a pixel defining layer PDL defining the pixel PX may be formed on the wiring layer 502. The first electrode ANE of each pixel PX may be exposed through an opening OP of the pixel defining layer PDL during the process. Both ends of each first electrode ANE may be covered by the pixel defining layer PDL. Operation 1830 is similar to the operation of reference numeral 1830. Fig.12 The described operation 1230 is substantially the same.

[0180] Reference Fig.18 and Fig.19In operation 1840, a contact hole CT810 extending through the pixel defining layer PDL and at least a portion of the insulating layer VIA of the wiring layer 502 is formed, and a connection electrode 820 electrically connected to the power wiring 830 of the wiring layer 502 is formed by filling the contact hole CT810. Then, a heating wiring 810 may be formed on the pixel defining layer PDL to cover the connection electrode 820 and surround each opening OP of the pixel defining layer PDL. Here, the first metal forming the heating wiring 810, the second metal forming the connection electrode 820, and the third metal forming the power wiring 830 may be different metals. Here, the resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal. That is, the resistance of the heating wiring 810 may be greater than the resistance of the connection electrode 820, and the resistance of the connection electrode 820 may be greater than the resistance of the power wiring 830. In operation 1840, the heating wiring 810 is formed to have an open slit area OA without completely surrounding each opening OP of the pixel defining layer PDL.

[0181] Reference Fig.18 and Fig. 20 In operation 1850, an intermediate layer ML may be deposited. For example, by using an opening mask (not shown), the intermediate layer ML may be deposited not only in the opening OP of the pixel defining layer PDL but also on the pixel defining layer PDL between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the intermediate layer ML may cover the first electrode ANE in each opening OP of the pixel defining layer PDL and the heating wiring 810 disposed on the pixel defining layer PDL. Operation 1850 is similar to that described with reference to FIG. Fig.12 The described operations 1250 are substantially the same.

[0182] Reference Fig.18 and Fig.21 , in operation 1860, the second electrode CAE may be deposited. For example, by using an opening mask (not shown), the second electrode CAE may be deposited not only in the opening OP of the pixel defining layer PDL, but also on the pixel defining layer PDL arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the second electrode CAE may cover the middle layer ML in each opening OP of the pixel defining layer PDL, and cover the middle layer ML arranged on the pixel defining layer PDL.

[0183] Reference Fig.18 and Fig. 22In operation 1870, the heating wiring 810 may be used to remove all or at least a portion of the intermediate layer ML and the second electrode CAE arranged between adjacent pixels PX (e.g., the first pixel PX1 and the second pixel PX2). To this end, a driving voltage (or a driving current) may be applied to the power supply pad 840, and the driving voltage (or a driving current) applied to the power supply pad 840 may be supplied to each heating wiring 810 passing through the power supply wiring 830 and the connection electrode 820. The heating wiring 810 is heated to a high temperature of about 400° C. or higher by the received driving voltage (or driving current). At least a portion of the intermediate layer ML deposited on the heating wiring 810 and a portion of the second electrode CAE deposited on the heating wiring 810 may be removed due to the high temperature of the heating wiring 810. However, since the heating wiring 810 does not completely surround each opening OP and provide an opening slit area OA, the intermediate layer ML and the second electrode CAE may be continuous in the opening slit area OA without disconnection.

[0184] Fig.23 is an exemplary view of a wearable device including a display device 2360 according to an embodiment.

[0185] In the above, the display device 10 according to the embodiment may be a display device 10 included in a mobile electronic device. The display device 10 according to the embodiment may be included in a wearable device developed in the form of glasses or a helmet, and forms a focus at a short distance from the user's eyes. For example, the wearable device may be a head-mounted display (HMD) or augmented reality (AR) glasses. Such a wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0186] Fig.23 The VR device 2300 to which the display device 2360 according to the embodiment is applied is shown. Here, the display device 2360 may be, for example, a device including the above Figures 1 to 22 The display device 2360 includes elements.

[0187] Reference Fig.23 According to an embodiment, the VR device 2300 may be an AR device in the form of glasses. According to an embodiment, the VR device 2300 may include a left lens 2311, a right lens 2312, a support frame 2320, glasses frame legs 2331 and 2332, and an image processing unit 2350.

[0188] The image processing unit 2350 may include a display device 2360 and a reflective member 2340. The image displayed on the display device 2360 may be reflected by the reflective member 2340 and provided to the right eye of the user through the right lens 2312. Therefore, the user may observe the VR image displayed on the display device 2360 through the right eye.

[0189] Despite Fig.23 The image processing unit 2350 is arranged at the right end of the supporting frame 2320, but the present disclosure is not limited thereto. For example, the image processing unit 2350 may also be arranged at the left end of the supporting frame 2320. In this case, the image displayed on the display device 2360 may be reflected by the reflective member 2340 and provided to the user's left eye through the left lens 2311. Therefore, the user can observe the VR image displayed on the display device 2360 through the left eye. Alternatively, the image processing unit 2350 may be arranged at both the right end and the left end of the supporting frame 2320. In this case, the user can observe the VR image displayed on the display device 2360 through both the left eye and the right eye.

[0190] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the preferred embodiment without departing from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; a driving element layer, wherein the driving element layer is arranged on the substrate; a wiring layer disposed on the driving element layer and including power supply wiring; as well as a light emitting element layer disposed on the wiring layer, Wherein, the light emitting element layer comprises: a pixel defining layer defining a plurality of openings for a plurality of pixels; a first electrode disposed in each of the plurality of openings; a heating wiring arranged on the pixel defining layer around each opening; a connecting electrode connecting the heating wiring to the power wiring through a contact hole extending through at least a portion of the wiring layer and the pixel defining layer; an intermediate layer covering the first electrode in each of the plurality of pixels and the pixel defining layer between the plurality of pixels and including a disconnected portion adjacent to the heating wiring on the pixel defining layer; and A second electrode is continuously disposed on the intermediate layer in the plurality of openings for the plurality of pixels and between the plurality of pixels.

2. The display device according to claim 1, in, The disconnected portion of the intermediate layer and the second electrode covering the disconnected portion of the intermediate layer are arranged on the pixel defining layer between the plurality of pixels, wherein the disconnected portion of the intermediate layer is disconnected from the pixel portion of the intermediate layer arranged in the plurality of openings of the pixel defining layer, and Wherein, the second electrode is continuously arranged on the disconnected portion and the pixel portion of the intermediate layer.

3. The display device according to claim 2, wherein: The plurality of pixels include a first pixel and a second pixel, and the plurality of openings include a first opening of the first pixel and a second opening of the second pixel, The first heating wiring around the first opening and the second heating wiring around the second opening are spaced apart at a predetermined interval on the pixel defining layer between the plurality of pixels.

4. The display device according to claim 3, in, The disconnected portion of the intermediate layer is arranged between the first heating wiring and the second heating wiring.

5. The display device according to claim 3, in, The power supply wiring includes a first power supply wiring that drives the first heating wiring and a second power supply wiring that drives the second heating wiring, wherein the first heating wiring is electrically connected to the first power wiring through a first connection electrode extending through the pixel defining layer, and The second heating wiring is electrically connected to the second power wiring through a second connection electrode extending through the pixel defining layer.

6. The display device according to claim 5, in, The first power wiring and the second power wiring are spaced apart at the predetermined interval on the wiring layer and are independently driven.

7. The display device according to claim 5, in, The first power wiring and the second power wiring are connected as one power wiring on the wiring layer, and a pair of heating wirings surrounding each of a plurality of adjacent pixels are electrically connected to the one power wiring.

8. The display device according to claim 1, in, A first metal forming the heating wiring, a second metal forming the connection electrode, and a third metal forming the power wiring are different metals.

9. The display device according to claim 8, in, The resistance of the first metal is greater than the resistance of the second metal, and the resistance of the second metal is greater than the resistance of the third metal.

10. The display device according to claim 1, in, The intermediate layer includes one or more conductive layers having a disconnected portion adjacent to the heating wiring, and Wherein, the conductive layer includes at least one of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer and a P-doped layer.

11. The display device according to claim 1, in, The heating wiring arranged around each opening includes an opening slit region opened in a predetermined lateral direction.

12. The display device according to claim 11, in, The intermediate layer and the second electrode are continuously arranged around the opening slit region.

13. A mobile electronic device, comprising a display panel, wherein: The display panel comprises: substrate; a driving element layer, wherein the driving element layer is arranged on the substrate; a wiring layer disposed on the driving element layer and including a power supply wiring; and a light emitting element layer disposed on the wiring layer, Wherein, the light emitting element layer comprises: a pixel defining layer defining a plurality of openings for a plurality of pixels; a first electrode disposed in each of the plurality of openings; a heating wiring arranged on the pixel defining layer around each opening; a connecting electrode connecting the heating wiring to the power wiring through a contact hole extending through at least a portion of the wiring layer and the pixel defining layer; an intermediate layer covering the first electrode in each of the plurality of pixels and the pixel defining layer between the plurality of pixels and including a disconnected portion adjacent to the heating wiring on the pixel defining layer; and A second electrode is continuously disposed on the intermediate layer in the plurality of openings for the plurality of pixels and between the plurality of pixels.

14. The mobile electronic device according to claim 13, in, The disconnected portion of the intermediate layer and the second electrode covering the disconnected portion of the intermediate layer are arranged on the pixel defining layer between the plurality of pixels, wherein the disconnected portion of the intermediate layer is disconnected from the pixel portion of the intermediate layer arranged in the plurality of openings of the pixel defining layer, and Wherein, the second electrode is continuously arranged on the disconnected portion and the pixel portion of the intermediate layer.

15. The mobile electronic device according to claim 14, wherein: The plurality of openings include a first opening for a first pixel and a second opening for a second pixel, The first heating wiring around the first opening and the second heating wiring around the second opening are spaced apart at a predetermined interval on the pixel defining layer between the plurality of pixels.

16. The mobile electronic device according to claim 15, in, The disconnected portion of the intermediate layer is arranged between the first heating wiring and the second heating wiring.

17. The mobile electronic device according to claim 15, in, The power supply wiring includes a first power supply wiring that drives the first heating wiring and a second power supply wiring that drives the second heating wiring, wherein the first heating wiring is electrically connected to the first power wiring through a first connection electrode extending through the pixel defining layer, and The second heating wiring is electrically connected to the second power wiring through a second connection electrode extending through the pixel defining layer.

18. The mobile electronic device according to claim 17, in, The first power wiring and the second power wiring are spaced apart at the predetermined interval on the wiring layer and are independently driven.

19. The mobile electronic device according to claim 17, in, The first power wiring and the second power wiring are connected as one power wiring on the wiring layer, and a pair of heating wirings surrounding each of a plurality of adjacent pixels are electrically connected to the one power wiring.

20. The mobile electronic device according to claim 13, in, A first metal forming the heating wiring, a second metal forming the connection electrode, and a third metal forming the power supply wiring are different metals, and The resistance of the first metal is greater than the resistance of the second metal, and the resistance of the second metal is greater than the resistance of the third metal.

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