Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof, the display device comprises a plurality of pixel units, and each pixel unit comprises a light emitting device and a driving circuit. According to the driving circuit, a capacitor is additionally arranged on the basis of a bootstrap capacitor, and charging and discharging of the capacitor are controlled through a thin film transistor switch, so that the voltage of a key control node is not influenced by the potential of a next frame of ramp signal, and each row of pixels can completely compare a data signal and the ramp signal in one frame; the display accuracy is improved. According to the invention, a global ramp signal control scheme is adopted, the circuit structure is simplified, the number of signal lines is reduced, and the realization of a narrow frame design is facilitated. According to the driving method, by accurately controlling the signal state of each time period, accurate regulation and control of pixel light-emitting time are achieved, the duty ratio range is expanded by 5%-99%, and the driving method can adapt to different display scenes.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and a driving method thereof. Background Art

[0002] MLED (micro light emitting diode) display technology is a current-driven display technology, and its brightness depends on the product of the light-emitting current and the light-emitting time. In order to better control the light emission of pixel units in MLED display devices, PWM (pulse width modulation) technology is widely used in the industry. PWM technology achieves different brightness displays by adjusting the proportion of light-emitting time (i.e., duty cycle).

[0003] In the PWM part of the comparative driving circuit of the pixel unit, the most critical part is the voltage control of the control node. When the ramp signal (Sweep) is coupled to the control node and its voltage is lower than the turn-on voltage of the driving thin film transistor (DTFT), the power supply voltage (VDD) will be sent to the current control module, thereby terminating the light emission. This process determines the light emission time of the pixel and thus controls the brightness.

[0004] However, this traditional PWM technology has a significant problem. When the pixel units in a row start to compare data, the ramp signal Sweep has already dropped for a period of time, resulting in the data signal and the ramp signal cannot be fully compared within the driving cycle of a frame. This problem seriously affects the accuracy of the display.

[0005] Therefore, how to achieve complete comparison of data signals and ramp signals by pixel units within a driving cycle of one frame has become a technical problem to be solved urgently in the field of MLED display technology. Summary of the invention

[0006] The embodiments of the present application provide a display device and a driving method thereof, which are intended to solve the problem that a traditional display device cannot completely compare a data signal and a ramp signal within a driving cycle of a frame.

[0007] An embodiment of the present application provides a display device, comprising: a display panel, the display panel comprising a plurality of pixel units, the plurality of pixel units being arranged in rows and columns; and a control circuit electrically connected to the plurality of pixel units, the control circuit being used to generate a ramp signal and output the ramp signal to the plurality of pixel units; wherein the pixel unit comprises a light-emitting device and a driving circuit, the driving circuit being electrically connected to the light-emitting device, the driving circuit comprising a pulse width modulation module; the pulse width modulation module comprising a first capacitor, a second capacitor, a first transistor, a second transistor and a third transistor; wherein one plate of the first capacitor is electrically connected to the first node, and the other plate is electrically connected to the third a node electrically connected; one plate of the second capacitor is electrically connected to the third node, and the other plate is electrically connected to the second node; the gate of the first transistor is electrically connected to the first scan signal input terminal, one of the source and the drain is electrically connected to the first node, and the other of the source and the drain is electrically connected to the third node; the gate of the second transistor is electrically connected to the light emitting signal input terminal, one of the source and the drain is electrically connected to the ramp signal input terminal, and the other of the source and the drain is electrically connected to the first node; the gate of the third transistor is electrically connected to the first reset signal input terminal, one of the source and the drain is electrically connected to the reference signal input terminal, and the other of the source and the drain is electrically connected to the third node.

[0008] An embodiment of the present application also provides a driving method for a display device, comprising the following steps: generating a ramp signal and outputting the ramp signal to a plurality of pixel units; in a first time period, controlling the first transistor to be turned on or off, the second transistor to be turned on, the third transistor to be turned off, and the voltage of the first node to be equal to the voltage Vsweep of the ramp signal; in a second time period, controlling the first transistor to be turned off, the second transistor and the third transistor to be turned on, the voltage of the third node to be pulled down from the maximum value SW(H) of the voltage of the ramp signal to 0V, and the voltage of the second node to be reset under the coupling action of the second capacitor; in a third time period, controlling the first transistor and the third transistor to be turned off, the second transistor to be turned on, and the voltage of the second node to be decreased as the voltage of the first node decreases. ; In a fourth time period, the first transistor, the second transistor and the third transistor are controlled to be turned off, and the fourth transistor, the fifth transistor, the sixth transistor and the ninth transistor are turned on, the data signal of the first data signal input terminal is written to the second node, and the voltage of the first power signal input terminal is written to the first node and the third node; In a fifth time period, the first transistor and the second transistor are controlled to be turned on, and the third transistor is turned off, and the voltage Vsweep of the ramp signal is written to the first node and the third node, and the eighth transistor controls the light-emitting time of the light-emitting device according to the comparison result of the first data signal written to the second node and the ramp signal; In a sixth time period, the first transistor is controlled to be turned on or off, the second transistor is turned on, and the third transistor is turned off.

[0009] In the display device and the driving method thereof provided by the present application, a capacitor is added on the basis of the bootstrap capacitor, and the charging and discharging of the capacitor is controlled by a thin film transistor switch, so that the voltage of the key control node is not affected by the potential of the ramp signal of the next frame. This technical solution enables each row of pixel units to completely compare the data signal and the ramp signal within the driving cycle of a frame, thereby significantly improving the accuracy of the display. Specifically, the display device and the driving method thereof provided by the present application allow the ramp signal to be reset at the beginning of each frame, ensuring that each row of pixels has the same comparison time.

[0010] In addition, the display device and the driving method thereof provided by the present application adopt a global ramp signal control scheme, which greatly simplifies the circuit structure of the pixel unit. Unlike the traditional technology that requires a ramp signal to be provided separately for each row of pixels, the display device and the driving method thereof provided by the present application only need a global ramp signal to control all rows of pixels, reducing the number of signal lines, which is conducive to realizing a narrow frame of the display device. This design not only simplifies the circuit structure, but also significantly reduces the instantaneous current of the panel and improves energy efficiency.

[0011] In addition, by applying a global ramp signal, progressive light emission is achieved. Combined with the timing control of the display device and the driving method provided by the present application, the optional range of duty is greatly expanded to 5%~99%. This greatly enhances the applicability of the display device in various scenarios, especially in low grayscale (such as night mode or dark scene display) and high grayscale (such as outdoor display in bright environment) display scenes. It can perform well, so that the display device of the present invention can provide a high-quality visual experience under different ambient light conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present application.

[0013] Figure 2 yes Figure 1 FIG. 1 is a circuit diagram of a first embodiment of a pixel unit of a display device.

[0014] Figure 3 yes Figure 2 The waveform diagram of the signal of the pixel unit shown.

[0015] Figure 4 yes Figure 1 FIG. 1 is a circuit diagram of a second embodiment of a pixel unit of a display device. DETAILED DESCRIPTION

[0016] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0017] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0018] The embodiments of the present application may be combined with each other.

[0019] refer to Figure 1 The display device provided in the embodiments of the present application may be, for example, a Micro-LED display device. Of course, the display device may also be a Mini-LED display device or an OLED display device. The embodiments of the present application are described with reference to a Micro-LED display device.

[0020] The display device includes a source driving circuit, a gate driving circuit, a timing controller, a light emitting controller, a power management chip, a substrate, a data line DATA, a scan line SCAN, a power line (VDD, VSS), a light emitting control signal line EM, a pixel array, an encapsulation layer, a polarizer, a color filter, etc.

[0021] The substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of a plurality of pixel units PX arranged in rows and columns, and each pixel unit PX includes a light-emitting device and a driving circuit. The driving circuit includes a TFT device, which is used to control the brightness of each light-emitting device of the display device. The TFT device includes low-temperature polycrystalline silicon (LTPS) and a metal oxide TFT. The TFT device may adopt a dual-gate structure, and the light-emitting device is electrically connected to the TFT device. The light-emitting device includes a light-emitting layer, an electron transport layer, a hole transport layer, a cathode and an anode, etc. Each level of the gate driving unit in the gate driving circuit controls a row of pixel units PX, and the gate driving unit is used to control the TFT device to realize the gating of the pixel unit PX. Each level of the gate driving unit is mainly composed of a thin film transistor (TFT) and a capacitor. The source driving circuit is used to provide a data signal to the pixel unit PX. The timing controller is used to receive externally input image data and synchronization signals, and generate signals required by the gate driving circuit and the source driving circuit. The power management chip is used to provide the required operating voltage for each part of the display device.

[0022] In addition, the display device of the present application may also integrate an embedded touch control circuit, which is electrically connected to the display driving circuit, and implements the touch control function and the display function in a time division multiplexing manner.

[0023] The present application provides a display device, which is a progressive light-emitting micro-light-emitting diode display device. The display device and its driving method use a global ramp signal to compare with a data signal and control light emission. The global ramp signal refers to using a ramp signal source to control multiple rows (or even all rows) of pixel units, which can simplify the circuit structure, reduce power consumption, and improve system stability.

[0024] The display device includes a display panel and a control circuit.

[0025] The display panel includes a plurality of pixel units PX, and the plurality of pixel units PX are arranged in rows and columns.

[0026] The control circuit is electrically connected to a plurality of pixel units PX, and the control circuit is used to generate a ramp signal Sweep and output the ramp signal Sweep to the plurality of pixel units PX. The control circuit is also used to dynamically adjust the slope of the pulse of the ramp signal according to the characteristics of the display content (such as brightness, contrast, color saturation, etc.) to optimize the display effect. For example, for a high-contrast image, the slope of the ramp signal can be increased to obtain a finer brightness control. By controlling the shape (slope) and timing of the ramp signal, the brightness of each pixel unit can be precisely controlled.

[0027] Among them, Figure 2 and Figure 4As shown, the pixel unit PX includes a light emitting device LED and a driving circuit. The driving circuit is electrically connected to the light emitting device LED, and the driving circuit includes a pulse width modulation module PWM.

[0028] The pulse width modulation module PWM includes a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2 and a third transistor T3.

[0029] One plate of the first capacitor C1 is electrically connected to the first node A, and the other plate is electrically connected to the third node C.

[0030] One plate of the second capacitor C2 is electrically connected to the third node C, and the other plate of the second capacitor C2 is electrically connected to the second node B.

[0031] The gate of the first transistor T1 is electrically connected to the first scan signal input terminal S(n+1), one of the source and the drain is electrically connected to the first node A, and the other of the source and the drain is electrically connected to the third node C.

[0032] The gate of the second transistor T2 is electrically connected to the light emitting signal input terminal EM(n), one of the source and the drain is electrically connected to the ramp signal input terminal Sweep, and the other of the source and the drain is electrically connected to the first node A.

[0033] The gate of the third transistor T3 is electrically connected to the first reset signal input terminal RST2 , one of the source and the drain is electrically connected to the reference signal input terminal Vref , and the other of the source and the drain is electrically connected to the third node C .

[0034] The third transistor T3 is used for pulling down the third node C by an amplitude Vsweep of a ramp signal Sweep when a low level signal is input to the first reset signal input terminal RST2.

[0035] The combination of the first transistor T1 , the second transistor T2 , and the third transistor T3 is used to control the voltages of the first node A, the second node B, and the third node C at different time periods.

[0036] As an improvement, the threshold voltages of the first transistor T1 , the second transistor T2 and the third transistor T3 are different, which can optimize the switching characteristics and power consumption of the driving circuit.

[0037] The pulse width modulation module PWM also includes: The fourth transistor T4 has a gate electrically connected to the second scan signal input terminal S(n), one of the source and the drain electrically connected to the first power signal input terminal Vdd, and the other of the source and the drain electrically connected to the first node A.

[0038] The fifth transistor T5 has a gate electrically connected to the second scan signal input terminal S(n), one of the source and the drain electrically connected to the first power signal input terminal Vdd, and the other of the source and the drain electrically connected to the third node C.

[0039] As an improvement, a first regulating resistor is arranged between the other of the source and the drain of the fourth transistor T4 and the first node A, and a second regulating resistor is arranged between the other of the source and the drain of the fifth transistor T5 and the third node C. The first regulating resistor and the second regulating resistor are used to limit the instantaneous current flowing to the first node A and the third node C, thereby improving the reliability of the driving circuit.

[0040] The pulse width modulation module PWM also includes: The sixth transistor T6 has a gate electrically connected to the second scan signal input terminal S(n), and one of a source and a drain electrically connected to the first data signal input terminal Data_PWM.

[0041] The seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the light emitting signal input terminal EM(n), one of the source and the drain is electrically connected to the first power signal input terminal Vdd, and the other of the source and the drain is electrically connected to the other of the source and the drain of the sixth transistor T6.

[0042] The eighth transistor T8 has a gate electrically connected to the second node B, and one of a source and a drain electrically connected to the other of the source and the drain of the sixth transistor T6.

[0043] The ninth transistor T9 has a gate electrically connected to the second scan signal input terminal S(n), one of the source and the drain electrically connected to the second node B, and the other of the source and the drain electrically connected to the other of the source and the drain of the eighth transistor T8.

[0044] The tenth transistor T10 has a gate electrically connected to the light emitting signal input terminal EM(n), and one of a source and a drain electrically connected to the other of the source and the drain of the eighth transistor T8.

[0045] As an improvement, the eighth transistor T8 is a dual-gate structure to improve its switching characteristics and stability, and the remaining transistors are all single-gate structures.

[0046] As an improvement, the eighth transistor T8 is a low threshold transistor to improve the current driving capability, and the sixth transistor T6 and the ninth transistor T9 are high threshold transistors to reduce leakage current.

[0047] The driving circuit also includes a pulse amplitude modulation module PAM, and the pulse amplitude modulation module PAM includes: The eleventh transistor T11 has a gate electrically connected to the second scan signal input terminal S(n), one of a source and a drain electrically connected to the second data signal input terminal Data_PAM, and the other of a source and a drain electrically connected to the fourth node D.

[0048] The twelfth transistor T12 has a gate electrically connected to the fourth node D.

[0049] The thirteenth transistor T13, the gate of the thirteenth transistor T13 is electrically connected to the light emitting signal input terminal EM(n), one of the source and the drain is electrically connected to one of the source and the drain of the twelfth transistor T12, and the other of the source and the drain is electrically connected to the anode of the light emitting device LED.

[0050] The fourteenth transistor T14 has a gate electrically connected to the second reset signal input terminal RST1, one of the source and the drain electrically connected to the first power signal input terminal Vdd, and the other of the source and the drain electrically connected to the other of the source and the drain of the twelfth transistor T12.

[0051] The control circuit is further configured to generate a second reset signal RST1 and a first reset signal RST2 , and input the second reset signal RST1 and the first reset signal RST2 to the plurality of pixel units PX.

[0052] Of course, the second reset signal RST1 and the first reset signal RST2 can be global signals or non-global signals. Taking non-global signals as an example, for a large-size display device, the display device is divided into multiple areas, and each area uses an independent reset signal. In this way, partial refresh of the display device can be achieved, display efficiency is improved, and it is suitable for application scenarios where only part of the content needs to be updated.

[0053] like Figure 3 As shown, the driving cycle of a frame of picture displayed by the display device includes a first time period, a second time period, a third time period, a fourth time period, a fifth time period and a sixth time period.

[0054] In the first time period, the second reset signal RST1, the first reset signal RST2, the second scan signal S(n) and the first scan signal S(n+1) are all high level signals, the light control signal EM(n) is a low level signal, and the ramp signal Sweep is a high level signal.

[0055] In the second time period, the second reset signal RST1, the second scan signal S(n) and the first scan signal S(n+1) are all high level signals, the first reset signal RST2 and the light emitting control signal EM(n) are all low level signals, and the ramp signal Sweep is a high level signal.

[0056] In the third time period, the first reset signal RST2, the second scan signal S(n) and the first scan signal S(n+1) are all high level signals, the second reset signal RST1 and the light emitting control signal EM(n) are all low level signals, and the voltage of the ramp signal Sweep decreases linearly.

[0057] In the fourth time period, the second reset signal RST1 and the second scan signal S(n) are both low level signals, the first reset signal RST2, the first scan signal S(n+1) and the light emitting control signal EM(n) are all high level signals, and the voltage of the ramp signal Sweep decreases linearly.

[0058] In the fifth time period, the first reset signal RST2 and the second scan signal S(n) are both high level signals, the second reset signal RST1, the first scan signal S(n+1) and the light emitting control signal EM(n) are all low level signals, and the voltage of the ramp signal Sweep decreases linearly.

[0059] In the sixth time period, the first reset signal RST2, the second scan signal S(n) and the first scan signal S(n+1) are all high-level signals, the second reset signal RST1 and the light-emitting control signal EM(n) are all low-level signals, and the voltage of the ramp signal Sweep decreases linearly. At the end of the sixth time period, the ramp signal Sweep is a low-level signal.

[0060] Of course, the ramp signal in the third to sixth time periods can be a multi-level ramp signal (a plurality of ramp signals with different slopes in the third to sixth time periods), for example, the ramp signal in the third to sixth time periods is a piecewise linear or nonlinear ramp signal, rather than a simple linear decreasing signal, so that better grayscale performance can be obtained.

[0061] like Figures 2 to 4 As shown, the present application also provides a driving method for a display device, the driving method comprising the following steps: A ramp signal Sweep is generated and output to a plurality of pixel units PX.

[0062] In the first time period, the first transistor T1 is controlled to be turned on or off, the second transistor T2 is turned on, and the third transistor T3 is turned off, and the voltage of the first node A is equal to the voltage Vsweep of the ramp signal Sweep.

[0063] In the second time period, the first transistor T1 is controlled to be turned off, the second transistor T2 and the third transistor T3 are turned on, the voltage of the third node C is pulled down from the maximum value SW(H) of the voltage of the ramp signal Sweep to 0V, and the voltage of the second node B is reset under the coupling effect of the second capacitor C2.

[0064] In the third time period, the first transistor T1 and the third transistor T3 are controlled to be turned off, the second transistor T2 is turned on, and the voltage of the second node B decreases as the voltage of the first node A decreases.

[0065] In the fourth time period, the first transistor T1, the second transistor T2 and the third transistor T3 are controlled to be turned off, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned on, the data signal of the first data signal input terminal Data_PWM is written to the second node B, and the voltage of the first power signal input terminal Vdd is written to the first node A and the third node C.

[0066] In the fifth time period, the first transistor T1 and the second transistor T2 are controlled to be turned on, the third transistor T3 is turned off, the voltage Vsweep of the ramp signal Sweep is written to the first node A and the third node C, and the eighth transistor T8 controls the light-emitting time of the light-emitting device LED according to the comparison result of the first data signal Data_PWM written to the second node B and the ramp signal Sweep.

[0067] In the sixth time period, the first transistor T1 is controlled to be turned on or off, the second transistor T2 is turned on, and the third transistor T3 is turned off.

[0068] In the first time period, the first reset signal RST2, the second reset signal RST1, the second scan signal S(n) and the first scan signal S(n+1) are all high level, the light emitting control signal EM(n) is low level, and the ramp signal Sweep is high level.

[0069] In the second time period, the second reset signal RST1, the second scan signal S(n) and the first scan signal S(n+1) are all high levels, the first reset signal RST2 and the light emitting control signal EM(n) are all low levels, and the ramp signal Sweep is high level.

[0070] In the third time period, the second reset signal RST1 and the light emitting control signal EM(n) are both low levels, the first reset signal RST2, the second scan signal S(n) and the first scan signal S(n+1) are all high levels, and the voltage of the ramp signal Sweep decreases linearly.

[0071] In the fourth time period, the second reset signal RST1 and the second scan signal S(n) are both low levels, the first reset signal RST2, the first scan signal S(n+1) and the light control signal EM(n) are all high levels, and the voltage of the ramp signal Sweep decreases linearly.

[0072] In the fifth time period, the first reset signal RST2 and the second scan signal S(n) are both high, the second reset signal RST1, the first scan signal S(n+1) and the light emitting control signal EM(n) are all low, and the voltage of the ramp signal Sweep decreases linearly.

[0073] In the sixth time period, the first reset signal RST2, the second scan signal S(n) and the first scan signal S(n+1) are all high levels, the second reset signal RST1 and the light emitting control signal EM(n) are low levels, the voltage of the ramp signal Sweep decreases linearly, and at the end of the sixth time period, the ramp signal Sweep is low.

[0074] At the end of the second time period, the voltage Vb of the second node B satisfies: Vb = V(data_pwm) + Vth - Vdd + Vsw(t1) Among them, V(data_pwm) is the voltage of the first data signal input terminal Data_PWM, Vth is the threshold voltage of the eighth transistor (T8), Vdd is the voltage of the first power signal input terminal Vdd, Vth is added to compensate for the threshold voltage of the eighth transistor to reduce the display unevenness caused by the difference in transistor characteristics, and Vsw(t1) is the voltage value of the ramp signal Sweep corresponding to the time t1 of the previous frame of light emission.

[0075] In the first time period and the second time period, the second reset signal RST1 is at a high level, and the pixel units PX of all rows of the display device do not emit light.

[0076] In the display device and the driving method thereof provided in the present application, the duration of the RST1 signal can be dynamically adjusted according to the characteristics of the display content. For example, for static images, the high level time of RST1 can be extended to further save power consumption, while for fast-changing dynamic content, the high level time of RST1 can be shortened to improve the response speed.

[0077] The pixel unit of the display device provided in the present application adds a second capacitor C2 on the basis of the first capacitor C1, and pulls down the voltage of the third node C by the amplitude Vsweep of the ramp signal Sweep through the third transistor T3, so that the second node B is not affected by the potential of the ramp signal Sweep. In this way, the comparison between the normal data signal and the ramp signal Sweep can be completed.

[0078] Example 1 like Figure 2As shown, the display device provided in Embodiment 1 includes a plurality of pixel units arranged in rows and columns. Each pixel unit includes a light emitting device LED and a driving circuit. The driving circuit is composed of a pulse width modulation module PWM and a pulse amplitude modulation module PAM.

[0079] The pulse width modulation module PWM includes first to tenth transistors (T1-T10), a first capacitor C1 and a second capacitor C2. The pulse amplitude modulation module PAM includes eleventh to fourteenth transistors (T11-T14). All transistors are P-type transistors.

[0080] The gate of the first transistor T1 is electrically connected to the first scan signal input terminal S(n+1), one of the source and the drain of the first transistor T1 is electrically connected to the first node A, and the other of the source and the drain of the first transistor T1 is electrically connected to the third node C. One plate of the first capacitor C1 is electrically connected to the first node A, and the other plate is electrically connected to the third node C. The gate of the second transistor T2 is electrically connected to the light emitting signal input terminal EM(n), the source is electrically connected to the ramp signal input terminal Sweep, and the drain is electrically connected to the first node A. The gate of the third transistor T3 is electrically connected to the first reset signal input terminal RST2, the source is electrically connected to the reference signal input terminal Vref, and the drain is electrically connected to the third node C. The gate of the fourth transistor T4 is electrically connected to the second scan signal input terminal S(n), the source is electrically connected to the first power signal input terminal Vdd, and the drain is electrically connected to the first node A. The gate of the fifth transistor T5 is electrically connected to the second scan signal input terminal S(n), the source is electrically connected to the first power signal input terminal Vdd, and the drain is electrically connected to the third node C. The gate of the sixth transistor T6 is electrically connected to the second scan signal input terminal S(n), and the source is electrically connected to the first data signal input terminal Data_PWM. The gate of the seventh transistor T7 is electrically connected to the light emitting signal input terminal EM(n), the source is electrically connected to the first power signal input terminal Vdd, and the drain is electrically connected to the drain of the sixth transistor T6. The gate of the eighth transistor T8 is electrically connected to the second node B, and the source is electrically connected to the drain of the sixth transistor T6. The gate of the ninth transistor T9 is electrically connected to the second scan signal input terminal S(n), the source is electrically connected to the second node B, and the drain is electrically connected to the drain of the eighth transistor T8. The gate of the tenth transistor T10 is electrically connected to the light emitting signal input terminal EM(n), and the source is electrically connected to the drain of the eighth transistor T8. The gate of the eleventh transistor T11 is electrically connected to the second scan signal input terminal S(n), the source is electrically connected to the second data signal input terminal Data_PAM, and the drain is electrically connected to the drain of the tenth transistor T10. The gate of the twelfth transistor T12 is electrically connected to the drain of the tenth transistor T10. The gate of the fourteenth transistor T14 is electrically connected to the second reset signal input terminal RST1, the source is electrically connected to the first power signal input terminal Vdd, and the drain is electrically connected to one of the source and the drain of the twelfth transistor T12. The other of the source and the drain of the twelfth transistor T12 is electrically connected to the source of the thirteenth transistor T13. The gate of the thirteenth transistor T13 is electrically connected to the light emitting signal input terminal EM(n), and the drain is electrically connected to the anode of the light emitting device LED. The cathode of the light emitting device LED is electrically connected to the second power signal input terminal Vss.

[0081] like Figure 3 As shown, the working process of the display device and the driving method thereof provided by the present application can be divided into six time periods: First time period ①: A frame begins, and each signal is initialized. At this stage, the second reset signal RST1, the first reset signal RST2, the second scan signal S(n) and the first scan signal S(n+1) are all high-level signals, the light-emitting control signal EM(n) is a low-level signal, and the voltage Vsweep of the ramp signal Sweep is the maximum value SW(H). At this time, the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off, and the second transistor T2 is turned on. The third node C and the second node B are floating, and the voltage of the first node A is equal to Vsweep. At this time, the value of Vsweep is raised to the highest point SW(H), the potential of the third node C is self-boosted to the highest point SW(H), and the potential of the second node B is self-boosted to (V(data_pwm)+Vth)-Vdd+Vsw(t1)+SW(H). t1 is the moment before the end of the previous frame.

[0082] Second time period ②: reset the voltage of the second node B. In this stage, the second reset signal RST1 is a high level signal, the first reset signal RST2 is a low level signal, the second scan signal S(n) and the first scan signal S(n+1) are both high level signals, the light emitting control signal EM(n) is a low level signal, and the voltage of the ramp signal Sweep is the maximum value SW(H). At this time, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned off, the second transistor T2 and the third transistor T3 are turned on, and the third node C is pulled down from SW(H) to Vref, and Vref is set to 0V. Since the first node A and the third node C are both stable voltage signals, the second node B will be coupled by the third node C and pulled down to 0V, and the voltage Vb of the second node B=(V(data_pwm)+Vth)-Vdd+Vsw(t1)+SW(H)-SW(H). It can be found that the voltage Vb of the second node B is equal to the potential at time t1 before the end of the previous frame.

[0083] The third time period ③: prepare for data writing. At this stage, the second reset signal RST1 is a low level signal, the first reset signal RST2 is a high level signal, the second scan signal S(n) and the first scan signal S(n+1) are both high level signals, the light control signal EM(n) is a low level signal, and the voltage of the ramp signal Sweep decreases linearly. The third transistor T3 is turned off, and the voltage Vb of the second node B is only affected by the pull-down of the first node A. Continue until the total time T required for light emission, and then turn off the light emission until the data of this row is written.

[0084] Fourth time period ④: Data writing. In this stage, the second reset signal RST1 is a low level signal, the first reset signal RST2 is a high level signal, the second scan signal S(n) is a low level signal, the first scan signal S(n+1) is a high level signal, the light emitting control signal EM(n) is a high level signal, and the voltage of the ramp signal Sweep decreases linearly. At this time, the fourth transistor T4 and the fifth transistor T5 are turned on, and Vdd is written into the first node A and the third node C at the same time to stabilize the voltage.

[0085] Fifth time period ⑤: The pixels in the Nth row emit light. In this stage, the second reset signal RST1 is a low-level signal, the first reset signal RST2 is a high-level signal, the second scan signal S(n) is a high-level signal, the first scan signal S(n+1) is a low-level signal, the light-emitting control signal EM(n) is a low-level signal, and the voltage of the ramp signal Sweep decreases linearly. At this time, the first transistor T1 and the second transistor T2 are turned on, and the first node A and the third node C are simultaneously written with the potential Vsweep of the ramp signal Sweep, and begin to emit light.

[0086] The sixth time period ⑥: complete a cycle and prepare for the next frame. At this stage, the second reset signal RST1 is a low level signal, the first reset signal RST2 is a high level signal, the second scan signal S(n) and the first scan signal S(n+1) are both high level signals, the light emitting control signal EM(n) is a low level signal, and the voltage of the ramp signal Sweep decreases linearly. At the end of the sixth time period, the voltage of the ramp signal Sweep is the minimum value and then jumps to the maximum value.

[0087] It should be noted that in the first time period and the second time period, since the fourteenth transistor T14 is turned off, the pixel units of all rows of the micro light emitting diode display panel do not emit light. This design can effectively prevent unnecessary light emission during the initialization and reset stages.

[0088] In the present application, the ramp signal Sweep, the first reset signal RST2 and the second reset signal RST1 are all global signals, that is, their output ends are electrically connected to all pixel units of the display panel. This design greatly simplifies the circuit structure and improves system efficiency.

[0089] Furthermore, the present application provides a pulse amplitude modulation module PAM in a display device, which also includes a third capacitor C3.

[0090] The pulse width modulation module PWM further includes a fifteenth transistor T15, a sixteenth transistor T16 and a fourth capacitor C4.

[0091] Among them, the gate of the fifteenth transistor T15 is electrically connected to the first scan signal input terminal S(n+1), one of the source and the drain is electrically connected to the second power signal input terminal Vss, and the other of the source and the drain is electrically connected to the fifth node E.

[0092] The gate of the first transistor T1 is electrically connected to the fifth node E.

[0093] The gate of the sixteenth transistor T16 is electrically connected to the first reset signal input terminal RST2, one of the source and the drain is electrically connected to the first power signal input terminal Vdd or the third reset signal input terminal VINT, and the other of the source and the drain is electrically connected to the fifth node E.

[0094] One plate of the third capacitor C3 is electrically connected to the fourth node D, and the other plate is electrically connected to the first power signal input terminal Vdd.

[0095] One plate of the fourth capacitor C4 is electrically connected to the second power signal input terminal Vss, and the other plate is electrically connected to the fifth node E.

[0096] The above technical solution can make the driving circuit of the pixel unit of the display device provided in the present application more stable under high-frequency driving, especially more stable in the potential control of the fifth node E, so as to better control the switching state of the first transistor T1 and improve the reliability and performance of the entire driving circuit.

[0097] Example 2 like Figure 4 As shown, Example 2 is similar to Example 1, except that: A fifteenth transistor T15, a sixteenth transistor T16 and a fourth capacitor C4 are added to the pulse width modulation module PWM, and a third capacitor C3 is added to the pulse amplitude modulation module PAM to stabilize the potential of the fifth node E and improve the reliability of the twelfth transistor T12.

[0098] The gate of the fifteenth transistor T15 is electrically connected to the first scan signal input terminal S(n+1), one of the source and the drain is electrically connected to the second power signal input terminal Vss, and the other of the source and the drain is electrically connected to the fifth node E. The gate of the first transistor T1 is not electrically connected to the first scan signal input terminal S(n+1), but is electrically connected to the fifth node E. The gate of the sixteenth transistor T16 is electrically connected to the first reset signal input terminal RST2, the source is electrically connected to the first power signal input terminal Vdd or the third reset signal input terminal VINT, and the drain is electrically connected to the fifth node E. One plate of the third capacitor C3 is electrically connected to the fourth node D, and the other plate is electrically connected to the first power signal input terminal Vdd. The fourth node D is connected to the gate point of the twelfth transistor T12. One plate of the fourth capacitor C4 is electrically connected to the second power signal input terminal Vss, and the other plate is electrically connected to the fifth node E.

[0099] The principle of Example 2 can be referred to Table 1.

[0100] Table 1

[0101] Embodiment 2 not only maintains the advantages of the global ramp signal in Embodiment 1, but also further improves the stability and reliability of the driving circuit, especially the performance under high-frequency driving and complex display scenarios.

[0102] In the display device and the driving method thereof provided by the present application, a capacitor is added on the basis of the bootstrap capacitor, and the charging and discharging of the capacitor is controlled by a thin film transistor switch, so that the voltage of the key control node is not affected by the potential of the ramp signal of the next frame. This technical solution enables each row of pixel units to completely compare the data signal and the ramp signal within the driving cycle of a frame, thereby significantly improving the accuracy of the display. Specifically, the display device and the driving method thereof provided by the present application allow the ramp signal to be reset at the beginning of each frame, ensuring that each row of pixels has the same comparison time.

[0103] In addition, the display device and the driving method thereof provided by the present application adopt a global ramp signal control scheme, which greatly simplifies the circuit structure of the pixel unit. Unlike the traditional technology that requires a ramp signal to be provided separately for each row of pixels, the display device and the driving method thereof provided by the present application only need a global ramp signal to control all rows of pixels, reducing the number of signal lines, which is conducive to realizing a narrow frame of the display device. This design not only simplifies the circuit structure, but also significantly reduces the instantaneous current of the panel and improves energy efficiency.

[0104] In addition, by applying a global ramp signal, progressive light emission is achieved. Combined with the timing control of the display device and the driving method provided by the present application, the optional range of duty is greatly expanded to 5%~99%. This greatly enhances the applicability of the display device in various scenarios, especially in low grayscale (such as night mode or dark scene display) and high grayscale (such as outdoor display in bright environment) display scenes. It can perform well, so that the display device of the present invention can provide a high-quality visual experience under different ambient light conditions.

[0105] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: include: A display panel, the display panel comprising a plurality of pixel units (PX), the plurality of pixel units (PX) being arranged in rows and columns; as well as A control circuit is electrically connected to the plurality of pixel units (PX), and is used to generate a ramp signal (Sweep) and output the ramp signal (Sweep) to the plurality of pixel units (PX); Wherein, the pixel unit (PX) comprises a light emitting device (LED) and a driving circuit, the driving circuit is electrically connected to the light emitting device (LED), and the driving circuit comprises a pulse width modulation module (PWM); The pulse width modulation module (PWM) includes a first capacitor (C1), a second capacitor (C2), a first transistor (T1), a second transistor (T2) and a third transistor (T3); wherein one plate of the first capacitor (C1) is electrically connected to the first node (A), and the other plate is electrically connected to the third node (C); One plate of the second capacitor (C2) is electrically connected to the third node (C), and the other plate is electrically connected to the second node (B); The gate of the first transistor (T1) is electrically connected to the first scan signal input terminal S(n+1), one of the source and the drain is electrically connected to the first node (A), and the other of the source and the drain is electrically connected to the third node (C); The gate of the second transistor (T2) is electrically connected to the light emitting signal input terminal (EM(n)), one of the source and the drain is electrically connected to the ramp signal input terminal (Sweep), and the other of the source and the drain is electrically connected to the first node (A); The gate of the third transistor (T3) is electrically connected to the first reset signal input terminal (RST2), one of the source and the drain is electrically connected to the reference signal input terminal (Vref), and the other of the source and the drain is electrically connected to the third node (C).

2. The display device according to claim 1, characterized in that The third transistor (T3) is used for pulling down the third node (C) by an amplitude Vsweep of the ramp signal (Sweep) when a low level signal is input to the first reset signal input terminal (RST2).

3. The display device according to claim 1, characterized in that The pulse width modulation module (PWM) also includes: a fourth transistor (T4), wherein a gate of the fourth transistor (T4) is electrically connected to the second scan signal input terminal S(n), one of a source and a drain is electrically connected to the first power signal input terminal (Vdd), and the other of the source and the drain is electrically connected to the first node (A); A fifth transistor (T5), wherein a gate of the fifth transistor (T5) is electrically connected to the second scan signal input terminal S(n), one of a source and a drain is electrically connected to the first power signal input terminal (Vdd), and the other of a source and a drain is electrically connected to the third node (C).

4. The display device according to claim 1, characterized in that The pulse width modulation module (PWM) also includes: a sixth transistor (T6), wherein a gate of the sixth transistor (T6) is electrically connected to the second scan signal input terminal S(n), and one of a source and a drain is electrically connected to the first data signal input terminal (Data_PWM); a seventh transistor (T7), wherein a gate of the seventh transistor (T7) is electrically connected to the light emitting signal input terminal (EM(n)), one of a source and a drain is electrically connected to the first power signal input terminal (Vdd), and the other of the source and the drain is electrically connected to the other of the source and the drain of the sixth transistor (T6); an eighth transistor (T8), wherein a gate of the eighth transistor (T8) is electrically connected to the second node (B), and one of a source and a drain is electrically connected to the other of the source and the drain of the sixth transistor (T6); a ninth transistor (T9), wherein a gate of the ninth transistor (T9) is electrically connected to the second scan signal input terminal S(n), one of a source and a drain is electrically connected to the second node (B), and the other of the source and the drain is electrically connected to the other of the source and the drain of the eighth transistor (T8); A tenth transistor (T10), wherein a gate of the tenth transistor (T10) is electrically connected to the light emitting signal input terminal (EM(n)), and one of a source and a drain is electrically connected to the other of a source and a drain of the eighth transistor (T8).

5. The display device according to claim 1, characterized in that: The driving circuit further includes a pulse amplitude modulation module (PAM), and the pulse amplitude modulation module (PAM) includes: an eleventh transistor (T11), wherein a gate of the eleventh transistor (T11) is electrically connected to the second scan signal input terminal S(n), one of a source and a drain is electrically connected to the second data signal input terminal (Data_PAM), and the other of the source and the drain is electrically connected to the fourth node (D); a twelfth transistor (T12), a gate of the twelfth transistor (T12) being electrically connected to the fourth node (D); a thirteenth transistor (T13), wherein a gate of the thirteenth transistor (T13) is electrically connected to the light emitting signal input terminal (EM(n)), one of a source and a drain is electrically connected to one of a source and a drain of the twelfth transistor (T12), and the other of the source and the drain is electrically connected to an anode of the light emitting device (LED); A fourteenth transistor (T14), wherein a gate of the fourteenth transistor (T14) is electrically connected to the second reset signal input terminal (RST1), one of the source and the drain is electrically connected to the first power signal input terminal (Vdd), and the other of the source and the drain is electrically connected to the other of the source and the drain of the twelfth transistor (T12).

6. The display device according to claim 5, characterized in that: The pulse amplitude modulation module (PAM) further comprises a third capacitor (C3); The pulse width modulation module (PWM) further includes a fifteenth transistor (T15), a sixteenth transistor (T16) and a fourth capacitor (C4); The gate of the fifteenth transistor (T15) is electrically connected to the first scan signal input terminal S(n+1), one of the source and the drain is electrically connected to the second power signal input terminal (Vss), and the other of the source and the drain is electrically connected to the fifth node (E); The gate of the first transistor (T1) is electrically connected to the fifth node (E); The gate of the sixteenth transistor (T16) is electrically connected to the first reset signal input terminal (RST2), one of the source and the drain is electrically connected to the first power signal input terminal (Vdd) or the third reset signal input terminal (VINT), and the other of the source and the drain is electrically connected to the fifth node (E); One plate of the third capacitor (C3) is electrically connected to the fourth node (D), and the other plate is electrically connected to the first power signal input terminal (Vdd); One plate of the fourth capacitor (C4) is electrically connected to the second power signal input terminal (Vss), and the other plate is electrically connected to the fifth node (E).

7. The display device according to claim 1, characterized in that The control circuit is further configured to generate a second reset signal (RST1) and a first reset signal (RST2), and input the second reset signal (RST1) and the first reset signal (RST2) to the plurality of pixel units (PX).

8. The display device according to claim 1, characterized in that: The driving cycle of a frame of picture displayed by the display device includes a first time period, a second time period, a third time period, a fourth time period, a fifth time period and a sixth time period; In the first time period, the second reset signal (RST1), the first reset signal (RST2), the second scan signal S(n) and the first scan signal S(n+1) are all high-level signals, the light-emitting control signal EM(n) is a low-level signal, and the ramp signal (Sweep) is a high-level signal; In the second time period, the second reset signal (RST1), the second scan signal S(n) and the first scan signal S(n+1) are all high-level signals, the first reset signal (RST2) and the light-emitting control signal EM(n) are all low-level signals, and the ramp signal (Sweep) is a high-level signal; In the third time period, the first reset signal (RST2), the second scan signal S(n) and the first scan signal S(n+1) are all high-level signals, the second reset signal (RST1) and the light-emitting control signal EM(n) are all low-level signals, and the voltage of the ramp signal (Sweep) decreases linearly; In the fourth time period, the second reset signal (RST1) and the second scan signal S(n) are both low-level signals, the first reset signal (RST2), the first scan signal S(n+1) and the light-emitting control signal EM(n) are all high-level signals, and the voltage of the ramp signal (Sweep) decreases linearly; In the fifth time period, the first reset signal (RST2) and the second scan signal S(n) are both high-level signals, the second reset signal (RST1), the first scan signal S(n+1) and the light-emitting control signal EM(n) are all low-level signals, and the voltage of the ramp signal (Sweep) decreases linearly; In the sixth time period, the first reset signal (RST2), the second scan signal S(n) and the first scan signal S(n+1) are all high-level signals, the second reset signal (RST1) and the light-emitting control signal EM(n) are all low-level signals, the voltage of the ramp signal (Sweep) decreases linearly, and at the end of the sixth time period, the ramp signal (Sweep) is a low-level signal.

9. A method for driving a display device, characterized in that: The following steps are involved: Generate a ramp signal (Sweep), and output the ramp signal (Sweep) to a plurality of pixel units (PX); In a first time period, the first transistor (T1) is controlled to be turned on or off, the second transistor (T2) is turned on, the third transistor (T3) is turned off, and the voltage of the first node (A) is equal to the voltage Vsweep of the ramp signal (Sweep); In a second time period, the first transistor (T1) is controlled to be turned off, the second transistor (T2) and the third transistor (T3) are turned on, the voltage of the third node (C) is pulled down from the maximum value SW (H) of the voltage of the ramp signal (Sweep) to 0V, and the voltage of the second node (B) is reset under the coupling effect of the second capacitor (C2); In a third time period, the first transistor (T1) and the third transistor (T3) are controlled to be turned off, the second transistor (T2) is turned on, and the voltage of the second node (B) decreases as the voltage of the first node (A) decreases; In a fourth time period, the first transistor (T1), the second transistor (T2) and the third transistor (T3) are controlled to be turned off, the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6) and the ninth transistor (T9) are turned on, the data signal of the first data signal input terminal (Data_PWM) is written to the second node (B), and the voltage of the first power signal input terminal (Vdd) is written to the first node (A) and the third node (C); In a fifth time period, the first transistor (T1) and the second transistor (T2) are controlled to be turned on, the third transistor (T3) is turned off, the voltage Vsweep of the ramp signal (Sweep) is written to the first node (A) and the third node (C), and the eighth transistor (T8) controls the light-emitting time of the light-emitting device (LED) according to the comparison result between the first data signal (Data_PWM) written to the second node (B) and the ramp signal (Sweep); In a sixth time period, the first transistor (T1) is controlled to be turned on or off, the second transistor (T2) is turned on, and the third transistor (T3) is turned off.

10. The driving method according to claim 9, characterized in that: In the first time period, the first reset signal (RST2), the second reset signal (RST1), the second scan signal S(n) and the first scan signal S(n+1) are all at high levels, the light emitting control signal EM(n) is at a low level, and the ramp signal (Sweep) is at a high level; In the second time period, the second reset signal (RST1), the second scan signal S(n) and the first scan signal S(n+1) are all at high levels, the first reset signal (RST2) and the light emitting control signal EM(n) are all at low levels, and the ramp signal (Sweep) is at a high level; In the third time period, the second reset signal (RST1) and the light emitting control signal EM(n) are both at low levels, the first reset signal (RST2), the second scanning signal S(n) and the first scanning signal S(n+1) are all at high levels, and the voltage of the ramp signal (Sweep) decreases linearly; In the fourth time period, the second reset signal (RST1) and the second scan signal S(n) are both at low levels, the first reset signal (RST2), the first scan signal S(n+1) and the light emitting control signal EM(n) are all at high levels, and the voltage of the ramp signal (Sweep) decreases linearly; In the fifth time period, the first reset signal (RST2) and the second scan signal S(n) are both at high levels, the second reset signal (RST1), the first scan signal S(n+1) and the light emitting control signal EM(n) are all at low levels, and the voltage of the ramp signal (Sweep) decreases linearly; In the sixth time period, the first reset signal (RST2), the second scan signal S(n) and the first scan signal S(n+1) are all at a high level, the second reset signal (RST1) and the light emitting control signal EM(n) are at a low level, the voltage of the ramp signal (Sweep) decreases linearly, and at the end of the sixth time period, the ramp signal (Sweep) is at a low level.

11. The driving method according to claim 9, characterized in that: At the end of the second time period, the voltage Vb of the second node (B) satisfies: Vb = V(data_pwm) + Vth - Vdd + Vsw(t1) Among them, V(data_pwm) is the voltage of the first data signal input terminal (Data_PWM), Vth is the threshold voltage of the eighth transistor (T8), Vdd is the voltage of the first power signal input terminal (Vdd), and Vsw(t1) is the voltage value of the ramp signal (Sweep) corresponding to the time t1 of the previous frame of light emission.

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