Scanning driving circuit, display panel, driving method of display panel and display device

Abstract

The embodiment of the invention provides a scanning driving circuit, a display panel, a driving method of the display panel and a display device. The scanning driving circuit comprises a driving signal generation module and a signal output control module, the driving signal generation module is respectively coupled with an input signal end, a clock signal end and a first output signal end, and the driving signal generation module is configured to provide a signal of the clock signal end for the first output signal end under the control of the input signal end; the signal output control module is respectively coupled with a trigger signal end, a first power supply end, a first output signal end and a second output signal end, the first output signal end provides a first signal for the second output signal end, and the signal output control module is configured to output a second signal to the second output signal end under the control of the trigger signal end. The first power supply end provides a second signal to the second output signal end to lower the first signal. According to the technical scheme, the output signal of the second output signal end of the scanning drive circuit can be controlled, row-by-row frequency division display in the same frame is achieved, and power consumption is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display devices, and in particular to a scan driving circuit, a display panel and a driving method thereof, and a display device. Background Art

[0002] Currently, the display panel operates at a set frequency, and the frequency of the display area of ​​the display panel is fixed within one frame, which will cause power consumption loss of the display panel. Summary of the invention

[0003] Embodiments of the present disclosure provide a scan driving circuit, a display panel and a driving method thereof, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a scan drive circuit, including a drive signal generating module and a signal output control module, the drive signal generating module is respectively coupled to an input signal terminal, a clock signal terminal and a first output signal terminal, and the drive signal generating module is configured to, under the control of the input signal terminal, provide a signal of the clock signal terminal to the first output signal terminal; the signal output control module is respectively coupled to a trigger signal terminal, a first power supply terminal, a first output signal terminal and a second output signal terminal, and the signal output control module is configured to, under the control of the trigger signal terminal, provide a signal of the first power supply terminal to the second output signal terminal to control the voltage of the signal of the first output signal terminal, or provide a signal of the first output signal terminal to the second output signal terminal.

[0005] In some possible embodiments, the signal output control module includes a first control transistor and a second control transistor, the gate of the first control transistor is coupled to the first output signal terminal, the first electrode of the first control transistor is coupled to the first output signal terminal, the second electrode of the second control transistor is coupled to the first power supply terminal, the gate of the second control transistor is coupled to the trigger signal terminal, the second output signal terminal is coupled to the second electrode of the first control transistor, and the second output signal terminal is coupled to the first electrode of the second control transistor.

[0006] In some possible implementations, the second signal is a constant voltage signal, and the first signal is a pulse signal.

[0007] In some possible implementations, the driving signal generating module includes a pull-up module, an output module, a first reset module, a pull-down module, a noise reduction module, a second reset module, a reset control module, and a third reset module;

[0008] A pull-up module, coupled to the input signal terminal, the second power terminal and the pull-up node respectively, and configured to provide the pull-up node with a signal of the second power terminal under the control of the input signal terminal;

[0009] An output module, coupled to the clock signal terminal, the pull-up node and the first output signal terminal respectively, and configured to provide a signal of the clock signal terminal to the first output signal terminal under the control of the pull-up node;

[0010] The first reset module is coupled to the reset signal terminal, the third power terminal and the pull-up node respectively, and is configured to provide a signal of the third power terminal to the pull-up node under the control of the reset signal terminal.

[0011] A pull-down module, coupled to the fourth power supply terminal, the pull-up node and the control node respectively, and configured to provide the signal of the fourth power supply terminal to the pull-down node and the control node under the control of the pull-up node;

[0012] A noise reduction module is coupled to the first control power supply terminal, the control node and the pull-down node respectively, and is configured to provide a signal of the first control power supply terminal to the control node under the control of the first control power supply terminal, and to provide a signal of the first control power supply terminal to the pull-down node under the control of the control node;

[0013] A second reset module is coupled to the pull-down node, the fourth power supply terminal and the first output signal terminal respectively, and is configured to provide a signal of the fourth power supply terminal to the first output signal terminal under the control of the pull-down node;

[0014] A reset control module, coupled to the pull-down node, the fourth power supply terminal and the pull-up node respectively, and configured to provide a signal of the fourth power supply terminal to the pull-up node under the control of the pull-down node;

[0015] The frame reset module is coupled to the fourth power supply terminal, the first output signal terminal and the second control power supply terminal respectively, and is configured to provide a signal of the fourth power supply terminal to the first output signal terminal under the control of the second control power supply terminal.

[0016] In some possible implementations, at least one of the following is included:

[0017] The pull-up module includes a first transistor, a gate of the first transistor is coupled to the input signal terminal, a first electrode of the first transistor is coupled to the second power supply terminal, and a second electrode of the first transistor is coupled to the pull-up node;

[0018] The output module includes a third transistor and a storage capacitor, the gate of the third transistor is coupled to the pull-up node, the first electrode of the third transistor is coupled to the clock signal terminal, the second electrode of the third transistor is coupled to the first output signal terminal, the first plate of the storage capacitor is coupled to the pull-up node, and the second plate of the storage capacitor is coupled to the first output signal terminal;

[0019] The first reset module includes a second transistor, a gate of the second transistor is coupled to the reset signal terminal, a first electrode of the second transistor is coupled to the third power supply terminal, and a second electrode of the second transistor is coupled to the pull-up node;

[0020] The pull-down module includes a sixth transistor and an eighth transistor, the gate of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the pull-down node, the second electrode of the sixth transistor is coupled to the fourth power supply terminal, the gate of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor is coupled to the control node, and the second electrode of the eighth transistor is coupled to the fourth power supply terminal;

[0021] The noise reduction module includes a fifth transistor and a ninth transistor, the gate of the ninth transistor is coupled to the first control power supply terminal, the first electrode of the ninth transistor is respectively coupled to the first control power supply terminal, the second electrode of the ninth transistor is coupled to the control node, the gate of the fifth transistor is coupled to the control node, the first electrode of the fifth transistor is coupled to the first control power supply terminal, and the second electrode of the fifth transistor is coupled to the pull-down node;

[0022] The second reset module includes an eleventh transistor, a gate of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the fourth power supply terminal, and a second electrode of the eleventh transistor is coupled to the first output signal terminal;

[0023] The reset control module includes a tenth transistor, a gate of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the fourth power supply terminal, and a second electrode of the tenth transistor is coupled to the pull-up node;

[0024] The frame reset module includes a seventh transistor, a gate of the seventh transistor is coupled to the second control power supply terminal, a first electrode of the seventh transistor is coupled to the fourth power supply terminal, and a second electrode of the seventh transistor is coupled to the first output signal terminal.

[0025] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including a gate signal generating module, including a plurality of cascaded gate driving circuits, and the gate driving circuit is a scanning driving circuit of any disclosed embodiment of the present disclosure.

[0026] In some possible embodiments, the display panel includes a first display area and a second display area, the first display area includes N gate lines, the N gate lines are correspondingly connected to N gate driving circuits, the second display area includes M gate lines, the M gate lines are correspondingly connected to M gate driving circuits, M and N are positive integers greater than 0, the voltage value of the signal of the gate driving circuit corresponding to the first display area is a first voltage, the voltage value of the signal of the gate driving circuit corresponding to the second display area is a second voltage, and the first voltage is less than the second voltage.

[0027] In some possible implementations, the display panel further includes a data chip, which transmits data signals to corresponding rows of the second display area when the data chip is turned on, and transmits data signals to corresponding rows of the first display area when the data chip is turned off.

[0028] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for driving a display panel, which is applied to the display panel of any embodiment of the present disclosure, and the method includes:

[0029] The trigger signal terminal provides a trigger signal to control the first output signal terminal to provide a signal to the second output signal terminal, or controls the first power supply terminal to provide a signal to the second output signal terminal to control the voltage of the signal at the first output signal terminal.

[0030] In some possible implementations, the method further includes:

[0031] The trigger signal terminal of the gate driving circuit corresponding to the first display area provides a first trigger signal, and controls the first power supply terminal to provide a signal to the second output signal terminal to control the voltage of the signal at the first output signal terminal;

[0032] The trigger signal terminal of the gate driving circuit corresponding to the second display area provides a second trigger signal to control the first output signal terminal to provide a signal to the second output signal terminal.

[0033] In some possible implementations, the method further includes:

[0034] The data chip controls the data signal to be transmitted to the corresponding row of the second display area, and the data chip controls the data signal to stop being transmitted to the corresponding row of the first display area.

[0035] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, comprising the display panel of any embodiment of the present disclosure.

[0036] The technical solution of the embodiment of the present disclosure can achieve the following beneficial effects: the output signal of the second output signal terminal of the scan driving circuit can be controlled to achieve line-by-line and frequency-by-frequency display within the same frame, thereby reducing power consumption.

[0037] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0039] Figure 1 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present disclosure;

[0040] Figure 2 is a schematic diagram of the structure of a scan driving circuit according to an embodiment of the present disclosure;

[0041] Figure 3 is a schematic diagram of a scan driving circuit according to an embodiment of the present disclosure;

[0042] Figure 4 This is a timing diagram of a driving signal generating module according to an embodiment of the present disclosure;

[0043] Figure 5 A schematic diagram of a gate signal generating module according to an embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of a display area of ​​a display panel according to an embodiment of the present disclosure;

[0045] Figure 7 4 is a timing diagram of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0047] The transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source (source electrode) is called the first pole, and the drain (drain electrode) is called the second pole, or the drain can be called the first pole and the source is the second pole. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain.

[0048] The switching transistor used in the embodiments of the present disclosure may be a P-type switching transistor or an N-type switching transistor. The P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level. The N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in various embodiments of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential state quantities of the signal, and do not represent that the first potential or the second potential in the full text has a specific value. The embodiments of the present disclosure are described by taking the first potential as an effective potential as an example.

[0049] The coupling may include: direct physical contact between the two ends or indirect connection between the two ends (such as connection between the two ends via a signal line). The embodiment of the present disclosure does not limit the coupling method between the two ends.

[0050] At present, the display panel uses a high frequency to ensure the image quality for dynamic images, and a low frequency to reduce power consumption for static images or slow dynamic images. In this way, the power consumption of the display panel can be reduced by switching the frequency between different frames. Since the gate drive circuit of the display panel outputs line by line, the frequency and duty cycle of the output signal are determined by the clock signal and cannot be adjusted within a frame. Therefore, when a frame of display includes a static display area and a dynamic display area, since the display panel of the related art cannot allocate different frequencies according to different rows within a frame, this results in the need to use high frequencies for both the static display area and the dynamic display area, resulting in power consumption loss of the display panel. It should be noted that the static display area is a static picture or a slow dynamic picture, and the dynamic display area is a dynamic picture.

[0051] In order to solve the power consumption loss problem in the related art, an embodiment of the present disclosure provides a scan driving circuit. The technical solution of the present disclosure is described in detail below through embodiments.

[0052] Figure 1 FIG. 1 is a schematic diagram of the structure of the scan driving circuit of an embodiment of the present disclosure. Figure 1 As shown, the scan driving circuit of the embodiment of the present disclosure may include a driving signal generating module 10 and a signal output control module 20 .

[0053] In one embodiment, Figure 1 As shown, the driving signal generating module 10 is coupled to the input signal terminal INPUT, the clock signal terminal CLK and the first output signal terminal OUTPUT_1 respectively. The driving signal generating module 10 is configured to provide the signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1 under the control of the input signal terminal INPUT.

[0054] In one embodiment, Figure 1 As shown, the signal output control module 20 is coupled to the trigger signal terminal Vf, the first power supply terminal VGL_1, the first output signal terminal OUTPUT_1 and the second output signal terminal OUTPUT_2 respectively, and the first output signal terminal OUTPUT_1 provides a first signal to the second output signal terminal OUTPUT_2. The signal output control module 20 is configured such that under the control of the trigger signal terminal Vf, the first power supply terminal VGL_1 provides a second signal to the second output signal terminal OUTPUT_2 to pull down the first signal.

[0055] It should be noted that, in the display panel, the second output signal terminal OUTPUT_2 of the scan driving circuit may be connected to the gate line of the display panel so as to provide a gate driving signal to the gate line.

[0056] In the scan driving circuit of the embodiment of the present disclosure, under the control of the trigger signal terminal Vf, the first power terminal VGL_1 provides a second signal to the second output signal terminal OUTPUT_2, and the second signal can adjust the output of the first output signal terminal OUTPUT_1 to the first signal of the second output signal terminal OUTPUT_2. In this way, the scan driving circuit can be controlled to output the signal of the first output signal terminal OUTPUT_1 adjusted by the first power terminal VGL_1 according to the display screen requirements of the display area of ​​the display panel, so that different display areas within a frame of the picture provide different drive signals to the second output signal terminal.

[0057] The scanning driving circuit of the embodiment of the present disclosure is applied to the display panel, and can provide different driving signals to the dynamic display area and the static display area respectively within one frame of the display panel, thereby reducing the power consumption of the static display area in the related technology and further reducing the power consumption of the display panel.

[0058] Exemplarily, the signal of the first power supply terminal VGL_1 is a low-level signal. Under the control of the trigger signal terminal Vf, the first power supply terminal VGL_1 provides the second signal as a low-level signal to the second output signal terminal OUTPUT_2. The second signal can pull down the level of the first output signal terminal OUTPUT_1 to the second output signal terminal OUTPUT_2. The trigger signal terminal Vf controls the first power supply terminal VGL_1 not to provide the second signal to the second output signal terminal OUTPUT_2, and the first output signal terminal OUTPUT_1 maintains normal output, so that the first power supply terminal VGL_1 can be controlled by the trigger signal terminal to pull down the level of the first output signal terminal OUTPUT_1 in the static display area, and the first output signal terminal OUTPUT_1 can be normally output to the second output signal terminal OUTPUT_2 in the dynamic display area, thereby reducing power consumption.

[0059] Figure 2 is a schematic diagram of the structure of a scan driving circuit according to an embodiment of the present disclosure, Figure 3 FIG. 1 is a schematic diagram of a scan driving circuit according to an embodiment of the present disclosure. Figure 3As shown, the signal output control module 20 includes a first control transistor M12 and a second control transistor M13. The gate of the first control transistor M12 is coupled to the first output signal terminal OUTPUT_1, the first electrode of the first control transistor M12 is coupled to the first output signal terminal OUTPUT_1, and the second electrode of the first control transistor M12 is coupled to the second output signal terminal OUTPUT_2. The second electrode of the second control transistor M13 is coupled to the first power supply terminal VGL_1, the gate of the second control transistor M13 is coupled to the trigger signal terminal Vf, and the first electrode of the second control transistor M13 is coupled to the second output signal terminal OUTPUT_2.

[0060] The signal of the first output signal terminal OUTPUT_1 of the embodiment of the present disclosure is connected to the gate and the first electrode of the first control transistor M12. The signal of the first output signal terminal OUTPUT_1 is a pulse signal. When the signal of the first output signal terminal OUTPUT_1 is a first potential, the first control transistor M12 is turned on. When the signal of the first output signal terminal OUTPUT_1 is a second potential, the first control transistor M12 is turned off. When the trigger signal terminal Vf is a high-level signal, the second control transistor M13 is turned on, and the first power supply terminal VGL_1 provides the second signal to the second output signal terminal OUTPUT_2. When the trigger signal terminal Vf is a low-level signal, the second control transistor M13 is turned off, and the first power supply terminal VGL_1 does not provide the second signal to the second output signal terminal OUTPUT_2.

[0061] The first power supply terminal VGL_1 is a low-level signal. The trigger signal terminal Vf is a high-level signal, the second control transistor M13 is turned on, and the second signal can pull down the potential of the second output signal terminal OUTPUT_2, the gate of the transistor in the display area is at a low potential, the transistor is turned off, and the pixel enters the hold state. The trigger signal terminal Vf is a low-level signal, the second control transistor M13 is turned off, the second output signal terminal OUTPUT_2 maintains the normal potential of the first output signal terminal OUTPUT_1, and the display area displays normally.

[0062] Exemplarily, the first control transistor M12 may be a P-type switch transistor, and the second control transistor M13 may be an N-type switch transistor. Alternatively, the first control transistor M12 may be an N-type switch transistor, and the second control transistor M13 may be a P-type switch transistor. The first control transistor M12 and the second control transistor M13 may both be P-type switch transistors or N-type switch transistors.

[0063] Exemplarily, the second control transistor M13 is an N-type switch transistor. When the trigger signal terminal Vf is a high potential signal, the second control transistor M13 is turned on, and the second output signal terminal OUTPUT_2 is pulled down to the low level of the first power supply terminal VGL_1, so that the gate line corresponding to the display area of ​​the display panel is at a low level, and the display panel enters a hold state. When the trigger signal terminal Vf is a low level signal, the second control transistor M13 is turned off, and the second output signal terminal OUTPUT_2 normally outputs the signal of the first output signal terminal OUTPUT_1, and the display area is in a normal refreshable state.

[0064] In one embodiment, the signal of the first power supply terminal VGL_1 is a constant voltage signal, and the signal of the first output signal terminal OUTPUT_1 is a pulse signal. The second signal provided by the first power supply terminal VGL_1 to the second output signal terminal OUTPUT_2 is a constant voltage signal, and the signal transmitted from the first output signal terminal OUTPUT_1 to the second output signal terminal OUTPUT_2 is a pulse signal. The first power supply terminal VGL_1 can pull down the signal of the first output signal terminal OUTPUT_1, so as to realize frequency division and line division display of the static display area and the dynamic display area, thereby reducing power consumption.

[0065] Exemplarily, the signal of the first power supply terminal VGL_1 is a low-level signal. It should be noted that the voltage of the first output signal terminal OUTPUT_1 is a pulse voltage, the first output signal terminal OUTPUT_1 includes a first voltage signal and a second voltage signal, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, the signal of the first power supply terminal VGL_1 is a third voltage signal, the voltage value of the third voltage signal can be greater than or equal to the voltage value of the first voltage signal, the direction of the third voltage signal is opposite to the direction of the first voltage signal, and the specific voltage value of the signal of the first power supply terminal VGL_1 can be set according to actual needs. The first power supply terminal VGL_1 can pull down the level of the second output signal terminal, so that the gate of the corresponding display area is at a low level, so that the pixel enters a hold state, so that the display area can be kept in a static picture to reduce power consumption.

[0066] Reference Figure 2 In one implementation, the driving signal generating module 10 at least includes a pull-up module 11, an output module 12, a first reset module 13, a pull-down module 14, a noise reduction module 15, a second reset module 16, a reset control module 17 and a frame reset module 18.

[0067] In one embodiment, Figure 2 As shown, the pull-up module 11 is coupled to the input signal terminal INPUT, the second power terminal VDD and the pull-up node PU respectively. The pull-up module 11 is configured to provide a signal of the second power terminal VDD to the pull-up node PU under the control of the input signal terminal INPUT.

[0068] In one embodiment, Figure 2 As shown, the output module 12 is coupled to the clock signal terminal CLK, the pull-up node PU and the first output signal terminal OUTPUT_1 respectively. The output module 12 is configured to provide the signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1 under the control of the pull-up node PU.

[0069] In one embodiment, Figure 2 As shown, the first reset module 13 is coupled to the reset signal terminal RST, the third power terminal VSS and the pull-up node PU respectively. The first reset module 13 is configured to provide a signal of the third power terminal VSS to the pull-up node PU under the control of the reset signal terminal RST.

[0070] In one embodiment, Figure 2 As shown, the pull-down module 14 is coupled to the fourth power terminal VGL_2, the pull-up node PU and the control node PD_CN respectively. The pull-down module 14 is configured to provide the signal of the fourth power terminal VGL_2 to the pull-down node PD and the control node PD_CN under the control of the pull-up node PU;

[0071] In one embodiment, Figure 2 As shown, the noise reduction module 15 is coupled to the first control power supply terminal VGH, the control node PD_CN and the pull-down node PD respectively. The noise reduction module 15 is configured to provide a signal of the first control power supply terminal VGH to the control node PD_CN under the control of the first control power supply terminal VGH, and provide a signal of the first control power supply terminal VGH to the pull-down node PD under the control of the control node PD_CN;

[0072] In one embodiment, Figure 2 As shown, the second reset module 16 is coupled to the pull-down node PD, the fourth power terminal VGL_2 and the first output signal terminal OUTPUT_1 respectively. The second reset module 16 is configured to provide a signal of the fourth power terminal VGL_2 to the first output signal terminal OUTPUT_1 under the control of the pull-down node PD.

[0073] In one embodiment, Figure 2 As shown, the reset control module 17 is coupled to the pull-down node PD, the fourth power terminal VGL_2 and the pull-up node PU respectively. The reset control module 17 is configured to provide a signal of the fourth power terminal VGL_2 to the pull-up node PU under the control of the pull-down node PD.

[0074] In one embodiment, Figure 2As shown, the frame reset module 18 is coupled to the fourth power supply terminal VGL_2 and the first output signal terminal OUTPUT_1 respectively. The third reset module 18 is configured to provide a signal of the fourth power supply terminal VGL_2 to the first output signal terminal OUTPUT_1 under the control of the fourth power supply terminal VGL_2.

[0075] When the scan drive circuit of the disclosed embodiment is applied to a display panel, the second output signal terminal OUTPUT_2 can be connected to the gate line so as to provide a gate drive signal to the gate line. In a frame of picture, the scan drive circuit may include a driving stage and a reset stage. In the driving stage, the pull-up module 11, under the control of the input signal terminal INPUT, provides a signal of the second power supply terminal VDD to the pull-up node PU, at which time, the voltage of the pull-up stage PU is the same as the voltage of the second power supply terminal VDD. The output module 12, under the control of the pull-up node PU, provides a signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1. When the first output signal terminal OUTPUT_1 provides a signal to the second output signal terminal OUTPUT_2, the second output signal terminal OUTPUT_2 provides a gate signal to the gate line, driving the corresponding row pixel display. In the reset stage, the first reset module 13 provides the signal of the third power supply terminal VSS to the pull-up node PU under the control of the reset signal terminal RST. At this time, the voltage of the pull-up node PU is the same as the voltage of the third power supply terminal VSS, the output module 12 is turned off, the first output signal terminal OUTPUT_1 has no signal output, and the corresponding row of pixels is not displayed. The second power supply terminal VDD is a high-level signal, and the third power supply terminal VSS is a low-level signal. In the reset stage, the pull-up node PU maintains the signal of the third power supply terminal VSS.

[0076] In one embodiment, Figure 3 As shown, the pull-up module 11 may include a first transistor M1. The gate of the first transistor M1 is coupled to the input signal terminal INPUT, the first electrode of the first transistor M1 is coupled to the second power supply terminal VDD, and the second electrode of the first transistor M1 is coupled to the pull-up node PU. Thus, when the input signal terminal INPUT is a valid level signal, the first transistor M1, under the control of the valid level signal of the input signal terminal INPUT, provides a signal of the second power supply terminal VDD to the pull-up node PU, and pulls up the pull-up node PU.

[0077] In one embodiment, Figure 3As shown, the output module 12 may include a third transistor M3 and a storage capacitor C. The gate of the third transistor M3 is coupled to the pull-up node PU, the first electrode of the third transistor M3 is coupled to the clock signal terminal CLK, and the second electrode of the third transistor M3 is coupled to the first output signal terminal OUTPUT_1. The first plate of the storage capacitor C is coupled to the pull-up node PU, and the second plate of the storage capacitor C is coupled to the first output signal terminal OUTPUT_1. Thus, when the pull-up node PU is a valid level signal, the third transistor M3, under the control of the valid level signal of the pull-up node PU, provides the signal of the clock signal terminal CLK to the first output signal terminal OUTPUT_1, so that the first output signal terminal OUTPUT_1 outputs a driving signal.

[0078] In one implementation, the second power supply terminal VDD may be a high level signal, the third power supply terminal VSS may be a low level signal, the fourth power supply terminal VGL_2 may be a low level signal, and the first control power supply terminal VGH may be a high level signal.

[0079] It should be noted that, although the second power supply terminal VDD is a high-level signal and the first control power supply terminal VGH is a high-level signal, it does not mean that the voltage of the second power supply terminal VDD is the same as the voltage of the first control power supply terminal VGH. The voltage of the second power supply terminal VDD may be the same as or different from the voltage of the first control power supply terminal VGH, and the specific voltage value of the second power supply terminal VDD and the specific voltage value of the first control power supply terminal VGH can be set as needed. Similarly, although the fourth power supply terminal VGL_2 is a low-level signal and the third power supply terminal VSS is a low-level signal, it does not mean that the voltage of the fourth power supply terminal VGL_2 is the same as the voltage of the third power supply terminal VSS. The voltage of the fourth power supply terminal VGL_2 may be the same as or different from the voltage of the third power supply terminal VSS, and the specific voltage value of the fourth power supply terminal VGL_2 and the specific voltage value of the third power supply terminal VSS can be set as needed.

[0080] In one embodiment, Figure 3 As shown, the first reset module 13 may include a second transistor M2. The gate of the second transistor M2 is coupled to the reset signal terminal RST, the first electrode of the second transistor M2 is coupled to the third power supply terminal VSS, and the second electrode of the second transistor M2 is coupled to the pull-up node PU. Thus, when the reset signal terminal RST is an effective level signal, the second transistor M2, under the control of the effective level signal of the reset signal terminal RST, provides a signal of the third power supply terminal VSS to the pull-up node PU, so that the pull-up node PU is reset.

[0081] In one embodiment, Figure 3As shown, the pull-down module 14 may include a sixth transistor M6 and an eighth transistor M8. The gate of the sixth transistor M6 is coupled to the pull-up node PU, the first electrode of the sixth transistor M6 is coupled to the pull-down node PD, and the second electrode of the sixth transistor M6 is coupled to the fourth power supply terminal VGL_2. The gate of the eighth transistor M8 is coupled to the pull-up node PU, the first electrode of the eighth transistor M8 is coupled to the control node PD_CN, and the second electrode of the eighth transistor M8 is coupled to the fourth power supply terminal VGL_2. Thus, when the pull-up node PU is a valid level signal, the sixth transistor M6, under the control of the valid level signal of the pull-up node PU, provides the signal of the fourth power supply terminal VGL_2 to the pull-down node PD, and pulls down the pull-down node PD. The eighth transistor M8, under the control of the valid level signal of the pull-up node PU, provides the signal of the fourth power supply terminal VGL_2 to the control node PD_CN, and pulls down the control node PD_CN.

[0082] Exemplarily, the sixth transistor M6 and the eighth transistor M8 may be of the same type. For example, the sixth transistor M6 and the eighth transistor M8 may both be NMOS.

[0083] In one embodiment, Figure 3 As shown, the noise reduction module 15 includes a fifth transistor M5 and a ninth transistor M9. The gate of the ninth transistor M9 is coupled to the first control power supply terminal VGH, the first electrode of the ninth transistor M9 is respectively coupled to the first control power supply terminal VGH, and the second electrode of the ninth transistor M9 is coupled to the control node PD_CN. Thus, when the first control power supply terminal VGH is at an effective level, the ninth transistor M9 can provide a signal of the first control power supply terminal VGH to the control node PD_CN under the control of the effective level of the first control power supply terminal VGH.

[0084] The gate of the fifth transistor M5 is coupled to the control node PD_CN, the first electrode of the fifth transistor M5 is coupled to the first control power supply terminal VGH, and the second electrode of the fifth transistor M5 is coupled to the pull-down node PD. When the signal of the control node PD_CN is at an effective level, the fifth transistor M5 can provide the signal of the first control power supply terminal VGH to the pull-down node PD under the control of the effective level of the control node PD_CN.

[0085] Exemplarily, the fifth transistor M5 and the ninth transistor M9 may be of the same type. For example, the fifth transistor M5 and the ninth transistor M9 may both be NMOS. It should be noted that, Figure 3 The circuit structure of the noise reduction module 15 is exemplarily shown in FIG. 1 , but the noise reduction module 15 is not limited to the structure in the figure. The noise reduction module can adopt other circuits as long as the function of the noise reduction module 15 can be realized.

[0086] In one embodiment, Figure 3As shown, the second reset module 16 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first electrode of the eleventh transistor M11 is coupled to the fourth power supply terminal VGL_2, and the second electrode of the eleventh transistor M11 is coupled to the first output signal terminal OUTPUT_1. Therefore, when the pull-down node PD is a valid level signal, the eleventh transistor M11, under the control of the valid level signal of the pull-down node PD, provides the signal of the fourth power supply terminal VGL_2 to the first output signal terminal OUTPUT_1, so that the first output signal terminal OUTPUT_1 is reset, so that the first output signal terminal OUTPUT_1 has no signal output.

[0087] In one embodiment, Figure 3 As shown, the reset control module 17 includes a tenth transistor M10. The gate of the tenth transistor M10 is coupled to the pull-down node PD, the first electrode of the tenth transistor M10 is coupled to the fourth power supply terminal VGL_2, and the second electrode of the tenth transistor M10 is coupled to the pull-up node PU. Therefore, when the pull-down node PD is a valid level signal, the tenth transistor M10, under the control of the valid level signal of the pull-down node PD, provides the signal of the fourth power supply terminal VGL_2 to the pull-up node PU, so that the pull-up node PU maintains the reset state.

[0088] In one embodiment, Figure 3 As shown, the frame reset module 18 includes a seventh transistor M7. The gate of the seventh transistor M7 is coupled to the fourth power supply terminal VGL_2, the first electrode of the seventh transistor M7 is coupled to the fourth power supply terminal VGL_2, and the second electrode of the seventh transistor M7 is coupled to the first output signal terminal OUTPUT_1. When the fourth power supply terminal VGL_2 is a valid level signal, the seventh transistor M7 is turned on and provides the signal of the fourth power supply terminal VGL_2 to the first output signal terminal OUTPUT_1. In the display stage of a frame image, the fourth power supply terminal VGL_2 provides an invalid level signal, and in the blank stage between two adjacent frames of images, the second control power supply terminal provides an effective level signal. For example, in the display stage of the Nth frame image, the second control power supply terminal provides an invalid level signal, and the seventh transistor M7 is turned off. After the Nth frame image and before the N+1th frame image, the second control power supply terminal provides a valid level signal, the seventh transistor M7 is turned on, and the signal of the fourth power supply terminal VGL_2 is provided to the first output signal terminal OUTPUT_1 to achieve reset, that is, to achieve frame image reset, so as to avoid affecting the image of the next frame.

[0089] Figure 3The circuit structure of the pull-up module 11, the output module 12, the first reset module 13, the pull-down module 14, the noise reduction module 15, the second reset module 16, the reset control module 17 and the frame reset module 18 is exemplarily shown. It can be understood that the pull-up module 11, the output module 12, the first reset module 13, the pull-down module 14, the noise reduction module 15, the second reset module 16, the reset control module 17 and the frame reset module 18 are not limited to Figure 3 The circuit structure shown in the figure may adopt other circuit structures as long as the functions can be achieved.

[0090] For example, Figure 3 Each transistor in the scan driving circuit shown is an NMOS transistor. In the case that each transistor in the scan driving circuit is an NMOS transistor, the effective level signal of each transistor is a high level signal.

[0091] It should be noted that, in the scan drive circuit of the embodiment of the present disclosure, in actual use, the type of each transistor is not limited. Each transistor can be set as an NMOS tube or a PMOS tube as needed, and the signals of the input signal terminal INPUT, the first power supply terminal VGL_1, the second power supply terminal VDD, the third power supply terminal, and the second control power supply terminal are set accordingly. In the case where the transistor in the scan drive circuit is a PMOS tube, the effective level signal of each transistor is a low level signal.

[0092] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including a gate signal generating module, including a plurality of cascaded gate driving circuits, and the gate driving circuit is a scanning driving circuit of any disclosed embodiment of the present disclosure.

[0093] Exemplarily, the display panel includes a display area and a frame area, and the gate driving circuit is located in the frame area.

[0094] Figure 4 FIG. 1 is a schematic diagram of a gate signal generating module according to an embodiment of the present disclosure. Figure 4As shown, the gate signal generating module includes n cascaded gate driving circuits. The input signal terminal INPUT of the first-level gate driving circuit is coupled to the control signal terminal STV, the input signal terminal INPUT of the i-th-level gate driving circuit is coupled to the first output signal terminal OUTPUT_1 of the i-1-th-level gate driving circuit, and the reset signal terminal RST of the i-th-level gate driving circuit is coupled to the first output signal terminal OUTPUT_1 of the i+1-th-level. In this way, different gate driving circuits are controlled to output driving signals according to the display screen of the display area, so that the display panel can allocate frequencies according to different rows within one frame. For example, the second output signal terminal OUTPUT_2 of the first-level gate driving circuit to the m-th-level gate driving circuit outputs the signal after the first power supply terminal is pulled low, and the second output signal terminal OUTPUT_2 of the m+1-th-level gate driving circuit to the n-th-level gate driving circuit normally outputs the signal of the first output signal terminal OUTPUT_1.

[0095] The display panel of the embodiment of the present disclosure can provide the signal of the first power supply terminal VGL_1 to the second output signal terminal OUTPUT_2 within one frame to lower the potential of the second output signal terminal OUTPUT_2 when the display area of ​​the display panel is a static picture or a slow dynamic picture, and provide the signal of the first output signal terminal OUTPUT_1 to the second output signal terminal OUTPUT_2 normally when the display area of ​​the display panel is a dynamic picture, which can reduce power consumption and improve product competitiveness.

[0096] Exemplarily, the display panel may be an organic light emitting diode display panel (OLED), or the display panel may also be a liquid crystal display panel (LCD).

[0097] In one embodiment, the display panel 100 includes a first display area 110 and a second display area 120. The first display area 110 includes N gate lines, which are connected to N gate drive circuits, and the second display area 120 includes M gate lines, which are connected to M gate drive circuits, and M and N are positive integers greater than 0. The voltage value of the signal of the gate drive circuit corresponding to the first display area 110 is a first voltage, and the voltage value of the signal of the gate drive circuit corresponding to the second display area 120 is a second voltage, the first voltage is less than the second voltage, the signal of the gate area circuit corresponding to the second display area is the signal of the first output signal terminal OUTPUT_1, and the signal of the gate drive circuit corresponding to the first display area 110 is the voltage after the first power supply terminal VGL_1_1 is pulled down.

[0098] Figure 6 FIG. 1 is a schematic diagram of a display area of ​​a display panel according to an embodiment of the present disclosure. Figure 6As shown, the display panel includes a second display area 120 (dynamic display area B) and two first display areas 110 (static display area A and static display area C) located on both sides. The picture in the first display area 110 remains unchanged as a static display area, and the picture in the second display area 120 is refreshed in real time as a dynamic display area. For example, when playing a video or playing a game, a frame of the picture may include a middle dynamic picture and upper and lower black frames on both sides of the middle dynamic picture or a normal display static picture. The middle dynamic picture is the second display area, and the upper and lower black frames are the static display area. For the static display area, the embodiment of the present disclosure only needs to maintain the picture, and the pixels can enter the hold state, which can reduce the power consumption of the static display area.

[0099] It should be noted that the range of the first display area 110 and the range of the second display area 120 can be adjusted, and the first display area 110 and the second display area 120 can adjust the number of corresponding grid lines according to the needs and the display screen, thereby adjusting the start line and the end line of the frequency division area. The first display area 110 can be one or more, the second display area 120 can be one or more, and the number of the first display area and the second display area can be equal or unequal.

[0100] In one embodiment, the display panel 100 further includes a data chip, which transmits a data signal DATA to a row corresponding to the second display area 120, and stops transmitting a data signal to a row corresponding to the first display area 110. The data chip can transmit a data signal to a row corresponding to the second display area or stop transmitting a signal to a row corresponding to the first display area 110, thereby further reducing power consumption.

[0101] Figure 7 FIG. 1 is a schematic diagram of the signal timing of an embodiment of the present disclosure. Figure 7As shown, in the static display area A and the static display area C, the trigger signal terminal Vf provides a high-level signal, the second control transistor M13 is turned on, the first power supply terminal VGL_1 provides a second signal, the second signal is a low-level signal, the first signal of the first output signal terminal OUTPUT_1 is pulled low, and the output of the second output signal terminal OUTPUT_2 is pulled low, so that the transistors of the static display area A and the static display area C are turned off, and the pixels of the static display area A and the static display area C enter the hold state, and the data chip synchronously stops transmitting data signals to the static display area A and the static display area C, and the static display area A and the static display area C no longer refresh the screen, and enter the hold low-frequency state. In the dynamic display area B, the trigger signal terminal B provides a low-level signal, the second control transistor M13 is turned off, the first power supply terminal VGL_1 does not provide the second signal to the second output signal terminal OUTPUT_2, the first output signal terminal OUTPUT_1 normally provides a pulse signal, the second output signal terminal OUTPUT_2 outputs the normal signal of the first output signal terminal OUTPUT_1, the data chip outputs the data signal corresponding to the screen, and the pixel enters the normal refreshable state.

[0102] During normal display of the display panel, the trigger signal terminal Vf provides a low level signal, the second control transistor M13 is turned off, and the second output signal terminal OUTPUT_2 of each gate driving circuit normally outputs the signal of the first output signal terminal OUTPUT_1. Figure 5 The gate driving circuit shown outputs gate driving signals row by row. When the first-level gate driving circuit to the m-th-level gate driving circuit of the display panel does not need to be refreshed, the trigger signal terminal Vf provides a high-level signal, the second control transistor M13 is turned on, and the second output signal terminal OUTPUT_2 of the gate driving circuit of the corresponding row outputs a signal pulled low by the first power supply terminal. When the m+1-th-level gate driving circuit to the n-th-level gate driving circuit of the display panel is refreshed normally, the trigger signal terminal Vf provides a low-level signal, the second control transistor is turned off, and the second output signal terminal of the corresponding row normally outputs the signal of the first output signal terminal OUTPUT_1, thereby realizing frequency division and row control of the static display area and the dynamic display area to reduce power consumption.

[0103] The data chip controls the data signal output from the first-level gate driving circuit to the corresponding row of the m-th-level gate driving circuit of the display panel, and the data chip controls the normal output of the data signal from the m+1-th-level gate driving circuit to the corresponding row of the n-th-level gate driving circuit of the display panel, thereby further reducing power consumption.

[0104] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for driving a display panel, which is applied to the display panel of any embodiment of the present disclosure, and the method includes:

[0105] The first output signal terminal OUTPUT_1 provides a first signal to the second output signal terminal OUTPUT_2, the trigger signal terminal Vf provides a trigger signal, and the first power supply terminal VGL_1 provides a second signal to the second output signal terminal OUTPUT_2, and the second signal pulls down the first signal.

[0106] The driving method of the embodiment of the present disclosure can control the first power supply end to provide a second signal to the second output signal end OUTPUT_2 through the trigger signal end to lower the signal level of the second output signal end OUTPUT_2, thereby adjusting the signals of the second output signal end OUTPUT_2 of different rows according to the static display area and the dynamic display area within one frame of the picture, thereby reducing power consumption.

[0107] In one embodiment, the method further comprises:

[0108] The trigger signal terminal Vf of the gate driving circuit corresponding to the first display area provides a first trigger signal to control the first power terminal VGL_1 to provide a second signal to the second output signal terminal OUTPUT_2. The second signal pulls down the first signal, and the output signal of the second output signal terminal OUTPUT_2 is pulled down.

[0109] The trigger signal terminal Vf of the gate driving circuit corresponding to the second display area provides a second trigger signal, and the second trigger signal controls the first power supply terminal VGL_1 not to provide the second signal to the second output signal terminal OUTPUT_2, so that the first output signal terminal OUTPUT_1 normally provides a signal to the second output signal terminal OUTPUT_2.

[0110] Exemplarily, the first trigger signal is a high level signal, the second trigger signal is a low level signal, and the first power supply terminal VGL_1 is a low level signal. The first trigger signal controls the first power supply terminal to provide a low level signal to the second output signal terminal OUTPUT_2 to lower the level of the second output signal terminal OUTPUT_2, thereby realizing frequency division display of the static display area and the dynamic display area within one frame, thereby reducing power consumption.

[0111] In one embodiment, the method further comprises:

[0112] The data chip controls the data signal to be transmitted to the corresponding row of the second display area, and the data chip controls the data signal to stop being transmitted to the corresponding row of the first display area.

[0113] The data chip can control the transmission of data signals to corresponding rows or turn off the transmission of data signals according to the positions of the first display area and the second display area, thereby further reducing power consumption.

[0114] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including a display panel according to any embodiment of the present disclosure. The display device provided by the embodiments of the present disclosure may be, for example, a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a car display, an e-book, a biometric device such as a smart skin device, a soft robot, and a biomedical device, and any product or component with display and touch functions.

[0115] The scan driving circuit, the display panel and other components of the display device in the above-mentioned embodiment may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0116] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0117] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0118] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0119] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0120] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0121] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A scanning driving circuit, characterized in that: include A driving signal generating module, coupled to the input signal terminal, the clock signal terminal and the first output signal terminal respectively, wherein the driving signal generating module is configured to provide the signal of the clock signal terminal to the first output signal terminal under the control of the input signal terminal; as well as The signal output control module is coupled to the trigger signal terminal, the first power supply terminal, the first output signal terminal and the second output signal terminal respectively. The first output signal terminal provides a first signal to the second output signal terminal. The signal output control module is configured such that under the control of the trigger signal terminal, the first power supply terminal provides a second signal to the second output signal terminal to pull down the first signal.

2. The scanning driving circuit according to claim 1, characterized in that: The signal output control module includes a first control transistor and a second control transistor, the gate of the first control transistor is coupled to the first output signal terminal, the first electrode of the first control transistor is coupled to the first output signal terminal, the second electrode of the second control transistor is coupled to the first power supply terminal, the gate of the second control transistor is coupled to the trigger signal terminal, the second output signal terminal is coupled to the second electrode of the first control transistor, and the second output signal terminal is coupled to the first electrode of the second control transistor.

3. The scanning driving circuit according to claim 1, characterized in that: The second signal is a constant voltage signal, and the first signal is a pulse signal.

4. The scanning driving circuit according to claim 1, characterized in that: The driving signal generating module includes a pull-up module, an output module, a first reset module, a pull-down module, a noise reduction module, a second reset module, a reset control module and a third reset module; The pull-up module is coupled to the input signal terminal, the second power terminal and the pull-up node respectively, and is configured to provide the signal of the second power terminal to the pull-up node under the control of the input signal terminal; The output module is coupled to the clock signal terminal, the pull-up node and the first output signal terminal respectively, and is configured to provide the signal of the clock signal terminal to the first output signal terminal under the control of the pull-up node; The first reset module is coupled to the reset signal terminal, the third power terminal and the pull-up node respectively, and is configured to provide the signal of the third power terminal to the pull-up node under the control of the reset signal terminal. The pull-down module is coupled to the fourth power supply terminal, the pull-up node and the control node respectively, and is configured to provide the signal of the fourth power supply terminal to the pull-down node and the control node under the control of the pull-up node; a noise reduction module, coupled to the first control power supply terminal, the control node and the pull-down node respectively, and configured to provide the signal of the first control power supply terminal to the control node under the control of the first control power supply terminal, and to provide the signal of the first control power supply terminal to the pull-down node under the control of the control node; a second reset module, coupled to the pull-down node, the fourth power supply terminal and the first output signal terminal respectively, and configured to provide a signal of the fourth power supply terminal to the first output signal terminal under the control of the pull-down node; a reset control module, coupled to the pull-down node, the fourth power supply terminal and the pull-up node respectively, and configured to provide a signal of the fourth power supply terminal to the pull-up node under the control of the pull-down node; The frame reset module is coupled to the fourth power supply terminal, the first output signal terminal, and the second control power supply terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output signal terminal under the control of the second control power supply terminal.

5. The scanning driving circuit according to claim 4, characterized in that: Include at least one of the following: The pull-up module comprises a first transistor, a gate of the first transistor is coupled to the input signal terminal, a first electrode of the first transistor is coupled to the second power supply terminal, and a second electrode of the first transistor is coupled to the pull-up node; The output module includes a third transistor and a storage capacitor, the gate of the third transistor is coupled to the pull-up node, the first electrode of the third transistor is coupled to the clock signal terminal, the second electrode of the third transistor is coupled to the first output signal terminal, the first plate of the storage capacitor is coupled to the pull-up node, and the second plate of the storage capacitor is coupled to the first output signal terminal; The first reset module includes a second transistor, a gate of the second transistor is coupled to the reset signal terminal, a first electrode of the second transistor is coupled to the third power supply terminal, and a second electrode of the second transistor is coupled to the pull-up node; The pull-down module includes a sixth transistor and an eighth transistor, the gate of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the pull-down node, the second electrode of the sixth transistor is coupled to the fourth power supply terminal, the gate of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor is coupled to the control node, and the second electrode of the eighth transistor is coupled to the fourth power supply terminal; The noise reduction module includes a fifth transistor and a ninth transistor, the gate of the ninth transistor is coupled to the first control power supply terminal, the first electrode of the ninth transistor is respectively coupled to the first control power supply terminal, the second electrode of the ninth transistor is coupled to the control node, the gate of the fifth transistor is coupled to the control node, the first electrode of the fifth transistor is coupled to the first control power supply terminal, and the second electrode of the fifth transistor is coupled to the pull-down node; The second reset module includes an eleventh transistor, a gate of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the fourth power supply terminal, and a second electrode of the eleventh transistor is coupled to the first output signal terminal; The reset control module includes a tenth transistor, a gate of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the fourth power supply terminal, and a second electrode of the tenth transistor is coupled to the pull-up node; The frame reset module includes a seventh transistor, a gate of the seventh transistor is coupled to the second control power supply terminal, a first electrode of the seventh transistor is coupled to the fourth power supply terminal, and a second electrode of the seventh transistor is coupled to the first output signal terminal.

6. A display panel, characterized in that: include: The gate signal generating module comprises a plurality of cascaded gate driving circuits, wherein the gate driving circuit is the scanning driving circuit according to any one of claims 1 to 5.

7. The display panel according to claim 6, characterized in that: The display panel includes a first display area and a second display area, the first display area includes N gate lines, and the N gate lines are correspondingly connected to N gate driving circuits, the second display area includes M gate lines, and the M gate lines are correspondingly connected to M gate driving circuits, M and N are positive integers greater than 0, the voltage value of the signal of the gate driving circuit corresponding to the first display area is a first voltage, the voltage value of the signal of the gate driving circuit corresponding to the second display area is a second voltage, and the first voltage is less than the second voltage.

8. The display panel according to claim 7, characterized in that: The display panel further includes a data chip. When the data chip is turned on, it transmits data signals to the corresponding rows of the second display area. When the data chip is turned off, it transmits data signals to the corresponding rows of the first display area.

9. A method for driving a display panel, applied to the display panel according to any one of claims 6 to 8, characterized in that: The method comprises: The first output signal terminal provides a first signal to the second output signal terminal; The trigger signal terminal provides a trigger signal to control the first power supply terminal to provide a second signal to the second output signal terminal to pull down the first signal.

10. The method for driving a display panel according to claim 9, characterized in that: The method further comprises: The trigger signal terminal of the gate driving circuit corresponding to the first display area provides a first trigger signal, and controls the first power supply terminal to provide a second signal to the second output signal terminal to pull down the first signal; The trigger signal terminal of the gate driving circuit corresponding to the second display area provides a second trigger signal, and the first power supply terminal is closed to provide a second signal to the second output signal terminal.

11. The method for driving a display panel according to claim 10, wherein: The method further comprises: The data chip controls the data signal to be transmitted to the row corresponding to the second display area, and the data chip controls the data signal to stop being transmitted to the row corresponding to the first display area.

12. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 6 to 8.

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