Pixel circuit, driving method thereof and display device

Abstract

The invention provides a pixel circuit, a driving method thereof and a display device. The pixel circuit comprises a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a first reset sub-circuit, the first light-emitting control sub-circuit is coupled to a first voltage end and a first end of the driving sub-circuit, the second light-emitting control sub-circuit is coupled to a second end of the driving sub-circuit and a first electrode of the light-emitting element, and the data writing sub-circuit is coupled to a data signal end and the first end of the driving sub-circuit. The compensation sub-circuit is coupled to the second end of the driving sub-circuit and the control end of the driving sub-circuit. The first reset sub-circuit is coupled to the compensation sub-circuit and a second voltage end. When the driving sub-circuit is reset, the first end and the second end of the driving sub-circuit are maintained at a fixed voltage difference, so that the driving sub-circuit has a stable current, better resets carrier distribution of a driving transistor channel, improves the reset effect, reduces the ghost influence, and improves the display quality.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) screens have gradually attracted widespread attention due to their advantages such as wide viewing angle, high contrast, fast response speed, higher luminous brightness and lower driving voltage compared to inorganic light-emitting display devices.

[0003] However, after an OLED screen displays a certain image for a long time, when switching to another image, the pattern of the previous image will remain, that is, the afterimage. The existence of the afterimage seriously affects the user experience, and for OLED screen manufacturers, the existence of the afterimage will affect the yield and delivery.

[0004] Therefore, how to reduce the influence of afterimage and improve screen display quality is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In order to solve the above problems, the inventors found the causes of the problems through research and development and formed solutions.

[0006] In a first aspect, the present invention provides a pixel circuit, which includes a driving subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a data writing subcircuit, a compensation subcircuit and a first reset subcircuit;

[0007] The first light emitting control subcircuit is coupled to the first voltage terminal and the first terminal of the driving subcircuit, and is configured to drive the light emitting element to emit light in response to a signal of the first light emitting signal control terminal;

[0008] The second light emitting control subcircuit is coupled to the second terminal of the driving subcircuit and the first electrode of the light emitting element, and is configured to drive the light emitting element to emit light in response to a signal of the second light emitting signal control terminal;

[0009] The data writing subcircuit is coupled to the data signal terminal and the first terminal of the driving subcircuit, and is configured to write the data signal of the data signal terminal into the first terminal of the driving subcircuit in response to the signal of the writing signal control terminal;

[0010] The compensation subcircuit is coupled to the second terminal of the driving subcircuit and the control terminal of the driving subcircuit, and is configured to perform threshold compensation on the driving subcircuit in response to a signal of the compensation signal control terminal;

[0011] The first reset subcircuit is coupled to the compensation subcircuit and the second voltage terminal, and is configured to, in a first reset phase, respond to a signal at the first reset signal control terminal and use the voltage at the second voltage terminal to reset the control terminal of the driving subcircuit, and, in a second reset phase, respond to a signal at the first reset signal control terminal and use the voltage at the second voltage terminal to reset the second terminal of the driving subcircuit, so that a fixed voltage difference exists between the first terminal of the driving subcircuit and the second terminal of the driving subcircuit.

[0012] Further, in the above-mentioned pixel circuit, the first reset subcircuit includes a first sub-reset circuit;

[0013] The second voltage terminal includes a first sub-voltage terminal;

[0014] The first end of the first sub-reset circuit is coupled to the control end of the driving sub-circuit, and the second end of the first reset sub-circuit is coupled to the first sub-voltage end, and is configured to, in a first reset phase, in response to a signal of the first reset signal control end, write the voltage of the first sub-voltage end into the control end of the driving sub-circuit to reset the control end of the driving sub-circuit, and, in a second reset phase, in response to a signal of the first reset signal control end, write the signal of the first sub-voltage end into the second end of the driving sub-circuit via the compensation sub-circuit to reset the second end of the driving sub-circuit;

[0015] The signal at the first reset signal control terminal is the signal at the first sub-reset circuit control terminal, and the compensation sub-circuit is in a disconnected state in the first reset stage.

[0016] Further, in the above-mentioned pixel circuit, the first sub-reset circuit includes at least one first sub-reset transistor;

[0017] When there are multiple first sub-reset transistors, the multiple first sub-reset transistors are connected in series.

[0018] Further, in the above-mentioned pixel circuit, the compensation subcircuit includes at least one compensation transistor;

[0019] When there are multiple compensation transistors, the multiple compensation transistors are connected in series.

[0020] Further, in the above-mentioned pixel circuit, the first reset sub-circuit includes a second sub-reset circuit;

[0021] The second voltage terminal includes a second sub-voltage terminal;

[0022] The first end of the second sub-reset circuit is coupled to the control end of the driving sub-circuit through the compensation sub-circuit, and the second end of the second sub-reset circuit is coupled to the second sub-voltage end, and is configured to, in a first reset phase, in response to a signal at the first reset signal control end, write the signal at the second sub-voltage end into the control end of the driving sub-circuit via the compensation sub-circuit to reset the control end of the driving sub-circuit, and, in a second reset phase, in response to a signal at the first reset signal control end, write the voltage at the second sub-voltage end into the second end of the driving sub-circuit to reset the control end of the driving sub-circuit and the second end of the driving sub-circuit;

[0023] The signal at the first reset signal control terminal is the signal at the second sub-reset circuit control terminal; and the compensation sub-circuit is in a disconnected state in the second reset stage.

[0024] Further, in the above-mentioned pixel circuit, the first reset subcircuit includes a first sub-reset circuit and a second sub-reset circuit;

[0025] The second voltage terminal includes a first sub-voltage terminal and a second sub-voltage terminal;

[0026] The first end of the first sub-reset circuit is coupled to the control end of the driving sub-circuit, and the second end of the first reset sub-circuit is coupled to the first sub-voltage end, and is configured to write the voltage of the first sub-voltage end into the control end of the driving sub-circuit in response to the signal of the first reset signal control end in the first reset stage and the second reset stage, so as to reset the control end of the driving sub-circuit;

[0027] The first end of the second sub-reset circuit is coupled to the control end of the driving sub-circuit through the compensation sub-circuit, and the second end of the second reset sub-circuit is coupled to the second sub-voltage end, and is configured to write the voltage of the second sub-voltage end into the second end of the driving sub-circuit in response to the signal of the first reset signal control end in the second reset stage, so as to reset the second end of the driving sub-circuit;

[0028] Among them, the first reset signal includes a signal from the first sub-reset circuit control end and a signal from the second sub-reset circuit control end. In the first reset stage, the signal from the first sub-reset circuit control end controls the first sub-reset circuit to close, and the signal from the second sub-reset circuit control end controls the second sub-reset circuit to open. In the second stage, the signal from the first sub-reset circuit control end controls the first sub-reset circuit to close, and the signal from the second sub-reset circuit control end controls the second sub-reset circuit to close.

[0029] Further, in the above-mentioned pixel circuit, the second sub-reset circuit includes at least one second sub-reset transistor;

[0030] When there are multiple second sub-reset transistors, the multiple second sub-reset transistors are connected in series.

[0031] Furthermore, in the above-mentioned pixel circuit, the first light-emitting sub-circuit includes at least one light-emitting control transistor;

[0032] When there are multiple light emitting control transistors, the multiple light emitting control transistors are connected in series.

[0033] Furthermore, in the pixel circuit described above, the first light-emitting signal control terminal and the second light-emitting signal control terminal are connected to different signal lines, and the first light-emitting control sub-circuit is also configured to write the voltage of the first voltage terminal into the first end of the driving sub-circuit in response to the signal of the first light-emitting signal control terminal in the first reset stage and / or the second reset stage, thereby resetting the first end of the driving sub-circuit.

[0034] Furthermore, in the above-mentioned pixel circuit, the first light emitting signal control terminal and the second light emitting signal control terminal are connected to the same signal line;

[0035] The pixel driving circuit also includes a second reset sub-circuit, which is coupled to a third voltage terminal and the first terminal of the driving sub-circuit and is configured to respond to a signal from a second reset signal control terminal, write the voltage of the third voltage terminal to the first terminal of the driving sub-circuit in the first reset phase and / or the second reset phase, and reset the first terminal of the driving sub-circuit.

[0036] In a second aspect, the present invention provides a driving method for a pixel circuit, comprising:

[0037] In the first reset stage, in response to the signal of the second light-emitting signal control terminal, the second light-emitting control subcircuit is controlled to be disconnected, and in response to the signal of the first reset signal control terminal, the control terminal of the driving subcircuit in the pixel circuit is reset by using the voltage of the second voltage terminal;

[0038] In the second reset stage, in response to the signal of the first reset signal control terminal, the second end of the driving subcircuit is reset using the voltage of the second voltage terminal, so that a fixed voltage difference exists between the first end of the driving subcircuit and the second end of the driving subcircuit;

[0039] In the data writing compensation stage, in response to the signal of the writing signal control terminal and the signal of the compensation signal control terminal, the data writing subcircuit and the compensation subcircuit in the pixel circuit are controlled to write data and perform threshold compensation on the driving subcircuit;

[0040] In the light emitting stage, in response to the signal of the first light emitting signal control terminal and the signal of the second light emitting signal control terminal, the light emitting element is controlled and driven to emit light.

[0041] Furthermore, in the above-mentioned driving method of the pixel circuit, the first light emitting signal control terminal and the second light emitting signal control terminal are connected to different signal lines;

[0042] The driving method further includes:

[0043] In the first reset stage and / or the second reset stage, in response to a signal from the first light-emitting signal control terminal, the voltage of the first voltage terminal is written into the first terminal of the driving subcircuit to reset the first terminal of the driving subcircuit.

[0044] Furthermore, in the above-mentioned driving method of the pixel circuit, the first light emitting signal control terminal and the second light emitting signal control terminal are connected to the same signal line; the pixel driving circuit further includes a second reset subcircuit, and the second reset subcircuit is coupled to the third voltage terminal and the first terminal of the driving subcircuit;

[0045] The driving method further includes:

[0046] In the first reset phase and / or the second reset phase, in response to a signal at the second reset signal control terminal, the voltage at the third voltage terminal is written into the first terminal of the driving sub-circuit to reset the first terminal of the driving sub-circuit.

[0047] In a third aspect, the present invention provides a display device, comprising any one of the pixel circuits described above.

[0048] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0049] When implementing the technical solution of the present invention, by configuring the timing of the first reset sub-circuit, when the driving sub-circuit is reset, the first end of the driving sub-circuit and the second end of the driving sub-circuit are maintained at a fixed voltage difference, so that the driving sub-circuit has a stable current and does not gradually decrease with time, and the carrier distribution in the driving transistor channel and the recovery of the defect state can be better reset, thereby improving the reset effect, thereby improving the reduction of the influence of the afterimage and improving the display quality. In addition, the reset degree can be adjusted by adjusting the voltage difference between the first end of the driving sub-circuit and the second end of the driving sub-circuit, and the controllability is also higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In addition, similar numbers in the drawings are used to represent similar components, wherein:

[0051] Figure 1 is a first structural schematic diagram of a pixel circuit of the present invention;

[0052] Figure 2 yes Figure 1 A timing control diagram of a pixel circuit;

[0053] Figure 3 is a second structural schematic diagram of the pixel circuit of the present invention;

[0054] Figure 4 yes Figure 3 A timing control diagram of a pixel circuit;

[0055] Figure 5 is a third structural schematic diagram of the pixel circuit of the present invention;

[0056] Figure 6 yes Figure 5 A timing control diagram of a pixel circuit;

[0057] Figure 7 is a fourth structural schematic diagram of the pixel circuit of the present invention;

[0058] Figure 8 yes Figure 7 A timing control diagram of a pixel circuit;

[0059] Fig. 9 is a fifth structural schematic diagram of the pixel circuit of the present invention;

[0060] Fig.10 yes Fig. 9 A timing control diagram of a pixel circuit;

[0061] Fig.11 is a sixth structural schematic diagram of the pixel circuit of the present invention;

[0062] Fig.12 yes Fig.11 Timing control diagram of the pixel circuit. DETAILED DESCRIPTION

[0063] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0064] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, in the present invention, unless otherwise clearly specified and defined, the terms "connected", "connected", and the like should be understood in a broad sense. For example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0065] In the description of the present invention, the transistors used in the circuits provided in the embodiments may be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples. The control terminal of any transistor mentioned is the gate of the transistor, the first terminal of any transistor is one of the source and drain of the transistor, and the second terminal of any transistor is the other of the source and drain of the transistor.

[0066] In the description of the present invention, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term "coupled" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0067] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0068] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0069] When the driving transistor in the pixel circuit of the OLED screen is affected by bias for a long time, the threshold voltage Vth of the transistor will drift. With different bias voltages, the Vth offset will be different, and the afterimage is caused by this reason.

[0070] In the related art, the driving transistor in the pixel circuit is usually reset to pull the offset Vth back to the same level as much as possible to reduce the afterimage phenomenon. However, it is found in practice that the existing reset method is not very effective in reducing the afterimage phenomenon. In response to this problem, further research has found that in the existing reset method, when resetting the driving transistor in the pixel circuit, only the gate and drain of the driving transistor are usually reset, or the gate and source are reset. That is to say, there is voltage on only one side of the source or drain of the driving transistor, and when the driving transistor is reset, it is in the on state. There will be charge movement between the source or drain of the driving transistor until it is balanced (Vgs=Vth), so the voltage difference (ie Vds) of the source or drain of the driving transistor will gradually decrease, and the current passing through the driving transistor will also gradually decrease. However, it has been found that the current passing through the driving transistor can reset the carrier distribution in the channel of the driving transistor and the recovery of the defect state, and the current passing through the driving transistor gradually decreases, which will cause the reset effect of the driving transistor to gradually deteriorate, or the reset effect is limited.

[0071] Based on the problem found, the present invention provides the following technical means:

[0072] Figure 1 is a schematic diagram of a first structure of a pixel circuit of the present invention, such as Figure 1 As shown, the pixel circuit includes a driving subcircuit 11, a first light-emitting control subcircuit 12, a second light-emitting control subcircuit 13, a data writing subcircuit 14, a compensation subcircuit 15 and a first reset subcircuit 16.

[0073] The first light-emitting control subcircuit 12 is coupled to the first voltage terminal V1 and the first terminal of the driving subcircuit 11, and is configured to drive the light-emitting element D to emit light in response to the signal EM1 of the first light-emitting signal control terminal; wherein the first light-emitting control subcircuit 12 is the fifth transistor T5.

[0074] The second light-emitting control subcircuit 13 is coupled to the second end of the driving subcircuit 11 and the first electrode of the light-emitting element D, and is configured to drive the light-emitting element D to emit light in response to the signal EM2 of the second light-emitting signal control end; wherein the second light-emitting control subcircuit 13 is the sixth transistor T6.

[0075] The data writing sub-circuit 14 is coupled to the data signal terminal D and the first terminal of the driving sub-circuit 11, and is configured to write the data signal Date of the data signal terminal D into the first terminal of the driving sub-circuit 11 in response to the signal Gate of the write signal control terminal; wherein the data writing sub-circuit 14 is a fourth transistor T4.

[0076] The compensation subcircuit 15 is coupled to the second end of the driving subcircuit 11 and the control end of the driving subcircuit 11, and is configured to perform threshold compensation on the driving subcircuit 11 in response to a signal Reset3 at the compensation signal control end; wherein the compensation subcircuit 15 is a second transistor T2.

[0077] The first reset subcircuit 16 is coupled to the compensation subcircuit 15 and the second voltage terminal V2, and is configured to, in a first reset stage t1, respond to a signal at the first reset signal control terminal and use the voltage of the second voltage terminal V2 to reset the control terminal of the driving subcircuit 11, and, in a second reset stage t2, respond to a signal at the first reset signal control terminal and use the voltage of the second voltage terminal V2 to reset the second terminal of the driving subcircuit 11, so that there is a fixed voltage difference between the first terminal of the driving subcircuit 11 and the second terminal of the driving subcircuit 11. In this way, when resetting the driving subcircuit 11, the driving subcircuit 11 has a stable current that does not gradually decrease over time, and can better reset the carrier distribution in the channel of the driving transistor and the recovery of the defect state, thereby improving the reset effect, and the reset degree can be adjusted by adjusting the voltage difference between the first terminal of the driving subcircuit 11 and the second terminal of the driving subcircuit 11, and the controllability is also higher. Among them, Figure 1 It is described by taking the example that the first reset sub-circuit 16 includes the first sub-reset circuit 161 , the second voltage terminal V2 includes the first sub-voltage terminal V21 , and the first sub-reset circuit 161 is the first transistor T1 .

[0078] Specifically, Figure 1 A low temperature polysilicon (LTPS) circuit is used as an example for description, and each transistor is described as a P-type transistor. Figure 1In the description, an example is taken in which the first light emitting signal control terminal and the second light emitting signal control terminal are connected to different signal lines, that is, the signal of the first light emitting signal control terminal is EM1, and the signal of the second light emitting signal control terminal is EM2. Figure 1 The first light emitting control subcircuit 12 in the embodiment is further configured to write the voltage Vdd of the first voltage terminal V1 into the first terminal of the driving subcircuit 11 in response to the signal EM1 of the first light emitting signal control terminal in the first reset stage t1 and / or the second reset stage t2, that is, Figure 1 In this way, the first end of the driving sub-circuit 11 can be reset, that is, the voltage of the node N2 is Vdd. In the subsequent resetting process, a fixed voltage difference can exist between the first end of the driving sub-circuit 11 and the second end of the driving sub-circuit 11.

[0079] Figure 2 yes Figure 1 The timing control diagram of the pixel circuit. Figure 2 As shown, the driving process of the pixel circuit may include a first reset phase t1, a second reset phase t2, a data writing compensation phase t3 and a light emitting phase t4. The pixel circuit driving method may include the following steps:

[0080] Step 100, in the first reset stage t1, in response to the signal of the second light-emitting signal control terminal, the second light-emitting control subcircuit 13 is controlled to be disconnected, and in response to the signal of the first reset signal control terminal, the control terminal of the driving subcircuit 11 in the pixel circuit is reset using the voltage of the second voltage terminal V2.

[0081] for Figure 2 For the pixel circuit shown, in the first reset stage t1, the level of the signal EM2 at the second light-emitting signal control terminal is the first level (such as a high level), which can control the sixth transistor T6 to be disconnected, and the light-emitting element D does not emit light, and the signal of the first reset signal control terminal is the signal Reset1 at the first sub-reset circuit control terminal, and the level of the signal Reset1 at the first sub-reset circuit control terminal is the second level (such as a low level), the first sub-reset circuit 161 is closed, and the voltage Vinit1 of the first sub-voltage terminal V21 is written into the node N1 corresponding to the driving end of the third transistor T3, thereby resetting the driving end of the third transistor T3 and preparing for the subsequent resetting of the other ends of the third transistor T3.

[0082] It should be noted that according to Figure 2 It can be seen from the timing shown that in the first reset stage t1, the fifth transistor T5 is in a closed state, and the voltage Vdd of the first voltage terminal V1 can be written into the first terminal of the driving sub-circuit 11. The second transistor T2, the fourth transistor T4, and the seventh transistor T7 are all in an open state under the control of the signals of their respective control terminals. Figure 2 The seventh transistor T7 is configured to respond to the signal of the third reset signal control terminal to reset the light emitting element D, and the writing voltage of the seventh transistor T7 is no longer shown in the figure. The third reset signal control terminal and the writing signal control terminal are connected to the same signal line, both of which are recorded as Gate.

[0083] Step 101, in a second reset stage t2, in response to a signal at the first reset signal control terminal, the second terminal of the driving sub-circuit 11 is reset using the voltage at the second voltage terminal V2, so that a fixed voltage difference exists between the first terminal of the driving sub-circuit 11 and the second terminal of the driving sub-circuit 11;

[0084] In a specific implementation process, after the driving end of the third transistor T3 is reset, the second end of the third transistor T3 may be reset to ensure that a fixed voltage difference exists between the first end of the third transistor T3 and the second end of the third transistor T3 .

[0085] Specifically, the signal of the first reset signal control terminal is still the signal Reset1 of the first sub-reset circuit control terminal, and its level is still the second level, which controls the first transistor T1 to close, so that the voltage Vinit1 of the first sub-voltage terminal V21 continues to maintain the voltage of the node N1. In this stage, the level of the signal Reset3 of the compensation signal control terminal is the second level, the second transistor T2 is closed, and the voltage Vinit1 of the first sub-voltage terminal V21 can be written to the second end of the third transistor T3, that is, the node N3. In this stage, the fifth transistor T5 is still in a closed state, the voltage difference between the node N1 and the node N2 is maintained at Vgs=Vinit1-Vdd<0, the third transistor T3 is turned on, the voltage of the node N2 is maintained at Vdd, and the voltage difference between the node N3 and the node N2 is maintained at Vds=Vinit1-Vdd<0. The current path is the fifth transistor T5-the third transistor T3-the second transistor T2-the first transistor T1, so that the current of the current path can be used to reset the third transistor T3. Among them, Vgs≤-5V, Vds≤-5V.

[0086] It should be noted that Figure 1 The first sub-reset circuit 161 is a first transistor T1, the compensation sub-circuit 15 is a second transistor T2, and the first light-emitting sub-circuit is a fifth transistor T5. That is to say, Figure 1The first sub-reset circuit 161 includes a first sub-reset transistor, the compensation sub-circuit 15 includes a compensation transistor, and the first light-emitting control sub-circuit 12 includes a light-emitting control transistor. In actual applications, the first sub-reset circuit 161 may include multiple first sub-reset transistors connected in series, the compensation sub-circuit 15 may include multiple compensation transistors connected in series, and the first light-emitting control sub-circuit 12 may include multiple light-emitting control transistors connected in series. In this way, by adding a transistor between the node N2 and the first voltage terminal V1, and adding a transistor between the node N3 and the second voltage terminal V2, the driving controllability is made stronger, and the voltage across the third transistor T3 can be accurately controlled to achieve different reset levels.

[0087] Continue to see Figure 2 ,according to Figure 2 It can be seen from the timing sequence shown that in the second reset phase t2, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are all in the off state.

[0088] In addition, based on the above description, it can be known that in this embodiment, the node N1 is reset first and then the node N3 is reset, rather than resetting the nodes N1 and N3 at the same time. This has the following effects:

[0089] Effect 1: Resetting node N1 first can make the reset more complete and the reset effect better. Specifically, in the actual process, the reset process is not for one pixel, but for a row of pixels, so there are thousands of pixels of node N1 that need to be reset. Figure 1 The storage capacitor cst corresponding to the middle node N1 will have charge movement during the reset process, that is, current is generated, and due to the existence of the wiring resistance of the voltage Vinit1 of the first sub-voltage terminal V21, a voltage drop will inevitably occur. If the node N1 and the node N3 are reset at the same time, the reset effect will be affected, so the node N1 is reset first. After the node N1 is reset, there is basically no charge movement, eliminating the voltage drop of the voltage Vinit1 of the first sub-voltage terminal V21, ensuring the reset effect of the node N1, and then the node N3 is reset to eliminate the influence of the node N1 and ensure the reset effect of the node N3.

[0090] Effect 2: The load when the voltage Vinit1 of the first sub-voltage terminal V21 is reset can be reduced, and the stability of the voltage Vinit1 signal of the first sub-voltage terminal V21 can be improved. That is to say, when the pixel circuit is reset, the node N1 will be charged, so that the storage capacitor (i.e., cst) corresponding to the node N1 is added to the load corresponding to the voltage Vinit1 of the first sub-voltage terminal V21. If the node N3 is reset at the same time, the capacitor of the node N3 (not shown in the figure) will also be added to the load corresponding to the voltage Vinit1 of the first sub-voltage terminal V21. In this way, the load corresponding to the voltage Vinit1 of the first sub-voltage terminal V21 will increase, and the time for the voltage Vinit1 of the first sub-voltage terminal V21 to recover to the initial value after fluctuation will be longer, which will cause the potential charged to the node N1 to be not the desired potential, and there will be a part of the point voltage loss, which will eventually reduce the reset effect.

[0091] Effect 3: The node N1 is first reset to a lower potential to ensure the bias state of the third transistor T3, which can make the third transistor T3 turn on more fully and achieve a better subsequent reset effect.

[0092] Step 102, in the data writing compensation phase t3, in response to the signal of the writing signal control terminal and the signal of the compensation signal control terminal, the data writing subcircuit 14 and the compensation subcircuit 15 in the pixel circuit are controlled to write data and perform threshold compensation on the driving subcircuit 11;

[0093] like Figure 2 As shown, in this stage, the levels of the signal Gate at the write signal control terminal and the signal Reset3 at the compensation signal control terminal are both at the second level, controlling the fourth transistor T4 and the second transistor T2 to close to complete data writing and threshold compensation for the drive sub-circuit 11.

[0094] It should be noted that according to Figure 2 It can be seen from the timing shown that in this stage, the seventh transistor T7 is also closed under the control of the signal Gate written into the signal control terminal to reset the light emitting element D. The first transistor T1, the fifth transistor T5 and the sixth transistor T6 are in the off state.

[0095] Step 103 , in the light emitting stage t4 , in response to the signal of the first light emitting signal control terminal and the signal of the second light emitting signal control terminal, control and drive the light emitting element D to emit light.

[0096] In this stage, the fifth transistor T5 is closed under the control of the signal EM1 of the first light-emitting signal control terminal, the sixth transistor T6 is closed under the control of the signal EM2 of the second light-emitting signal control terminal, the third transistor T3 remains in a closed state, and the other transistors are in an open state, controlling the light-emitting element D to emit light.

[0097] The pixel circuit of this embodiment configures the timing of the first reset subcircuit 16 so that when the driving subcircuit 11 is reset, the first end of the driving subcircuit 11 and the second end of the driving subcircuit 11 are maintained at a fixed voltage difference, so that the driving subcircuit 11 has a stable current and does not gradually decrease with time, which can better reset the carrier distribution in the channel of the driving transistor and the recovery of the defect state, thereby improving the reset effect, thereby improving the reduction of the influence of the afterimage and improving the display quality. In addition, the reset degree can be adjusted by adjusting the voltage difference between the first end of the driving subcircuit 11 and the second end of the driving subcircuit 11, and the controllability is also higher.

[0098] Figure 3 is a second structural schematic diagram of the pixel circuit of the present invention, such as Figure 3 and Figure 1 As shown, the pixel circuit is Figure 1 The difference of the pixel circuit shown is that: the first reset sub-circuit 16 includes a second sub-reset circuit 162 in addition to the first sub-reset circuit 161; the corresponding second voltage terminal V2 includes a second sub-voltage terminal V22 in addition to the first sub-voltage terminal V21. The second sub-reset circuit 162 is the eighth transistor T8, and in this pixel circuit, the seventh transistor T7 is no longer set on the first pole side of the light-emitting element D. Its pixel circuit is still an LTPS circuit, and the transistors therein are also explained by taking P-type transistors as examples. And the write signal control terminal and the compensation signal control terminal are connected to the same signal line, both of which are recorded as Gate.

[0099] In a specific implementation process, the first end of the first sub-reset circuit 161 is coupled to the control end of the driving sub-circuit 11, and the second end of the first reset sub-circuit 16 is coupled to the first sub-voltage end V21, and is configured to write the voltage of the first sub-voltage end V21 into the control end of the driving sub-circuit 11 in response to the signal of the first reset signal control end in the first reset stage t1 and the second reset stage t2, so as to reset the control end of the driving sub-circuit 11;

[0100] The first end of the second sub-reset circuit 162 is coupled to the control end of the driving sub-circuit 11 through the compensation sub-circuit 15, and the second end of the second sub-reset circuit 162 is coupled to the second sub-voltage end V22, and is configured to write the voltage of the second sub-voltage end V22 into the second end of the driving sub-circuit 11 in response to the signal of the first reset signal control end in the second reset stage t2, so as to reset the second end of the driving sub-circuit 11;

[0101] Among them, the first reset signal includes a signal Reset1 at the first sub-reset circuit control end and a signal Reset2 at the second sub-reset circuit control end. In the first reset stage t1, the signal Reset1 at the first sub-reset circuit control end controls the first sub-reset circuit 161 to be closed, and the signal Reset2 at the second sub-reset circuit control end controls the second sub-reset circuit 162 to be opened. In the second stage, the signal Reset1 at the first sub-reset circuit control end controls the first sub-reset circuit 161 to be closed, and the signal Reset2 at the second sub-reset circuit control end controls the second sub-reset circuit 162 to be closed.

[0102] That is, in the first reset stage t1 and the second reset stage t2, the first sub-reset circuit 161 only resets the control end of the driving sub-circuit 11, and the second sub-reset circuit 162 only resets the second end of the driving sub-circuit 11 in the second reset stage t2.

[0103] Figure 4 yes Figure 3 The timing control diagram of the pixel circuit is as follows: Figure 4 As shown, the driving process of the pixel circuit is as follows:

[0104] In the first reset stage t1, the level of the signal EM2 at the second light-emitting signal control terminal is the first level, which can control the sixth transistor T6 to be disconnected, and the light-emitting element D does not emit light, and the signal at the first reset signal control terminal includes the signal Reset1 at the first sub-reset circuit control terminal and the signal Reset2 at the second sub-reset circuit control terminal. Among them, the level of the signal Reset1 at the first sub-reset circuit control terminal is the second level, the first sub-reset circuit 161 is closed, and the voltage Vinit1 of the first sub-voltage terminal V21 is written into the node N1 corresponding to the driving end of the third transistor T3, so as to reset the driving end of the third transistor T3 and prepare for the subsequent reset of the other ends of the third transistor T3. The level of the signal Reset2 at the second sub-reset circuit control terminal is the first level, and the second sub-reset circuit 162 is disconnected.

[0105] It should be noted that according to Figure 4 As shown in the timing sequence, in the first reset phase t1, the fifth transistor T5 is in a closed state, and can write the voltage Vdd of the first voltage terminal V1 into the first terminal of the driving subcircuit 11. The second transistor T2 and the fourth transistor T4 are both in an open state under the control of the signals of their respective control terminals.

[0106] In the second reset stage t2, the level of the signal Reset1 at the control end of the first sub-reset circuit is still the second level, and the first transistor T1 is controlled to be closed, so that the voltage Vinit1 of the first sub-voltage terminal V21 continues to maintain the voltage of the node N1. The level of the signal Reset2 at the control end of the second sub-reset circuit is the second level, and the eighth transistor T8 is controlled to be closed, so that the voltage Vinit2 of the second sub-voltage terminal V22 writes the voltage to the node N3, thereby resetting the node N3. In this stage, the fifth transistor T5 is still in a closed state, and the voltage difference between the node N1 and the node N2 is maintained at Vgs=Vinit1-Vdd<0, the third transistor T3 is turned on, the voltage of the node N2 is maintained at Vdd, and the voltage difference between the node N3 and the node N2 is maintained at Vds=Vinit2-Vdd<0. The current path is the fifth transistor T5-the third transistor T3-the eighth transistor T8, so that the current of the current path can be used to reset the third transistor T3.

[0107] It should be noted that Figure 3 In the description, the second sub-reset circuit 162 is described as the eighth transistor T8, that is, the second sub-reset circuit 162 includes one second sub-reset transistor, and in actual application, the second sub-reset circuit 162 may include a plurality of second sub-reset transistors connected in series. Figure 1 The relevant records of the embodiments of the present invention will not be repeated here.

[0108] Continue to see Figure 4 ,according to Figure 4 It can be seen from the timing sequence shown that in the second reset phase t2, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are all in the off state.

[0109] In addition, in this embodiment, the node N1 is reset first and then the node N3 is reset, rather than resetting the nodes N1 and N3 at the same time. The effect that can be achieved can be referred to the embodiment for Figure 1 The relevant records of the embodiments of the present invention will not be repeated here.

[0110] In the data writing compensation phase t3 , the levels of the signal Gate received by the writing signal control terminal and the compensation signal control terminal are both at the second level, and the fourth transistor T4 and the second transistor T2 are controlled to close to complete the data writing and threshold compensation of the driving sub-circuit 11 .

[0111] It should be noted that according to Figure 4 It can be seen from the timing sequence shown that in this stage, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all in the off state.

[0112] In the light-emitting stage t4, the fifth transistor T5 is closed under the control of the signal EM1 of the first light-emitting signal control terminal, the sixth transistor T6 is closed under the control of the signal EM2 of the second light-emitting signal control terminal, the third transistor T3 remains in the closed state, and the other transistors are in the open state, controlling the light-emitting element D to emit light.

[0113] Figure 5 is a third structural schematic diagram of the pixel circuit of the present invention, such as Figure 5 and Figure 3 As shown, the pixel circuit is Figure 3 The difference between the pixel circuits shown is that the write signal control terminal and the compensation signal control terminal are connected to different signal lines. The signal of the write signal control terminal is recorded as Gate, and the signal of the compensation signal control terminal is recorded as Reset3.

[0114] Figure 6 yes Figure 5 Timing control diagram of the pixel circuit. Figure 5 The control process of the pixel circuit shown is similar to Figure 3 The control process of the pixel circuit shown is similar, except that different signals are changed during the data writing compensation stage. Please refer to the above-mentioned related records for details, which will not be repeated here.

[0115] Figure 7 is a fourth structural schematic diagram of the pixel circuit of the present invention, see Figure 7 and Figure 1 The difference between the two is that Figure 7 It is a low temperature poly-oxide (LTPO) circuit, wherein the first transistor T1 and the second transistor T2 are N-type transistors, and the other transistors are P-type transistors.

[0116] Figure 8 yes Figure 7 The timing control diagram of the pixel circuit is as follows: Figure 8 As shown, the driving process of the pixel circuit is as follows:

[0117] In the first reset stage t1, the level of the signal EM2 at the second light-emitting signal control terminal is the first level, which can control the sixth transistor T6 to be disconnected, and the light-emitting element D does not emit light. The level of the signal Reset1 at the control terminal of the first sub-reset circuit is the first level, and the first sub-reset circuit 161 is closed. The voltage Vinit1 of the first sub-voltage terminal V21 is written into the node N1 corresponding to the driving end of the third transistor T3, thereby resetting the driving end of the third transistor T3 and preparing for the subsequent resetting of the other ends of the third transistor T3.

[0118] It should be noted that according to Figure 8As shown in the timing sequence, in the first reset stage t1, the fifth transistor T5 is in a closed state, and the voltage Vdd of the first voltage terminal V1 can be written into the first terminal of the driving subcircuit 11. The second transistor T2, the fourth transistor T4, and the seventh transistor T7 are all in an open state under the control of the signals of their respective control terminals.

[0119] In the second reset stage t2, the level of the signal Reset1 at the control end of the first sub-reset circuit is still the first level, and the first transistor T1 is controlled to be closed, so that the voltage Vinit1 of the first sub-voltage terminal V21 continues to maintain the voltage of the node N1. In this stage, the level of the signal GateN at the compensation signal control end is the first level, the second transistor T2 is closed, and the voltage Vinit1 of the first sub-voltage terminal V21 can be written to the second end of the third transistor T3, that is, the node N3. In this stage, the fifth transistor T5 is still in a closed state, the voltage difference between the node N1 and the node N2 is maintained at Vgs=Vinit1-Vdd<0, the third transistor T3 is turned on, the voltage of the node N2 is maintained at Vdd, and the voltage difference between the node N3 and the node N2 is maintained at Vds=Vinit1-Vdd<0. The current path is the fifth transistor T5-the third transistor T3-the second transistor T2-the first transistor T1, so that the current of the current path can be used to reset the third transistor T3.

[0120] Continue to see Figure 8 ,according to Figure 8 It can be seen from the timing sequence shown that in the second reset phase t2, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are all in the off state.

[0121] In addition, in this embodiment, the node N1 is reset first and then the node N3 is reset, rather than resetting the nodes N1 and N3 at the same time. The effect that can be achieved can be referred to the embodiment for Figure 1 The relevant records of the embodiments of the present invention will not be repeated here.

[0122] In the data writing compensation stage t3 , the levels of the signal GateP at the writing signal control terminal and the signal GateN at the compensation signal control terminal are both at the second level, controlling the fourth transistor T4 and the second transistor T2 to close to complete the data writing and threshold compensation of the driving sub-circuit 11 .

[0123] It should be noted that according to Figure 8 It can be seen from the timing sequence shown that in this stage, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all in the off state.

[0124] In the light-emitting stage t4, the fifth transistor T5 is closed under the control of the signal EM1 of the first light-emitting signal control terminal, the sixth transistor T6 is closed under the control of the signal EM2 of the second light-emitting signal control terminal, the third transistor T3 remains in the closed state, and the other transistors are in the open state, controlling the light-emitting element D to emit light.

[0125] Fig. 9 is a fifth structural schematic diagram of the pixel circuit of the present invention, see Fig. 9 and Figure 7 , the difference between the two is that the first light-emitting signal control terminal and the second light-emitting signal control terminal are connected to the same signal line, and their respective signals are both recorded as EM. In this case, the pixel driving circuit further includes a second reset subcircuit 17, the second reset subcircuit 17 is coupled to the third voltage terminal V3 and the first end of the driving subcircuit 11, and is configured to respond to the signal Reset4 of the second reset signal control terminal, in the first reset stage t1 and / or the second reset stage t2, write the voltage Vinit3 of the third voltage terminal V3 to the first end of the driving subcircuit 11, and reset the first end (node ​​N2) of the driving subcircuit 11. Among them, the second reset subcircuit 17 is a ninth transistor T9. In actual applications, the number of the ninth transistors T9 can also be multiple, and they are connected in series. The effect is the same as the effect of the first light-emitting subcircuit using multiple transistors connected in series. Please refer to the above-mentioned related records for details, which will not be repeated here.

[0126] Fig.10 yes Fig. 9 The timing control diagram of the pixel circuit is as follows: Fig.10 As shown, the driving process of the pixel circuit is as follows:

[0127] In the first reset stage t1, the levels of the signal EM at the first light-emitting signal control terminal and the signal EM at the second light-emitting signal control terminal are the first level, which can control the fifth transistor T5 and the sixth transistor T6 to be disconnected, and the light-emitting element D does not emit light. The level of the signal Reset1 at the control terminal of the first sub-reset circuit is the first level, the first sub-reset circuit 161 is closed, and the voltage Vinit1 of the first sub-voltage terminal V21 is written into the node N1 corresponding to the driving end of the third transistor T3, thereby resetting the driving end of the third transistor T3 and preparing for the subsequent resetting of the other ends of the third transistor T3.

[0128] It should be noted that according to Fig.10 It can be seen from the timing sequence shown that in the first reset stage t1, the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the ninth transistor T9 are all in the disconnected state under the control of the signals of their respective control terminals.

[0129] In the second reset stage t2, the level of the signal Reset1 at the control end of the first sub-reset circuit is still the first level, and the first transistor T1 is controlled to be closed, so that the voltage Vinit1 of the first sub-voltage terminal V21 continues to maintain the voltage of the node N1. In this stage, the level of the signal GateN at the compensation signal control end is the first level, the second transistor T2 is closed, and the voltage Vinit1 of the first sub-voltage terminal V21 can be written into the second end of the third transistor T3, that is, the node N3. In this stage, the level of the signal Reset4 at the second reset signal control end is the second level, the ninth transistor T9 is closed, and the voltage Vinit3 of the third voltage terminal V3 is written into the first end (node ​​N2) of the driving sub-circuit 11, and the voltage difference between the node N1 and the node N2 is maintained at Vgs=Vinit1-Vinit3<0, the third transistor T3 is turned on, the voltage of the node N2 is maintained at Vinit3, and the voltage difference between the node N3 and the node N2 is maintained at Vds=Vinit1-Vinit3<0. The current path is the ninth transistor T9T9 - the third transistor T3 - the second transistor T2 - the first transistor T1 , so the third transistor T3 can be reset by using the current in the current path.

[0130] Continue to see Fig.10 ,according to Fig.10 It can be seen from the timing sequence shown that in the second reset phase t2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all in the off state.

[0131] In addition, in this embodiment, the node N1 is reset first and then the node N3 is reset, rather than resetting the nodes N1 and N3 at the same time. The effect that can be achieved can be referred to the embodiment for Figure 1 The relevant records of the embodiments of the present invention will not be repeated here.

[0132] In the data writing compensation stage t3 , the levels of the signal GateP at the writing signal control terminal and the signal GateN at the compensation signal control terminal are both at the second level, controlling the fourth transistor T4 and the second transistor T2 to close to complete the data writing and threshold compensation of the driving sub-circuit 11 .

[0133] It should be noted that according to Fig.10 It can be seen from the timing sequence shown that in this stage, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are all in the off state.

[0134] In the light-emitting stage t4, the fifth transistor T5 is closed under the control of the signal EM of the first light-emitting signal control terminal, the sixth transistor T6 is closed under the control of the signal EM of the second light-emitting signal control terminal, the third transistor T3 remains in the closed state, and the other transistors are in the open state, controlling the light-emitting element D to emit light.

[0135] Fig.11 is a sixth structural diagram of the pixel circuit of the present invention, see Fig.11 and Fig. 9 The difference between the two is that the first reset sub-circuit 16 only includes the second sub-reset circuit 162; the second voltage terminal V2 includes the second sub-voltage terminal V22. The first end of the second sub-reset circuit 162 is coupled to the control end of the driving sub-circuit 11 through the compensation sub-circuit 15, and the second end of the second reset sub-circuit 17 is coupled to the second sub-voltage terminal V22.

[0136] Among them, the second sub-reset circuit 162 is configured as follows: in the first reset stage t1, in response to the signal Reset4 of the second reset signal control end, the voltage of the second sub-voltage terminal V22 is written into the control end of the driving sub-circuit 11 via the compensation sub-circuit 15, and the control end of the driving sub-circuit 11 is reset; and, in the second reset stage t2, in response to the signal of the first reset signal control end, the voltage of the second sub-voltage terminal V22 is written into the second end of the driving sub-circuit 11, and the control end of the driving sub-circuit 11 and the second end of the driving sub-circuit 11 are reset; wherein, the signal of the first reset signal control end is the signal Reset4 of the control end of the second sub-reset circuit 162; the compensation sub-circuit 15 is in a disconnected state in the second reset stage t2, so that the voltage of the node N1 can be maintained by the storage capacitor, and is not affected by the voltage fluctuation of the second sub-voltage terminal V22, the voltage of N1 is more stable, and the subsequent reset effect is better.

[0137] Fig.12 yes Fig.11 The timing control diagram of the pixel circuit is as follows: Fig.12 As shown, the driving process of the pixel circuit is as follows:

[0138] In the first reset stage t1, the levels of the signal EM at the first light-emitting signal control terminal and the signal EM at the second light-emitting signal control terminal are the first level, which can control the fifth transistor T5 and the sixth transistor T6 to be disconnected, and the light-emitting element D does not emit light; the level of the signal GateN at the compensation signal control terminal is the first level, the second transistor T2 is closed, the level of the signal Reset1 at the first sub-reset circuit control terminal is the first level, the first sub-reset circuit 161 is closed, and the voltage Vinit2 at the second sub-voltage terminal V22 is written into the node N1 corresponding to the driving end of the third transistor T3 via the second transistor T2, thereby resetting the driving end of the third transistor T3 and preparing for the subsequent resetting of the other ends of the third transistor T3.

[0139] It should be noted that according to Fig.12It can be seen from the timing sequence shown that in the first reset stage t1, the fourth transistor T4, the seventh transistor T7 and the ninth transistor T9 are all in the disconnected state under the control of the signals of their respective control terminals.

[0140] In the second reset stage t2, the level of the signal Reset2 at the control end of the second sub-reset circuit is still the first level, and the ninth transistor T9 is controlled to be closed, so that the voltage Vinit2 at the second sub-voltage end V22 continues to maintain the voltage of the node N3. In this stage, the level of the signal GateN at the compensation signal control end is the second level, the second transistor T2 is disconnected, and the voltage of the node N1 is maintained as Vinit2 by the storage capacitor. In this stage, the level of the signal Reset4 at the second reset signal control end is the second level, the ninth transistor T9 is closed, the voltage Vinit3 at the third voltage end V3 is written into the first end (node ​​N2) of the driving sub-circuit 11, the voltage difference between the node N1 and the node N2 is maintained at Vgs=Vinit2-Vinit3<0, the third transistor T3 is turned on, the voltage of the node N2 is maintained at Vinit3, and the voltage difference between the node N3 and the node N2 is maintained at Vds=Vinit2-Vinit3<0. The current path is the ninth transistor T9T9 - the third transistor T3 - the eighth transistor T8, so the third transistor T3 can be reset by using the current in the current path.

[0141] Continue to see Fig.12 ,according to Fig.12 It can be seen from the timing sequence shown that in the second reset phase t2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all in the off state.

[0142] In the data writing compensation stage t3, the level of the signal GateP at the writing signal control terminal is the second level and the level of the signal GateN at the compensation signal control terminal is the first level, controlling the fourth transistor T4 and the second transistor T2 to close to complete the data writing and threshold compensation of the driving sub-circuit 11.

[0143] It should be noted that according to Fig.12 It can be seen from the timing sequence shown that in this stage, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all in the off state.

[0144] In the light-emitting stage t4, the fifth transistor T5 is closed under the control of the signal EM of the first light-emitting signal control terminal, the sixth transistor T6 is closed under the control of the signal EM of the second light-emitting signal control terminal, the third transistor T3 remains in the closed state, and the other transistors are in the open state, controlling the light-emitting element D to emit light.

[0145] Furthermore, the present invention also provides a display device, which includes the pixel circuit of the above embodiment.

[0146] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a driving subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a data writing subcircuit, a compensation subcircuit and a first reset subcircuit; The first light emitting control subcircuit is coupled to the first voltage terminal and the first terminal of the driving subcircuit, and is configured to drive the light emitting element to emit light in response to a signal of the first light emitting signal control terminal; The second light emitting control subcircuit is coupled to the second terminal of the driving subcircuit and the first electrode of the light emitting element, and is configured to drive the light emitting element to emit light in response to a signal of the second light emitting signal control terminal; The data writing subcircuit is coupled to the data signal terminal and the first terminal of the driving subcircuit, and is configured to write the data signal of the data signal terminal into the first terminal of the driving subcircuit in response to the signal of the writing signal control terminal; The compensation subcircuit is coupled to the second terminal of the driving subcircuit and the control terminal of the driving subcircuit, and is configured to perform threshold compensation on the driving subcircuit in response to a signal of the compensation signal control terminal; The first reset subcircuit is coupled to the compensation subcircuit and the second voltage terminal, and is configured to, in a first reset phase, respond to a signal at the first reset signal control terminal and use the voltage at the second voltage terminal to reset the control terminal of the driving subcircuit, and, in a second reset phase, respond to a signal at the first reset signal control terminal and use the voltage at the second voltage terminal to reset the second terminal of the driving subcircuit, so that a fixed voltage difference exists between the first terminal of the driving subcircuit and the second terminal of the driving subcircuit.

2. The pixel circuit according to claim 1, characterized in that: The first reset sub-circuit comprises a first sub-reset circuit; The second voltage terminal includes a first sub-voltage terminal; The first end of the first sub-reset circuit is coupled to the control end of the driving sub-circuit, and the second end of the first reset sub-circuit is coupled to the first sub-voltage end, and is configured to, in a first reset phase, in response to a signal of the first reset signal control end, write the voltage of the first sub-voltage end into the control end of the driving sub-circuit to reset the control end of the driving sub-circuit, and, in a second reset phase, in response to a signal of the first reset signal control end, write the signal of the first sub-voltage end into the second end of the driving sub-circuit via the compensation sub-circuit to reset the second end of the driving sub-circuit; The signal at the first reset signal control terminal is the signal at the first sub-reset circuit control terminal, and the compensation sub-circuit is in a disconnected state in the first reset stage.

3. The pixel circuit according to claim 2, characterized in that: The first sub-reset circuit includes at least one first sub-reset transistor; When there are multiple first sub-reset transistors, the multiple first sub-reset transistors are connected in series.

4. The pixel circuit according to claim 2, characterized in that: The compensation subcircuit includes at least one compensation transistor; When there are multiple compensation transistors, the multiple compensation transistors are connected in series.

5. The pixel circuit according to claim 1, characterized in that: The first reset sub-circuit includes a second sub-reset circuit; The second voltage terminal includes a second sub-voltage terminal; The first end of the second sub-reset circuit is coupled to the control end of the driving sub-circuit through the compensation sub-circuit, and the second end of the second sub-reset circuit is coupled to the second sub-voltage end, and is configured to, in a first reset phase, in response to a signal at the first reset signal control end, write the signal at the second sub-voltage end into the control end of the driving sub-circuit via the compensation sub-circuit to reset the control end of the driving sub-circuit, and, in a second reset phase, in response to a signal at the first reset signal control end, write the voltage at the second sub-voltage end into the second end of the driving sub-circuit to reset the control end of the driving sub-circuit and the second end of the driving sub-circuit; The signal at the first reset signal control terminal is the signal at the second sub-reset circuit control terminal; and the compensation sub-circuit is in a disconnected state in the second reset stage.

6. The pixel circuit according to claim 1, characterized in that: The first reset sub-circuit includes a first sub-reset circuit and a second sub-reset circuit; The second voltage terminal includes a first sub-voltage terminal and a second sub-voltage terminal; The first end of the first sub-reset circuit is coupled to the control end of the driving sub-circuit, and the second end of the first reset sub-circuit is coupled to the first sub-voltage end, and is configured to write the voltage of the first sub-voltage end into the control end of the driving sub-circuit in response to the signal of the first reset signal control end in the first reset stage and the second reset stage, so as to reset the control end of the driving sub-circuit; The first end of the second sub-reset circuit is coupled to the control end of the driving sub-circuit through the compensation sub-circuit, and the second end of the second reset sub-circuit is coupled to the second sub-voltage end, and is configured to write the voltage of the second sub-voltage end into the second end of the driving sub-circuit in response to the signal of the first reset signal control end in the second reset stage, so as to reset the second end of the driving sub-circuit; Among them, the first reset signal includes a signal from the first sub-reset circuit control end and a signal from the second sub-reset circuit control end. In the first reset stage, the signal from the first sub-reset circuit control end controls the first sub-reset circuit to close, and the signal from the second sub-reset circuit control end controls the second sub-reset circuit to open. In the second stage, the signal from the first sub-reset circuit control end controls the first sub-reset circuit to close, and the signal from the second sub-reset circuit control end controls the second sub-reset circuit to close.

7. The pixel circuit according to claim 5 or 6, characterized in that: The second sub-reset circuit includes at least one second sub-reset transistor; When there are multiple second sub-reset transistors, the multiple second sub-reset transistors are connected in series.

8. The pixel circuit according to claim 1, characterized in that: The first light-emitting control subcircuit comprises at least one light-emitting control transistor; When there are multiple light emitting control transistors, the multiple light emitting control transistors are connected in series.

9. The pixel circuit according to claim 1, characterized in that: The first light-emitting signal control terminal and the second light-emitting signal control terminal are connected to different signal lines, and the first light-emitting control sub-circuit is also configured to write the voltage of the first voltage terminal into the first terminal of the driving sub-circuit in response to the signal of the first light-emitting signal control terminal in the first reset stage and / or the second reset stage, so as to reset the first terminal of the driving sub-circuit.

10. The pixel circuit according to claim 1, characterized in that: The first light emitting signal control terminal and the second light emitting signal control terminal are connected to the same signal line; The pixel driving circuit also includes a second reset sub-circuit, which is coupled to a third voltage terminal and the first terminal of the driving sub-circuit and is configured to respond to a signal from a second reset signal control terminal, write the voltage of the third voltage terminal to the first terminal of the driving sub-circuit in the first reset phase and / or the second reset phase, and reset the first terminal of the driving sub-circuit.

11. A driving method of a pixel circuit according to any one of claims 1 to 10, characterized in that: include: In the first reset stage, in response to the signal of the second light-emitting signal control terminal, the second light-emitting control subcircuit is controlled to be disconnected, and in response to the signal of the first reset signal control terminal, the control terminal of the driving subcircuit in the pixel circuit is reset by using the voltage of the second voltage terminal; In the second reset stage, in response to the signal of the first reset signal control terminal, the second end of the driving subcircuit is reset using the voltage of the second voltage terminal, so that a fixed voltage difference exists between the first end of the driving subcircuit and the second end of the driving subcircuit; In the data writing compensation stage, in response to the signal of the writing signal control terminal and the signal of the compensation signal control terminal, the data writing subcircuit and the compensation subcircuit in the pixel circuit are controlled to write data and perform threshold compensation on the driving subcircuit; In the light emitting stage, in response to the signal of the first light emitting signal control terminal and the signal of the second light emitting signal control terminal, the light emitting element is controlled and driven to emit light.

12. The driving method of the pixel circuit according to claim 11, characterized in that: The first light emitting signal control terminal and the second light emitting signal control terminal are connected to different signal lines; The driving method further comprises: In the first reset stage and / or the second reset stage, in response to a signal from the first light-emitting signal control terminal, the voltage of the first voltage terminal is written into the first terminal of the driving subcircuit to reset the first terminal of the driving subcircuit.

13. The driving method of the pixel circuit according to claim 11, characterized in that: The first light emitting signal control terminal and the second light emitting signal control terminal are connected to the same signal line; the pixel driving circuit further includes a second reset subcircuit, the second reset subcircuit is coupled to the third voltage terminal and the first terminal of the driving subcircuit; The driving method further comprises: In the first reset phase and / or the second reset phase, in response to a signal at the second reset signal control terminal, the voltage at the third voltage terminal is written into the first terminal of the driving sub-circuit to reset the first terminal of the driving sub-circuit.

14. A display device, characterized in that: A pixel circuit comprising the pixel circuit according to any one of claims 1 to 10.

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