Phase-gate-free modular multiplication circuit capable of being used for quantum key recovery attack

Abstract

The invention relates to the field of quantum computing and quantum cryptography, in particular to a modular multiplication circuit which can be used for quantum key recovery attack and does not contain a phase gate. Comprising the following steps: constructing a summing circuit required by + 1; constructing a + 1 circuit; a semi-classic carry unit is constructed; a semi-classic constant arithmetic addition circuit is constructed, and a semi-classic comparator is constructed; constructing a semi-classic constant modulus addition circuit based on a dichotomy; a semi-classic out-of-plane constant modular multiplication circuit is constructed; a semi-classic in-plane constant modular multiplication circuit is constructed; the circuit only comprises an X gate, a square root X gate, a CX gate and multiple CXs, so that the quantum circuit can be easily simulated on a classic computer, the correctness of the quantum circuit can be tested under the condition that a large number of computing resources do not exist, and meanwhile, the circuit can avoid the loss of computing precision caused by phase synthesis as much as possible.

Description

Technical Field

[0001] The invention relates to the fields of quantum computing and quantum cryptography, and in particular to a modular multiplication circuit without a phase gate that can be used for quantum key recovery attacks. Background Art

[0002] Quantum cryptography and quantum computing are two important branches of quantum information science. They both use the basic principles of quantum mechanics, such as superposition, entanglement and the uncertainty principle, to achieve advantages in information processing and communication.

[0003] Quantum computing uses quantum bits (qubits) as the basic unit of information and operates through quantum gates. Compared with classical computing, the main advantages of quantum computing are its parallelism and low energy consumption. Parallelism enables quantum computers to process a large amount of information at the same time, while low energy consumption makes quantum computers more advantageous when processing large-scale data.

[0004] Quantum cryptography, especially quantum key recovery attack, applies the basic principles of quantum mechanics, such as quantum entanglement and Heisenberg uncertainty principle, combined with the advantages of quantum computing, and uses quantum algorithms to attack classical cryptographic systems (such as RSA, ECC), providing people with a key recovery attack method based on quantum algorithms.

[0005] Most of the algorithmic circuits for quantum key recovery attacks proposed so far are based on phase gates, or are not based on quantum computing methods but on classical computing methods. There are still very few algorithmic circuits that are not based on phase gates. Summary of the invention

[0006] In order to solve the above problems, the present invention provides a modular multiplication circuit without phase gates that can be used for quantum key recovery attacks. The characteristics are that the designed quantum circuit does not contain phase gates, and adopts a semiclassical control method. The construction of the circuit includes the following steps:

[0007] S1. Use Figure 2 PG gate construction in Figure 1 The PGAdder circuit shown. The PGAdder circuit is used to calculate |b>|a>→|b+a>|a>, and does not receive the carry from the external input before the circuit is executed, nor does it output the carry of the highest bit after b+a;

[0008] S2. Use by Figure 1 The PGAdder circuit in the above example executes the generated PGSubtractor and X gates in reverse order to construct Figure 3The +1 circuit shown. This circuit is used to calculate |x>|g> → |x + 1>|g>, which does not receive the carry input externally before the circuit execution, nor does it output the carry of the highest bit after +1, and g is a qubit in an unknown state;

[0009] S3. Use X, CX, CCX to construct a semi - classical carry adder as Figure 4 . If there is a carry in b + a, then c4 = 1, otherwise there is no carry, where a is classically known, b is stored in a qubit, c4 is the highest bit of b + a, and g is in an unknown state;

[0010] S4. Based on the semi - classical carry adder in Figure 4 , construct a semi - classical comparator, and let this circuit perform subtraction, i.e., b - a. If c4 = 1, then b ≥ a; if c4 = 0, then b < a. Before constructing this comparator, the complement of - a needs to be calculated first, and a is classically known, b is stored in a qubit, and g is in an unknown state;

[0011] S5. Based on the binary - splitting idea, use the semi - classical carry adder in Figure 4 , and the +1 circuit in Figure 3 to construct a semi - classical constant addition circuit that calculates b + a, where a is classically known, b is stored in a qubit, and g is in an unknown state. The specific construction process of the semi - classical constant addition circuit (as shown in Figure 5 ) based on the binary - splitting idea is as follows:

[0012] Suppose we use 7 qubits to store b. First, based on the binary - splitting idea, we construct the tree - like diagram shown in Fig.10 :

[0013] The small numbers in the nodes represent the lower - order bits of the binary of b. The left child of the node represents the lower - order bit b l of b, and the right child of the node represents the higher - order bit b h of b. Then, in the order of level - order traversal, we perform the operations shown in Fig.11 on each node except the leaf nodes in this tree - like diagram, where carrier represents the semi - classical carry adder in Figure 4 :

[0014] Finally, for the leaf nodes, if the binary bit of a i corresponding to a qubit of b is 1, then we apply an X - gate to this qubit, otherwise do nothing;

[0015] S6. Use the semi - classical comparator in S4 and the semi - classical constant addition circuit in Figure 5 to construct a semi - classical constant modulo - addition circuit as shown in Figure 6 ;

[0016] S7. Use Figure 6 The semiclassical constant modulus addition circuit is constructed as Figure 7 The semiclassical out-of-place version of the constant modular multiplication circuit is constructed according to the following formula:

[0017]

[0018] S8. Use Figure 7 The semiclassical out-of-place version of the constant modular multiplication circuit uses classical modular inverse calculation and decomposition techniques to construct Figure 8 A semiclassical in-place version of a constant modular multiplication circuit;

[0019] Beneficial effects of the present invention:

[0020] The present invention proposes a modular multiplication circuit without phase gates that can be used for quantum key recovery attacks. The circuit can be easily simulated on a classical computer and its correctness can also be tested without a large amount of computing resources.

[0021] The present invention can avoid the loss of calculation accuracy caused by phase synthesis as much as possible.

[0022] The present invention has strong versatility and can theoretically perform any number of continuous modular multiplication calculations in the case of quantum hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 8 All basic quantum circuit diagrams required for a modular multiplication circuit without a phase gate that can be used for quantum key recovery attack provided by an embodiment of the present invention;

[0024] Figure 1 PGAdder circuit diagram provided by an embodiment of the present invention;

[0025] Figure 2 A PG gate circuit diagram of a circuit provided by an embodiment of the present invention;

[0026] Figure 3 The +1 circuit diagram provided by the embodiment of the present invention, wherein PGSubtractor is composed of Figure 1 The circuit in the figure is executed in reverse order, and g is in an unknown state;

[0027] Figure 4 A semi-classical carry circuit diagram provided by an embodiment of the present invention, a classically known i = 1, the part in the dotted box is inserted into the circuit b i The corresponding position, otherwise it is not inserted, c4 is the highest bit of b+a, and g is in an unknown state;

[0028] Figure 5 A semiclassical constant addition circuit diagram provided in an embodiment of the present invention, a is classically known, and g is in an unknown state;

[0029] Figure 6 A semi-classical constant modulus addition circuit diagram provided in an embodiment of the present invention, N and a are classically known, and cmp is Figure 4 The controlled circuit is transformed from the middle circuit. Figure 5 A controlled version of the mid-circuit;

[0030] Figure 7 A semi-classical out-of-place version of a constant modular multiplication circuit diagram provided by an embodiment of the present invention, wherein the controlled circuit is composed of Figure 6 Transformed;

[0031] Figure 8 A semi-classical in-place version of a constant modular multiplication circuit diagram provided by an embodiment of the present invention, wherein the modular multiplication circuit is composed of Figure 7 The circuit structure of SWAPs represents the circuit diagram of n consecutively acting switching gates;

[0032] Fig. 9 A quantum circuit for Shor's prime factorization algorithm provided by an embodiment of the present invention;

[0033] Fig.10 A tree diagram provided for an embodiment of the present invention;

[0034] Fig.11 A schematic diagram of node operation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The embodiment of the present invention provides a quantum circuit for Shor prime factorization, such as Fig. 9 Shown in and L is the binary length of j, j k is the kth digit of j in binary.

[0037] In one embodiment, the present invention is based on Figures 1 to 8 The required modular multiplication circuit is constructed, and the construction process is as follows:

[0038] S1. Use Figure 2The PG gate structure in Figure 1 The PGAdder circuit shown. The PGAdder circuit is used to calculate |b>|a> → |b + a>|a>, does not receive the carry input from outside before the circuit execution, and does not output the carry of the highest bit after b + a;

[0039] S2. Use the PGSubtractor generated by reversing the execution of the PGAdder circuit in Figure 1 and the X gate to construct the Figure 3 +1 circuit shown. This circuit is used to calculate |x>|g> → |x + 1>|g>, does not receive the carry input from outside before the circuit execution, does not output the carry of the highest bit after +1, and g is a qubit in an unknown state;

[0040] S3. Use X, CX, CCX to construct the semi - classical carry adder as shown in Figure 4 . If there is a carry in b + a, then c4 = 1, otherwise there is no carry, where a is classically known, b is stored in a qubit, c4 is the highest bit of b + a, and g is in an unknown state;

[0041] S4. Based on the Figure 4 semi - classical carry adder in, construct a semi - classical comparator, let the circuit perform subtraction, that is, b - a. If c4 = 1, then b ≥ a; if c4 = 0, then b < a. Before constructing this comparator, the complement code of -a needs to be calculated first, and a is classically known, b is stored in a qubit, and g is in an unknown state;

[0042] S5. Based on the binary idea, use the Figure 4 semi - classical carry adder in, and the Figure 3 +1 circuit in to construct a semi - classical constant addition circuit, which calculates b + a, where a is classically known, b is stored in a qubit, and g is in an unknown state. The specific construction process of the semi - classical constant addition circuit (as shown in Figure 5 ) based on the binary method idea is as follows:

[0043] Suppose we use 7 qubits to store b. First, based on the binary method idea, we first construct the Fig.10 tree - like diagram shown:

[0044] The small numbers in the nodes represent the low - order bits of b in binary. The left child of the node represents the low - order bit b l , and the right child of the node represents the high - order bit b h . Then, in the order of level - order traversal, we perform the following Fig.11 operation on each node in the tree - like diagram except the leaf nodes, where carrier represents the Figure 4 semi - classical carry adder in:

[0045] Finally, for a leaf node, if a corresponding to a qubit of b i If the binary bit is 1, we apply an X gate to this quantum bit, otherwise we do nothing;

[0046] S6. Use the semiclassical comparator in S4 and Figure 5 The semiclassical constant addition circuit is used to construct Figure 6 Semiclassical constant analog addition circuit;

[0047] S7. Use Figure 6 The semiclassical constant modulus addition circuit is constructed as Figure 7 The semiclassical out-of-place version of the constant modular multiplication circuit is constructed according to the following formula:

[0048]

[0049] S8. Use Figure 7 The semiclassical out-of-place version of the constant modular multiplication circuit uses classical modular inverse calculation and decomposition techniques to construct Figure 8 A semiclassical in-place version of a constant modular multiplication circuit;

[0050] S9. Application in cycle phase estimation Figure 8 A controlled version of the circuit is generated as Fig. 9 A quantum circuit for Shor's prime factorization algorithm

[0051] The above embodiments illustrate the advantages of the present invention. The design of the present invention avoids the use of a phase gate and also tries to avoid the loss of calculation accuracy caused by phase synthesis, while having a strong anti-noise capability.

[0052] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A modular multiplication circuit without phase gates that can be used for quantum key recovery attacks, characterized in that The designed quantum circuit does not contain a phase gate and adopts a semiclassical control method. The construction of the circuit includes the following steps: S1. Use the PG gates in Figure 2 to construct the PGAdder circuit shown in Figure 1. The PGAdder circuit is used to calculate |b>|a>→|b+a>|a>; S2. Use the PGSubtractor and X gate generated by the reverse execution of the PGAdder circuit in Figure 1 to construct the +1 circuit shown in Figure 3. The +1 circuit is used to calculate |x>|g>→|x+1>|g>; S3. Use X, CX, and CCX to construct a semiclassical carry generator as shown in Figure 4. If b+a has a carry, then c4=1, otherwise there is no carry, where c4 represents the highest bit of b+a; S4. Based on the semiclassical carry device in FIG4, a semiclassical comparator is constructed, and the circuit is made to perform a subtraction operation, that is, to perform ba. If c4=1, then b≥a. If c4=0, then b <a; S5. Based on the binary idea, the semiclassical carry device in FIG4 and the +1 circuit in FIG3 are used to construct a semiclassical constant addition circuit as shown in FIG5 . This circuit calculates |b>|g>→|b+a>|g>; S6. Use the semiclassical comparator in S4 and the semiclassical constant addition circuit in FIG. 5 to construct a semiclassical constant analog addition circuit as shown in FIG. 6; S7. Use the semiclassical constant modular addition circuit in FIG6 to construct a semiclassical out-of-place constant modular multiplication circuit as shown in FIG7; S8. Use the semiclassical out-of-place constant modular multiplication circuit in FIG7 to construct a semiclassical in-place constant modular multiplication circuit as shown in FIG8.

2. A modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 1, characterized in that: The PGAdder circuit in the circuit (as shown in FIG. 1 ) does not process the carry of the external input before the circuit is executed, nor does it generate the carry of the highest bit of the summation result.

3. The modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 1, characterized in that: The +1 circuit in this circuit (as shown in FIG3 ) does not process the carry of the external input before the execution of the circuit, nor does it generate the carry of the highest bit after +1, and g in this circuit is a quantum bit in an unknown state.

4. The modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 1, characterized in that: In the semiclassical carry unit in this circuit (as shown in FIG3 ), a is known classically, b is stored in the quantum bit, and g is in an unknown state.

5. The modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 1, characterized in that: The semiclassical comparator in the circuit (see step S4) needs to calculate the complement of -a before construction, and a is known classically, b is stored in the quantum bit, and g is in an unknown state.

6. A modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 1, characterized in that: In this circuit, the semiclassical constant addition circuit (as shown in Figure 5) has a known in a classical way, b stored in the quantum bit, and g in an unknown state. The specific construction process of the semiclassical constant addition circuit (as shown in Figure 5) based on the idea of ​​dichotomy is as follows: Assume that we use 7 qubits to store b. First, based on the idea of ​​dichotomy, we construct the tree diagram shown in Figure 10: The small number in the node represents the low bit of b in binary, and the left child of the node represents the low bit of b. l , the right child of the node represents the high bit b of b h Then, in the order of level-order traversal, we perform the following operations shown in Figure 11 on each node in the tree graph except the leaf nodes, where carrier represents the semiclassical carry in Figure 4: Finally, for a leaf node, if a corresponding to a qubit of b i If the binary bit of is 1, then we apply an X gate to this quantum bit, otherwise we do nothing.

7. The modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 1, characterized in that: The semiclassical out-of-place version of the constant modular multiplication circuit in this circuit is constructed according to the following formula:

8. The modular multiplication circuit without phase gates that can be used for quantum key recovery attack according to claim 7, characterized in that: The semiclassical in-place version of the constant modular multiplication circuit in this circuit (as shown in FIG. 8 ) requires the use of classical modular inverse calculations and decomposition techniques.

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