Asymmetric trench gate type display sensing module and manufacturing method thereof

Abstract

The invention relates to the technical field of display manufacturing, in particular to an asymmetric trench gate type display sensing module and a manufacturing method thereof. The asymmetric trench gate type display sensing module comprises a plurality of pixels, each pixel comprises a light-emitting area and an image sensing area, the light-emitting area comprises three light-emitting diodes, and the image sensing area comprises three image sensing units; the driving backboard is provided with a plurality of via holes which are regularly arranged, the light emitting diode and the image sensing unit cover at least one via hole, the driving backboard bears a plurality of pixels and drives the light emitting diode to emit light, and the light emitting diode emits light according to the configuration of the image sensing unit. According to the invention, the asymmetric trench gate type display sensing module is prepared and carried by using a semiconductor process, so that not only can the display functions of high resolution, high brightness, high contrast and low response time be realized, but also external full-color images can be received in real time, and a feasible scheme is provided for single-chip integration of interactive display.

Description

Technical Field

[0001] The present invention relates to the technical field of display manufacturing, and in particular to an asymmetric groove gate type display sensor module and a manufacturing method thereof. Background Art

[0002] As consumers pursue a better visual experience, high-definition display products are becoming more and more popular, which has driven display technology to develop in the direction of higher resolution, higher brightness, higher contrast and lower response time. However, if the display sensor module of the existing technology wants to receive full-color images from the outside world in real time, it needs to be processed by specific software simultaneously.

[0003] If an asymmetric groove gate display sensor module is used to integrate display and image sensing into one device, it can provide a practical solution for single-chip integration of interactive display. Summary of the invention

[0004] The technical problem to be solved by the present invention is: in order to solve the problems existing in the prior art in the above-mentioned background technology, an asymmetric trench gate type display sensor module and a manufacturing method thereof are provided.

[0005] The technical solution adopted by the present invention to solve the technical problem is: an asymmetric trench gate display sensor module, comprising: A plurality of pixels, each of the pixels comprising a light emitting area and an image sensing area, the light emitting area comprising three light emitting diodes, namely a red light emitting diode, a green light emitting diode and a blue light emitting diode, and the image sensing area comprising three image sensing units, namely a red image sensing unit, a green image sensing unit and a blue image sensing unit; A driving backplane, wherein the driving backplane is provided with a plurality of regularly arranged via holes, the light-emitting diode and the image sensing unit cover at least one of the via holes, the driving backplane carries a plurality of pixels and drives the light-emitting diode to emit light, and the light-emitting diode emits light according to the configuration of the image sensing unit; The light emitting diode and the image sensing unit both include an anode, a semiconductor device and an ITO thin film layer. The anode is located on the driving backplane and covers at least one via hole. The semiconductor device is located on a side of the anode away from the driving backplane. The semiconductor device comprises an N-type highly doped region and an N-type epitaxial layer, wherein the N-type highly doped region is located on a side of the anode away from a driving back plate, an N-type epitaxial layer is formed on the N-type highly doped region, ions are implanted on the N-type epitaxial layer to form an asymmetric P+ region, or ions are implanted on the N-type epitaxial layer to form a symmetric P+ region and an asymmetric groove is formed by etching, a gate oxide layer is provided on the surface of the groove, a polysilicon gate is deposited in the groove with the gate oxide layer, and a gate oxide layer is provided on the polysilicon gate.

[0006] Furthermore, the asymmetric P+ region includes a first P+ region located in the middle of the left half of the N-type epitaxial layer and a second P+ region located in the upper part of the right half, a P-well region is formed on the upper part of the first P+ region, an N+ region is formed on the P-well region, and the upper surface of the N+ region is flush with the upper surface of the second P+ region.

[0007] Furthermore, a groove is provided between the middle section of the plane where the upper surface of the N+ region is located and the plane where the upper surface of the first P+ region is located, a gate oxide layer is provided on the surface of the groove, a metal layer is provided above the plane where the upper surface of the N+ region is located, and an ITO thin film layer is provided on the metal layer.

[0008] Furthermore, a left P+ region, a middle P+ region and a right P+ region are formed on the N-type epitaxial layer, and grooves are formed by etching the right sides of the left P+ region and the middle P+ region. Polysilicon gates are deposited in the grooves and a gate oxide layer is provided on the surface.

[0009] Furthermore, a P- region is formed between the outer side of the groove and the adjacent P+ region, an N+ region is formed on the upper part of the P- region, a metal layer is provided above the plane where the upper surface of the P+ region is located, and an ITO thin film layer is provided on the metal layer.

[0010] Furthermore, the red light-emitting diode includes a P-pad layer, a P-GaAs layer, a MQW layer, an n-GaAs layer and an N-pad layer which are sequentially arranged on the ITO thin film layer, and the green light-emitting diode and the blue light-emitting diode both include a P-pad layer, a P-GaN layer, a MQW layer, an n-GaN layer and an N-pad layer which are sequentially arranged on the ITO thin film layer.

[0011] Furthermore, it also includes an interlayer dielectric layer, a common cathode and a thin film packaging layer, wherein the interlayer dielectric layer encapsulates and covers the semiconductor device, the ITO thin film layer, the light-emitting diode and the upper surface of the driving backplane, and an electrode groove is opened on the corresponding interlayer dielectric layer in the light-emitting diode and the image sensor unit; The common cathode is arranged on a layer of the interlayer dielectric layer away from the driving backplane and covers the electrode groove, and the common cathode contacts the upper surface of the image sensor unit through the electrode groove and contacts the upper surface of the light-emitting diode through the electrode groove; The thin film encapsulation layer is arranged on a side of the common cathode away from the driving back plate and covers the common cathode.

[0012] Furthermore, it also includes an RGB filter layer, a microlens and a glass packaging layer, wherein the RGB filter layer is arranged on a side of the thin film packaging layer away from the driving backplane in the image sensing area, and the RGB filter layer includes a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, wherein the red filter unit R, the green filter unit G and the blue filter unit B are arranged in sequence and spaced apart on the upper surface of the thin film packaging layer, and the red filter unit R, the green filter unit G and the blue filter unit B overlap with the projections of the semiconductor devices in the three image sensing units on the driving backplane respectively; the black matrix is ​​arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and the red filter unit R, the green filter unit G and the blue filter unit B are all provided with microlenses on the side away from the driving backplane; the glass packaging layer is arranged above the microlens and is bonded to the side of the thin film packaging layer away from the driving backplane by UV glue.

[0013] A method for manufacturing an asymmetric trench gate display sensor module is also mentioned, comprising the following steps: S1, forming a number of regularly arranged via holes on the driving backplane, and filling the via holes with conductive material, and then forming a number of anodes on the upper surface of the driving backplane, and each anode covers at least one via hole; S2, sequentially growing an N-type highly doped region and an N-type epitaxial layer on the driving back plate and the anode to form a semiconductor layer; S3, patterning the semiconductor layer so that the N-type high-doping region and the N-type epitaxial layer are divided into several blocks, and each block is consistent with the width of the anode; S4, ion implantation is performed in the middle of the left half and the upper part of the right half of the N-type epitaxial layer to obtain a first P+ region and a second P+ region; S5, ion implantation is performed above the first P+ region to form a P-well layer, and ion implantation is performed above the P-well region to obtain an N+ region; S6, etching a groove between the middle section of the plane where the upper surface of the N+ region is located and the plane where the upper surface of the first P+ region is located, and plating a gate oxide layer on the surface of the groove; S7, depositing a polysilicon gate and a thick gate oxide layer in the trench plated with the gate oxide layer, then plate a metal layer and an ITO thin film layer, growing a filling interlayer dielectric layer, and using a chemical mechanical polishing process to polish the interlayer dielectric layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the ITO thin film layer; S8, using mass transfer and vacuum bonding technology to connect the RGB LED chip integrating the red light-emitting diode, the green light-emitting diode and the blue light-emitting diode to the driving backplane; S9, setting a common cathode, growing and patterning a thin film encapsulation layer; S10, preparing an RGB filter layer in the image sensing area by using a yellow light process, and making microlenses on the red filter unit R, the green filter unit G and the blue filter unit B of the RGB filter layer, and finally using UV glue to bond the glass packaging layer to the top of the thin film packaging layer.

[0014] Another method for manufacturing an asymmetric trench gate display sensor module is also mentioned, comprising the following steps: Sa, forming a number of regularly arranged via holes on the driving backplane, and filling the via holes with a conductive material, and then forming a number of anodes on the upper surface of the driving backplane, and each anode covers at least one via hole; Sb, sequentially growing an N-type highly doped region and an N-type epitaxial layer on the driving back plate and the anode to form a semiconductor layer; Sc, patterning the semiconductor layer so that the N-type high-doped region and the N-type epitaxial layer are divided into several blocks, and each block is consistent with the width of the anode; Sd is ion-implanted into the left, middle and right positions of the N-type epitaxial layer to obtain a left P+ region, a middle P+ region and a right P+ region; Se, a groove is formed by etching the left P+ region and the right side of the middle P+ region, and a gate oxide layer is plated on the surface of the groove; Sf, depositing a polysilicon gate in the trench plated with a gate oxide layer and coating a layer of gate oxide layer for encapsulation; Sg, ion implantation is performed between the outer side of the trench and the adjacent P+ region to form a P- region, and ion implantation is performed on the upper part of the P- region to form an N+ region; Sh, forming a metal layer by PVD production on the plane where the upper surface of the P+ region is located, and coating an ITO thin film layer on the metal layer, growing and filling an interlayer dielectric layer, and smoothing the interlayer dielectric layer by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the ITO thin film layer; Si. Use mass transfer and vacuum bonding technology to connect the RGB LED chip integrating red light-emitting diodes, green light-emitting diodes and blue light-emitting diodes to the driving backplane; Sj, setting a common cathode, growing and patterning a thin film encapsulation layer; Sk, prepare the RGB filter layer in the image sensing area by yellow light process, and make microlenses on the red filter unit R, green filter unit G and blue filter unit B of the RGB filter layer, and finally use UV glue to bond the glass packaging layer to the top of the thin film packaging layer.

[0015] Beneficial effects of the present invention: The present invention uses semiconductor technology to prepare an asymmetric groove gate display sensor module, which can not only achieve display functions of high resolution, high brightness, high contrast and low response time, but also receive external full-color images in real time, providing a practical solution for single-chip integration of interactive display. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0017] Figure 1 It is a structural diagram of embodiment 1 of the present invention.

[0018] Figure 2 It is a schematic diagram of step 1 of embodiment 1 of the present invention.

[0019] Figure 3 It is a schematic diagram of step 2 of embodiment 1 of the present invention.

[0020] Figure 4 It is a schematic diagram of step 3 of embodiment 1 of the present invention.

[0021] Figure 5 It is a schematic diagram of step 4 of embodiment 1 of the present invention.

[0022] Figure 6 It is a schematic diagram of step 5 of embodiment 1 of the present invention.

[0023] Figure 7 It is a schematic diagram of step 6 of embodiment 1 of the present invention.

[0024] Figure 8 It is a schematic diagram of step 7 of embodiment 1 of the present invention.

[0025] Fig. 9 It is a schematic diagram of step 8 of embodiment 1 of the present invention.

[0026] Fig.10 It is a schematic diagram of step 9 of embodiment 1 of the present invention.

[0027] Fig.11 It is a schematic diagram of step 10 of the first embodiment of the present invention.

[0028] Fig.12 It is a structural diagram of embodiment 2 of the present invention.

[0029] Fig.13 It is a schematic diagram of step a of embodiment 2 of the present invention.

[0030] Fig.14 It is a schematic diagram of step b of embodiment 2 of the present invention.

[0031] Fig.15 It is a schematic diagram of step c of embodiment 2 of the present invention.

[0032] Fig.16 It is a schematic diagram of step d of embodiment 2 of the present invention.

[0033] Fig.17 It is a schematic diagram of step e of embodiment 2 of the present invention.

[0034] Fig.18 It is a schematic diagram of step f of embodiment 2 of the present invention.

[0035] Fig.19 It is a schematic diagram of step g of embodiment 2 of the present invention.

[0036] Fig. 20 It is a schematic diagram of step h of embodiment 2 of the present invention.

[0037] Fig.21 It is a schematic diagram of step i of embodiment 2 of the present invention.

[0038] Fig. 22 It is a schematic diagram of step j of embodiment 2 of the present invention.

[0039] Fig.23 It is a schematic diagram of step k of embodiment 2 of the present invention.

[0040] Fig.24 1 is a driving circuit diagram of Embodiment 1 and Embodiment 2 of the present invention.

[0041] In the figure: 1. Driving backplane; 2. Via hole; 3. Anode; 4. Semiconductor device; 41. N-type highly doped region; 42. N-type epitaxial layer; 43. P+ region; 431. First P+ region; 432. Second P+ region; 431′. Left P+ region; 432′. Middle P+ region; 433′. Right P+ region; 44. P-well region; 45. N+ region; 46. Metal layer; 47. P- region; 48. Gate oxide layer; 49. Polysilicon gate; 5. ITO thin film layer; 6. Interlayer dielectric layer; 7. Common cathode; 8. Thin film encapsulation layer; 9. RGB filter layer; 10. Microlens; 11. Glass encapsulation layer; 12. Light-emitting diode; 121. P-pad layer; 122. P-GaAs layer; 123. MQW layer; 124. n-GaAs layer; 125. N-pad layer; 126. P-GaN layer; 127. n-GaN layer; 13. Image sensing unit. DETAILED DESCRIPTION

[0042] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0043] Embodiment 1 like Figure 1 As shown, an asymmetric trench gate type display sensor module comprises: A plurality of pixels, each pixel comprising a light-emitting area and an image sensing area, the light-emitting area comprising three light-emitting diodes 12, namely a red light-emitting diode, a green light-emitting diode and a blue light-emitting diode, the image sensing area comprising three image sensing units 13, namely a red image sensing unit, a green image sensing unit and a blue image sensing unit; a driving backplane 1, the driving backplane 1 being provided with a plurality of regularly arranged vias 2, the light-emitting diodes and the image sensing unit 13 covering at least one via 2, the driving backplane 1 carrying a plurality of pixels and driving the light-emitting diodes to emit light 12, and the light-emitting diodes 12 emit light according to the configuration of the image sensing unit 13; the light-emitting diodes 12 and the image sensing unit 13 both comprising an anode 3, a semiconductor device 4 and an ITO thin film layer 5, the anode 3 being located on the driving backplane 1 and covering at least one via 2, the semiconductor device 4 being located on the side of the anode 3 away from the driving backplane 1.

[0044] It also includes: an interlayer dielectric layer 6, a common cathode 7 and a thin film packaging layer 8, the interlayer dielectric layer 6 encapsulates and covers the semiconductor device 4, the ITO thin film layer 5, the light-emitting diode 12 and the upper surface of the driving backplane 1, and an electrode groove is opened on the corresponding interlayer dielectric layer 6 in the light-emitting diode 12 and the image sensing unit 13; the common cathode 7 is arranged on a layer of the interlayer dielectric layer 6 away from the driving backplane 1 and covers the electrode groove, the common cathode 7 contacts with the upper surface of the image sensing unit 13 through the electrode groove, and contacts with the upper surface of the light-emitting diode 12 through the electrode groove; the thin film packaging layer 8 is arranged on the side of the common cathode 7 away from the driving backplane 1 and covers the common cathode 7.

[0045] The invention also includes: an RGB filter layer 9, a microlens 10 and a glass packaging layer 11. The RGB filter layer 9 is arranged on the side of the thin film packaging layer 8 away from the driving backplane 1 in the image sensing area. The RGB filter layer 9 includes a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix. The red filter unit R, the green filter unit G and the blue filter unit B are arranged in sequence and spaced apart on the upper surface of the thin film packaging layer 8. The red filter unit R, the green filter unit G and the blue filter unit B overlap with the projections of the semiconductor devices 4 in the three image sensing units 13 on the driving backplane 1 respectively; the black matrix is ​​arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and the red filter unit R, the green filter unit G and the blue filter unit B are all provided with microlenses 10 on the side away from the driving backplane 1; the glass packaging layer 11 is arranged above the microlens 10 and is bonded to the side of the thin film packaging layer 8 away from the driving backplane 1 by UV glue.

[0046] Among them, the semiconductor device 4 has an N-type high-doped region 41 and an N-type epitaxial layer 42, the N-type high-doped region 41 is located on the side of the anode 3 away from the driving backplane 1, an N-type epitaxial layer 42 is formed on the N-type high-doped region 41, and ion implantation is performed on the N-type epitaxial layer 42 to form an asymmetric P+ region 43. Specifically, the asymmetric P+ region 43 includes a first P+ region 431 located in the middle of the left half of the N-type epitaxial layer 42 and a second P+ region 432 located in the upper part of the right half, a P-well region 44 is formed on the upper part of the first P+ region 431, an N+ region 45 is formed on the P-well region 44, and the upper surface of the N+ region 45 is flush with the upper surface of the second P+ region 432. A groove is provided between the middle section of the plane where the upper surface of the N+ region 45 is located and the plane where the upper surface of the first P+ region 431 is located. A gate oxide layer 48 is provided on the surface of the groove. A metal layer 46 is provided above the plane where the upper surface of the N+ region 45 is located. An ITO thin film layer 5 is provided on the metal layer 46.

[0047] The red light-emitting diode includes a P-pad layer 121, a P-GaAs layer 122, a MQW layer 123, an n-GaAs layer 124 and an N-pad layer 125 which are sequentially arranged on the ITO thin film layer 5, and the green light-emitting diode and the blue light-emitting diode both include a P-pad layer 121, a P-GaN layer 126, a MQW layer 123, an n-GaN layer 127 and an N-pad layer 125 which are sequentially arranged on the ITO thin film layer 5.

[0048] The manufacturing method of the asymmetric trench gate display sensor module of the first embodiment is specifically as follows: Step 1: If Figure 2 As shown, a plurality of regularly arranged via holes 2 are formed on the driving back plate 1, and a conductive material is filled in the via holes 2, and then a plurality of anodes 3 are formed on the upper surface of the driving back plate 1, and each anode 3 covers at least one via hole 2; Step 2: If Figure 3 As shown, an N-type highly doped region 41 and an N-type epitaxial layer 42 are sequentially grown on the driving backplane 1 and the anode to form a semiconductor layer; Step 3: If Figure 4 As shown, the semiconductor layer is patterned so that the N-type highly doped region 41 and the N-type epitaxial layer 42 are divided into several blocks, and each block is consistent with the width of the anode 3; Step 4: Figure 5 As shown, ion implantation is performed in the middle of the left half and the upper part of the right half of the N-type epitaxial layer 42 to obtain a first P+ region 431 and a second P+ region 432; Step 5: Figure 6 As shown, ion implantation is performed above the first P+ region 431 to form a P-well layer 44, and ion implantation is performed above the P-well region 44 to obtain an N+ region 45; Step 6: Figure 7As shown, a groove is etched between the middle section of the plane where the upper surface of the N+ region 45 is located and the plane where the upper surface of the first P+ region 431 is located, and a gate oxide layer 48 is plated on the surface of the groove; Step 7: Figure 8 As shown, polysilicon 49 is deposited in the trench where the gate oxide layer 48 is plated, and a thick gate oxide layer 48 is deposited, and then a metal layer 46 and an ITO thin film layer 5 are plated, and an interlayer dielectric layer 6 is grown and filled, and the interlayer dielectric layer 6 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 6 is flush with the upper surface of the ITO thin film layer 5; Step 8: Fig. 9 As shown, the RGB LED chip integrating the red light-emitting diode, the green light-emitting diode and the blue light-emitting diode is connected to the driving backplane 1 by using mass transfer and vacuum bonding technology; Step 9: Fig.10 As shown, a common cathode 7 is provided, and a thin film encapsulation layer 8 is grown and patterned; Step 10: Fig.11 As shown, in the image sensing area, the RGB filter layer 9 is prepared by yellow light process, and microlenses 10 are made on the red filter unit R, green filter unit G and blue filter unit B of the filter layer 9. Finally, the glass packaging layer 11 is bonded to the thin film packaging layer 8 by UV glue. The current flow is shown by the orange arrow.

[0049] Embodiment 2 like Figure 12 to Figure 23 As shown, the difference from the first embodiment is that: a left P+ region 431′, a middle P+ region 432′ and a right P+ region 433′ are formed on the N-type epitaxial layer 42 in the semiconductor device 4, and a groove is formed by etching the right side of the left P+ region 431′ and the middle P+ region 432′, and a polysilicon gate 49 is deposited in the groove and a gate oxide layer 48 is provided on the surface. A P- region 47 is formed between the outer side of the groove and the adjacent P+ region 43, an N+ region 45 is formed on the upper part of the P- region 47, a metal layer 46 is provided above the plane where the upper surface of the P+ region 43 is located, and an ITO thin film layer 5 is provided on the metal layer 46.

[0050] The manufacturing method of the asymmetric trench gate display sensor module of the second embodiment is specifically as follows: Step a: Fig.13 As shown, a number of regularly arranged via holes 2 are formed on the driving back plate 1, and a conductive material is filled in the via holes. Subsequently, a number of anodes 3 are formed on the upper surface of the driving back plate 1, and each anode 3 covers at least one via hole 2; Step b: Fig.14 As shown, an N-type highly doped region 41 and an N-type epitaxial layer 42 are sequentially grown on the driving backplane 1 and the anode 3 to form a semiconductor layer; Step c: Fig.15As shown, the semiconductor layer is patterned so that the N-type highly doped region 41 and the N-type epitaxial layer 42 are divided into several blocks, and each block is consistent with the width of the anode 3; Step d: Fig.16 As shown, ion implantation is performed at the left, middle and right positions of the N-type epitaxial layer 41 to obtain a left P+ region 431′, a middle P+ region 432′ and a right P+ region 433′; Step e: Fig.17 As shown, a groove is formed by etching the right side of the left P+ region 431' and the middle P+ region 432', and a gate oxide layer 48 is plated on the surface of the groove; Step f: Fig.18 As shown, a polysilicon gate 49 is deposited in the trench coated with a gate oxide layer 48 and a layer of gate oxide layer 48 is plated for encapsulation; Step g: Fig.19 As shown, ion implantation is performed between the outer side of the trench and the adjacent P+ region 43 to form a P- region 47, and ion implantation is performed on the upper part of the P- region 47 to form an N+ region 45; Step h: Fig. 20 As shown, a metal layer 46 is formed by PVD (physical vapor deposition) on the plane where the upper surface of the P+ region 43 is located, and an ITO thin film layer 5 is plated on the metal layer 46, and an interlayer dielectric layer 6 is grown and filled, and the interlayer dielectric layer 6 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 6 is flush with the upper surface of the ITO thin film layer 5; Step i: Fig.21 As shown, the RGB LED chip integrating the red light-emitting diode, the green light-emitting diode and the blue light-emitting diode is connected to the driving backplane 1 by using mass transfer and vacuum bonding technology; Step j: Fig. 22 As shown, a common cathode 7 is provided, and a thin film encapsulation layer 8 is grown and patterned; Step k: Fig.23 As shown, in the image sensing area, an RGB filter layer 9 is prepared by a yellow light process, and microlenses 10 are made on the red filter unit R, the green filter unit G and the blue filter unit B of the RGB filter layer 9. Finally, a glass encapsulation layer 11 is bonded to the thin film encapsulation layer 8 by UV glue, and the current flow is shown by the orange arrow.

[0051] Embodiment 1 and embodiment 2 are matched as follows Fig.24 The driving circuit shown can improve the performance and reliability of the display, and has the beneficial effects of high integration, low power consumption, high speed and good stability, so that it has a wide range of applications.

[0052] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. An asymmetric trench gate display sensor module, characterized in that: include: A plurality of pixels, each pixel comprising a light emitting area and an image sensing area, the light emitting area comprising three light emitting diodes (12), namely a red light emitting diode, a green light emitting diode and a blue light emitting diode, and the image sensing area comprising three image sensing units (13), namely a red image sensing unit, a green image sensing unit and a blue image sensing unit; A driving backplane (1), wherein the driving backplane (1) is provided with a plurality of regularly arranged via holes (2), the light-emitting diode (12) and the image sensing unit (13) cover at least one of the via holes (2), the driving backplane (1) carries a plurality of pixels and drives the light-emitting diode (12) to emit light, and the light-emitting diode (12) emits light according to the configuration of the image sensing unit (13); The light-emitting diode (12) and the image sensing unit (13) both comprise an anode (3), a semiconductor device (4) and an ITO thin film layer (5); the anode (3) is located on the driving backplane (1) and covers at least one via hole (2); the semiconductor device (4) is located on a side of the anode (3) away from the driving backplane (1); The semiconductor device (4) comprises an N-type highly doped region (41) and an N-type epitaxial layer (42); the N-type highly doped region (41) is located on a side of the anode (3) away from the driving back plate (1); an N-type epitaxial layer (42) is formed on the N-type highly doped region (41); ions are implanted on the N-type epitaxial layer (42) to form an asymmetric P+ region (43); or ions are implanted on the N-type epitaxial layer (42) to form a symmetric P+ region (43) and then etched to form an asymmetric groove; a gate oxide layer (48) is provided on the surface of the groove; a polysilicon gate (49) is deposited in the groove with the gate oxide layer (48); and a gate oxide layer (48) is provided on the polysilicon gate (49).

2. The asymmetric trench gate display sensor module according to claim 1, characterized in that: The asymmetric P+ region (43) comprises a first P+ region (431) located in the middle of the left half of the N-type epitaxial layer (42) and a second P+ region (432) located in the upper part of the right half, a P-well region (44) is formed on the upper part of the first P+ region (431), an N+ region (45) is formed on the P-well region (44), and the upper surface of the N+ region (45) is flush with the upper surface of the second P+ region (432).

3. The asymmetric trench gate display sensor module according to claim 2, characterized in that: A groove is provided between the middle section of the plane where the upper surface of the N+ region (45) is located and the plane where the upper surface of the first P+ region (431) is located, a gate oxide layer (48) is provided on the surface of the groove, a metal layer (46) is provided above the plane where the upper surface of the N+ region (45) is located, and an ITO thin film layer (5) is provided on the metal layer (46).

4. The asymmetric trench gate display sensor module according to claim 1, characterized in that: A left P+ region (431′), a middle P+ region (432′) and a right P+ region (433′) are formed on the N-type epitaxial layer (42); grooves are formed by etching the right sides of the left P+ region (431′) and the middle P+ region (432′); polysilicon gates (49) are deposited in the grooves and a gate oxide layer (48) is provided on the surface.

5. The asymmetric trench gate display sensor module according to claim 4, characterized in that: A P-region (47) is formed between the outer side of the groove and the adjacent P+ region (43), an N+ region (45) is formed on the upper part of the P-region (47), a metal layer (46) is provided above the plane where the upper surface of the P+ region (43) is located, and an ITO thin film layer (5) is provided on the metal layer (46).

6. An asymmetric trench gate display sensor module according to claim 3 or 5, characterized in that: The red light-emitting diode comprises a P-pad layer (121), a P-GaAs layer (122), a MQW layer (123), an n-GaAs layer (124), and an N-pad layer (125) which are sequentially arranged on an ITO thin film layer (5); and the green light-emitting diode and the blue light-emitting diode both comprise a P-pad layer (121), a P-GaN layer (126), a MQW layer (123), an n-GaN layer (127), and an N-pad layer (125) which are sequentially arranged on an ITO thin film layer (5).

7. The asymmetric trench gate display sensor module according to claim 6, characterized in that: It also includes an interlayer dielectric layer (6), a common cathode (7) and a thin film packaging layer (8), wherein the interlayer dielectric layer (6) packages and covers the semiconductor device (4), the ITO thin film layer (5), the light-emitting diode (12) and the upper surface of the driving backplane (1), and an electrode groove is formed on the corresponding interlayer dielectric layer (6) in the light-emitting diode (12) and the image sensing unit (13); The common cathode (7) is arranged on a layer of the interlayer dielectric layer (6) away from the driving backplane (1) and covers the electrode groove, and the common cathode (7) contacts the upper surface of the image sensing unit (13) through the electrode groove, and contacts the upper surface of the light-emitting diode (12) through the electrode groove; The thin film encapsulation layer (8) is arranged on a side of the common cathode (7) away from the driving backplane (1) and covers the common cathode (7).

8. The asymmetric trench gate display sensor module according to claim 6, characterized in that: The invention also comprises an RGB filter layer (9), a microlens (10) and a glass encapsulation layer (11), wherein the RGB filter layer (9) is arranged on a side of the thin film encapsulation layer (8) in the image sensing area away from the driving backplane (1), and the RGB filter layer (9) comprises a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, wherein the red filter unit R, the green filter unit G and the blue filter unit B are arranged in sequence and spaced apart on the upper surface of the thin film encapsulation layer (8), and the red filter unit R, the green filter unit G and the blue filter unit B are arranged on the upper surface of the thin film encapsulation layer (8). The units B overlap with the projections of the semiconductor devices (4) in the three image sensing units (13) on the driving backplane (1); the black matrix is ​​arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and a microlens (10) is arranged on the side of the red filter unit R, the green filter unit G and the blue filter unit B away from the driving backplane (1); the glass encapsulation layer (11) is arranged above the microlens (10) and is bonded to the side of the thin film encapsulation layer (8) away from the driving backplane (1) by UV adhesive.

9. A method for manufacturing an asymmetric trench gate display sensor module as claimed in claim 3, characterized in that: The steps include: S1, forming a plurality of regularly arranged via holes (2) on a driving back plate (1), and filling the via holes (2) with a conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), with each anode (3) covering at least one via hole (2); S2, sequentially growing an N-type highly doped region (41) and an N-type epitaxial layer (42) on the driving back plate (1) and the anode (3) to form a semiconductor layer; S3, patterning the semiconductor layer so that the N-type high-doping region (41) and the N-type epitaxial layer (42) are divided into a plurality of blocks, and each block has the same width as the anode (3); S4, ion implantation is performed in the middle of the left half and the upper part of the right half of the N-type epitaxial layer (42) to obtain a first P+ region (431) and a second P+ region (432); S5, ion implantation is performed above the first P+ region (431) to form a P-well layer (44), and ion implantation is performed above the P-well region (44) to obtain an N+ region (45); S6, etching a groove between the middle section of the plane where the upper surface of the N+ region (45) is located and the plane where the upper surface of the first P+ region (431) is located, and coating a gate oxide layer (48) on the surface of the groove; S7, depositing a polysilicon gate (49) and a thick gate oxide layer (48) in the trench coated with the gate oxide layer (48), then coating a metal layer (46) and an ITO thin film layer (5), growing a filling interlayer dielectric layer (6), and using a chemical mechanical polishing process to polish the interlayer dielectric layer (6) so that the upper surface of the interlayer dielectric layer (6) is flush with the upper surface of the ITO thin film layer (5); S8, connecting the RGB LED chip integrating the red light emitting diode, the green light emitting diode and the blue light emitting diode to the driving backplane (1) by using mass transfer and vacuum bonding technology; S9, setting a common cathode (7), growing and patterning a thin film encapsulation layer (8); S10, preparing an RGB filter layer (9) in the image sensing area using a yellow light process, and manufacturing microlenses (10) on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer (9), and finally bonding the glass encapsulation layer (11) to the top of the thin film encapsulation layer (8) using UV glue.

10. A method for manufacturing an asymmetric trench gate display sensor module according to claim 5, characterized in that: The steps include: Sa, forming a plurality of regularly arranged via holes (2) on the driving back plate (1), and filling the via holes (2) with a conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), with each anode (3) covering at least one via hole (2); Sb, sequentially growing an N-type highly doped region (41) and an N-type epitaxial layer (42) on the driving back plate (1) and the anode to form a semiconductor layer; Sc, patterning the semiconductor layer so that the N-type high-doping region (41) and the N-type epitaxial layer (42) are divided into a plurality of blocks, and each block has the same width as the anode (3); Sd is ion-implanted at the left, middle and right positions of the N-type epitaxial layer (42) to obtain a left P+ region (431′), a middle P+ region (432′) and a right P+ region (433′); Se, a groove is formed by etching the right side of the left P+ region (431′) and the middle P+ region (432′), and a gate oxide layer (48) is plated on the surface of the groove; Sf, depositing a polysilicon gate (49) in a trench coated with a gate oxide layer (48) and coating a gate oxide layer (48) for packaging; Sg, ion implantation between the outer side of the trench and the adjacent P+ region (43) to form a P- region (47), and ion implantation on the upper part of the P- region (47) to form an N+ region (45); Sh, forming a metal layer (46) by PVD production on the plane where the upper surface of the P+ region (43) is located, and coating an ITO thin film layer (5) on the metal layer (46), growing a filling interlayer dielectric layer (6), and grinding the interlayer dielectric layer (6) by a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (6) is flush with the upper surface of the ITO thin film layer (5); Si, connecting the RGB LED chip integrating the red light emitting diode, the green light emitting diode and the blue light emitting diode to the driving backplane (1) by using mass transfer and vacuum bonding technology; Sj, setting a common cathode (7), growing and patterning a thin film encapsulation layer (8); Sk, in the image sensing area, an RGB filter layer (9) is prepared by a yellow light process, and microlenses (10) are made on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer (9), and finally a glass encapsulation layer (11) is bonded to the top of the thin film encapsulation layer (8) by using UV glue.

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