Computing task processing method and device and hybrid heterogeneous computing system

Abstract

The invention provides a computing task processing method and device and a hybrid heterogeneous computing system.The method comprises the steps that a kernel function corresponding to a computing task is disassembled into a plurality of sub-kernel functions according to relevant information of all acceleration chips and a basic execution model of all the acceleration chips, and the acceleration chips to which all the sub-kernel functions are to be sent are determined; respectively sending each sub-kernel function to a corresponding acceleration chip, and executing the sub-kernel function by the acceleration chip; according to the embodiment of the invention, flexible distributed hybrid execution of calculation tasks is realized; according to the method, the same calculation task can be processed in parallel by utilizing the calculation characteristics of different acceleration chips, and the optimal calculation performance of each type of acceleration chips is fully exerted.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and more particularly to a method and device for processing computing tasks and a hybrid heterogeneous computing system. Background Art

[0002] With the rapid development of applications such as artificial intelligence and big data, higher requirements are brought about for the computing power and timeliness of diversified massive data, which requires huge computing power for computing support. Limited by technical processes such as hardware architecture and communication bus, the computing power of traditional general-purpose central processing units (CPUs) tends to be saturated. Therefore, in order to improve computing performance, increase the flexibility and adaptability of the system, and thus meet the needs of different computing tasks, computing systems are developing towards heterogeneity and parallelization. Heterogeneity refers to the use of processors and accelerators that are different from the CPU architecture in computing systems to optimize the execution of specific computing tasks, such as graphics processing units (GPUs), domain-specific architecture chips (DSA), digital signal processors (DSPs), and tensor processing units (TPUs). These accelerators have higher performance and efficiency on specific tasks. By assigning tasks to processors and accelerators suitable for execution, heterogeneous computing systems can better utilize hardware resources and improve overall computing performance. Parallelization refers to breaking down a computing task into multiple subtasks and interconnecting multiple processor nodes or accelerator nodes to form a distributed parallel system on which these subtasks are executed. By distributing tasks to multiple computing nodes, multiple subtasks can be processed simultaneously, thereby speeding up the entire computing process.

[0003] The existing mainstream heterogeneous high-performance computing systems are mainly parallel systems that integrate multiple types of accelerator architectures. The heterogeneity of this system refers to the heterogeneity between the CPU and the accelerator, and the accelerator can only be one of the accelerators such as GPU, DSA, DSP or TPU, and does not support the mixed use of multiple accelerators. The existing computing task execution method is a static method.

[0004] With the prosperity of the intelligent computing field, more and more types of accelerators will be used, and heterogeneous high-performance computing systems will support the coexistence of CPU + more than one accelerator; for example, a hybrid heterogeneous high-performance computing system will have CPU + GPU + DSA + TPU, etc., and the servers are interconnected (thus the accelerators are interconnected). If the existing static method is still used to design and implement computing task execution, when migrating the application to other accelerators, the application needs to be redesigned and developed, which increases the difficulty of cross-architecture development and migration of applications; secondly, the static method does not support distributed hybrid execution of kernel functions (kernel). Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a method and device for processing computing tasks and a hybrid heterogeneous computing system to solve the problem that the existing static methods for computing tasks cannot be applied to hybrid heterogeneous high-performance computing systems.

[0006] In order to solve the above problems, an embodiment of the present application provides a method for processing a computing task, which is applied to a hybrid heterogeneous computing system including multiple acceleration chips, and the method includes:

[0007] According to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, the kernel function corresponding to the computing task is decomposed into multiple sub-kernel functions, and the acceleration chip to which each sub-kernel function is to be sent is determined;

[0008] Each sub-kernel function is sent to a corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

[0009] The relevant information of the acceleration chip includes at least one of the following:

[0010] The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory;

[0011] Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip;

[0012] The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

[0013] Wherein, the method further comprises:

[0014] A basic execution model of the acceleration chip is determined according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

[0015] The method of splitting the kernel function corresponding to the computing task into multiple sub-kernel functions according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, and determining the acceleration chip corresponding to each sub-kernel function, includes:

[0016] Determine the kernel function disassembly strategy based on the relevant information of each acceleration chip and the basic execution model of each acceleration chip;

[0017] According to the kernel function decomposition strategy, the kernel function is decomposed into a plurality of sub-kernel functions, and an acceleration chip corresponding to each sub-kernel function is determined.

[0018] The kernel function decomposition strategy satisfies at least one of the following:

[0019] The difference between the target times of each sub-kernel function is minimized;

[0020] The sum of the target times of each sub-kernel function is minimized;

[0021] Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

[0022] Before sending each sub-kernel function to the corresponding acceleration chip, the method further includes:

[0023] Modify each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent;

[0024] The changes include: instruction changes, and / or data structure changes.

[0025] Wherein, the method further comprises:

[0026] Obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation;

[0027] The execution results are integrated or restored into a target data structure, where the target data structure is used to indicate the execution results of the computing task.

[0028] Wherein, the method further comprises:

[0029] Monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation;

[0030] When the execution status indicates that at least one of the sub-kernel functions fails to execute, the sub-kernel functions are re-disassembled, and the re-disassembled sub-kernel functions are respectively sent to corresponding acceleration chips.

[0031] The present application also provides a computing task processing device, which is applied to a hybrid heterogeneous computing system including a plurality of acceleration chips, and the device includes:

[0032] A first processing module is used to decompose the kernel function corresponding to the computing task into multiple sub-kernel functions according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, and determine the acceleration chip to which each sub-kernel function is to be sent;

[0033] The sending module is used to send each sub-kernel function to the corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

[0034] The embodiment of the present application further provides a hybrid heterogeneous computing system, the hybrid heterogeneous computing system includes a plurality of acceleration chips, the hybrid heterogeneous computing system also includes a processor and a transceiver, the transceiver receives and sends data under the control of the processor, and the processor is used to perform the following operations:

[0035] According to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, the kernel function corresponding to the computing task is decomposed into multiple sub-kernel functions, and the acceleration chip to which each sub-kernel function is to be sent is determined;

[0036] Each sub-kernel function is sent to a corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

[0037] The relevant information of the acceleration chip includes at least one of the following:

[0038] The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory;

[0039] Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip;

[0040] The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

[0041] The processor is further configured to perform the following operations:

[0042] A basic execution model of the acceleration chip is determined according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

[0043] The processor is further configured to perform the following operations:

[0044] Determine the kernel function disassembly strategy based on the relevant information of each acceleration chip and the basic execution model of each acceleration chip;

[0045] According to the kernel function decomposition strategy, the kernel function is decomposed into a plurality of sub-kernel functions, and an acceleration chip corresponding to each sub-kernel function is determined.

[0046] The kernel function decomposition strategy satisfies at least one of the following:

[0047] The difference between the target times of each sub-kernel function is minimized;

[0048] The sum of the target times of each sub-kernel function is minimized;

[0049] Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

[0050] The processor is further configured to perform the following operations:

[0051] Modify each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent;

[0052] The changes include: instruction changes, and / or data structure changes.

[0053] The processor is further configured to perform the following operations:

[0054] Obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation;

[0055] The execution results are integrated or restored into a target data structure, where the target data structure is used to indicate the execution results of the computing task.

[0056] The processor is further configured to perform the following operations:

[0057] Monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation;

[0058] When the execution status indicates that at least one of the sub-kernel functions fails to execute, the sub-kernel functions are re-disassembled, and the re-disassembled sub-kernel functions are respectively sent to corresponding acceleration chips.

[0059] An embodiment of the present application also provides a hybrid heterogeneous computing system, including a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor implements the above-described processing method for computing tasks when executing the program.

[0060] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the processing method of the computing task as described above are implemented.

[0061] An embodiment of the present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the steps of the processing method of the computing task as described above.

[0062] The above technical solution of the present application has at least the following beneficial effects:

[0063] In the computing task processing method, device and hybrid heterogeneous computing system of the embodiment of the present application, the kernel function corresponding to the computing task is disassembled into multiple sub-kernel functions, and sent to the corresponding acceleration chip to perform the calculation, so as to realize the flexible distributed hybrid execution of the computing task; the method can use the computing characteristics of different acceleration chips to process the same computing task in parallel, giving full play to the optimal computing performance of each type of acceleration chip. On the one hand, it can complete the cross-architecture execution of kernel functions for more and more hybrid environments in the future; on the other hand, it can give full play to the synergistic efficiency of parallel computing of multiple heterogeneous acceleration chips, avoiding the performance loss caused by a large computing task waiting for a single type of acceleration chip for a long time to perform calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A flowchart showing a method for processing a computing task provided by an embodiment of the present application;

[0065] Figure 2 An example diagram showing a hybrid heterogeneous computing system in a method for processing computing tasks provided in an embodiment of the present application;

[0066] Figure 3 A schematic diagram showing the disassembly of a kernel function in a method for processing a computing task provided in an embodiment of the present application;

[0067] Figure 4 A schematic diagram showing the structure of a computing task processing device provided in an embodiment of the present application;

[0068] Figure 5A schematic diagram showing the structure of a hybrid heterogeneous computing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the technical problems, technical solutions and advantages to be solved by the present application clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0070] like Figure 1 As shown, an embodiment of the present application provides a method for processing a computing task, which is applied to a hybrid heterogeneous computing system including multiple acceleration chips, and the method includes:

[0071] Step 101, according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, the kernel function corresponding to the computing task is decomposed into multiple sub-kernel functions, and the acceleration chip to which each sub-kernel function is to be sent is determined;

[0072] Step 102: Send each sub-kernel function to a corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

[0073] Optionally, a kernel function can be called a kernel, and correspondingly, a sub-kernel function can also be called a kernel block.

[0074] Optionally, the hybrid heterogeneous computing system includes a CPU and one or more heterogeneous acceleration chips (such as GPU, DSA, NPU, TPU, etc.).

[0075] In the hybrid heterogeneous computing system provided in the embodiment of the present application, multiple accelerators with different architectures are selected to execute a kernel function. For example, a DSA chip with higher computing performance and a GPU chip that requires multiple iterative calculations are used simultaneously to process the same kernel function, and the processing results are integrated to give full play to the synergy between different accelerators and improve the efficiency of computing task processing.

[0076] In at least one embodiment of the present application, the relevant information of the acceleration chip includes at least one of the following:

[0077] The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory;

[0078] Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip;

[0079] The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

[0080] Optionally, as Figure 2 shown, the hybrid heterogeneous computing system in the embodiment of the present application includes a global device perception module, which supports perceiving relevant information of the acceleration chips in the current hybrid heterogeneous computing system. The relevant information of the acceleration chips includes but is not limited to static structure information, static topology information, dynamic operation information, etc., which are not specifically limited herein. This relevant information is used to support subsequent operations such as the distribution and transformation of kernel functions.

[0081] Optionally, for each acceleration chip, perceive the static structure information of its computing units and / or the static structure information of its memory. Among them, for the computing units, at least the following information needs to be obtained: {Static structure information of computing units: chip model, computing unit type, number of computing units, {list of computing instructions}, clock frequency, {supported computing precision}}; for the memory, at least the following information needs to be obtained: {Static structure information of memory: memory capacity, memory bit width, memory frequency, expected data structure}. If each acceleration chip contains multiple types of computing units and memory, the information of multiple pairs of [{computing unit, supporting memory}] is obtained in the form of an array. For example, taking the acceleration chip as a GPU chip, its relevant information includes {Static structure information of computing units: GF110, CUDA core - thread, 512, {add, mul, div, sin, cosine}, 830MHz, {FP16}}, and the supporting {Static structure information of memory: 2×1536MB, 2×384bit, 3414MHz, scalar}. Another example, taking the acceleration chip as a DSA chip, its relevant information includes {Static structure information of computing units: Zaitian VA10, Tensor core, 1, {add, cov, relu, softmax, matmul}, 600MHz, {INT8, FP16, BF16}}, and the supporting {Static structure information of memory: 32GB, 32*32bit, 1066MHz, Tensor{shape = x*y*z, 0 <= x < X, 0 <= y < Y, 0 <= z < Z (X, Y, Z are all constants)}}.

[0082] Optionally, for each acceleration chip, perceive static topology information such as the server information where it is located and the network interconnection information. Among them, for the server information where each acceleration chip is located, at least the following information needs to be obtained: {Server information where the chip is located: graphics card slot, server - graphics card interface, server - graphics card interface bandwidth, server external data plane interconnection interface information {type, bandwidth}}; the network interconnection of each acceleration chip mainly refers to the interconnection method with other chips, and the information needs to include at least: {Network interconnection information of the chip: whether to achieve external data plane interconnection through the server {yes / no}, direct chip connection {yes / no, direct connection type, direct connection bandwidth}}.

[0083] Optionally, for each acceleration chip, its current workload information, data access bandwidth information and other dynamic operation information are sensed, wherein the current workload information of each chip at least includes {chip workload: computing unit occupancy, occupied computing unit number, idle computing unit number, memory occupancy}; the data access bandwidth information refers to the actual bandwidth when the chip copies data.

[0084] In at least one embodiment of the present application, Figure 2 As shown, step 101 is executed by the kernel distribution control module of the hybrid heterogeneous computing system. The kernel distribution control module supports determining the kernel function disassembly control strategy based on the relevant information of the heterogeneous acceleration chip in the current hybrid heterogeneous computing system provided by the global device perception module, that is, how to disassemble the kernel function and data, which part of the kernel function and related data are sent to which chip for processing and execution; in addition, it also supports pushing the disassembled sub-kernel function to the next stage for execution and other operations.

[0085] As an optional embodiment, step 101 includes:

[0086] Determine the kernel function disassembly strategy based on the relevant information of each acceleration chip and the basic execution model of each acceleration chip;

[0087] According to the kernel function decomposition strategy, the kernel function is decomposed into a plurality of sub-kernel functions, and an acceleration chip corresponding to each sub-kernel function is determined.

[0088] The kernel function decomposition strategy satisfies at least one of the following:

[0089] The difference between the target times of each sub-kernel function is minimized;

[0090] The sum of the target times of each sub-kernel function is minimized;

[0091] Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

[0092] Optionally, the kernel distribution control module uses the basic execution model of each type of acceleration chip and related information of the acceleration chip to comprehensively determine how many sub-kernel functions the kernel function is decomposed into according to different basic execution models, and each sub-kernel function is sent to a certain chip for specific execution. The kernel function decomposition strategy must meet at least one of the following:

[0093] ① Each sub-kernel function is sent to different acceleration chips (first time), each acceleration chip is executed for calculation (second time), and the result is synchronized back to the host side after the execution is completed (third time). The total time consumption of these three steps is relatively balanced, avoiding the situation where a sub-kernel function waits for a long time for another sub-kernel function to be sent for synchronization after the execution is completed. For example, the following formula can be used to express it:

[0094]

[0095] Where n represents the number of sub-kernel functions that are split; T delivery (i) represents the first time corresponding to the i-th sub-kernel function, T calculate (i) represents the second time corresponding to the i-th sub-kernel function, T synchronize (i) represents the third time corresponding to the i-th sub-kernel function; T delivery (i+1) represents the first time corresponding to the i+1th sub-kernel function; T calculate (i+1) represents the second time corresponding to the i+1th sub-kernel function; T synchronize (i+1) represents the third time corresponding to the i+1th sub-kernel function.

[0096] Among them, i and Kernel_size(i) are the results to be obtained, n represents the number of sub-kernel functions, and the time it takes for the i-th sub-kernel function to be sent to different chips is T. delivery (i) Depends on {memory information, chip server information, network interconnection information, chip data access bandwidth} obtained by the global device perception module; the sub-kernel function is executed on each chip The time T calculate (i) Depends on {basic execution model, current chip workload}. Considering that some computing units of each chip may be occupied by other computing tasks, the basic execution model will be converted according to the proportion of the current chip workload when used to calculate the time consumption. After the execution is completed, the time consumption of synchronizing the results back to the host side is T synchronize (i) Depends on {memory information, chip server information, and chip data access bandwidth}.

[0097] ②The total execution time of the kernel function should be as short as possible, which can be expressed by the following formula:

[0098]

[0099] Where n represents the number of sub-kernel functions that are split; T delivery (i) represents the first time corresponding to the i-th sub-kernel function, T calculate (i) represents the second time corresponding to the i-th sub-kernel function, T synchronize (i) represents the third time corresponding to the i-th sub-kernel function.

[0100] For example, the final decomposition effect of the kernel function is as follows Figure 3 As shown, the kernel function is decomposed into four sub-kernel functions, one sub-kernel function is sent to GPGPU1 for execution, one sub-kernel function is sent to DSA1 for execution, one sub-kernel function is sent to DSA2 for execution, and one sub-kernel function is sent to DSA3 for execution.

[0101] Optionally, the steps for determining the kernel function basic execution model are as follows:

[0102] A basic execution model of the acceleration chip is determined according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

[0103] For example, for each acceleration chip, the basic execution model is defined only based on its minimum computing unit, the data structure that can be processed by the minimum computing unit, and the computing instruction list supported by the minimum computing unit.

[0104] Taking GPU chip as an example, the smallest computing unit of GPU chip is: a CUDA core, which is equivalent to a Thread, and can process 1 scalar; the data structure that can be processed by the smallest computing unit is: scalar; the computing instruction list supported by the smallest computing unit is: {add, add, mul, div, sin, cosine}. The total number of computing units in a single chip is X, and each time it supports parallel computing of X scalars.

[0105] Taking the DSA chip as an example, the smallest computing unit of the DSA chip is a Tensor core; a Tensor core can process x*y*z scalars; the data structure that the smallest computing unit can process is a tensor; the computing instruction list supported by the smallest computing unit is {add, cov, relu, softmax, matmul}. The total number of computing units in a single chip is 1, and the number of parallel computing Tensors supported each time is 1, and a Tensor can carry x*y*z scalars.

[0106] The minimum computing unit of the above-mentioned GPU chip and the minimum computing unit of the DSA chip support different lists of computing instructions; if the kernel function is to perform addition calculations, without considering data accuracy, the number of kernel functions that can be executed at one time by the DSA chip is x*y*z times that of the GPU chip; if the kernel function is to perform convolution, the number of kernel functions that can be executed at one time by the DSA chip will also be a multiple of that of the GPU chip.

[0107] In at least one embodiment of the present application, before step 102, the method further includes:

[0108] Modify each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent;

[0109] The changes include: instruction changes, and / or data structure changes.

[0110] Alternatively, if Figure 2 As shown, the hybrid heterogeneous computing system provided by the embodiment of the present application also includes a kernel conversion module, which can complete the kernel function change according to the characteristics of the chip computing unit, specifically including instruction change and data structure change. After the kernel function uniformly expressed in the application source code is disassembled, each sub-kernel function is converted into a new sub-kernel function that can be recognized and calculated by the target chip to which the sub-kernel function is intended to be issued (or sent).

[0111] The instruction change is to translate the mathematical calculation content expressed by the original kernel function into the calculation method that is most suitable for this chip. For example, the original kernel function describes the convolution calculation in detail from the scalar dimension with GPGPU as the final execution chip. When changing to the DSA chip, all the calculation details can be simply translated into a cov instruction; if the original kernel function roughly describes the convolution calculation from the tensor dimension with DSA as the final execution chip, that is, the kernel function is described in the form of a simple cov interface + tensor, then when changing to the GPGPU chip, the cov interface can be expanded to a series of detailed convolution calculations including add and mul instructions. The data change is to convert the data object calculated by the original kernel function into the most suitable data structure for the target chip for each sub-kernel function according to the result of the kernel function splitting. The data change generally includes the conversion of data_shape, data_count, and data_type. For example, the DSA chip mainly accepts integer tensors. For floating-point scalar or vector inputs, data quantization can be performed first, and multiple scalars or vectors can be merged into tensors.

[0112] In at least one embodiment of the present application, the method further includes:

[0113] Monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation;

[0114] When the execution status indicates that at least one of the sub-kernel functions fails to execute, the sub-kernel functions are re-disassembled, and the re-disassembled sub-kernel functions are respectively sent to corresponding acceleration chips.

[0115] For example, Figure 2As shown, the hybrid heterogeneous computing system provided by the embodiment of the present application also includes an execution tracking module, which tracks the execution status of each sub-kernel function sent to a specific acceleration chip for calculation, maintains a mapping table of [sub-kernel function, sent chip], provides execution stages {H2D (memory copied from CPU to GPU device) data copy, calculation execution, D2H (memory copied from GPU device to CPU) data copy}, execution results {Success, Failed, Pending}, and generates logs and alarms in real time according to the execution results. Once a fault such as Failed or Pending occurs for a long time, it is necessary to interact with the Kernel distribution control module in time to redistribute the sub-kernel function that is currently unsuccessful in execution.

[0116] In another optional embodiment of the present application, the method further includes:

[0117] Obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation;

[0118] The execution results are integrated or restored into a target data structure, where the target data structure is used to indicate the execution results of the computing task.

[0119] For example, Figure 2 As shown, the hybrid heterogeneous computing system provided in the embodiment of the present application also includes a data integration module, which obtains the execution results of all distributed execution sub-kernel functions and integrates / restores them into a target data structure.

[0120] In order to more clearly describe the processing method of the computing task provided in the embodiment of the present application, an example is provided below for explanation. Figure 2 As shown, the dynamic execution method of computing tasks for a hybrid heterogeneous computing system includes:

[0121] 1. The global device perception module perceives the static structure information, static topology information, dynamic operation information, etc. of the global acceleration chip;

[0122] 2. When a computing task is issued, the kernel distribution control module obtains relevant information of the acceleration chip, completes the kernel function disassembly strategy design, and triggers the issuance of the sub-kernel function;

[0123] 3. The kernel conversion module converts the sub-kernel function into the most suitable kernel function structure for the corresponding chip according to the kernel function disassembly strategy;

[0124] 4. The execution tracking module monitors the execution of kernel functions;

[0125] 5. The execution tracking module reports the abnormal situation to the kernel distribution control module;

[0126] 6. For abnormally executed sub-kernel functions, the kernel distribution control module redesigns the disassembly strategy, distributes the sub-kernel functions, and transforms the kernel functions, i.e. repeats steps 1, 2, 3, and 4 until the sub-kernel function is successfully executed;

[0127] 7. The data integration module unifies the computational structures of each sub-kernel function.

[0128] In summary, the embodiments of the present application are directed to the issuance of computing tasks for hybrid heterogeneous computing systems, and can utilize the computing characteristics of different acceleration chips to process the same computing task in parallel, giving full play to the optimal computing performance of each type of acceleration chip. On the one hand, it can be oriented towards the increasingly hybrid environments in the future, completing the cross-architecture execution of kernel functions; on the other hand, it can give full play to the synergistic efficiency of parallel computing of multiple heterogeneous acceleration chips, avoiding the performance loss caused by a large computing task waiting for a single type of acceleration chip for a long time to perform calculations, and can also be used as a technology for the arbitrary flow and rapid calculation of computing tasks in the computing power network.

[0129] like Figure 4 As shown, an embodiment of the present application further provides a computing task processing device, which is applied to a hybrid heterogeneous computing system including multiple acceleration chips, and the device includes:

[0130] The first processing module 401 is used to decompose the kernel function corresponding to the computing task into multiple sub-kernel functions according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, and determine the acceleration chip to which each sub-kernel function is to be sent;

[0131] The sending module 402 is used to send each sub-kernel function to the corresponding acceleration chip, so that the acceleration chip executes the sub-kernel function.

[0132] As an optional embodiment, the relevant information of the acceleration chip includes at least one of the following:

[0133] The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory;

[0134] Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip;

[0135] The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

[0136] As an optional embodiment, the device further includes:

[0137] A determination module is used to determine a kernel function basic execution model of the acceleration chip according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

[0138] As an optional embodiment, the first processing module includes:

[0139] The first submodule is used to determine the kernel function disassembly strategy according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip;

[0140] The second submodule is used to decompose the kernel function into multiple sub-kernel functions according to the kernel function decomposition strategy, and determine the acceleration chip corresponding to each sub-kernel function.

[0141] As an optional embodiment, the kernel function decomposition strategy satisfies at least one of the following:

[0142] The difference between the target times of each sub-kernel function is minimized;

[0143] The sum of the target times of each sub-kernel function is minimized;

[0144] Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

[0145] As an optional embodiment, the device further includes:

[0146] A conversion module, used to change each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent;

[0147] The changes include: instruction changes, and / or data structure changes.

[0148] As an optional embodiment, the device further includes:

[0149] An acquisition module is used to obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation;

[0150] An integration module is used to integrate or restore the execution results into a target data structure, and the target data structure is used to indicate the execution results of the computing task.

[0151] As an optional embodiment, the device further includes:

[0152] A monitoring module is used to monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation;

[0153] The second processing module is used to re-disassemble the sub-kernel function when the execution status indicates that at least one of the sub-kernel functions has failed to execute, and send the re-disassembled sub-kernel functions to the corresponding acceleration chips respectively.

[0154] The embodiment of the present application decomposes the kernel function corresponding to the computing task into multiple sub-kernel functions, and sends them to the corresponding acceleration chip for computing, so as to realize flexible distributed hybrid execution of computing tasks; this method can utilize the computing characteristics of different acceleration chips to process the same computing task in parallel, giving full play to the optimal computing performance of each type of acceleration chip. On the one hand, it can complete the cross-architecture execution of kernel functions for the increasingly mixed environments in the future; on the other hand, it can give full play to the synergistic efficiency of parallel computing of multiple heterogeneous acceleration chips, avoiding the performance loss caused by a large computing task waiting for a single type of acceleration chip for a long time to perform computing.

[0155] It should be noted that the processing device for computing tasks provided in the embodiment of the present application is a device capable of executing the processing method for the above-mentioned computing tasks. All embodiments of the processing method for the above-mentioned computing tasks are applicable to the device and can achieve the same or similar beneficial effects, which will not be repeated here.

[0156] like Figure 5 As shown, the embodiment of the present application further provides a hybrid heterogeneous computing system, the hybrid heterogeneous computing system includes multiple acceleration chips, the hybrid heterogeneous computing system also includes a processor 500 and a transceiver 510, the transceiver 510 receives and sends data under the control of the processor 500, and the processor 500 is used to perform the following operations:

[0157] According to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, the kernel function corresponding to the computing task is decomposed into multiple sub-kernel functions, and the acceleration chip to which each sub-kernel function is to be sent is determined;

[0158] Each sub-kernel function is sent to a corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

[0159] As an optional embodiment, the relevant information of the acceleration chip includes at least one of the following:

[0160] The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory;

[0161] Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip;

[0162] The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

[0163] As an optional embodiment, the processor is further configured to perform the following operations:

[0164] A basic execution model of the acceleration chip is determined according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

[0165] As an optional embodiment, the processor is further configured to perform the following operations:

[0166] Determine the kernel function disassembly strategy based on the relevant information of each acceleration chip and the basic execution model of each acceleration chip;

[0167] According to the kernel function decomposition strategy, the kernel function is decomposed into a plurality of sub-kernel functions, and an acceleration chip corresponding to each sub-kernel function is determined.

[0168] As an optional embodiment, the kernel function decomposition strategy satisfies at least one of the following:

[0169] The difference between the target times of each sub-kernel function is minimized;

[0170] The sum of the target times of each sub-kernel function is minimized;

[0171] Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

[0172] As an optional embodiment, the processor is further configured to perform the following operations:

[0173] Modify each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent;

[0174] The changes include: instruction changes, and / or data structure changes.

[0175] As an optional embodiment, the processor is further configured to perform the following operations:

[0176] Obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation;

[0177] The execution results are integrated or restored into a target data structure, where the target data structure is used to indicate the execution results of the computing task.

[0178] As an optional embodiment, the processor is further configured to perform the following operations:

[0179] Monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation;

[0180] When the execution status indicates that at least one of the sub-kernel functions fails to execute, the sub-kernel functions are re-disassembled, and the re-disassembled sub-kernel functions are respectively sent to corresponding acceleration chips.

[0181] The embodiment of the present application decomposes the kernel function corresponding to the computing task into multiple sub-kernel functions, and sends them to the corresponding acceleration chip for computing, so as to realize flexible distributed hybrid execution of computing tasks; this method can utilize the computing characteristics of different acceleration chips to process the same computing task in parallel, giving full play to the optimal computing performance of each type of acceleration chip. On the one hand, it can complete the cross-architecture execution of kernel functions for the increasingly mixed environments in the future; on the other hand, it can give full play to the synergistic efficiency of parallel computing of multiple heterogeneous acceleration chips, avoiding the performance loss caused by a large computing task waiting for a single type of acceleration chip for a long time to perform computing.

[0182] It should be noted that the hybrid heterogeneous computing system provided in the embodiment of the present application is a system capable of executing the processing method of the above-mentioned computing tasks. All embodiments of the processing method of the above-mentioned computing tasks are applicable to the system and can achieve the same or similar beneficial effects, which will not be repeated here.

[0183] An embodiment of the present application also provides a hybrid heterogeneous computing system, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, each process in the embodiment of the processing method for the computing task as described above is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0184] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, each process in the processing method embodiment of the computing task described above is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0185] An embodiment of the present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the various processes of the processing method embodiment of the computing task as described above, and can achieve the same technical effect. To avoid repetition, they are not repeated here.

[0186] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0187] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A device that specifies functions in one or more processes and / or one or more blocks.

[0188] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable storage medium produce a paper product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0189] These computer program instructions may also be loaded onto a computer or other programmable data processing device to cause the computer or other programmable device to execute a series of operating steps to produce a computer-implemented process, thereby providing instructions executed on the computer or other programmable device for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0190] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for processing a computing task, characterized in that: Applied to a hybrid heterogeneous computing system including multiple acceleration chips, the method includes: According to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, the kernel function corresponding to the computing task is decomposed into multiple sub-kernel functions, and the acceleration chip to which each sub-kernel function is to be sent is determined; Each sub-kernel function is sent to a corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

2. The method according to claim 1, characterized in that: The relevant information of the acceleration chip includes at least one of the following: The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory; Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip; The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

3. The method according to claim 1, characterized in that The method further comprises: A basic execution model of the acceleration chip is determined according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

4. The method according to claim 1 or 2, characterized in that: The step of splitting the kernel function corresponding to the computing task into multiple sub-kernel functions according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, and determining the acceleration chip corresponding to each sub-kernel function, includes: Determine the kernel function disassembly strategy based on the relevant information of each acceleration chip and the basic execution model of each acceleration chip; According to the kernel function decomposition strategy, the kernel function is decomposed into a plurality of sub-kernel functions, and an acceleration chip corresponding to each sub-kernel function is determined.

5. The method according to claim 4, characterized in that The kernel function decomposition strategy satisfies the following two conditions: The difference between the target times of each sub-kernel function is minimized; The sum of the target times of each sub-kernel function is minimized; Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

6. The method according to claim 1, characterized in that Before sending each sub-kernel function to the corresponding acceleration chip, the method further includes: Modify each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent; The changes include: instruction changes, and / or data structure changes.

7. The method according to claim 1, characterized in that The method further comprises: Obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation; The execution results are integrated or restored into a target data structure, where the target data structure is used to indicate the execution results of the computing task.

8. The method according to claim 1, characterized in that The method further comprises: Monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation; When the execution status indicates that at least one of the sub-kernel functions fails to execute, the sub-kernel functions are re-disassembled, and the re-disassembled sub-kernel functions are respectively sent to corresponding acceleration chips.

9. A computing task processing device, characterized in that: Applied to a hybrid heterogeneous computing system including multiple acceleration chips, the device includes: A first processing module is used to decompose the kernel function corresponding to the computing task into multiple sub-kernel functions according to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, and determine the acceleration chip to which each sub-kernel function is to be sent; The sending module is used to send each sub-kernel function to the corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

10. A hybrid heterogeneous computing system, comprising a plurality of acceleration chips, a processor and a transceiver, wherein the transceiver receives and sends data under the control of the processor, characterized in that: The processor is configured to perform the following operations: According to the relevant information of each acceleration chip and the basic execution model of each acceleration chip, the kernel function corresponding to the computing task is decomposed into multiple sub-kernel functions, and the acceleration chip to which each sub-kernel function is to be sent is determined; Each sub-kernel function is sent to a corresponding acceleration chip, and the acceleration chip executes the sub-kernel function.

11. The system according to claim 10, characterized in that The relevant information of the acceleration chip includes at least one of the following: The static structure information of the acceleration chip; the static structure information includes: static parameters of the computing unit, and / or static parameters of the memory; Static topology information of the acceleration chip; the static topology information includes: information of the server where the acceleration chip is located, and / or interconnection topology information of the acceleration chip; The dynamic operation information of the acceleration chip includes: current workload information of the acceleration chip and / or real-time bandwidth of data access of the acceleration chip.

12. The system according to claim 10, characterized in that The processor is further configured to perform the following operations: A basic execution model of the acceleration chip is determined according to a minimum computing unit of the acceleration chip, a data structure processable by the minimum computing unit, and a computing instruction supported by the minimum computing unit.

13. The system according to claim 10 or 11, characterized in that: The processor is further configured to perform the following operations: Determine the kernel function disassembly strategy based on the relevant information of each acceleration chip and the basic execution model of each acceleration chip; According to the kernel function decomposition strategy, the kernel function is decomposed into a plurality of sub-kernel functions, and an acceleration chip corresponding to each sub-kernel function is determined.

14. The system according to claim 13, characterized in that The kernel function decomposition strategy satisfies at least one of the following: The difference between the target times of each sub-kernel function is minimized; The sum of the target times of each sub-kernel function is minimized; Among them, the target time of each sub-kernel function is the sum of the first time, the second time and the third time; the first time is the time when the sub-kernel function is sent to the acceleration chip, the second time is the time when the sub-kernel function is executed and calculated in the acceleration chip, and the third time is the time when the execution result is synchronized after the sub-kernel function is executed.

15. The system according to claim 10, characterized in that The processor is further configured to perform the following operations: Modify each sub-kernel function and convert the sub-kernel function into a new sub-kernel function that can be recognized and calculated by the acceleration chip to which the sub-kernel function is to be sent; The changes include: instruction changes, and / or data structure changes.

16. The system according to claim 10, characterized in that The processor is further configured to perform the following operations: Obtain the execution results of each sub-kernel function sent to the acceleration chip for calculation; The execution results are integrated or restored into a target data structure, where the target data structure is used to indicate the execution results of the computing task.

17. The system according to claim 10, characterized in that The processor is further configured to perform the following operations: Monitor the execution status of each sub-kernel function sent to the acceleration chip for calculation; When the execution status indicates that at least one of the sub-kernel functions fails to execute, the sub-kernel functions are re-disassembled, and the re-disassembled sub-kernel functions are respectively sent to corresponding acceleration chips.

18. A hybrid heterogeneous computing system, comprising a memory, a processor, and a program stored in the memory and executable on the processor; characterized in that: When the processor executes the program, the method for processing a computing task as described in any one of claims 1 to 8 is implemented.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the method for processing a computing task as described in any one of claims 1 to 8 are implemented.

20. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of the method for processing a computing task as described in any one of claims 1 to 8.

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