Integrated circuit bus I2C slave device, system and wake-up method

Abstract

The present invention relates to an integrated circuit bus I2C slave device, system, and wake-up method. When the I2C slave device is in a low-power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned off. After the I2C communication module receives a device address match, or when the partial wake-up enable configured in the I2C communication module is turned on, the I2C communication module receives a device address and the address matches, and the received register access address is greater than or equal to the wake-up address configured in the I2C communication module. The I2C communication module generates a wake-up signal and outputs it to the system control module and the system-on-chip (SoC), recovers the system clock, and the SoC exits the low-power mode after receiving the wake-up signal. The present invention can enter a low-power state when idle, saving power consumption. During I2C communication, the I2C slave device can be awakened non-sensingly and selectively, and data transmission can also be completed in a low-power state.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an integrated circuit bus I2C slave device, system, and wake-up method. Background Art

[0002] When a slave device system based on the integrated circuit bus I2C is idle and receives a command indicating entry into a low-power state, the entire system enters a low-power state to save power. In this low-power state, the master device initiates I2C communication to wake up the system. When a wake-up signal indicating exit from the low-power state is generated, the entire system exits the low-power state. There are two main methods for waking up a system based on I2C communication in the prior art: 1. During the communication process, after the slave device detects the I2C start signal, it generates a wake-up signal to wake up the system. 2. During the communication process, after the slave device receives the device address and the device address matches, it generates a wake-up signal to wake up the system.

[0003] In the first wake-up method of the prior art, if there are multiple slave devices on the integrated circuit bus I2C, as long as the master device initiates communication, each slave device will detect the start signal, and all slave devices will be awakened. In the second wake-up method, each time a communication is performed, as long as the slave device receives a matching device address, the system will be awakened. In addition, in the process of waking up the system with both of these prior art methods, the slave device needs to use the clock stretching mechanism in the I2C protocol to keep the serial clock line SCL in a low state, thereby lengthening the clock cycle and forcing the master device to suspend data transmission to ensure that the slave device has enough time to wake up the system. Only after the slave device system wakes up and the clock recovers, the serial clock line SCL is released, and data transmission can continue.

[0004] Existing technologies fail to meet the needs of an I2C master device selectively waking up a slave system when the slave system is in a low-power state. Furthermore, existing technologies require pulling down the SCL line of the I2C bus during system wakeup, forcing the master device to suspend data transmission and wait for the slave device to wake up the system and restore the clock before communication can resume. Furthermore, clock stretching is optional in the I2C protocol, and most devices may not support it. To utilize this feature, existing technologies require slave devices to implement clock stretching and must also require the master device to support it or have a corresponding processing mechanism. Failure to do so can result in communication failure and data loss. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an integrated circuit bus I2C slave device, system and wake-up method to solve the shortcomings of the prior art.

[0006] The object of the present invention is achieved by the following technical solution: an integrated circuit bus I2C slave device, which is connected to a power supply, and the I2C slave device includes a system on chip SoC, a system control module, an I2C communication module and an I2C interface;

[0007] The system on chip SoC enters a low power consumption mode after receiving an instruction for instructing to enter a low power consumption state, and transmits a low power consumption mode signal to the system control module;

[0008] After receiving the low-power mode signal, the system control module turns off unnecessary system clocks and generates a low-power state signal to output to the power supply to make it enter the low-power mode. After receiving the wake-up signal, the system control module restores the clock signal and cancels the low-power state signal of the power supply to restore the normal working mode, and makes the system on chip SoC exit the low-power mode.

[0009] The I2C communication module is provided with two configuration signals, partial wake-up enable and wake-up address. Different configuration signals are used to select whether to wake up the I2C slave device during I2C communication and the timing of the wake-up signal generation. I2C communication is implemented in an asynchronous manner, that is, the serial clock line SCL is used as the clock to complete the transmission of serial data SDA, so as to complete data read / write access in a low-power state without a system clock.

[0010] The I2C interface is connected to communicate with external devices.

[0011] The selection of whether to wake up the I2C slave device during I2C communication and the timing of generating the wake-up signal by using different configuration signals includes:

[0012] Partial wake-up enable is turned off. The system will wake up after receiving a matching device address. Otherwise, the system will not wake up and communication will not continue.

[0013] Partial wake-up is enabled. After receiving a matching device address, the system will not wake up immediately. Instead, it will wake up the system only after receiving a register access address that is greater than or equal to the configured wake-up address. Otherwise, the system will not wake up, but communication will continue, that is, data transmission will be performed in a low-power state.

[0014] The I2C slave device also includes a glitch filtering circuit, which is connected to the I2C interface and the I2C communication module respectively; in the absence of a system clock, the glitch filtering circuit filters high-level glitches and low-level glitches on the serial clock line SCL and serial data SDA on the integrated circuit bus I2C to ensure reliable data transmission in the I2C communication implemented in an asynchronous manner.

[0015] The I2C slave device also includes a memory, and uses the serial clock line SCL as a clock to access data, and data access can be completed without the participation of the system clock.

[0016] An integrated circuit bus (I2C) system includes an I2C master device and an I2C slave device. The I2C master device is communicatively connected to an I2C interface. The I2C master device initiates read / write access operations to the I2C slave device to wake up the system without any sense of presence or complete data transmission in a low-power state.

[0017] A method for waking up an I2C slave device, the method comprising:

[0018] When the I2C slave device is in low power mode, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned off, the I2C communication module generates a wake-up signal after receiving a device address match and outputs it to the system control module and the system-on-chip SoC. The system control module recovers the system clock, and the system-on-chip SoC exits low power mode after receiving the wake-up signal, and the entire system exits low power mode.

[0019] Alternatively, when the I2C slave device is in a low-power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned on, the I2C communication module generates a wake-up signal and outputs it to the system control module and the system-on-chip SoC when it receives the device address and the address matches, and the received register access address is greater than or equal to the wake-up address configured in the I2C communication module. The system control module restores the system clock, and the system-on-chip SoC exits the low-power mode after receiving the wake-up signal, and the entire system exits the low-power state.

[0020] The awakening method further includes:

[0021] When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned on, the I2C communication module does not generate a wake-up signal when it receives the device address and the address matches, and the received register access address is less than the wake-up address configured in the I2C communication module. The I2C communication module continues to complete data transmission in low power state.

[0022] The awakening method further includes:

[0023] When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, but the device address received by the I2C slave device does not match. Regardless of whether the partial wake-up enable configured in the I2C communication module is turned on, the slave device neither wakes up nor continues to transmit data, and the communication ends.

[0024] The present invention has the following advantages: an integrated circuit bus I2C slave device, system, and wake-up method can enter a low-power state when idle, saving power. During I2C communication, the I2C slave device system can be selectively and seamlessly awakened, and data transmission can be completed in the low-power state. When the I2C slave device is in the low-power state, each read / write access operation initiated by the I2C master device to the slave device is treated as normal data transmission by the I2C slave device, thereby improving transmission efficiency. The I2C communication module uses an asynchronous method to implement I2C communication, namely, using the serial clock line (SCL) as the clock to complete data transmission. Combined with the above configuration, data transmission can be completed without waking up the system when reading / writing certain memories that do not require a system clock. This improves flexibility and saves power. Furthermore, during the system wake-up process, there is no need to pull down the serial clock line (SCL) to suspend I2C communication. The master device is not forced to wait for the slave device clock to recover before continuing communication. Therefore, neither the master nor the slave device needs to support clock stretching, simplifying the design and enhancing applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of the present invention;

[0026] Figure 2 Schematic diagram of the data transmission format of the I2C read / write access operation of the present invention;

[0027] Figure 3 This is the I2C communication timing diagram;

[0028] Figure 4 Schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the present application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0030] like Figure 1As shown, one embodiment of the present invention relates to an integrated circuit bus I2C slave device system, which includes a system on chip SoC, a system control module, a memory, an I2C communication module, a glitch filtering circuit and an I2C interface.

[0031] When the SoC receives a command to enter a low-power state, it enters low-power mode and outputs a low-power mode signal to the system control module. When a wake-up signal is generated, the system control module turns on the clock, and the SoC exits low-power mode after receiving the wake-up signal.

[0032] The system control module is used to, upon receiving a signal indicating that the SoC has entered low-power mode, shut down system clocks not needed by the SoC and other modules, and generate a low-power state signal to output to the power supply, forcing it to enter low-power mode. Upon receiving a wake-up signal, the system control module restores the clocks of the SoC and other modules, and removes the low-power state signal from the power supply, returning it to normal operation.

[0033] The I2C communication module has two configuration signals: partial wakeup enable and wakeup address. These signals can be used to select whether to wake up the I2C slave device during I2C communication and when to generate the wakeup signal. This allows the system to be woken up only when needed, rather than every time communication occurs, thus saving power.

[0034] At the same time, the I2C communication module uses an asynchronous method to implement I2C communication, that is, the serial clock line SCL is used as the clock to complete the transmission of serial data SDA. In this way, data read / write access can be completed in a low-power state without a system clock. Figure 3 As shown in the figure, communication begins with a start bit (S) and ends with a stop bit (P). When communication is idle, both the serial clock line SCL and the serial data line SDA are high. Each SCL clock corresponds to one bit of SDA data, and SDA data transitions always occur when the SCL clock is low. Therefore, serial data SDA can be transmitted without relying on the system clock, using only the serial clock SCL as the clock.

[0035] The glitch filtering circuit can filter out high-level glitches and low-level glitches on the serial clock line SCL and serial data line SDA on the integrated circuit bus I2C in the absence of a system clock, thereby ensuring reliable data transmission for I2C communication implemented in an asynchronous manner.

[0036] The memory uses the serial clock line (SCL) as a clock to access data, and can complete data access without the participation of the system clock. The memory is not limited to a specific form and can be a register or a whole memory module.

[0037] The I2C interface includes a serial clock SCL port and a serial data SDA port. Only two signal lines are needed to connect the master and slave devices to complete data transmission, saving valuable I / O resources.

[0038] Another embodiment of the present invention relates to an integrated circuit bus (IC) system, comprising the I2C slave device of the previous embodiment and an I2C master device. The I2C master device communicates with an I2C interface in the I2C slave device and can enter a low-power state when idle to save power. During I2C communication, the I2C slave device system can be selectively and seamlessly awakened, and data transmission can also be completed in the low-power state.

[0039] That is, when the system is in a low-power state, when the I2C master device accesses a slave device, the I2C communication is a normal read / write access operation for the slave device, waking up the system during the access process. During the entire I2C communication process, the slave device does not need to pull down the serial clock line (SCL) for clock stretching, nor does the master device need to suspend data transmission to wait for system wakeup and clock recovery; data transmission can still be completed. In addition, the timing of generating the wake-up signal can be selectively specified by configuring partial wake-up enable and wake-up address. Communications before this time will not wake up the system, allowing normal access to memory that does not require the system clock even when the system is in a low-power state.

[0040] like Figure 4 As shown, another embodiment of the present invention relates to a method for waking up an integrated circuit bus I2C slave device system, which specifically includes the following contents:

[0041] After the SoC receives the instruction for instructing to enter the low power consumption state, the SoC enters the low power consumption mode, the system control module turns off the system clock, and instructs the power supply to enter the low power consumption mode.

[0042] The I2C communication module has two configuration signals: partial wake-up enable and wake-up address. These two configuration signals are used to select whether to generate a wake-up signal and when to generate the wake-up signal.

[0043] When the I2C slave device system is in low power state, when the I2C master device reads / writes the memory of the slave device, it is a normal data transmission operation for the I2C slave device. The above configuration can wake up the system silently during the data transmission process.

[0044] When the system is in low power state, the I2C master device initiates a read / write access operation, but the device address received by the slave device does not match. Regardless of whether the partial wake-up enable is turned on, the system is neither woken up nor the transmission continues, and the communication ends.

[0045] When the system is in low-power mode and the I2C master device initiates a read / write access operation with partial wake-up enabled, the slave device's I2C communication module receives a device address match and generates a wake-up signal to the system control module and SoC. The system control module recovers the system clock, and the SoC exits low-power mode after receiving the wake-up signal. The entire system then exits low-power mode.

[0046] When the system is in low-power mode, the I2C master initiates a read / write access operation with partial wake-up enabled. If the slave receives a device address that matches the address, and the subsequent register access address is greater than or equal to the configured wake-up address, it generates a wake-up signal and outputs it to the system control module and SoC. The system control module recovers the system clock, and the SoC exits low-power mode after receiving the wake-up signal. The entire system then exits low-power mode.

[0047] When the system is in low power state, the I2C master device initiates a read / write access operation and partial wake-up is enabled. If the slave device receives a device address and the address matches, but the received register access address is smaller than the configured wake-up address, no wake-up signal is generated and the I2C communication module continues to complete data transmission in low power state.

[0048] During the system wake-up process, the I2C slave device does not need to pull down the serial clock line SCL for clock stretching to wait for the system to wake up, and the master device does not need to suspend data transmission. The I2C communication module continues to communicate normally.

[0049] The data transmission format of the I2C communication module read / write access is transmitted in bytes, and each byte is followed by an acknowledge signal (A). Figure 2 As shown in Figure 2, the data transfer format for read / write accesses includes both the device address and the register access address. Each transfer begins with a start bit (S), followed by a 7-bit device address, followed by a 1-bit read / write (R / W) indicator ("0" for write and "1" for read). This is followed by the N-byte register access address. The transfer ends with a stop bit (P).

[0050] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention is capable of various other combinations, modifications, and improvements, and is capable of modifications within the scope of the concepts described herein, through the above teachings, or through techniques or knowledge in the relevant fields. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. An integrated circuit bus I2C slave device connected to a power supply, characterized in that: The I2C slave device includes a system on chip SoC, a system control module, an I2C communication module and an I2C interface; The system on chip SoC enters a low power mode after receiving a low power mode signal, and transmits the low power mode signal to the system control module; After receiving the low-power mode signal, the system control module turns off unnecessary system clocks and generates a low-power state signal to output to the power supply to make it enter the low-power mode. After receiving the wake-up signal, the system control module restores the clock signal and cancels the low-power state signal of the power supply to restore the normal working mode, and makes the system on chip SoC exit the low-power mode. The I2C communication module is provided with two configuration signals, partial wake-up enable and wake-up address. Different configuration signals are used to select whether to wake up the I2C slave device during I2C communication and the timing of the wake-up signal generation. I2C communication is implemented in an asynchronous manner, that is, the serial clock line SCL is used as the clock to complete the transmission of serial data SDA, so as to complete data read / write access in a low-power state without a system clock. The I2C interface is connected to the external device for communication; The selection of whether to wake up the I2C slave device during I2C communication and the timing of generating the wake-up signal by using different configuration signals includes: Partial wake-up enable is turned off. The system will wake up after receiving a matching device address. Otherwise, the system will not wake up and communication will not continue. Partial wake-up is enabled. After receiving a matching device address, the system will not wake up immediately. Instead, it will wake up the system only after receiving a register access address that is greater than or equal to the configured wake-up address. Otherwise, the system will not wake up, but communication will continue, that is, data transmission will be performed in a low-power state.

2. The integrated circuit bus I2C slave device according to claim 1, wherein: The I2C slave device also includes a glitch filtering circuit, which is connected to the I2C interface and the I2C communication module respectively; in the absence of a system clock, the glitch filtering circuit filters high-level glitches and low-level glitches on the serial clock line SCL and serial data SDA on the integrated circuit bus I2C to ensure reliable data transmission in the I2C communication implemented in an asynchronous manner.

3. The integrated circuit bus I2C slave device according to claim 1, wherein: The I2C slave device also includes a memory, and uses the serial clock line SCL as a clock to access data, and data access can be completed without the participation of the system clock.

4. An integrated circuit bus I2C system, characterized in that: The system includes an I2C master device and an I2C slave device according to any one of claims 1 to 3; the I2C master device is communicatively connected to an I2C interface, the I2C master device initiates read / write access operations to the I2C slave device, wakes up the system unconsciously, or completes data transmission in a low-power state.

5. A method for waking up an I2C slave device according to any one of claims 1 to 3, characterized in that: The awakening method includes: When the I2C slave device is in low power mode, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned off, the I2C communication module generates a wake-up signal after receiving a device address match and outputs it to the system control module and the system-on-chip SoC. The system control module recovers the system clock, and the system-on-chip SoC exits low power mode after receiving the wake-up signal, and the entire system exits low power mode. Alternatively, when the I2C slave device is in a low-power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned on, the I2C communication module generates a wake-up signal and outputs it to the system control module and the system-on-chip SoC when it receives the device address and the address matches, and the received register access address is greater than or equal to the wake-up address configured in the I2C communication module. The system control module restores the system clock, and the system-on-chip SoC exits the low-power mode after receiving the wake-up signal, and the entire system exits the low-power state.

6. A wake-up method according to claim 5, characterized in that: The awakening method further includes: When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured in the I2C communication module is turned on, the I2C communication module does not generate a wake-up signal when it receives the device address and the address matches, and the received register access address is less than the wake-up address configured in the I2C communication module. The I2C communication module continues to complete data transmission in low power state.

7. The wake-up method according to claim 5, characterized in that: The awakening method further includes: When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, but the device address received by the I2C slave device does not match. Regardless of whether the partial wake-up enable configured in the I2C communication module is turned on, the slave device neither wakes up nor continues to transmit data, and the communication ends.

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