Workload-based block rendering mode graphic processing method and system

Abstract

The invention discloses a block rendering mode graphic processing method and system based on workload. The system comprises a geometry processing system and a fragment processing system. The geometric processing system is used for carrying out geometric processing on the primitives and partitioning the visible primitives into a plurality of blocks in a screen visual space; the fragment processing system comprises a block processing module and a plurality of fragment processing pipelines, and the block processing module is used for distributing the plurality of blocks to the plurality of fragment processing pipelines for rendering according to the sequence of rendering workloads of the plurality of blocks from large to small. According to the method, the workload in rendering is balanced, long-time processing delay of the blocks with large workload is avoided, the overall performance is improved, the method is simple, and management in a computer graphic processing system is more convenient.

Description

Technical Field

[0001] The present invention belongs to the technical field of image processing, and more specifically, relates to a workload-based block rendering mode graphics processing method and system. Background Art

[0002] A computer graphics processing system is used to process graphics data (including primitive data and vertex data) for various computer graphics applications (such as computer games) and output a rendered image produced by a rendering pipeline.

[0003] The three-dimensional model in the graphics application is established by dividing the objects in the scene using primitives (such as but not limited to triangles, lines, and points), which are defined by vertices for their positions in the three-dimensional space, as well as lighting effects and shading characteristics. The geometric data of the primitives and vertices in the three-dimensional model are sent to the computer graphics processing system as an input data stream of the geometry processing stage (geometry processing) in the rendering process, and the input primitives are subjected to geometry processing, including converting the primitives to the screen space and deleting the primitives that are not visible in the screen space. After geometry processing, the geometric data of the primitives and vertices are sent to the fragment processing pipeline (fragment processing pipeline) for rendering in the computer graphics processing system. As a result of the rendering process, the computer graphics processing system generates an output image of the 3D model and displays it on a display unit (such as a display screen).

[0004] Existing computer graphics processing systems include a tile-based block rendering mode. In the block rendering mode, the screen is divided into multiple rectangular tiles, and the primitives are classified into different tiles on the screen after geometric processing, and then fragment processing is performed separately in each tile on the screen to generate a rendered image. Summary of the invention

[0005] In response to the above defects or improvement needs of the prior art, the present invention provides a workload-based block rendering mode graphics processing method and system, which helps to balance the workload in rendering and avoid long processing delays for tiles with large workloads, thereby improving the overall performance. The method is simple and easier to manage in a computer graphics processing system.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present invention, a graphics processing system is provided, including a geometry processing system and a fragment processing system; the geometry processing system is used to divide the visible primitives into multiple tiles in the screen visual space after geometric processing; the fragment processing system includes a tile processing module and multiple fragment processing pipelines, and the tile processing module is used to distribute multiple tiles to multiple fragment processing pipelines for rendering in the order of the rendering workload of the multiple tiles from large to small.

[0007] In some embodiments, the block processing module is further used to estimate the rendering workload of multiple tiles according to the workload of the same tile in the previous frame rendering.

[0008] In some embodiments, the block processing module is also used to: in the same rendering of the previous frame, for each tile, obtain the total number of cycles CycleCount required for rendering in the corresponding fragment processing pipeline; based on the total number of cycles CycleCount required for rendering each tile, calculate the workload weight Weight = CycleCount / CycleUnit of each tile, where CycleUnit is a set cycle unit; and distribute multiple tiles to multiple fragment processing pipelines for rendering in the order of the calculated workload weight Weight from large to small.

[0009] In some embodiments, the tile processing module is also used to: generate a tile rendering list containing Lw sequentially arranged workload levels; calculate the workload level TileLevel of each tile based on the calculated workload weight Weight; classify each tile into the corresponding workload level in the tile rendering list based on the calculated workload level TileLevel; and distribute multiple tiles to multiple fragment processing pipelines for rendering in order of workload levels from high to low.

[0010] In some embodiments, the workload level of the tile TileLevel = Weight / WeightGrade, where WeightGrade = ( WeightMax – WeightMin ) / Lw, WeightMax is the maximum workload weight of the calculated tile, and WeightMin is the minimum workload weight of the calculated tile.

[0011] In some embodiments, the geometry processing system includes a geometry processing pipeline and a blocking module; the geometry processing pipeline is used to delete invisible primitives in the screen visual space and retain only visible primitives in the screen visual space; the blocking module is used to block the visible primitives into multiple tiles in the screen visual space and generate a tile display list for each tile; the tile processing module is used to obtain the tile display list generated by the blocking module, and distribute the primitives required for rendering tiles in the tile display list to multiple fragment processing pipelines in units of tiles.

[0012] In some implementations, each fragment processing pipeline is used to render a tile according to primitive data and converted vertex data of the primitive referenced in the tile display list to generate a rendered image of the tile.

[0013] In some embodiments, each fragment processing pipeline includes a rasterization module, a hidden surface removal module, and a pixel shading module; the rasterization module is used to obtain the primitive data and converted vertex data required by the primitives referenced in the block display list, and rasterize the primitives into visible pixels; the hidden surface removal module is used to perform depth testing on the visible pixels output by the rasterization module, and remove pixels behind other primitives at the same pixel position; the pixel shading module is used to shade the visible pixels output by the hidden surface removal module.

[0014] In some embodiments, each fragment processing pipeline further includes a post-processing module for performing post-processing operations on the accumulated primitive pixel colors; the post-processing operations include at least one of masking, format conversion, downsampling, and pixel filtering.

[0015] According to another aspect of the present invention, there is provided a graphics processing method, comprising: After geometric processing of primitives, visible primitives are divided into multiple tiles in the screen visual space; According to the order of rendering workload of the multiple tiles from large to small, the multiple tiles are distributed to the multiple fragment processing pipelines for rendering.

[0016] In some embodiments, the method further includes: estimating the rendering workload of the plurality of tiles according to the workload of the tile in the same rendering in the previous frame.

[0017] In some embodiments, estimating the rendering workload of multiple tiles based on the workload of the tiles in the same rendering of the previous frame includes: in the same rendering of the previous frame, for each tile, obtaining the total number of cycles CycleCount required for rendering in the corresponding fragment processing pipeline; based on the total number of cycles CycleCount required for rendering each tile, calculating the workload weight Weight = CycleCount / CycleUnit of each tile, where CycleUnit is a set cycle unit; and using the calculated workload weight Weight as the workload weight of multiple tiles.

[0018] In some embodiments, distributing multiple tiles to multiple fragment processing pipelines for rendering in order of rendering workload of the multiple tiles from large to small includes: distributing multiple tiles to multiple fragment processing pipelines for rendering in order of calculated workload weights Weight from large to small.

[0019] In some embodiments, distributing multiple tiles to multiple fragment processing pipelines for rendering in order of calculated workload weights Weight from large to small includes: generating a tile rendering list containing Lw sequentially arranged workload levels; calculating the workload level TileLevel of each tile according to the generated workload weight Weight; classifying each tile into the corresponding workload level in the tile rendering list according to the calculated workload level TileLevel; distributing multiple tiles to multiple fragment processing pipelines for rendering in order of workload levels from high to low.

[0020] According to another aspect of the present invention, there is provided an electronic device comprising the above-mentioned graphics processing system; or, the electronic device comprises: a processor; a memory communicatively connected to the processor; the memory stores instructions executable by the processor, the instructions being executed by the processor so that the processor can execute the above-mentioned method.

[0021] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the above method is implemented.

[0022] In general, the above technical scheme conceived by the present invention has the following beneficial effects compared with the prior art: before rendering, the workload of the tile is estimated according to the number of cycles required to complete the tile rendering of the previous frame, and a tile rendering list based on the workload is generated. The tiles are distributed to multiple fragment processing pipelines for rendering in the order of the workload level from high to low in the tile rendering list, so that the tiles with large workload are processed first, which helps to balance the workload in rendering and avoid long processing delays for tiles with large workload, thereby improving the overall performance; in addition, the division based on the workload level and only one tile rendering list are required, which is more convenient to manage in the computer graphics processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the structure of a graphics processing system in a block rendering mode based on workload according to an embodiment of the present invention; Figure 2 It is a typical tile allocation method when distributing tiles to multiple fragment processing pipelines for rendering; Figure 3 is an example of a tile to be rendered on the screen; Figure 4 Yes Figure 3 The amount of work to be done to shade the tiles shown; Figure 5 It is a flowchart of a block rendering mode graphics processing method based on workload according to an embodiment of the present invention; Figure 6 It is a structural block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. As those skilled in the art can appreciate, the described embodiments can be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0025] like Figure 1 As shown, the workload-based tile rendering mode graphics processing system of an embodiment of the present invention includes a geometry processing system and a fragment processing system. The geometry processing system is used to construct primitives according to input geometry data (such as vertex data), and after geometric processing of the primitives, the visible primitives are divided into multiple tiles in the screen visual space, and a tile display list is generated for each tile.

[0026] The geometry processing system further includes an input assembly module, a geometry processing pipeline and a tile module. The input assembly module is used to construct primitives according to the input geometry data. The geometry processing pipeline is used to process the constructed primitives, delete the primitives that are not visible in the screen visual space, and only retain the primitives that are visible in the screen visual space. The tile module is used to tile the visible primitives into multiple tiles of the screen visual space and generate a tile display list for each tile.

[0027] In some embodiments, the tile display list includes all graphics elements that at least partially overlap with the tile and need to be rendered in the tile; when a certain graphics element is located in multiple tiles, the graphics element will be included in the tile display list of each tile in the screen visual space where the graphics element is located.

[0028] The geometry processing pipeline further includes a geometry conversion module, a clipping and culling module, and a data receiving module. The geometry conversion module is used to convert the vertex data of the primitives constructed by the input assembly module to the screen visual space. The clipping and culling module is used to delete the primitives that are not visible in the screen visual space and only retain the primitives that are visible in the screen visual space. These primitives are the primitives required for rendering the scene. The data receiving module is used to receive and store the primitive data and the converted vertex data of the primitives that are visible in the screen visual space.

[0029] In some embodiments, the geometry processing system includes a geometry processing pipeline, and the primitives constructed by the input assembly module are sent to the geometry processing pipeline for processing. In some embodiments, the geometry processing system includes multiple geometry processing pipelines, and the primitives constructed by the input assembly module are distributed to multiple downstream geometry processing pipelines for processing respectively by the multiple geometry processing pipelines.

[0030] The graphic element data and the converted vertex data in the data receiving module are written into the first memory of the storage module, and the block display list generated by the block module is written into the second memory of the storage module.

[0031] The fragment processing system is used to render multiple tiles according to the tile display list generated by the geometry processing system, and generate rendering images of the multiple tiles. The fragment processing system includes a tile processing module and multiple fragment processing pipelines. The tile processing module is used to read the tile display list of the tile generated by the geometry processing system from the second memory, and distribute the primitives required for rendering the tiles in the tile display list (i.e., the primitives referenced in the tile display list) to multiple fragment processing pipelines in units of tiles; each fragment processing pipeline is used to render the tile according to the primitive metadata and converted vertex data of the primitive referenced in the tile display list, and generate a rendering image of the tile.

[0032] That is to say, the block processing module distributes the graphics primitives required for rendering the multiple tiles in the block display list of the multiple tiles to the multiple fragment processing pipelines, wherein the graphics primitives required for rendering a tile in the block display list of the tile are sent to a fragment processing pipeline, and the multiple fragment processing pipelines work together to complete the rendering of the multiple tiles.

[0033] In some embodiments, the fragment processing pipeline includes a rasterization module, a hidden surface removal module, and a pixel shading module. In other embodiments, the fragment processing pipeline includes a rasterization module, a hidden surface removal module, a pixel shading module, and a post-processing module.

[0034] The rasterization module is used to read the primitive data and converted vertex data required by the primitives referenced in the tile display list from the first memory, and rasterize the primitives into visible pixels. In some embodiments, for each tile, the primitives are rasterized into visible pixels within the tile.

[0035] The hidden surface removal module is used to perform a depth test on the visible pixels output by the rasterization module. Specifically, the depth value of the visible pixels output by the rasterization module is compared with the depth value of the previous primitive pixel stored in the depth buffer. When the primitive pixel output by the rasterization module is blocked by the previous primitive pixel, it is considered that the depth test has not passed, and the primitive pixel output by the rasterization module is removed. Otherwise, the primitive pixel output by the rasterization module is sent to the pixel shading module. In other words, the pixels behind other primitives at the same pixel position are removed by the hidden surface removal module. In some embodiments, the depth value of the previous primitive pixel is a preset value. In some embodiments, the depth value of the previous primitive pixel is the depth value of the primitive pixel that previously passed the depth test.

[0036] The pixel coloring module is used to color the visible pixels output by the hidden surface removal module to obtain the final color of the primitive pixel. In some embodiments, the color information of the pixels in the tile is stored in an on-chip color buffer in a computer graphics processing system in a tile rendering mode to avoid frequent data exchange with an external memory, which affects processing efficiency.

[0037] The post-processing module is used to perform post-processing operations on the accumulated primitive pixel colors, such as masking, format conversion, downsampling and pixel filtering, to obtain the final rendered image of the block. The final rendered image can be sent to a display unit outside the computer graphics processing system for display.

[0038] Tiles are distributed to multiple fragment processing pipelines for rendering. Since the rendering of different tiles is performed independently, the allocation of tiles can follow arbitrary rules. Figure 2As shown in FIG. 1 , a typical allocation method is to use a fixed scan line mode, with 2×2 tiles as the unit, linear scan allocation, and within the 2×2 tiles, allocation in an inverted N-type order. This fixed tile allocation mode is easy to implement in hardware, but it is not the optimal solution for the performance of computer graphics processing systems, especially when the rendering workload is unevenly distributed among the tiles on the screen.

[0039] In fact, the amount of work required to render a tile on the screen depends on the settings of the rendering scene. In many cases, the amount of work required to render different tiles varies greatly. Figure 3 Take the tiles to be rendered on the screen as an example. Figure 4 Given in Figure 1 The pixel shading module shown is Figure 3 The amount of shading work done on these tiles is shown, represented by the execution cycles in the tile on the screen.

[0040] from Figure 4 It can be seen that the rendering workload is unevenly distributed, and the shading execution time of each tile varies greatly. The minimum shading execution time of a tile is 105 cycles, while the maximum shading execution time of a tile is 9075 cycles. In other words, the maximum shading execution time of a tile is about 86 times the minimum shading execution time. If a fixed tile allocation mode is used and the workload of the tile is not controlled, Figure 4 The busiest tile in a rendering may not be processed until near the end, so it is difficult to avoid long processing delays relative to other tiles, thus affecting overall performance.

[0041] To this end, the embodiments of the present invention consider the workload in allocating tiles during rendering. Tiles are allocated according to their workload, so that tiles with large workloads are processed first, which helps to avoid long processing delays for tiles with large workloads, thereby improving overall performance. Furthermore, the workload of the tiles needs to be known before rendering so that it can be used for tile allocation during rendering. However, the workload of the rendering can only be known after the tiles are rendered, so the workload of the tiles must be estimated before rendering.

[0042] According to the rendering workload of the tile, the embodiment of the present invention distributes the tile to multiple fragment processing pipelines for rendering, so as to enhance the performance of the tile-based computer graphics processing system. In some embodiments, the workload of the current rendering is estimated according to the workload in the previous rendering by using time statistics. Specifically, the workload of the rendering of the tile can be known through some statistical counters after rendering. Assuming that the rendering content does not change much between adjacent frames, the workload of the rendering of the tile can be used to estimate the workload of the tile in the same rendering of the next frame.

[0043] In some embodiments, during the stage when the fragment processing pipeline renders tiles, a statistical counter is used to count the processing cycles of the tiles to obtain the number of cycles required for the fragment processing pipeline to complete all work of rendering the tiles. Therefore, it is very suitable for estimating the workload of the fragment processing pipeline for rendering tiles.

[0044] In some embodiments, in order to estimate the workload of the fragment processing pipeline for rendering a tile, the accumulation of statistical counters needs to be done on a per-tile basis. Figure 1 The block processing module shown stores the initial value of the statistical counter at the beginning of a tile (that is, before the fragment processing pipeline renders the tile). After the fragment processing pipeline starts rendering the tile (that is, after the rasterization module starts processing the tile), the statistical counter starts counting the processing cycles of the tile. When the rendering of this tile is completed (that is, when the pixel shading module completes the processing of the tile, or when the post-processing module completes the processing of the tile), the current value of the statistical counter is subtracted from the initial value to obtain the total number of cycles required for the fragment processing pipeline to render the tile.

[0045] In some embodiments, for each tile, after rendering is completed, the number of cycles required to complete the rendering is stored in a separate memory, so as to estimate the workload of the fragment processing pipeline to render the tile in the same rendering of the next frame.

[0046] When the rendering of the tile is completed, the total number of cycles required to render the tile can be calculated by tracking the cycle count of the tile. In some embodiments, for each tile, a workload weight of the tile is generated based on the total number of cycles required to render the tile. Specifically, the total number of cycles required to render the tile may be thousands, and for the workload weight of the tile, there is no need to use the actual cycle count of the tile. For example, the unit of the total number of cycles required to render the tile can be 4024 cycles to form the workload weight of the tile. In this case, only 8 bits are needed to store the workload weight of the tile, which allows the total number of cycles for each tile to be as high as 1M cycles.

[0047] In some implementations, the workload weight Weight of a tile and the total number of cycles CycleCount required to render the tile satisfy the following relationship: Weight = CycleCount / CycleUnit, Wherein, CycleUnit is a set cycle unit. In some implementations, CycleUnit is 4024 cycles.

[0048] In some embodiments, after the rendering of a tile is completed, an 8-bit workload weight of the tile is calculated. The workload weight can be stored in a memory so as to be used for sorting the tile workload after the rendering of all tiles on the screen is completed.

[0049] In order to balance the workload of the tiles on the screen, the tiles with large workload should be processed first to avoid the increase in the total rendering cycle due to tailing. Therefore, in some embodiments, after the rendering is completed, the tiles are sorted according to the workload weight of the tiles to form a tile rendering list. The sorted tile rendering list can be written to the memory so as to be read out in the same rendering of the next frame.

[0050] In some embodiments, a maximum workload weight and a minimum workload weight are set to calculate the range of workload weights in rendering. In some embodiments, the maximum workload weight in rendering is initialized to 0 at the beginning of rendering, and the minimum workload weight in rendering is initialized to 0xFF at the beginning of rendering. After calculating the workload weight of the tile, the maximum workload weight and the minimum workload weight are updated. At the end of rendering, the maximum workload weight and the minimum workload weight of the rendering can be known.

[0051] Although 8 bits have been used to represent the workload weight of a tile in rendering, in order to allocate tiles according to their workload, in some embodiments, the workload weight is divided into levels, and the 8-bit workload weight of the tile is converted into the workload level of the tile. In some embodiments, the workload weight of the tile is divided into Lw levels, and the workload level TileLevel of the tile can be expressed as: TileLevel = Weight / WeightGrade, WeightGrade = (WeightMax – WeightMin) / Lw, Among them, WeightMax is the maximum workload weight, WeightMin is the minimum workload weight, and WeightGrade is the weight interval size of each level.

[0052] After rendering is completed, the workload levels of all tiles are calculated, and according to the workload levels of the tiles, a workload-based tile rendering list is generated.

[0053] In some embodiments, the tile coordinates Tile(X, Y) are stored in a tile rendering list to indicate the tile in the workload level of the rendering list. In some embodiments, the tile rendering list includes Lw workload levels arranged in sequence. After rendering is completed, each tile on the screen is classified into one of the workload levels according to the workload level of each tile. After all tiles are sorted, the number of tile entries in each workload level is stored respectively.

[0054] In some embodiments, in the stage where multiple fragment processing pipelines render tiles (i.e., the fragment processing stage), tiles are processed starting from the highest workload level (i.e., level Lw) in the tile rendering list for rendering. After all tiles in the current workload level are rendered, tiles in the next workload level are processed. During the rendering process, the workload levels are processed in descending order until all tiles in all workload levels are rendered.

[0055] The storage space for storing tile workload weight and tile workload level should be allocated by the software driver at the beginning of the tile processing stage of rendering. For example, for each tile, 8 bits of storage space can be allocated for the tile workload weight at the beginning of rendering. After the tile workload level is calculated based on the tile workload weight and the tile is sorted into the tile rendering list, the storage space for the tile workload weight is released at the end of rendering.

[0056] The storage space of the tile rendering list can be allocated from the first frame when rendering starts. The storage space of the tile rendering list can be used for the same rendering in the next frame, so it cannot be released at the end of rendering. The storage space of the tile rendering list can be allocated as persistent memory during the life cycle of the application.

[0057] like Figure 5 As shown, the workload-based block rendering mode graphics processing method of an embodiment of the present invention includes: Step S501: After geometric processing of the primitives, the visible primitives are divided into a plurality of blocks in the screen visual space.

[0058] Step S503: Estimate the rendering workload of multiple tiles according to the workload of the same tile in the previous frame.

[0059] In some embodiments, in the same rendering of the previous frame, for each tile, the total number of cycles CycleCount required for rendering in the corresponding fragment processing pipeline is obtained; based on the total number of cycles CycleCount required for rendering each tile, the workload weight Weight = CycleCount / CycleUnit of each tile is calculated, where CycleUnit is a set cycle unit; the calculated workload weight Weight is used as the workload weight of multiple tiles.

[0060] Step S505: Distribute the multiple tiles to multiple fragment processing pipelines for rendering in descending order of the rendering workload of the multiple tiles.

[0061] In some implementations, multiple tiles are distributed to multiple fragment processing pipelines for rendering in descending order of calculated workload weights Weight.

[0062] In some embodiments, a tile rendering list comprising Lw sequentially arranged workload levels is generated; the workload level TileLevel of each tile is calculated based on the generated workload weight Weight; each tile is classified into a corresponding workload level in the tile rendering list based on the calculated workload level TileLevel; and multiple tiles are distributed to multiple fragment processing pipelines for rendering in order of workload levels from high to low.

[0063] More details of the above-mentioned workload-based block rendering mode graphics processing method have been described in detail in the above-mentioned workload-based block rendering mode graphics processing system, and the present invention will not be repeated here.

[0064] The advantages of the present invention are that the rendering order of tiles is based on their workload on the entire rendering screen, which is conducive to balancing the workload in rendering; in addition, the division is based on the workload level and only one tile rendering list is required, which is easier to manage in a computer graphics system.

[0065] Figure 6 is a structural block diagram of an electronic device according to an embodiment of the present application. The present application embodiment also provides an electronic device, such as Figure 6As shown, the electronic device includes: at least one processor 601, and a memory 603 connected to the at least one processor 601 in communication. Instructions that can be executed by at least one processor 601 are stored in the memory 603. The instructions are executed by at least one processor 601. When the processor 601 executes the instructions, the graphics processing method in the above embodiment is implemented. The number of the memory 603 and the processor 601 can be one or more. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only examples, and are not intended to limit the implementation of the present application described and / or required herein.

[0066] The electronic device may also include a communication interface 605 for communicating with external devices and performing data exchange transmission. The various devices are interconnected using different buses and may be installed on a common motherboard or in other ways as needed. The processor 601 may process instructions executed within the electronic device, including instructions stored in or on a memory to display graphical information of a graphical user interface (GUI) on an external input / output device (such as a display device coupled to an interface). In other embodiments, if necessary, multiple processors and / or multiple buses may be used together with multiple memories and multiple memories. Similarly, multiple electronic devices may be connected, each device providing some of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). The bus may be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 6 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0067] Optionally, in a specific implementation, if the memory 603, the processor 601 and the communication interface 605 are integrated on a chip, the memory 603, the processor 601 and the communication interface 605 can communicate with each other through an internal interface.

[0068] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor that supports the Advanced RISC Machines (ARM) architecture.

[0069] The embodiment of the present application provides a computer-readable storage medium (such as the memory 603 described above), which stores computer instructions. When the program is executed by a processor, the method provided in the embodiment of the present application is implemented.

[0070] Optionally, the memory 603 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the electronic device of the graphics processing method, etc. In addition, the memory 603 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 603 may optionally include a memory remotely arranged relative to the processor 601, and these remote memories may be connected to the electronic device of the graphics processing method via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0071] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0073] Any process or method description in the flow chart or otherwise described herein can be understood to represent a module, fragment or portion of a code including one or more (two or more) executable instructions for implementing the steps of a specific logical function or process. And the scope of the preferred embodiment of the present application includes other implementations, in which the functions may not be performed in the order shown or discussed, including in a substantially simultaneous manner or in a reverse order according to the functions involved.

[0074] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, apparatus or device and execute instructions), or used in combination with these instruction execution systems, apparatuses or devices.

[0075] It should be understood that the various parts of the present application can be implemented with hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above embodiment method can be completed by instructing the relevant hardware through a program, which can be stored in a computer-readable storage medium, and when the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0076] In addition, each functional unit in each embodiment of the present application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the above-mentioned integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium can be a read-only memory, a disk or an optical disk, etc.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A graphics processing system, characterized in that: Includes geometry processing system and fragment processing system; The geometry processing system is used to divide the visible graphics primitives into a plurality of graphics blocks in the screen visual space after geometry processing is performed on the graphics primitives; The fragment processing system includes a block processing module and a plurality of fragment processing pipelines. The block processing module is used to distribute the plurality of tiles to the plurality of fragment processing pipelines for rendering in a descending order of the rendering workload of the plurality of tiles.

2. The graphics processing system according to claim 1, wherein: The block processing module is also used to estimate the rendering workload of the multiple blocks according to the workload of the block in the same rendering of the previous frame.

3. The graphics processing system according to claim 2, characterized in that: The block processing module is also used to: in the same rendering of the previous frame, for each tile, obtain the total number of cycles CycleCount required for rendering in the corresponding fragment processing pipeline; according to the total number of cycles CycleCount required for rendering each tile, calculate the workload weight Weight = CycleCount / CycleUnit of each tile, where CycleUnit is a set cycle unit; and distribute the multiple tiles to the multiple fragment processing pipelines for rendering in the order of the calculated workload weight Weight from large to small.

4. The graphics processing system according to claim 3, characterized in that: The block processing module is also used to: generate a tile rendering list containing Lw sequentially arranged workload levels; calculate the workload level TileLevel of each tile according to the calculated workload weight Weight; classify each tile into the corresponding workload level in the tile rendering list according to the calculated workload level TileLevel; and distribute the multiple tiles to the multiple fragment processing pipelines for rendering in order of workload levels from high to low.

5. The graphics processing system according to claim 4, characterized in that: The workload level of the tile TileLevel =Weight / WeightGrade, where WeightGrade = (WeightMax – WeightMin) / Lw, WeightMax is the maximum workload weight of the calculated tile, and WeightMin is the minimum workload weight of the calculated tile.

6. The graphics processing system according to any one of claims 1 to 5, characterized in that: The geometry processing system includes a geometry processing pipeline and a blocking module; the geometry processing pipeline is used to delete the graphics primitives that are not visible in the screen visual space and only retain the graphics primitives that are visible in the screen visual space; The blocking module is used to block the visible graphic element into the plurality of tiles in the screen visual space, and generate a block display list for each tile; The block processing module is used to obtain the block display list generated by the block module, and distribute the graphics elements required for rendering the tiles in the block display list to the multiple fragment processing pipelines in units of tiles.

7. The graphics processing system according to claim 6, characterized in that: Each of the fragment processing pipelines is used to render a tile according to the primitive data and the converted vertex data of the primitive referenced in the tile display list to generate a rendered image of the tile.

8. The graphics processing system according to claim 7, characterized in that: Each fragment processing pipeline includes a rasterization module, a hidden surface removal module and a pixel shading module; the rasterization module is used to obtain the graphics data and converted vertex data required by the graphics primitives referenced in the block display list, and rasterize the graphics primitives into visible pixels; the hidden surface removal module is used to perform depth testing on the visible pixels output by the rasterization module, and remove pixels located behind other graphics primitives at the same pixel position; the pixel shading module is used to shade the visible pixels output by the hidden surface removal module.

9. The graphics processing system according to claim 8, characterized in that: Each of the fragment processing pipelines further includes a post-processing module, which is used to perform a post-processing operation on the accumulated primitive pixel colors; the post-processing operation includes at least one of masking, format conversion, downsampling and pixel filtering.

10. A graphics processing method, characterized in that: include: After geometric processing of primitives, visible primitives are divided into multiple tiles in the screen visual space; The plurality of tiles are distributed to a plurality of fragment processing pipelines for rendering in a descending order of the rendering workload of the plurality of tiles.

11. The graphics processing method according to claim 10, characterized in that: Also includes: The rendering workload of the plurality of tiles is estimated according to the workload of the tile in the same rendering of the previous frame.

12. The graphics processing method according to claim 11, characterized in that: According to the workload of the tiles in the same rendering of the previous frame, estimating the rendering workload of the multiple tiles includes: in the same rendering of the previous frame, for each tile, obtaining the total number of cycles CycleCount required for rendering in the corresponding fragment processing pipeline; according to the total number of cycles CycleCount required for rendering each tile, calculating the workload weight Weight = CycleCount / CycleUnit of each tile, where CycleUnit is a set cycle unit; and using the calculated workload weight Weight as the workload weight of the multiple tiles.

13. The graphics processing method according to claim 12, characterized in that: Distributing the multiple tiles to multiple fragment processing pipelines for rendering in a descending order of the rendering workload of the multiple tiles includes: distributing the multiple tiles to multiple fragment processing pipelines for rendering in a descending order of the calculated workload weights Weight.

14. The graphics processing method according to claim 13, characterized in that: Distributing the multiple tiles to multiple fragment processing pipelines for rendering in order of the calculated workload weight Weight from large to small includes: generating a tile rendering list containing Lw sequentially arranged workload levels; calculating the workload level TileLevel of each tile according to the generated workload weight Weight; classifying each tile to the corresponding workload level in the tile rendering list according to the calculated workload level TileLevel; distributing the multiple tiles to multiple fragment processing pipelines for rendering in order of the workload levels from high to low.

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