Gate driving unit and display device

Abstract

The invention provides a gate driving unit and a display device, the gate driving unit comprises a first frequency division control line, a second frequency division control line and a plurality of cascaded gate driving circuits, each gate driving circuit comprises a cascade transmission module and an output module, the output module is electrically connected with the first frequency division control line or the second frequency division control line and a first node and a second node in the level transmission module so as to output a first frequency division control signal or a second frequency division control signal to the scanning output end of the gate drive circuit of the level according to signals of the first node and the second node. Therefore, the level state of a gate control signal output by the gate drive circuit through the scanning output end is correspondingly controlled by the level state of the first frequency division control signal or the second frequency division control signal, so that the effective pulse of the gate control signal is controlled.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving unit and a display device. Background Art

[0002] Display panels using variable frequency technology can enter low-frequency mode when in standby mode or when using specific application software, which can save power consumption of the display panel and help improve the battery life of the display device. However, when existing display panels enter low-frequency mode, the full screen enters the low-frequency display module, which limits the use scenarios. Summary of the invention

[0003] The embodiments of the present invention provide a gate driving unit and a display device, which can facilitate frequency division driving of a display panel.

[0004] The present invention provides a gate driving unit, comprising: a first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded gate driving circuits, each of which comprises a level transmission module and an output module. The level transmission module receives an upper level transmission signal, a first clock signal, and a second clock signal, and outputs the current level transmission signal to the lower level gate driving circuit; the output module is electrically connected to the first frequency division control line or the second frequency division control line, a first node and a second node in the level transmission module, and the output module outputs the first frequency division control signal or the second frequency division control signal to a scan output terminal of the current level gate driving circuit according to the signals of the first node and the second node.

[0005] The embodiment of the present invention also includes a display device, comprising any of the above-mentioned gate driving units and a display panel. The display panel includes a plurality of sub-pixels and a plurality of first scan lines, and the plurality of sub-pixels include a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, and the pixel driving circuit includes at least one transistor. The gate control signals output by the plurality of gate driving circuits are transmitted to the control terminals of the transistors of the plurality of pixel driving circuits via the plurality of first scan lines.

[0006] The present invention provides a gate driving unit and a display device, comprising a first frequency division control line, a second frequency division control line and a plurality of cascaded gate driving circuits, each of which comprises a level transmission module and an output module, wherein the output module is electrically connected to the first frequency division control line or the second frequency division control line, and the first node and the second node in the level transmission module, so as to output the first frequency division control signal or the second frequency division control signal to the scanning output end of the gate driving circuit of the same level according to the signals of the first node and the second node, so that the level state of the gate control signal output by the gate driving circuit through the scanning output end is correspondingly controlled by the level state of the first frequency division control signal or the second frequency division control signal, thereby realizing the control of the effective pulse of the gate control signal, and then when the gate driving circuit does not need to output the effective pulse, so that the display panel using the gate driving circuit realizes the frequency division function, by controlling the level state of the first frequency division control signal or the second frequency division control signal, whether the gate control signal has the effective pulse can be controlled, so as to control a transistor of a pixel driving circuit in the display panel using the gate driving circuit to be non-conductive, so that the corresponding sub-pixel does not refresh the display data, so that the display panel realizes the frequency division function. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1A to Figure 1B is a schematic structural diagram of a gate driving unit provided by an embodiment of the present invention;

[0009] Figure 2A to Figure 2B is a timing diagram corresponding to the gate driving unit provided in an embodiment of the present invention;

[0010] Figure 3A to Figure 3B is a schematic structural diagram of a display device provided by an embodiment of the present invention;

[0011] Figure 4 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0012] Figure 5A to Figure 5B It is a timing diagram corresponding to the display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0014] The present invention realizes the level transmission setting through the level transmission module included in the gate driving circuit, and makes the gate driving circuit include an output module, so that the output module outputs the first frequency division control signal and the second frequency division control signal through the scanning output end according to the signals of the first node and the second node in the level transmission module, so as to generate a gate control signal.

[0015] Specifically, Figure 1A to Figure 1B Schematic diagram of the structure of a gate driving unit provided by an embodiment of the present invention; the present invention provides a gate driving unit 10, including a first frequency division control line FDL1, a second frequency division control line FDL2 and a plurality of cascaded gate driving circuits.

[0016] The first frequency-division control line FDL1 is configured to transmit a first frequency-division control signal FD1 .

[0017] The second frequency-division control line FDL2 is configured to transmit a second frequency-division control signal FD2 .

[0018] The plurality of cascaded gate driving circuits are configured to generate a plurality of gate control signals Scan. Optionally, each of the gate driving circuits comprises a stage transmission module 11 and an output module 12.

[0019] The stage transmission module 11 receives an upper stage stage transmission signal Cas, a first clock signal CK1 and a second clock signal CK2, and outputs a current stage transmission signal Cas to the lower stage gate driving circuit.

[0020] The output module 12 is electrically connected to the first frequency division control line FDL1 or the second frequency division control line FDL2, the first node P and the second node Q in the stage transmission module 11. The output module 12 outputs the first frequency division control signal FD1 or the second frequency division control signal FD2 to the scan output end of the gate drive circuit of this stage according to the signals of the first node P and the second node Q, so that the level state of the gate control signal Scan output by the gate drive circuit through the scan output end is correspondingly controlled by the level state of the first frequency division control signal FD1 or the second frequency division control signal FD2, thereby realizing the control of the effective pulse of the gate control signal Scan.

[0021] Optionally, the m-th level transmission signal Cas(m) output by the m-th level gate driving circuit via the level transmission output terminal is output to the m+A-th level gate driving circuit, the m+A-th level gate driving circuit receives the m-th level transmission signal Cas(m), the first clock signal CK1 and the second clock signal CK2, and outputs the m+A-th level transmission signal Cas(m+A). Wherein, the m-th level gate driving circuit is electrically connected to the first frequency division control line FDL1 to output the first frequency division control signal FD1 to the scan output terminal of the m-th level gate driving circuit, so that the level state of the m-th level gate control signal Scan output by the m-th level gate driving circuit through the scan output terminal is correspondingly controlled by the level state of the first frequency division control signal FD1; the m+A-th level gate driving circuit is electrically connected to the second frequency division control line FDL2 to output the second frequency division control signal FD2 to the scan output terminal of the m+A-th level gate driving circuit, so that the level state of the m+A-th level gate control signal Scan(m+A) output by the m+A-th level gate driving circuit through the scan output terminal is correspondingly controlled by the level state of the second frequency division control signal FD2, so that the two-stage gate driving circuits cascaded with each other can generate corresponding gate control signals Scan according to the first frequency division control signal FD1 and the second frequency division control signal FD2 respectively. Wherein, m≥1, A≥1.

[0022] Optionally, Figure 2A to Figure 2B This is a timing diagram corresponding to the gate driving unit provided in an embodiment of the present invention. In order to enable the display panel using the gate driving unit 10 to achieve frequency division display, the first frequency division control signal FD1 is partially identical to the second frequency division control signal FD2.

[0023] Optionally, the transistor to which the gate control signal Scan generated by the gate driving unit 10 is applied is a P-type transistor. Then, the first frequency-division control signal FD1 and the second frequency-division control signal FD2 have a time period in which they are both in a high-level state, so that the gate control signal Scan generated by the gate driving unit 10 according to the first frequency-division control signal FD1 and the second frequency-division control signal FD2 has a corresponding high-level state, and then the transistor to which the gate control signal Scan is applied is not turned on, so that the corresponding sub-pixel does not refresh the display data, thereby enabling the display panel to achieve low-frequency display in the portion corresponding to the sub-pixel.

[0024] Optionally, the transistor to which the gate control signal Scan generated by the gate driving unit 10 is applied is an N-type transistor. Then, the first frequency-division control signal FD1 and the second frequency-division control signal FD2 have a period of time in the same low-level state, so that the gate control signal Scan generated by the gate driving unit 10 according to the first frequency-division control signal FD1 and the second frequency-division control signal FD2 has a corresponding low-level state, and then the transistor to which the gate control signal Scan is applied is not turned on, so that the corresponding sub-pixel does not refresh the display data, thereby enabling the display panel to achieve low-frequency display in the portion corresponding to the sub-pixel.

[0025] Optionally, see Figure 1B , the output module 12 includes a first output transistor Tso1 and a second output transistor Tso2.

[0026] The control end of the first output transistor Tso1 is electrically connected to the first node P, the input end of the first output transistor Tso1 is electrically connected to the first voltage end VGH, and the output end of the first output transistor Tso1 is electrically connected to the scan output end.

[0027] The control end of the second output transistor Tso2 is electrically connected to the second node Q, the output end of the second output transistor Tso2 is electrically connected to the scan output end, and the input end of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1 or the second frequency division control line FDL2, so that when the second output transistor Tso2 is turned on according to the signal of the second node Q, the first frequency division control signal FD1 or the second frequency division control signal FD2 is output to the scan output end through the second output transistor Tso2.

[0028] Optionally, see Figure 1B The level transmission module 11 includes a first node control module, a second node control module and a level transmission output module.

[0029] The first node control module is electrically connected to the first node P. The first node control module receives the first clock signal CK1 or the second clock signal CK2 to control the signal of the first node P.

[0030] Optionally, the first node control module includes a first transistor T1 and a second transistor T2. The input terminal of the first transistor T1 is electrically connected to the second voltage terminal VGL; the control terminal of the second transistor T2 is electrically connected to the second node Q, the input terminal of the second transistor T2 is electrically connected to the control terminal of the first transistor T1, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1. The control terminal of the first transistor T1 is electrically connected to the first clock signal line CKL1 or the second clock signal line CKL2.

[0031] The second node control module is electrically connected to the second node Q, and receives the first clock signal CK1, the second clock signal CK2, and the upper-level transmission signal to control the signal of the second node Q.

[0032] Optionally, the second node control module includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5. The input end of the third transistor T3 receives the upper stage transmission signal, and the output end of the third transistor T3 is electrically connected to the second node Q; the control end of the fourth transistor T4 is electrically connected to the first node P, and the input end of the fourth transistor T4 is electrically connected to the first voltage end VGH; the input end of the fifth transistor T5 is electrically connected to the output end of the fourth transistor T4, and the output end of the fifth transistor T5 is electrically connected to the second node Q. Among them, the control end of the third transistor T3 is electrically connected to one of the first clock signal line CKL1 and the second clock signal line CKL2, and the control end of the fifth transistor T5 is electrically connected to the other of the first clock signal line CKL1 and the second clock signal line CKL2. Optionally, the control end of the third transistor T3 is electrically connected to the control end of the first transistor T1.

[0033] The stage transmission output module is electrically connected to the first node P, the second node Q and the stage transmission output end of the gate driving circuit. The stage transmission output module outputs the stage transmission signal to the next stage gate driving circuit through the stage transmission output end according to the signals of the first node P and the second node Q.

[0034] Optionally, the stage transmission output module includes a first stage transmission output transistor T6, a second stage transmission output transistor T7, a first capacitor C1 and a second capacitor C2. The control end of the first stage transmission output transistor T6 is electrically connected to the first node P, the input end of the first stage transmission output transistor T6 is electrically connected to the first voltage end VGH, and the output end of the first stage transmission output transistor T6 is electrically connected to the stage transmission output end; the control end of the second stage transmission output transistor T7 is electrically connected to the second node Q, and the output end of the second stage transmission output transistor T7 is electrically connected to the stage transmission output end; the first capacitor C1 is connected in series between the input end of the first stage transmission output transistor T6 and the control end of the first stage transmission output transistor T6; the second capacitor C2 is connected in series between the input end of the second stage transmission output transistor T7 and the control end of the second stage transmission output transistor T7.

[0035] Optionally, the input terminal of the second-stage transmission output transistor T7 may be electrically connected to the second voltage terminal VGL, and the input terminal of the second-stage transmission output transistor T7 may also be electrically connected to the first clock signal line CKL1 or the second clock signal line CKL2.

[0036] Optionally, the first-stage transmission output transistor T6 is a P-type transistor, and the voltage value supplied by the second voltage terminal VGL is smaller than the voltage value supplied by the first voltage terminal VGH.

[0037] Optionally, if the transistor to which the gate control signal Scan is applied is a P-type transistor, then the effective pulse of the gate control signal Scan corresponds to a low level state; if the transistor to which the gate control signal Scan is applied is an N-type transistor, then the effective pulse of the gate control signal Scan corresponds to a high level state.

[0038] Optionally, the stage transmission module 11 further includes a shielding module, the shielding module includes a shielding transistor T8, the control end of the shielding transistor T8 is electrically connected to the third voltage end, the input end of the shielding transistor T8 is electrically connected to the output end of the third transistor T3 and the output end of the fifth transistor T5, and the output end of the shielding transistor T8 is electrically connected to the control end of the second-stage transmission output transistor T7. The second-stage transmission output transistor T7 is a P-type transistor, and the voltage value supplied by the third voltage end is equal to the voltage value supplied by the second voltage end VGL. The second-stage transmission output transistor T7 is an N-type transistor, and the voltage value supplied by the third voltage end is equal to the voltage value supplied by the first voltage end VGH.

[0039] Optionally, see Figure 1B, in the m-th level gate driving circuit, the input end of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1; the first node control module receives the first clock signal CK1, the control end of the first transistor T1 and the control end of the third transistor T3 are electrically connected to the first clock signal line CKL1 transmitting the first clock signal CK1, and the control end of the fifth transistor T5 and the input end of the second-level transmission output transistor T7 are electrically connected to the second clock signal line CKL2 transmitting the second clock signal CK2. In the m+Ath level gate driving circuit, the input end of the second output transistor Tso2 is electrically connected to the second frequency division control line FDL2; the first node control module receives the second clock signal CK2, the control end of the first transistor T1 and the control end of the third transistor T3 are electrically connected to the second clock signal line CKL2, and the control end of the fifth transistor T5 and the input end of the second-level transmission output transistor T7 are electrically connected to the first clock signal line CKL1, so that the m+Ath level gate driving circuit and the mth level gate driving circuit that receive the mth level transmission signal Cas(m) output by the mth level gate driving circuit can generate corresponding gate control signals Scan according to the second frequency division control signal FD2 and the first frequency division control signal FD1 respectively.

[0040] Optionally, see Figure 2A to Figure 2B , so that the two-stage gate driving circuits cascaded with each other can generate the corresponding gate control signal Scan according to the first frequency division control signal FD1 and the second frequency division control signal FD2, the second clock signal CK2 is partially identical to the first frequency division control signal FD1, and the first clock signal CK1 is partially identical to the second frequency division control signal FD2. That is, when the display panel using the gate driving unit 10 does not need frequency division display, the second clock signal CK2 is identical to the first frequency division control signal FD1 (i.e., both are low level or both are high level), and the first clock signal CK1 is identical to the second frequency division control signal FD2 (i.e., both are low level or both are high level); when the display panel using the gate driving unit 10 needs frequency division display, the second clock signal CK2 is different from the first frequency division control signal FD1, the first clock signal CK1 is different from the second frequency division control signal FD2, and the first frequency division control signal FD1 is identical to the second frequency division control signal FD2 (i.e., both are low level or both are high level).

[0041] Optionally, the m-th level gate driving circuit and the m+A-th level gate driving circuit may both be odd-level gate driving circuits (e.g., if m is an odd number, A is also an even number; or m is an even number, A is also an odd number; the m-th level gate driving circuit and the m+A-th level gate driving circuit constitute an interlaced level transmission), so that the odd-level gate driving circuit generates a corresponding gate control signal Scan according to the first frequency division control signal FD1 and the second frequency division control signal FD2; the m-th level gate driving circuit and the m+A-th level gate driving circuit may both be even-level gate driving circuits (e.g., if m is an odd number, A is also an odd number; or m is an even number, A is also an even number; the m-th level gate driving circuit and the m+A-th level gate driving circuit constitute an interlaced level transmission), so that the even-level gate driving circuit generates a corresponding gate control signal Scan according to the first frequency division control signal FD1 and the second frequency division control signal FD2. In addition, the m-th level gate driving circuit can be one of the odd-level gate driving circuit and the even-level gate driving circuit, and the m+A-th level gate driving circuit is the other of the odd-level gate driving circuit and the even-level gate driving circuit, so that the odd-level gate driving circuit and the even-level gate driving circuit generate corresponding gate control signals Scan according to the first frequency division control signal FD1 and the second frequency division control signal FD2 respectively.

[0042] Optionally, in order to reduce the number of control signal lines used in the gate driving circuit, the first frequency division control line FDL1 can be electrically connected to the odd-numbered gate driving circuit, and the second frequency division control line FDL2 can be electrically connected to the even-numbered gate driving circuit, so that the odd-numbered gate driving circuit generates a corresponding gate control signal Scan according to the first frequency division control signal FD1, and the even-numbered gate driving circuit generates a corresponding gate control signal Scan according to the second frequency division control signal FD2.

[0043] Optionally, in the odd-numbered gate drive circuit, the input end of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1; the first node control module receives the first clock signal CK1, the control end of the first transistor T1 is electrically connected to the first clock signal line CKL1 that transmits the first clock signal CK1, the control end of the third transistor T3 is electrically connected to the first clock signal line CKL1 that transmits the first clock signal CK1, the control end of the fifth transistor T5 is electrically connected to the second clock signal line CKL2 that transmits the second clock signal CK2, and the input end of the second-stage transmission output transistor T7 is electrically connected to the second clock signal line CKL2. In the even-numbered gate drive circuit, the input end of the second output transistor Tso2 is electrically connected to the second frequency division control line FDL2; the first node control module receives the second clock signal CK2, the control end of the first transistor T1 is electrically connected to the second clock signal line CKL2 that transmits the second clock signal CK2, the control end of the third transistor T3 is electrically connected to the second clock signal line CKL2, the control end of the fifth transistor T5 is electrically connected to the first clock signal line CKL1, and the input end of the second-stage transmission output transistor T7 is electrically connected to the first clock signal line CKL1.

[0044] Please continue reading Figure 1B and Figure 2A , taking the m-th level gate driving circuit electrically connected to the first frequency division control line FDL1, the m+A-th level gate driving circuit electrically connected to the second frequency division control line FDL2, the transistors included in the multiple gate driving circuits are P-type transistors, the transistors using the gate control signal Scan are P-type transistors, the multiple gate driving circuits are transmitted row by row, and the display panel using the gate driving unit 10 starts to realize frequency division display from the m+3th row as an example, the working principle of the gate driving unit 10 is explained.

[0045] The first stage t1: the first frequency division control signal FD1 and the second clock signal CK2 are high levels, the second frequency division control signal FD2 and the first clock signal CK1 are low levels, the upper-level stage transmission signal Cas(m-1) received by the m-th stage gate driving circuit is high level, and the m+1-th stage gate driving circuit receives the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit as a high level.

[0046] In the m-th gate driving circuit, the first transistor T1 and the third transistor T3 are turned on according to the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first-stage transmission output transistor T6 and the first output transistor Tso1 are turned on, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first-stage transmission output transistor T6, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the upper stage transmission signal Cas(m-1) received by the m-th stage gate driving circuit turns off the second transistor T2, the second-stage transmission output transistor T7 and the second output transistor Tso2; the fifth transistor T5 is turned off according to the second clock signal CK2.

[0047] In the m+1th-level gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the second clock signal CK2, the fourth transistor T4, the first-level transmission output transistor T6, and the first output transistor Tso1 remain turned on, and the fifth transistor T5 is turned on according to the first clock signal CK1, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the second node Q via the fourth transistor T4 and the fifth transistor T5; the first voltage transmitted by the first voltage terminal VGH is transmitted to the level transmission output terminal via the first-level transmission output transistor T6, so that the m+1th level transmission signal Cas(m+1) output by the m+1th-level gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal via the first output transistor Tso1, so that the m+1th level gate control signal Scan(m+1) output by the m+1th-level gate driving circuit has a high level state; the second transistor T2, the second-level transmission output transistor T7, and the second output transistor Tso2 remain turned off.

[0048] Second stage t2: the second clock signal CK2 and the first frequency division control signal FD1 are at low level, and the first clock signal CK1, the second frequency division control signal FD2 and the upper stage transmission signal Cas(m-1) are at high level.

[0049] In the m-th level gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the first clock signal CK1, the fourth transistor T4, the first-level transmission output transistor T6, and the first output transistor Tso1 remain turned on, and the fifth transistor T5 is turned on according to the second clock signal CK2, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the second node Q via the fourth transistor T4 and the fifth transistor T5, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the level transmission output terminal via the first-level transmission output transistor T6, so that the m-th level transmission signal Cas(m) output by the m-th level gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal via the first output transistor Tso1, so that the m-th level gate control signal Scan(m) output by the m-th level gate driving circuit has a high level state; the second transistor T2, the second-level transmission output transistor T7, and the second output transistor Tso2 remain turned off.

[0050] The (m+1)th gate driving circuit performs the same operation as the (m)th gate driving circuit in the first stage t1.

[0051] The third stage t3: the second clock signal CK2 and the first frequency division control signal FD1 are at high level, and the first clock signal CK1, the second frequency division control signal FD2 and the upper stage transmission signal Cas(m-1) are at low level.

[0052] In the m-th gate driving circuit, the first transistor T1 and the third transistor T3 are turned on according to the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first-stage transmission output transistor T6, and the first output transistor Tso1 are turned on, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first-stage transmission output transistor T6, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the upper stage transmission signal Cas(m-1) turns on the second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2, the first clock signal CK1 is transmitted to the first node P through the second transistor T2, the second clock signal CK2 is transmitted to the stage transmission output terminal through the second-stage transmission output transistor T7, and the first frequency division control signal FD1 is output to the scan output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the fifth transistor T5 is turned off according to the second clock signal CK2.

[0053] The m+1th gate driving circuit performs the same operation as the mth gate driving circuit in the second stage t2, and the m+2th gate driving circuit performs the same operation as the m+1th gate driving circuit in the second stage t2.

[0054] Fourth stage t4: the second clock signal CK2 and the first frequency division control signal FD1 are at low level, and the first clock signal CK1, the second frequency division control signal FD2 and the upstream stage transmission signal Cas(m-1) are at high level.

[0055] In the m-th stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the first clock signal CK1, and the second capacitor C2 maintains the second-stage transmission output transistor T7 to be turned on, so that the second clock signal CK2 jumps from a high level to a low level and is coupled to the second node Q through the second capacitor C2 to further lower the potential of the second node Q, and the second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2 remain turned on, so that the first clock signal CK1 is transmitted to the first node P through the second transistor T2, so that the first-stage transmission output transistor T6 and the first output transistor Tso1 are turned off; the second clock signal CK2 is output to the stage transmission output terminal through the second-stage transmission output transistor T7, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit has a low level state; the first frequency division control signal FD1 is output to the scan output terminal through the second output transistor Tso2, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a low level state.

[0056] The m+1th level gate driving circuit performs the same operation as the mth level gate driving circuit in the third stage t3, the m+2th level gate driving circuit performs the same operation as the m+1th level gate driving circuit in the third stage t3, and the m+3th level gate driving circuit performs the same operation as the m+2th level gate driving circuit in the third stage t3.

[0057] The fifth stage t5: the second clock signal CK2 and the first frequency division control signal FD1 are at high level, the first clock signal CK1 and the second frequency division control signal FD2 are at low level, and the upstream stage transmission signal Cas(m-1) is at high level.

[0058] In the m-th gate driving circuit, the first transistor T1 and the third transistor T3 are turned on according to the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first-stage transmission output transistor T6, and the first output transistor Tso1 are turned on, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first-stage transmission output transistor T6, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the upper stage transmission signal Cas(m-1) turns off the second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2; the fifth transistor T5 is turned off according to the second clock signal CK2.

[0059] The m+1th level gate driving circuit performs the same operation as the mth level gate driving circuit in the fourth stage t4, the m+2th level gate driving circuit performs the same operation as the m+1th level gate driving circuit in the fourth stage t4, and the m+3th level gate driving circuit performs the same operation as the m+2th level gate driving circuit in the fourth stage t4.

[0060] The sixth stage t6: the second clock signal CK2 and the first frequency division control signal FD1 are at a low level, and the first clock signal CK1, the second frequency division control signal FD2 and the upper stage transmission signal Cas(m-1) are at a high level.

[0061] The m-th level gate driving circuit performs the same operation as in the second stage t2, the m+1-th level gate driving circuit performs the same operation as in the fifth stage t5, the m+2-th level gate driving circuit performs the same operation as in the fifth stage t5, and the m+3-th level gate driving circuit performs the same operation as in the fifth stage t5.

[0062] The seventh stage t7: the second clock signal CK2, the first frequency division control signal FD1 and the second frequency division control signal FD2 are at high level, and the first clock signal CK1 and the upstream stage transmission signal Cas(m-1) are at low level.

[0063] The mth gate driving circuit performs the same operation as the first stage t1, the m+1th gate driving circuit performs the same operation as the mth gate driving circuit in the sixth stage t6, and the m+2th gate driving circuit performs the same operation as the m+1th gate driving circuit in the sixth stage t6.

[0064] In the m+3-th level gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the second clock signal CK2, and the second capacitor C2 maintains the second-level transmission output transistor T7 to be turned on, so that the first clock signal CK1 jumps from a high level to a low level and is coupled to the second node Q through the second capacitor C2 to further lower the potential of the second node Q, and the second transistor T2, the second-level transmission output transistor T7, and the second output transistor Tso2 remain turned on, so that the second clock signal CK2 is transmitted to the first node P through the second transistor T2, so that the first-level transmission output transistor T6 and the first output transistor Tso1 are turned off; the first clock signal CK1 is output to the level transmission output terminal through the second-level transmission output transistor T7, so that the m+3-th level transmission signal Cas(m+3) output by the m+3-th level gate driving circuit has a low level state; the first frequency division control signal FD1 is output to the scan output terminal through the second output transistor Tso2, so that the m-th level gate control signal Scan(m+3) output by the m+3-th level gate driving circuit has a high level state.

[0065] Therefore, the m+3-level gate driving circuit can still provide the m+3-level transmission signal Cas(m+3) to the lower-level gate driving circuit, while the gate control signal Scan(m+3) output by the m+3-level gate driving circuit does not have a valid pulse, so that the transistor electrically connected to the m+3-level gate driving circuit cannot be turned on. Subsequently, when the gate driving unit 10 is used in the display panel, the sub-pixels electrically connected to the m+3-level gate driving circuit will not refresh the display data, so that the display panel can achieve frequency division display in the corresponding area.

[0066] In the eighth stage t8, the first frequency division control signal FD1 and the second frequency division control signal FD2 are maintained at a high level, and the second clock signal CK2 and the first clock signal CK1 jump between a low level state and a high level state.

[0067] The multi-stage gate driving circuit located after the m+3-stage gate driving circuit (such as the m+3-stage gate driving circuit to the m+C-stage gate circuit) makes the output multi-stage transmission signals Cas(m+3) to Cas(m+C) have valid pulses in sequence according to the first frequency division control signal FD1, the second frequency division control signal FD2, the second clock signal CK2 and the first clock signal CK1, while the gate control signals Scan(m+3) to Scan(m+C) output by the multi-stage gate driving circuit located after the m+3-stage gate driving circuit (such as the m+3-stage gate driving circuit to the m+C-stage gate circuit) do not have valid pulses. Wherein, C is greater than or equal to 0.

[0068] Until at least one of the first frequency division control signal FD1 and the second frequency division control signal FD2 starts to jump from a high level state to a low level state, part of the gate driving circuits in the multi-stage gate driving circuit starts to resume the output of valid pulses. Figure 3B In the ninth stage t9, the second clock signal CK2 and the first frequency division control signal FD1 are at high level, and the first clock signal CK1 and the second frequency division control signal FD2 are at low level. The m+C+1th gate circuit performs the same operation as the mth gate driving circuit in the fourth stage t4 in the ninth stage t9, so that the m+C+1th gate control signal Scan(m+C+1) output by the m+C+1th gate circuit has a valid pulse.

[0069] Optionally, the upper stage transmission signal may be inverted, so that the corresponding gate control signal Scan valid pulse is in a high level state.

[0070] It can be understood that in the first gate driving circuit of the multi-stage gate driving circuit, the start signal STV can be used as the upper-stage transmission signal.

[0071] Figure 3A to Figure 3B is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Figure 4 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention, Figure 5A to Figure 5B 1 is a timing diagram corresponding to the display device provided in an embodiment of the present invention; an embodiment of the present invention also includes a display device, including any of the above-mentioned gate driving units 10 and a display panel.

[0072] Optionally, the display panel includes a display area and a non-display area 100a located outside the display area, wherein the gate driving unit 10 may be located in the non-display area 100a.

[0073] The display panel includes a plurality of sub-pixels Pi and a plurality of first scan lines SL1, wherein the plurality of sub-pixels Pi include a light-emitting device Di and a pixel driving circuit for driving the light-emitting device Di to emit light, and the pixel driving circuit includes at least one transistor. The gate control signals Scan output by the plurality of gate driving circuits are transmitted to the control ends of the transistors of the plurality of pixel driving circuits via the plurality of first scan lines SL1, so that the display panel can control the plurality of sub-pixels Pi to realize frequency division display within a display cycle according to the gate control signal Scan.

[0074] Optionally, when the display panel implements frequency division display, a display cycle includes a write frame WF and a hold frame HF. In the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 jump between a high level state and a low level state, so that the plurality of sub-pixels Pi can write display data in the write frame WF to implement picture update.

[0075] If the transistors to which the plurality of gate control signals Scan output by the gate driving unit 10 are applied are P-type transistors, then, in the blanking interval after the writing frame WF or in at least one holding frame HF after the writing frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 may have a period of time in the same high level state, so that the sub-pixels Pi of the corresponding row do not refresh the written data. If the transistors to which the plurality of gate control signals Scan output by the gate driving unit 10 are applied are N-type transistors, then, in the blanking interval after the writing frame WF or in at least one holding frame HF after the writing frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 may have a period of time in the same low level state, so that the sub-pixels Pi of the corresponding row do not refresh the written data.

[0076] Optionally, the blanking interval includes a horizontal blanking interval and a vertical blanking interval.

[0077] Optionally, the number of times that the first frequency-division control signal FD1 and the second frequency-division control signal FD2 maintain the same level state in each holding frame HF may be the same or different, and the moments when the first frequency-division control signal FD1 and the second frequency-division control signal FD2 maintain the same level state in each holding frame HF may be the same or different, so that the display panel can have different display frequencies corresponding to different rows in a display cycle, thereby realizing frequency-division display at any position.

[0078] Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0079] Optionally, the plurality of first scan lines SL1 are arranged along the second direction y, each first scan line SL1 extends along a first direction x crossing the second direction y, and the plurality of first scan lines SL1 are configured to transmit a plurality of gate control signals Scan.

[0080] Please continue reading Figure 3A The display panel includes a plurality of data lines DL electrically connected to the plurality of sub-pixels Pi, the plurality of data lines DL are arranged along a first direction x, each data line DL extends along a second direction y, and the plurality of data lines DL are configured to transmit a plurality of data signals.

[0081] Please continue reading Figure 4 , the pixel driving circuit includes a driving transistor Tdr and a data transistor Tda.

[0082] The driving transistor Tdr and the light emitting device Di are connected in series between the first power line Vdd and the second power line Vss, the input end of the data transistor Tda is electrically connected to the corresponding data line DL, and the output end of the data transistor Tda is electrically connected to the input end of the driving transistor Tdr.

[0083] Optionally, the control end of the data transistor Tda of multiple sub-pixels Pi can be electrically connected to the gate driving unit 10 through the first scanning line SL1, so as to control the data transistor Tda of the multiple sub-pixels Pi to be turned on or off through the gate driving circuit, thereby controlling whether data is written into the control end of the driving transistor Tdr to determine whether the sub-pixel Pi performs a display data refresh operation.

[0084] Optionally, see Figure 3A to Figure 3B and Figure 4 The pixel driving circuit further includes a compensation transistor Tc, a reset transistor Ti1, an initialization transistor Ti2, a first light emission control transistor Ts1 and a second light emission control transistor Ts2.

[0085] The input and output terminals of the compensation transistor Tc are electrically connected between the control terminal of the driving transistor Tdr and the output terminal of the driving transistor Tdr, and the compensation transistor Tc is configured to connect the driving transistor Tdr in a diode form. Optionally, the compensation transistor Tc includes an oxide transistor or a silicon transistor.

[0086] The input terminal and the output terminal of the reset transistor Ti1 are electrically connected between the first reset line and the control terminal of the driving transistor Tdr, and the reset transistor Ti1 is configured to transmit the first reset signal VI1 transmitted by the first reset line to the control terminal of the driving transistor Tdr to achieve resetting of the potential of the control terminal of the driving transistor Tdr. Optionally, the reset transistor Ti1 includes an oxide transistor or a silicon transistor.

[0087] The input end of the initial transistor Ti2 is electrically connected to the second reset line, and the output end of the initial transistor Ti2 is electrically connected to the light-emitting device Di. The initial transistor Ti2 is configured to transmit the second reset signal VI2 transmitted by the second reset line to the anode of the light-emitting device Di to initialize the anode potential of the light-emitting device Di.

[0088] The input and output ends of the first light-emitting control transistor Ts1 are electrically connected between the first power line Vdd and the input end of the driving transistor Tdr, and the input and output ends of the second light-emitting control transistor Ts2 are electrically connected between the light-emitting device Di and the output end of the driving transistor Tdr. The first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 are configured to control the light-emitting moment of the light-emitting device Di.

[0089] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a third capacitor Cst, and the third capacitor Cst is connected in series between the first power line Vdd and the control end of the driving transistor Tdr.

[0090] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a fourth capacitor Cboost, and the fourth capacitor Cboost is connected in series between the control end of the driving transistor Tdr and the control end of the data transistor Tda.

[0091] Optionally, the pixel driving circuit of each sub-pixel Pi also includes a reset transistor Ti3, the input end of the reset transistor Ti3 is electrically connected to the third reset line, and the output end of the reset transistor Ti3 is electrically connected to the input end of the driving transistor Tdr; the control end of the reset transistor Ti3 is electrically connected to the control end of the initialization transistor Ti2, and the reset transistor Ti3 is configured to transmit the third reset signal VI3 transmitted by the third reset line to the input end of the driving transistor Tdr, so as to reset the potential of the input end of the driving transistor Tdr.

[0092] Optionally, the gate driving unit 10 included in the display panel can also be electrically connected to the control end of at least one of the compensation transistor Tc, reset transistor Ti1, initial transistor Ti2, reset transistor Ti3, first light-emitting control transistor Ts1, and second light-emitting control transistor Ts2 of multiple sub-pixels Pi.

[0093] Optionally, the display panel further includes a plurality of light emitting control lines EML, a plurality of second scan lines SL2, a plurality of third scan lines SL3, and a plurality of reset control lines VL. The plurality of light emitting control lines EML, the plurality of second scan lines SL2, the plurality of third scan lines SL3, and the plurality of reset control lines are arranged along the second direction y and extend along the first direction x, the plurality of light emitting control lines EML are configured to transmit a plurality of light emitting control signals EMA, the plurality of second scan lines SL2 transmit a plurality of second scan signals Scan2, the plurality of third scan lines SL3 transmit a plurality of third scan signals Scan3, and the plurality of reset control lines VL transmit a reset control signal EMB. Among them, the control end of the data transistor Tda of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding first scan line SL1 to the gate driving unit 10, the control end of the compensation transistor Tc of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding second scan line SL2, the control end of the reset transistor Ti1 of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding third scan line SL3, the control end of the initialization transistor Ti2 of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding reset control line VL, and the control ends of the first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 of the multiple sub-pixels Pi located in the same row are electrically connected to the corresponding light-emitting control line EML.

[0094] Taking the control end of the data transistor Tda being electrically connected to the gate driving unit 10 and the data transistor Tda being a P-type transistor as an example, the frequency division display working principle of the display panel in a display cycle is described. The writing frame WF includes a first reset phase tim1, a second reset phase tim2, a data writing phase tim3 and a light emitting phase tim4.

[0095] In the writing frame WF, in order to realize that the control end data of the multiple driving transistors Tdr included in the display panel can be written normally, the first frequency division control signal FD1 transmitted by the first frequency division control line FDL1 electrically connected to the gate driving unit 10 has a jump between a high level state and a low level state, and the second frequency division control signal FD2 transmitted by the second frequency division control line FDL2 electrically connected to the gate driving unit 10 has a jump between a high level state and a low level state, so that the gate driving unit 10 can output multiple levels of gate control signals Scan with valid pulses in the writing frame WF. Therefore, in the writing frame WF, the sub-pixels Pi of each row correspondingly undergo the first reset stage tim1, the second reset stage tim2, the data writing stage tim3 and the light emitting stage tim4.

[0096] Taking a row of multiple sub-pixels Pi as an example, the working principle of each stage of writing a frame WF is described as follows: Figure 5A shown.

[0097] In the first reset stage tim1, the initial transistor Ti2 and the reset transistor Ti3 are turned on according to the corresponding reset control signal EMB, and the compensation transistor Tc is turned on according to the corresponding second scan signal Scan2, so that the anode of the light-emitting device Di can be reset according to the second reset signal VI2, and the input end, output end and control end of the driving transistor Tdr can be reset according to the third reset signal VI3.

[0098] In the second reset stage tim2, the reset transistor Ti1 is turned on according to the corresponding third scan signal Scan3, and the compensation transistor Tc is turned on according to the corresponding second scan signal Scan2, so that the output end and the control end of the driving transistor Tdr are reset according to the second reset signal VI2.

[0099] In the data writing phase tim3, the data transistor Tda is turned on according to the corresponding first scanning signal Scan, and the compensation transistor Tc is turned on according to the corresponding second scanning signal Scan2, so that the control end of the driving transistor Tdr can be written with the data signal Vdata.

[0100] In the light emitting stage tim4 , the first light emitting control transistor Ts1 and the second light emitting control transistor Ts2 are turned on according to the light emitting control signal EMA, so that the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0101] Optionally, between the light emitting stage tim4 and the data writing stage tim3, a third reset stage tin is also included. In the third reset stage tin, the initial transistor Ti2 and the reset transistor Ti3 are turned on according to the corresponding reset control signal EMB, so that the anode of the light emitting device Di can be reset according to the second reset signal VI2, and the input and output ends of the driving transistor Tdr can be reset according to the third reset signal VI3.

[0102] Optionally, the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in the high level state at the first frequency division moment tfd1 (if the transistor to which the gate control signal Scan is applied is N-type, the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in the low level state at the first frequency division moment tfd1), and respectively have a high level state and a low level state jump at the second frequency division moment tfd2, and are both in the high level state again at the third frequency division moment tfd3 (if the transistor to which the gate control signal Scan is applied is N-type, the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in the low level state again at the third frequency division moment tfd3). The first frequency division moment tfd1 may correspond to a vertical blanking interval or a horizontal blanking interval, the second frequency division moment tfd2 may correspond to a vertical blanking interval or a horizontal blanking interval, and the third frequency division moment tfd3 may correspond to a vertical blanking interval or a horizontal blanking interval.

[0103] Please continue reading Figure 5A to Figure 5B, taking the first frequency division moment tfd1 corresponding to the vertical blanking interval, the second frequency division moment tfd2 and the third frequency division moment tfd3 corresponding to the horizontal blanking interval, and the first frequency division moment tfd1, the second frequency division moment tfd2 and the third frequency division moment tfd3 all being located in the same holding frame HF as an example, the working principle of the display panel in the holding frame HF is described. For the convenience of description, the multi-stage gate driving circuits located between the first frequency division moment tfd1 and the second frequency division moment tfd2 in the first holding frame HF and corresponding to the high level state of the first frequency division control signal FD1 and the second frequency division control signal FD2 are recorded as the first-stage gate driving circuit to the m-th-stage gate driving circuit; the multi-stage gate driving circuits corresponding to the high level state and the low level state jump of the first frequency division control signal FD1 and the second frequency division control signal FD2 after the second frequency division moment tfd2 in the first holding frame HF1 are recorded as the m+1-th-stage gate driving circuit to the m+n-th-stage gate driving circuit. After the third frequency division moment tfd3 in the first holding frame HF1, the multi-stage first gate driving circuit corresponding to the first frequency division control signal FD1 and the second frequency division control signal FD2 being in the same high level state again is recorded as the m+n+1-th stage gate driving circuit to the z-th stage gate driving circuit. The plurality of sub-pixels Pi located in the 1st to mth rows in the display panel are electrically connected to the 1st to mth stage gate driving circuits, the plurality of sub-pixels Pi located in the m+1st to m+nth rows are electrically connected to the m+1st to m+nth stage gate driving circuits, and the plurality of sub-pixels Pi located in the m+n+1st to zth rows are electrically connected to the m+n+1st to zth stage gate driving circuits.

[0104] Then, in the first hold frame HF1, the gate control signals Scan(1) to Scan(m) generated by the 1st to mth gate drive circuits do not output valid pulses, the data transistors Tda of the multiple sub-pixels Pi in the 1st to mth rows are turned off, and the multiple sub-pixels Pi located in the 1st to mth rows maintain the display screen of the write frame WF. The gate control signals Scan(m+1) to Scan(m+n) generated by the m+1st to m+nth gate drive circuits have valid pulse outputs, and the multiple sub-pixels Pi located in the m+1st to m+nth rows undergo the various stages of the write frame WF in the first hold frame HF1, so that the multiple sub-pixels Pi located in the m+1st to m+nth rows display a screen different from the screen displayed in the write frame WF in the first hold frame HF1. The gate control signals Scan(m+n+1)~Scan(z) generated by the m+n+1th-level gate driving circuit~the zth-level gate driving circuit do not output valid pulses, the data transistors Tda of the multiple sub-pixels Pi in the m+n+1th-level row to the zth-level row are turned off in the first hold frame HF1, and the multiple sub-pixels Pi located in the m+n+1th-level row to the zth-level row maintain the display screen of the write frame WF in the first hold frame HF1.

[0105] Please continue reading Figure 5A , Vgdb represents the gate-drain voltage difference of the driving transistor Tdr when the low-frequency display area in the prior art keeps refreshing the display data in the frame HF, and Scanb represents the gate control signal used in the prior art when the low-frequency display area keeps refreshing the display data in the frame HF. Vgd represents the gate-drain voltage difference of the driving transistor Tdr when the low-frequency display area in the present application stops refreshing the display data in the frame HF, and Scan represents the gate control signal used in the low-frequency display area in the present application stops refreshing the display data in the frame HF. Since the voltage state of the gate-drain voltage difference of the driving transistor Tdr will have an instantaneous bias on the driving transistor Tdr, resulting in a threshold shift of the driving transistor Tdr. The positive gate-drain voltage difference of the driving transistor Tdr causes the threshold voltage of the driving transistor Tdr to be positively biased, such as Figure 5A As shown in ①③⑤⑦; the negative gate-drain voltage difference of the driving transistor Tdr causes the threshold voltage of the driving transistor Tdr to be negatively biased, as shown in Figure 5AIn the prior art, in order to balance the bias influence of ② and ⑦ on the driving transistor Tdr, processes ④⑥ are added. However, in the prior art, the low-frequency display area does not stop refreshing the display data while maintaining the frame HF (that is, in the prior art, the gate control signals Scan(1)~Scan(m) generated by the 1st-level gate driving circuit to the mth-level gate driving circuit still output valid pulses, and the gate control signals Scan(m+n+1)~Scan(z) generated by the m+n+1th-level gate driving circuit to the zth-level gate driving circuit still output valid pulses). Compared with the present application, in which the low-frequency display area stops refreshing the display data while maintaining the frame HF (such as the gate control signals Scan(1)~Scan(m) generated by the 1st-level gate driving circuit to the mth-level gate driving circuit in the present application do not output valid pulses, and the gate control signals Scan(m+n+1)~Scan(z) generated by the m+n+1th-level gate driving circuit to the zth-level gate driving circuit do not output valid pulses), the prior art has an additional process ⑤, and the addition of process ⑤ will weaken the effects of processes ④ and ⑥, thereby worsening the offset of the threshold voltage Vth and causing worsening of the flicker. However, the present application does not have process ⑤, and thus will not worsen the offset of the threshold voltage Vth. Therefore, the present application stops outputting the effective pulse of the gate control signal Scan in the corresponding low-frequency display area, which is beneficial to improving the flicker problem.

[0106] Optionally, the state of the first frequency division control signal FD1 and the second frequency division control signal FD2 being both high level after the third frequency division time tfd3 can continue until the second holding frame HF2 after the first holding frame HF1. ​​Optionally, the state of the first frequency division control signal FD1 and the second frequency division control signal FD2 being both high level after the third frequency division time tfd3 can continue until the vertical blanking interval.

[0107] Taking the case that the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in the high level state after the third frequency division moment tfd3 and can continue to the vertical blanking interval as an example, in the second holding frame HF2, the first frequency division control signal FD1 and the second frequency division control signal FD2 are again in the high level state corresponding to the fourth frequency division moment tfd4. If before the fourth frequency division moment tfd4, the multi-stage gate driving circuit corresponding to the high level state and the low level state jump of the first frequency division control signal FD1 and the second frequency division control signal FD2 is the first-stage gate driving circuit to the m+n-th-stage gate driving circuit; after the fourth frequency division moment tfd4, the multi-stage gate driving circuit corresponding to the high level state of the first frequency division control signal FD1 and the second frequency division control signal FD2 is the m+n+1-th-stage gate driving circuit to the z-th-stage gate driving circuit.

[0108] Then, in the second hold frame HF2, the multiple sub-pixels Pi located in the 1st to m+nth rows have valid pulses according to the gate control signals Scan(1) to Scan(m+n) generated by the 1st to m+nth gate drive circuits, which turn on the data transistors Tda, so that the multiple sub-pixels Pi located in the 1st to m+nth rows display a screen different from the screen displayed in the write frame WF in the second hold frame HF2. The gate control signals Scan(m+n+1) to Scan(z) generated by the m+n+1st to zth gate drive circuits do not have valid pulse outputs, so that the multiple sub-pixels Pi located in the m+n+1st to zth rows maintain the display screen of the write frame WF.

[0109] Similarly, the working principle of a display cycle in the remaining holding frames HF can also be obtained.

[0110] Therefore, within a display cycle, multiple sub-pixels Pi in the 1st to mth rows can be used to display at a first frequency, multiple sub-pixels Pi in the m+1th to m+nth rows can be used to display at a second frequency, and multiple sub-pixels Pi in the m+n+1th to zth rows can be used to display at a third frequency.

[0111] Optionally, the first frequency may be greater than, less than or equal to the second frequency, so that the first display area and the second display area may display images at different or the same frequencies within a display cycle. Optionally, the third frequency may be equal to the first frequency or the second frequency. Optionally, the third frequency may be different from both the first frequency and the second frequency.

[0112] Optionally, the first frequency may be 1Hz to 360Hz, the second frequency may be 1Hz to 360Hz, and the third frequency may be 1Hz to 360Hz. Optionally, the first frequency may be 60Hz, so that the multiple sub-pixels Pi in the 1st to mth rows can be used to display a display screen with a lower refresh frequency (such as used to continuously display power information, time information, certain signal status information (such as wifi information, traffic information, Bluetooth information, etc.), and also used to display barrage messages, etc.). The second frequency may be 120Hz, so that the multiple sub-pixels Pi in the m+1th to m+nth rows can be used to display a display screen with a higher refresh frequency (such as movie screens, game screens, etc.). The third frequency may be 30Hz, so that the multiple sub-pixels Pi in the m+n+1th to zth rows can be used to display a display screen with a frequency different from that of the first display area and the second display area (such as information used to implement information input functions (such as keyboards, handwriting boxes, etc.), text boxes, comment areas, etc.), such as Figure 3B shown.

[0113] Among them, z can be less than or equal to the number of rows of sub-pixels Pi included in the display panel. In addition, m+n can also be less than or equal to the number of rows of sub-pixels Pi included in the display panel. That is, the number of sub-display areas with different display frequencies in the display panel is greater than or equal to 2. If m+n is equal to the number of rows of sub-pixels Pi included in the display panel, the display panel includes two sub-display areas with different display frequencies; z is equal to the number of rows of sub-pixels Pi included in the display panel, and the display panel includes three sub-display areas with different display frequencies; z is less than the number of rows of sub-pixels Pi included in the display panel, and the display panel includes at least four sub-display areas with different display frequencies. It can be understood that a plurality of sub-pixels Pi included in a row can be used as a sub-display area, and a plurality of sub-pixels Pi included in multiple consecutive rows can also be used as a sub-display area.

[0114] It can be understood that the number of sub-display areas corresponding to each display period of the display panel may be different, and the corresponding frequency division positions may also be different, so that the display panel is suitable for different application scenarios.

[0115] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A gate driving unit, characterized in that: include: A first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded gate drive circuits, each of the gate drive circuits comprising: A level transmission module, the level transmission module receives the upper level transmission signal, the first clock signal and the second clock signal, and outputs the current level transmission signal to the lower level gate driving circuit; as well as An output module, wherein the output module is electrically connected to the first frequency division control line or the second frequency division control line, and the first node and the second node in the stage transmission module, and the output module outputs the first frequency division control signal or the second frequency division control signal to the scan output end of the gate drive circuit of this stage according to the signals of the first node and the second node.

2. The gate driving unit according to claim 1, characterized in that: The first frequency division control line is electrically connected to the gate driving circuit of the odd-numbered stage, and the second frequency division control line is electrically connected to the gate driving circuit of the even-numbered stage; The first frequency division control signal is partially identical to the second frequency division control signal.

3. The gate driving unit according to claim 2, characterized in that: The output module comprises: a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the first node, an input terminal of the first output transistor is electrically connected to a first voltage terminal, and an output terminal of the first output transistor is electrically connected to the scan output terminal; and a second output transistor, wherein a control terminal of the second output transistor is electrically connected to the second node, and an output terminal of the second output transistor is electrically connected to the scan output terminal; Among them, the input end of the second output transistor in the odd-numbered gate driving circuit is electrically connected to the first frequency division control line, and the input end of the second output transistor in the even-numbered gate driving circuit is electrically connected to the second frequency division control line.

4. The gate driving unit according to claim 2, characterized in that: The level transmission module comprises: A first node control module, electrically connected to the first node, the first node control module receiving the first clock signal or the second clock signal to control a signal of the first node; a second node control module electrically connected to the second node, the second node control module receiving the first clock signal, the second clock signal and the upper level transmission signal to control the signal of the second node; and The level transmission output module is electrically connected to the first node, the second node and the level transmission output terminal of the gate driving circuit. The level transmission output module outputs the level transmission signal of the current level to the gate driving circuit of the next level through the level transmission output terminal according to the signals of the first node and the second node.

5. The gate driving unit according to claim 4, characterized in that: The first node control module in the odd-numbered gate driving circuit receives the first clock signal, and the first node control module in the even-numbered gate driving circuit receives the second clock signal; The first clock signal is partially identical to the second frequency-division control signal, and the second clock signal is partially identical to the first frequency-division control signal.

6. The gate driving unit according to claim 4, characterized in that: The first node control module includes: a first transistor, wherein an input terminal of the first transistor is electrically connected to a second voltage terminal; and a second transistor, wherein a control terminal of the second transistor is electrically connected to the second node, an input terminal of the second transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the second transistor is electrically connected to the output terminal of the first transistor; Among them, the control end of the first transistor in the odd-numbered gate driving circuit is electrically connected to the first clock signal line transmitting the first clock signal, and the control end of the first transistor in the even-numbered gate driving circuit is electrically connected to the second clock signal line transmitting the second clock signal.

7. The gate driving unit according to claim 4, characterized in that: The second node control module includes: a third transistor, wherein an input terminal of the third transistor receives the upper-stage transmission signal, and an output terminal of the third transistor is electrically connected to the second node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the first node, and an input terminal of the fourth transistor is electrically connected to the first voltage terminal; a fifth transistor, wherein an input terminal of the fifth transistor is electrically connected to an output terminal of the fourth transistor, and an output terminal of the fifth transistor is electrically connected to the second node; Among them, the control end of the third transistor in the odd-numbered gate driving circuit is electrically connected to the first clock signal line transmitting the first clock signal, and the control end of the fifth transistor is electrically connected to the second clock signal line transmitting the second clock signal; the control end of the third transistor in the even-numbered gate driving circuit is electrically connected to the second clock signal line, and the control end of the fifth transistor is electrically connected to the first clock signal line.

8. The gate driving unit according to claim 7, characterized in that: The level transmission output module comprises: a first-stage transmission output transistor, wherein a control terminal of the first-stage transmission output transistor is electrically connected to the first node, an input terminal of the first-stage transmission output transistor is electrically connected to the first voltage terminal, and an output terminal of the first-stage transmission output transistor is electrically connected to the stage transmission output terminal; a second-stage transmission output transistor, wherein a control terminal of the second-stage transmission output transistor is electrically connected to the second node, and an output terminal of the second-stage transmission output transistor is electrically connected to the stage transmission output terminal; a first capacitor, the first capacitor being connected in series between the input terminal of the first-stage transmission output transistor and the control terminal of the first-stage transmission output transistor; and A second capacitor, the second capacitor is connected in series between the input terminal of the second-stage transmission output transistor and the control terminal of the second-stage transmission output transistor; Among them, the input end of the second-stage transmission output transistor in the odd-numbered gate driving circuit is electrically connected to the second clock signal line, and the input end of the second-stage transmission output transistor in the even-numbered gate driving circuit is electrically connected to the first clock signal line.

9. The gate driving unit according to claim 8, characterized in that: The level transmission module also includes: The shielding module comprises a shielding transistor, wherein the control end of the shielding transistor is electrically connected to the third voltage end, the input end of the shielding transistor is electrically connected to the output end of the third transistor and the output end of the fifth transistor, and the output end of the shielding transistor is electrically connected to the control end of the second-stage transmission output transistor.

10. A display device, characterized in that: include: The gate driving unit according to any one of claims 1 to 9; The display panel comprises a plurality of sub-pixels and a plurality of first scan lines, wherein the plurality of sub-pixels comprise light-emitting devices and a pixel driving circuit for driving the light-emitting devices to emit light, wherein the pixel driving circuit comprises at least one transistor; Wherein, the gate control signals output by the plurality of gate driving circuits are transmitted to the control ends of the transistors of the plurality of pixel driving circuits via the plurality of first scanning lines.

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