Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display. The first mode is equivalent to a high-frequency display mode, the second mode is equivalent to a low-frequency display mode, and the duration of the threshold compensation transistor in an on state in the first mode is shortened, namely the duration of a control signal received by the grid electrode of the threshold compensation transistor in a high-level state is shortened. The duration is smaller than the duration of the threshold compensation transistor in the open state in the second mode, so that the total duration of the threshold compensation transistor in the open state in the first mode is reduced, the influence on the threshold voltage of the threshold compensation transistor is reduced, the threshold compensation transistor is prevented from being turned off earlier, and the service life of the threshold compensation transistor is prolonged. The potential of the grid electrode of the driving transistor can be stabilized in a voltage range based on the current display requirement, so that the display effect of the display panel is improved, and the service life of the display panel is prolonged.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, various display devices have been widely used in people's lives and work, bringing great convenience to people's daily lives. As one of the important components of display devices, the design of display panels will directly or indirectly affect the display effect of display devices.

[0003] Therefore, how to improve the display effect and service life of the display panel is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] In view of the above problems, the present application provides a display panel and a display device to achieve the purpose of improving the display effect and service life of the display panel. The specific solution is as follows:

[0005] A first aspect of the present application provides a display panel, the display panel comprising: a pixel circuit and a light emitting element;

[0006] The pixel circuit includes a driving transistor and a threshold compensation transistor, wherein the active layer of the threshold compensation transistor is a metal oxide active layer; the first electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor; the gate of the threshold compensation transistor is used to receive a control signal to control the working state of the threshold compensation transistor; the driving transistor is used to provide a driving current for the light-emitting element;

[0007] The working mode of the pixel circuit includes a first mode and a second mode;

[0008] In the first mode, the data refresh frequency of the pixel circuit is a first data refresh frequency F1; in the second mode, the data refresh frequency of the pixel circuit is a second data refresh frequency F2; wherein F1>F2;

[0009] In the first mode, the duration that the threshold compensation transistor is in the on state is T1; in the second mode, the duration that the threshold compensation transistor is in the on state is T2; wherein T1<T2.

[0010] A second aspect of the present application provides a display device, which includes the display panel described above.

[0011] By means of the above technical scheme, the present application provides a display panel and a display device, wherein the first mode is equivalent to a high-frequency display mode, and the second mode is equivalent to a low-frequency display mode. By shortening the duration that the threshold compensation transistor is in an on state in the first mode, it is equivalent to reducing the duration that the control signal received by the gate of the threshold compensation transistor is in a high-level state, so that it is less than the duration that the threshold compensation transistor is in an on state in the second mode, thereby reducing the total duration that the threshold compensation transistor is in an on state in the first mode, thereby reducing the impact on the threshold voltage of the threshold compensation transistor, avoiding the threshold compensation transistor from being turned off earlier, and ensuring that the potential of the gate of the driving transistor will be stable within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0013] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of a control timing of a threshold compensation transistor provided by an embodiment of the present invention;

[0015] Figure 3 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0016] Figure 4 A schematic diagram of the working timing of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 5 A schematic diagram of the working timing of another pixel circuit provided by an embodiment of the present invention;

[0018] Figure 6 A schematic diagram of the working timing of another pixel circuit provided by an embodiment of the present invention;

[0019] Figure 7 A schematic diagram of the working timing of another pixel circuit provided by an embodiment of the present invention;

[0020] Figure 8 A schematic diagram of the working timing of another pixel circuit provided by an embodiment of the present invention;

[0021] Fig. 9 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation mode of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] It should be noted that the directional words appearing in the present invention are based on the relative position relationship shown in the drawings and cannot be used as an absolute limitation to the present application.

[0025] refer to Figure 1 , Figure 1 A schematic diagram of a display panel according to an embodiment of the present invention is provided. Figure 2 , Figure 2 A control timing diagram of a threshold compensation transistor provided by an embodiment of the present invention. Figure 1 As shown, the display panel 100 provided by the embodiment of the present invention includes a pixel circuit 11 and a light emitting element Q. The pixel circuit 11 is implemented by using LTPO (Low Temperature Polycrystalline Oxide) technology.

[0026] Among them, the pixel circuit 11 includes a driving transistor M1 and a threshold compensation transistor M2, the active layer of the threshold compensation transistor M2 is a metal oxide active layer; the first electrode of the threshold compensation transistor M2 is electrically connected to the gate of the driving transistor M1 to form a first node N1, and the second electrode of the threshold compensation transistor M2 is electrically connected to the first electrode of the driving transistor M1 to form a second node N2; the gate of the threshold compensation transistor M2 is used to receive a control signal S1 to control the working state of the threshold compensation transistor M2; the first electrode of the driving transistor M1 is coupled to the anode of the light-emitting element Q, and provides a driving current to the light-emitting element Q after the driving transistor M1 is turned on.

[0027] The threshold compensation transistor M2 is used to compensate the threshold voltage of the driving transistor M1, and the gate of the threshold compensation transistor M2 is used to receive the control signal S1. The control signal S1 received by the threshold compensation transistor M2 is a pulse signal, and the effective pulse of the control signal S1 controls the threshold compensation transistor M2 to be in an on state to compensate the threshold voltage of the driving transistor M1; the invalid pulse of the control signal S1 controls the threshold compensation transistor M2 to be in an off state. Therefore, under the control of the control signal S1, the threshold compensation transistor M2 selectively compensates the threshold voltage of the driving transistor M1.

[0028] It should be noted that the threshold compensation transistor M2 is in an on state when the control signal S1 is in a high level state, and is in an off state when the control signal S1 is in a low level state. When the threshold compensation transistor M2 is turned off, that is, when the gate of the threshold compensation transistor M2 receives a low level signal, the voltage of the second node N2 will be pulled down, and the first node N1 will write a charge to the second node N2, and finally the potential of the first node N1 will be stabilized within a voltage range based on the current display requirements.

[0029] The operation mode of the pixel circuit 11 includes a first mode and a second mode.

[0030] In the first mode, the data refresh frequency of the pixel circuit 11 is a first data refresh frequency F1; in the second mode, the data refresh frequency of the pixel circuit 11 is a second data refresh frequency F2; wherein F1>F2.

[0031] like Figure 2 As shown, in the first mode, the duration of the threshold compensation transistor M2 being in the on state is T1; in the second mode, the duration of the threshold compensation transistor M2 being in the on state is T2; wherein T1<T2.

[0032] Specifically, in the embodiment of the present invention, the first mode can be understood as the working mode when the display panel 100 adopts a high-frequency data refresh frequency (for example, 120Hz) driving mode to drive the display, which is also called a high-frequency display mode in the field; the second mode can be understood as the working mode when the display panel 100 adopts a low-frequency data refresh frequency (for example, 1Hz or 10Hz) driving mode to drive the display, which is also called a low-frequency display mode in the field. In the first mode, in a data refresh cycle, the number of frames is kept zero or the number of frames is kept very small, and the gate of the driving transistor M1 maintains the input of the data signal, that is, the gate potential of the driving transistor M1 is refreshed more frequently, and the total time length of the threshold compensation transistor M2 in the on state will be longer. In the second mode, in a data refresh cycle, the number of frames is kept relatively large, and in a data refresh cycle, the gate potential of the driving transistor M1 remains unchanged for a long time, and the total time length of the threshold compensation transistor M2 in the off state will be longer.

[0033] For the pixel circuit 11 implemented by LTPO technology, when the threshold compensation transistor M2 is in the on state, that is, when the gate of the threshold compensation transistor M2 receives a high-level signal, its metal oxide active layer will be subjected to a positive bias. After being turned on for a long time, the threshold voltage Vth of the threshold compensation transistor M2 will gradually become positively biased, which will cause the threshold compensation transistor M2 to be turned off earlier, and ultimately cause the charge written from the first node N1 to the second node N2 to be less, so that the potential of the first node N1 will be higher, and the driving current provided by the driving transistor M1 to the light-emitting element Q will be reduced, which is reflected in the reduction of the brightness of the light-emitting element Q, thereby affecting the display effect and service life of the display panel 100.

[0034] It can be seen from this that the longer the control signal S1 received by the gate of the threshold compensation transistor M2 is in the high level state, the more seriously the threshold voltage Vth of the threshold compensation transistor M2 is positively biased.

[0035] It can be seen from the above description that in the first mode, since the total time duration of the threshold compensation transistor M2 being in the on state is relatively long, that is, the control signal S1 received by the gate of the threshold compensation transistor M2 is in the high level state for a long time, the threshold voltage Vth of the threshold compensation transistor M2 is greatly affected. In the second mode, since the total time duration of the threshold compensation transistor M2 being in the off state is relatively long, that is, the control signal S1 received by the gate of the threshold compensation transistor M2 is in the low level state for a long time, the threshold voltage Vth of the threshold compensation transistor M2 is less affected.

[0036] Therefore, in the embodiment of the present invention, the control logic in the first mode is improved by shortening the duration T1 that the threshold compensation transistor M2 is in the on state in the first mode, which is equivalent to reducing the duration that the control signal S1 received by the gate of the threshold compensation transistor M2 is in the high level state, so that it is less than the duration T2 that the threshold compensation transistor M2 is in the on state in the second mode, thereby reducing the total time that the threshold compensation transistor M2 is in the on state in the first mode, thereby reducing the impact on the threshold voltage Vth of the threshold compensation transistor M2, avoiding the threshold compensation transistor M2 from being turned off earlier, and ensuring that the first node N1 can write sufficient charge to the second node N2, so that the potential of the first node N1 will eventually stabilize within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel 100.

[0037] refer to Figure 3 , Figure 3 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention. The pixel circuit 11 also includes: a data write transistor M3, the data write transistor M3 is connected between the second electrode of the driving transistor M1 and the data signal line L1, the first electrode of the data write transistor M3 is used to receive the data signal Vdata, the second electrode of the data write transistor M3 is connected to the second electrode of the driving transistor M1, and the gate of the data write transistor M3 is used to receive the control signal S2. Among them, the control signal S2 received by the data write transistor M3 is a pulse signal, and the effective pulse of the control signal S2 controls the data write transistor M3 to be in an on state to provide the data signal Vdata to the driving transistor M1; the invalid pulse of the control signal S2 controls the data write transistor M3 to be in an off state. Therefore, under the control of the control signal S2, the data write transistor M3 selectively provides the data signal Vdata to the driving transistor M1.

[0038] Optional, such as Figure 3 As shown, the pixel circuit 11 also includes a first transistor M4 and a second transistor M5. The first transistor M4 is connected between the first power signal terminal PVDD and the second electrode of the driving transistor M1, and the second transistor M5 is connected between the first electrode of the driving transistor M1 and the light-emitting element Q, and is used to control whether the pixel circuit 11 is in the light-emitting stage or the non-light-emitting stage.

[0039] The cathode of the light emitting element Q is connected to the second power signal terminal PVEE.

[0040] The gates of the first transistor M4 and the second transistor M5 simultaneously receive the control signal EM. Under the control of the control signal EM, the first transistor M4 and the second transistor M5 are in an on state or an off state. The control signal EM received by the gates of the first transistor M4 and the second transistor M5 is a pulse signal. In the light-emitting stage, the control signal EM outputs a valid pulse to control the first transistor M4 and the second transistor M5 to be in an on state, so that the driving current provided by the driving transistor M1 flows into the light-emitting element Q to make it emit light; in the non-light-emitting stage, the control signal EM outputs an invalid pulse to control the first transistor M4 and the second transistor M5 to be in an off state, so that the light-emitting element Q does not emit light.

[0041] Optional, such as Figure 3 As shown, the pixel circuit 11 also includes a gate reset transistor M6; the gate reset transistor M6 is connected between the gate reset signal line L2 and the gate of the driving transistor M1, the first electrode of the gate reset transistor M6 receives the reset signal Vref1, the second electrode of the gate reset transistor M6 is connected to the gate of the driving transistor M1, and the gate of the gate reset transistor M6 is used to receive the control signal S3. Among them, the control signal S3 received by the gate reset transistor M6 is a pulse signal, and the effective pulse of the control signal S3 controls the gate reset transistor M6 to be in the on state, then the reset signal Vref1 is written into the gate of the driving transistor M1 through the gate reset transistor M6 to reset the gate of the driving transistor M1; the invalid pulse of the control signal S3 controls the gate reset transistor M6 to be in the off state.

[0042] The working process of the pixel circuit 11 includes a gate reset stage; in the gate reset stage, the gate reset transistor M6 is in an on state, and the gate reset signal line L2 writes a gate reset signal Vref1 to the gate of the driving transistor M1.

[0043] It should be noted that in an optional embodiment of the present invention, the active layer of the gate reset transistor M6 is a metal oxide active layer to reduce the leakage current of the gate reset transistor M6 in the off state, improve the stability of the potential at the first node N1, and further improve the display effect of the display panel 100.

[0044] It should be further noted that in the embodiment of the present invention, the metal oxide active layer is an IGZO active layer. It is understandable that the active layer of the gate reset transistor M6 is an IGZO active layer, and the active layer of the threshold compensation transistor M2 is an IGZO active layer.

[0045] Optional, such as Figure 3As shown, the pixel circuit 11 further includes an anode reset transistor M7; the first electrode of the anode reset transistor M7 is used to receive the reset signal Vref2, the second electrode of the anode reset transistor M7 is connected to the anode of the light emitting element Q, and the gate of the anode reset transistor M7 is used to receive the control signal S4. The control signal S4 received by the anode reset transistor M7 is a pulse signal, and the effective pulse of the control signal S4 controls the anode reset transistor M7 to be in the on state, then the reset signal Vref2 is written into the anode of the light emitting element Q through the anode reset transistor M7 to reset the anode of the light emitting element Q; the invalid pulse of the control signal S4 controls the anode reset transistor M7 to be in the off state.

[0046] Optional, such as Figure 3 As shown, the pixel circuit 11 also includes a bias adjustment transistor M8; the bias adjustment transistor M8 is connected between the second electrode of the driving transistor M1 and the bias adjustment signal line L3; the first electrode of the bias adjustment transistor M8 is used to receive the bias adjustment signal DVH, the second electrode of the bias adjustment transistor M8 is connected to the second electrode of the driving transistor M1, and the gate of the bias adjustment transistor M8 is used to receive the control signal S5. Among them, the control signal S5 received by the bias adjustment transistor M8 is a pulse signal, and the effective pulse of the control signal S5 controls the bias adjustment transistor M8 to be in the on state, so as to provide the bias adjustment signal DVH to the gate of the driving transistor M1; the invalid pulse of the control signal S5 controls the bias adjustment transistor M8 to be in the off state. Therefore, under the control of the control signal S5, the bias adjustment transistor M8 selectively provides the bias adjustment signal DVH to the driving transistor M1.

[0047] Optional, such as Figure 3 As shown, the pixel circuit 11 further includes a storage capacitor C1, a first plate of the storage capacitor C1 is connected to the first power signal terminal PVDD, and a second plate of the storage capacitor C1 is connected to the first node N1.

[0048] It should be noted that the transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other pole is called the drain, that is, when the first pole is the source, the second pole is the drain. In addition, the threshold compensation transistor M2 and the gate reset transistor M6 in the transistors used in the embodiment of the present application are N-type transistors, and the remaining transistors are P-type transistors. Among them, the P-type transistor is turned on when the control signal received by the gate is in a low level state, and is turned off when the control signal received by the gate is in a high level state; the N-type transistor is turned on when the control signal received by the gate is in a high level state, and is turned off when the control signal received by the gate is in a low level state.

[0049] In other words, for an N-type transistor, the valid pulse of the control signal is the pulse corresponding to the high level period, and the invalid pulse of the control signal is the pulse corresponding to the low level period; for a P-type transistor, the valid pulse of the control signal is the pulse corresponding to the low level period, and the invalid pulse of the control signal is the pulse corresponding to the high level period.

[0050] It should be further explained that the pixel circuit 11 in the display panel 100 can be in various forms. Figure 3 The pixel circuit 11 shown is only one type of pixel circuit used in the display panel provided in the embodiment of the present application, and the same improvement can be made to other types of pixel circuits.

[0051] In an optional embodiment of the present invention, reference Figure 4 , Figure 4 A schematic diagram of the working timing of a pixel circuit provided by an embodiment of the present invention; Figure 5 , Figure 5 A schematic diagram of another working timing of a pixel circuit provided by an embodiment of the present invention; Figure 6 , Figure 6 A working timing diagram of another pixel circuit provided by an embodiment of the present invention. The working process of the pixel circuit 11 includes a data writing phase and a first phase; in the data writing phase, a data signal Vdata is written to the gate of the driving transistor M1. The working process of the pixel circuit 11 includes a bias adjustment phase and a second phase; in the bias adjustment phase, a bias adjustment signal DVH is written to the gate of the driving transistor M1.

[0052] The starting time of the data writing phase is the same as the starting time of the first phase, and the threshold compensation transistor M2 is in an on state in the first phase. The starting time of the bias adjustment phase is the same as the starting time of the second phase, and the threshold compensation transistor M2 is in an on state in the second phase.

[0053] In the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3<T4. And / or, in the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5<T6.

[0054] Specifically, in the embodiment of the present invention, in the data writing stage, the data writing transistor M3 is in an on state, and the threshold compensation transistor M2 is in an on state, and the data signal line L1 writes the data signal Vdata to the gate of the driving transistor M1. In the bias adjustment stage, the bias adjustment transistor M8 is in an on state, and the threshold compensation transistor M2 is in an on state, and the bias adjustment signal line L3 writes the bias adjustment signal DVH to the gate of the driving transistor M1.

[0055] like Figure 4 As shown, in the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3<T4. Also in the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5=T6. That is, only the time when the threshold compensation transistor M2 is in a high level state in the first stage corresponding to the data writing stage in the high-frequency display mode (i.e., the first mode) is improved.

[0056] That is to say, the technical solution of the present application shortens the time during which the threshold compensation transistor M2 is in a high-level state in the first stage corresponding to the data writing stage in the high-frequency display mode (i.e., the first mode), that is, shortens the time during which the threshold compensation transistor M2 is in an on state in the first stage corresponding to the data writing stage in the high-frequency display mode, so that it is less than the time during which the threshold compensation transistor M2 is in a high-level state in the first stage corresponding to the data writing stage in the low-frequency display mode (i.e., the second mode), thereby reducing the total time during which the threshold compensation transistor M2 is in an on state in the first mode, that is, there is a relationship of (T3+T5)<(T4+T6), thereby reducing the impact on the threshold voltage Vth of the threshold compensation transistor M2, avoiding the threshold compensation transistor M2 from being turned off earlier, ensuring that the first node N1 can write sufficient charge to the second node N2, so that the potential of the first node N1 will eventually stabilize within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel 100.

[0057] like Figure 5 As shown, in the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3=T4. Also in the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5<T6. That is, only the time when the threshold compensation transistor M2 is in the high level state in the second stage corresponding to the bias adjustment stage in the high frequency display mode (i.e., the first mode) is improved.

[0058] That is to say, the technical solution of the present application shortens the time during which the threshold compensation transistor M2 is in a high-level state in the second stage corresponding to the bias adjustment stage in the high-frequency display mode (i.e., the first mode), that is, shortens the time during which the threshold compensation transistor M2 is in an on state in the second stage corresponding to the bias adjustment stage in the high-frequency display mode, so that it is less than the time during which the threshold compensation transistor M2 is in a high-level state in the second stage corresponding to the bias adjustment stage in the low-frequency display mode (i.e., the second mode), thereby reducing the total time during which the threshold compensation transistor M2 is in an on state in the first mode, that is, there is a relationship of (T3+T5)<(T4+T6), thereby reducing the impact on the threshold voltage Vth of the threshold compensation transistor M2, avoiding the threshold compensation transistor M2 from being turned off earlier, ensuring that the first node N1 can write sufficient charge to the second node N2, so that the potential of the first node N1 will eventually stabilize within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel 100.

[0059] like Figure 6As shown, in the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3<T4. Also in the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5<T6. That is, the time when the threshold compensation transistor M2 is in a high level state in the first stage corresponding to the data writing stage in the high-frequency display mode (i.e., the first mode) is improved, and at the same time, the time when the threshold compensation transistor M2 is in a high level state in the second stage corresponding to the bias adjustment stage in the high-frequency display mode (i.e., the first mode) is improved.

[0060] That is to say, the technical solution of the present application shortens the time when the threshold compensation transistor M2 is in a high-level state in the first stage corresponding to the data writing stage in the high-frequency display mode (i.e., the first mode), that is, shortens the time when the threshold compensation transistor M2 is in an on state in the first stage corresponding to the data writing stage in the high-frequency display mode, so that it is shorter than the time when the threshold compensation transistor M2 is in a high-level state in the first stage corresponding to the data writing stage in the low-frequency display mode (i.e., the second mode); at the same time, shortens the time when the threshold compensation transistor M2 is in a high-level state in the second stage corresponding to the bias adjustment stage in the high-frequency mode (i.e., the first mode), that is, shortens the time when the threshold compensation transistor M2 is in a high-level state in the second stage corresponding to the bias adjustment stage in the high-frequency mode. The time in the on state is made shorter than the time when the threshold compensation transistor M2 is in the high level state in the second stage corresponding to the bias adjustment stage in the low-frequency mode (i.e., the second mode), so as to minimize the total time when the threshold compensation transistor M2 is in the on state in the first mode, that is, there is a relationship of (T3+T5)<(T4+T6), thereby reducing the influence on the threshold voltage Vth of the threshold compensation transistor M2, avoiding the threshold compensation transistor M2 from being turned off earlier, ensuring that the first node N1 can write enough charge to the second node N2, so that the potential of the first node N1 will eventually stabilize within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel 100.

[0061] In an optional embodiment of the present invention, Figure 4-Figure 6 As shown, the duration of the first phase is greater than or equal to the duration of the data writing phase. The duration of the second phase is greater than or equal to the duration of the bias adjustment phase.

[0062] Specifically, in the embodiment of the present invention, the duration of the first stage is longer than the duration of the data writing stage, so as to ensure that the data signal Vdata can be completely written into the gate of the driving transistor M1.

[0063] In the embodiment of the present invention, the duration of the second stage is longer than the duration of the bias adjustment stage, which is used as an example to ensure that the bias adjustment signal DVH can be completely written into the gate of the driving transistor M1.

[0064] In an optional embodiment of the present invention, reference Figure 7 , Figure 7 A schematic diagram of the working timing of another pixel circuit provided by an embodiment of the present invention; Figure 8 , Figure 8 A schematic diagram of another working timing of a pixel circuit provided by an embodiment of the present invention: The working process of the pixel circuit 11 includes a bias adjustment stage and a second stage; in the bias adjustment stage, a bias adjustment signal DVH is written to the gate of the driving transistor M1.

[0065] The starting time of the bias adjustment phase is the same as the starting time of the second phase, and in the second phase the threshold compensation transistor M2 is in an on state.

[0066] In the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5=0, and T6>0.

[0067] Specifically, in the embodiments of the present invention, Figure 7 As shown, in the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3=T4. Also in the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5=0, and T6>0. That is, only the time when the threshold compensation transistor M2 is in a high level state in the second stage corresponding to the bias adjustment stage in the high-frequency display mode (i.e., the first mode) is improved.

[0068] Since the display panel 100 generally does not have a flickering problem in the high-frequency display mode, the gate of the driving transistor M1 may not be biased in the high-frequency display mode, that is, there is no need to transmit the bias adjustment signal DVH to the gate of the driving transistor M1. Based on this, the technical solution of the present application cancels the bias adjustment stage and the second stage in the high-frequency display mode (i.e., the first mode), thereby reducing the total time that the threshold compensation transistor M2 is in the on state in the first mode, that is, there is a relationship of (T3+0)<(T4+T6), thereby minimizing the impact on the threshold voltage Vth of the threshold compensation transistor M2, avoiding the threshold compensation transistor M2 from being turned off earlier, ensuring that the first node N1 can write enough charge to the second node N2, so that the potential of the first node N1 will eventually stabilize within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel 100.

[0069] like Figure 8 As shown, in the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3<T4. Also in the first mode, the duration of the second stage is T5; in the second mode, the duration of the second stage is T6; wherein T5=0, and T6>0. That is, the time when the threshold compensation transistor M2 is in a high level state in the first stage corresponding to the data writing stage in the high-frequency display mode (i.e., the first mode) is improved, and at the same time, the time when the threshold compensation transistor M2 is in a high level state in the second stage corresponding to the bias adjustment stage in the high-frequency display mode (i.e., the first mode) is improved.

[0070] That is to say, the technical solution of the present application cancels the bias adjustment stage and the second stage under the high-frequency display mode (i.e., the first mode); at the same time, by shortening the time when the threshold compensation transistor M2 is in a high-level state in the first stage corresponding to the data writing stage in the high-frequency mode (i.e., the first mode), that is, shortening the time when the threshold compensation transistor M2 is in an on state in the first stage corresponding to the data writing stage in the high-frequency mode, so that it is less than the time when the threshold compensation transistor M2 is in a high-level state in the first stage corresponding to the data writing stage in the low-frequency mode (i.e., the second mode), the total time when the threshold compensation transistor M2 is in an on state in the first mode is minimized, that is, there is a relationship of (T3+0)<(T4+T6), thereby reducing the impact on the threshold voltage Vth of the threshold compensation transistor M2, avoiding the threshold compensation transistor M2 from being turned off earlier, ensuring that the first node N1 can write sufficient charge to the second node N2, so that the potential of the first node N1 will eventually stabilize within a voltage range based on the current display requirements, thereby improving the display effect and service life of the display panel 100.

[0071] In an optional embodiment of the present invention, Figure 7-Figure 8 As shown, the duration of the first phase is greater than or equal to the duration of the data writing phase. In the second mode, the duration of the second phase is greater than or equal to the duration of the bias adjustment phase.

[0072] Specifically, in the embodiment of the present invention, the duration of the first stage is longer than the duration of the data writing stage, so as to ensure that the data signal Vdata can be completely written into the gate of the driving transistor M1.

[0073] In the embodiment of the present invention, the duration of the second stage is longer than the duration of the bias adjustment stage, which is used as an example to ensure that the bias adjustment signal DVH can be completely written into the gate of the driving transistor M1.

[0074] Based on the above embodiments of the present invention, accordingly, the embodiments of the present application further provide a display device, referring to Fig. 9 , Fig. 9 The display device 200 includes the display panel described in the above embodiment of the present application, and can be any display device with display function, such as a touch screen, a mobile phone, a tablet computer, a laptop, an e-book or a television.

[0075] The display panel and display device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0076] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0077] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0078] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel comprises: a pixel circuit and a light emitting element; The pixel circuit includes a driving transistor and a threshold compensation transistor, the active layer of the threshold compensation transistor is a metal oxide active layer; the first electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor, and the second electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor; the gate of the threshold compensation transistor is used to receive a control signal to control the working state of the threshold compensation transistor; the driving transistor is used to provide a driving current for the light-emitting element; The working mode of the pixel circuit includes a first mode and a second mode; In the first mode, the data refresh frequency of the pixel circuit is a first data refresh frequency F1; in the second mode, the data refresh frequency of the pixel circuit is a second data refresh frequency F2; wherein F1>F2; In the first mode, the duration that the threshold compensation transistor is in the on state is T1; in the second mode, the duration that the threshold compensation transistor is in the on state is T2; wherein T1<T2.

2. The display panel according to claim 1, characterized in that: The working process of the pixel circuit includes a data writing phase and a first phase; in the data writing phase, a data signal is written to the gate of the driving transistor; The starting time of the data writing phase is the same as the starting time of the first phase, and the threshold compensation transistor is in an on state in the first phase; In the first mode, the duration of the first stage is T3; in the second mode, the duration of the first stage is T4; wherein T3<T4.

3. The display panel according to claim 2, characterized in that: The duration of the first phase is greater than or equal to the duration of the data writing phase.

4. The display panel according to any one of claims 1 to 3, characterized in that: The working process of the pixel circuit includes a bias adjustment stage and a second stage; in the bias adjustment stage, a bias adjustment signal is written to the gate of the driving transistor; The starting time of the bias adjustment phase is the same as the starting time of the second phase, and the threshold compensation transistor is in an on state in the second phase; In the first mode, the duration of the second stage is T5; In the second mode, the duration of the second stage is T6, wherein T5<T6.

5. The display panel according to claim 4, characterized in that: The duration of the second phase is greater than or equal to the duration of the bias adjustment phase.

6. The display panel according to any one of claims 1 to 3, characterized in that: The working process of the pixel circuit includes a bias adjustment stage and a second stage; in the bias adjustment stage, a bias adjustment signal is written to the gate of the driving transistor; The starting time of the bias adjustment phase is the same as the starting time of the second phase, and the threshold compensation transistor is in an on state in the second phase; In the first mode, the duration of the second stage is T5; In the second mode, the duration of the second stage is T6, wherein T5=0, and T6>0.

7. The display panel according to claim 6, characterized in that: In the second mode, the duration of the second phase is greater than or equal to the duration of the bias adjustment phase.

8. The display panel according to claim 1, characterized in that: The pixel circuit also includes a data writing transistor; The data writing transistor is connected to the data signal line; the working process of the pixel circuit includes a data writing stage; In the data writing phase, the data writing transistor is in an on state, and the data signal line writes a data signal to the gate of the driving transistor.

9. The display panel according to claim 1, characterized in that: The pixel circuit also includes a bias adjustment transistor; The bias adjustment module is connected to the bias adjustment signal line; The working process of the pixel circuit includes a bias adjustment stage; In the bias adjustment stage, the bias adjustment transistor is in an on state, and the bias adjustment signal line writes a bias adjustment signal to the gate of the driving transistor.

10. The display panel according to claim 1, characterized in that: The pixel circuit also includes a gate reset transistor; The gate reset transistor is connected to the gate reset signal line; the working process of the pixel circuit includes a gate reset stage; In the gate reset phase, the gate reset transistor is in an on state, and the gate reset signal line writes a gate reset signal to the gate of the driving transistor.

11. The display panel according to claim 10, characterized in that: The active layer of the gate reset transistor is a metal oxide active layer.

12. The display panel according to claim 1 or 10, characterized in that: The metal oxide active layer is an IGZO active layer.

13. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1-12.

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