Receiving end regulation and control method for VxLan / NvGRE tunnel frame and related device

Abstract

The invention discloses a receiving end regulation and control method for a VxLan / NvGRE tunnel frame and a related device, and the method comprises the steps: analyzing a receiving frame type which comprises a TCP / IP frame, a VxLan tunnel frame or an NvGRE tunnel frame; a receiving frame type extraction enable signal is controlled, the receiving frame type extraction enable signal comprises a VNM signal and a VNE signal, the value of the VNM signal comprises 1 or 0, and the value of the VNE signal comprises 1 or 0; extracting an enable signal and a receiving frame type according to the receiving frame type, and extracting a TCP / IP frame header, a VxLan tunnel frame header or an NvGRE tunnel frame header to obtain TCP / IP frame header extraction content, VxLan tunnel frame header extraction content or NvGRE tunnel frame header extraction content; performing Hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content or the NvGRE tunnel frame header extraction content to obtain a Hash calculation result; mapping of processor cores is completed according to the Hash calculation result and the load condition of the multi-core processor of the system. The invention aims to overcome the defects of the existing RSS technology and realize effective processing and load balancing of the VxLan / NVGRE tunnel frame on the basis of reserving the RSS function for the traditional TCP / IP frame.

Description

Technical Field

[0001] The present invention belongs to the technical field of Ethernet control, and in particular relates to a receiving end control method for VxLan / NvGRE tunnel frames and related devices. Background Art

[0002] Currently, the mainstream Ethernet controllers all use Receive-side Scaling (RSS) technology, mainly because RSS technology is relatively mature and has good software compatibility. The main advantage of RSS technology is that it can efficiently utilize the performance of multi-core processors to achieve load balancing of network data processing. Specifically, when the Ethernet end node receives a TCP / IP frame, RSS technology will dynamically distribute the data to each processor core of the system according to the hash algorithm (usually based on fields such as source IP address, destination IP address, source TCP / UDP port address, and destination TCP / UDP port address), thereby effectively avoiding overload of a single processor core and improving overall data processing efficiency.

[0003] With the rapid development of cloud computing and virtualization technology, large-scale data centers have an increasing demand for virtual networks. VxLan (Virtual Extensible Local Area Network) and NVGRE (Network Virtualization using Generic Routing Encapsulation) are two major tunnel encapsulation technologies. By adding header information to the second-layer data frame and encapsulating it into a new UDP data packet, the number of VLAN (Virtual Local Area Network) segments has been greatly expanded from the traditional 4096 to 16 million, effectively solving the problem of insufficient virtual network resources in cloud computing data centers. Therefore, VxLan / NVGRE tunnel frames have been widely used in the Ethernet field.

[0004] Since the VxLan / NVGRE tunnel frame changes the structure of the original Ethernet frame during the encapsulation process, especially adding additional header information, the traditional hash calculation method based on the source IP address, destination IP address, source TCP / UDP port address, and destination TCP / UDP port address is no longer applicable. In other words, the traditional RSS technology cannot effectively dynamically distribute the VxLan / NVGRE tunnel frame to each processor core of the system, and thus cannot achieve load balancing, affecting the network data processing capability of the multi-core processor. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a receiving-end control method and related devices for VxLan / NvGRE tunnel frames, which aims to overcome the shortcomings of the existing RSS technology and achieve effective processing and load balancing of VxLan / NVGRE tunnel frames while retaining the RSS function for traditional TCP / IP frames.

[0006] In order to solve the above technical problems, the present invention is implemented by the following technical solutions:

[0007] According to a first aspect of the present invention, a receiving end control method for a VxLan / NvGRE tunnel frame is provided, comprising:

[0008] Parsing a received frame type, where the received frame type includes a TCP / IP frame, a VxLan tunnel frame, or an NvGRE tunnel frame;

[0009] Controlling a reception frame type extraction enable signal, wherein the reception frame type extraction enable signal includes a VNM signal and a VNE signal, wherein the value of the VNM signal includes 1 or 0, and the value of the VNE signal includes 1 or 0;

[0010] Extract the TCP / IP frame header, the VxLan tunnel frame header, or the NvGRE tunnel frame header according to the received frame type extraction enable signal and the received frame type, and obtain the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content, or the NvGRE tunnel frame header extraction content;

[0011] Performing hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content, or the NvGRE tunnel frame header extraction content to obtain a hash calculation result;

[0012] The mapping of the processor cores is completed according to the hash calculation result and the load condition of the system multi-core processor.

[0013] In a possible implementation manner of the first aspect, extracting the TCP / IP frame header, the VxLan tunnel frame header, or the NvGRE tunnel frame header according to the frame type extraction enable signal and the received frame type is specifically:

[0014] When the received frame type is a TCP / IP frame, and the value of the VNM signal is 0, and the value of the VNE signal is 0, extracting the TCP / IP frame header;

[0015] When the received frame type is an NvGRE tunnel frame, and the value of the VNM signal is 1, and the value of the VNE signal is 1, extracting the NvGRE tunnel frame header;

[0016] When the received frame type is a VxLan tunnel frame, the value of the VNM signal is 1, and the value of the VNE signal is 0, extract the VxLan tunnel frame header;

[0017] When the received frame type is a VxLan tunnel frame, the value of the VNM signal is 0, and the value of the VNE signal is 1, the VxLan tunnel frame header is extracted.

[0018] In a possible implementation manner of the first aspect, when extracting the NvGRE tunnel frame header, the extracted content specifically includes:

[0019] {Flow_ID[7:0], L2_DA[47:0], VSID[23:0], VLAN_tag[15:0]}.

[0020] In a possible implementation manner of the first aspect, when extracting the VxLan tunnel frame header, the extracted content specifically includes:

[0021] {L2_DA[47:0], VNID[23:0], VLAN_tag[15:0]}.

[0022] In a possible implementation manner of the first aspect, when the TCP / IP frame header is extracted, the extracted content specifically includes:

[0023] {source IPv4 address, destination IPv4 address, source port address, destination port address}.

[0024] In a possible implementation manner of the first aspect, when extracting the NvGRE tunnel frame header, the extraction length is 10B or 12B.

[0025] In a possible implementation manner of the first aspect, when extracting the VxLan tunnel frame header, the extraction length is 9B or 11B.

[0026] According to a second aspect of the present invention, there is provided a receiving end control device for a VxLan / NvGRE tunnel frame, comprising:

[0027] A receiving frame parsing module, used for parsing the receiving frame type, wherein the receiving frame type includes a TCP / IP frame, a VxLan tunnel frame or an NvGRE tunnel frame;

[0028] A mode control module, used for controlling a received frame type extraction enable signal, wherein the received frame type extraction enable signal includes a VNM signal and a VNE signal, wherein the value of the VNM signal includes 1 or 0, and the value of the VNE signal includes 1 or 0;

[0029] A frame header extraction module, used to extract an enable signal and the received frame type according to the received frame type, perform TCP / IP frame header extraction, VxLan tunnel frame header extraction or NvGRE tunnel frame header extraction, and obtain TCP / IP frame header extraction content, VxLan tunnel frame header extraction content or NvGRE tunnel frame header extraction content;

[0030] A hash calculation module is used to perform hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content or the NvGRE tunnel frame header extraction content to obtain a hash calculation result;

[0031] The DMA channel selection module is used to complete the mapping of the processor core according to the hash calculation result and the load condition of the system multi-core processor.

[0032] According to a third aspect of the present invention, a device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the receiving end control method for VxLan / NvGRE tunnel frames is implemented.

[0033] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the receiving end control method for a VxLan / NvGRE tunnel frame is implemented.

[0034] Compared with the prior art, the present invention has at least the following beneficial effects:

[0035] Traditional RSS technology is mainly applicable to load balancing processing of TCP / IP frames, but for VxLan / NVGRE tunnel frames, due to the change of frame structure and the addition of additional header information, traditional methods cannot be effectively applied. The present invention provides a receiving end control method for VxLan / NvGRE tunnel frames, which dynamically extracts the frame header content of TCP / IP frames, VxLan tunnel frames or NvGRE tunnel frames by parsing the received frame type and extracting an enable signal according to the received frame type, thereby realizing the effective support of RSS technology for VxLan / NVGRE tunnel frames and expanding the scope of application of RSS technology. The present invention performs hash calculation on the extracted tunnel frame header content, and completes the mapping of processor cores according to the hash calculation result and the load of the system multi-core processor, so that VxLan / NVGRE tunnel frames can be dynamically allocated to each processor core of the system like traditional TCP / IP frames, effectively avoiding the overload of a single processor core, realizing load balancing processing of tunnel frames, and improving the overall network data processing efficiency. Through the implementation of the present invention, the VxLan / NVGRE tunnel frames widely used in cloud computing and virtualization technologies can be efficiently processed and no longer become a bottleneck for network data processing, which not only improves the resource utilization of multi-core processors, but also improves the overall performance of the system. In summary, the present invention, while retaining the RSS function for traditional TCP / IP frames, solves the problem that the existing RSS technology is not applicable to VxLan / NVGRE tunnel frames, realizes load balancing processing of tunnel frames, and improves resource utilization and system performance.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the specific implementation modes of the present invention, the drawings required for use in the description of the specific implementation modes will be briefly introduced below. Obviously, the drawings described below are some implementation modes of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 The present invention is a flowchart of a receiving end control method for VxLan / NvGRE tunnel frames according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] like Figure 1 As shown, an embodiment of the present invention provides a receiving end regulation method for VxLan / NvGRE tunnel frames, the purpose of which is to solve the problem that the existing RSS technology cannot effectively achieve load balancing when processing VxLan / NVGRE tunnel frames. The receiving end regulation method for VxLan / NvGRE tunnel frames specifically includes the following steps:

[0041] Step 1: parse the received frame type, where the received frame type includes a TCP / IP frame, a VxLan tunnel frame, or an NvGRE tunnel frame.

[0042] That is to say, when the Ethernet end node receives a data frame, it first identifies the type of the frame and determines whether the current received frame is a traditional TCP / IP frame or a VxLan / NVGRE tunnel frame.

[0043] Specifically, it is determined whether the received frame is a TCP / IP frame, a VxLan tunnel frame or an NvGRE tunnel frame according to the frame header information.

[0044] Step 2, control the received frame type extraction enable signal, the received frame type extraction enable signal includes a VNM (Vxlan-NvGRE mode) signal and a VNE (Vxlan-NvGRE enable) signal, the value of the VNM signal includes 1 or 0, and the value of the VNE signal includes 1 or 0.

[0045] That is to say, the system generates the receive frame type extraction enable signal (VNM and VNE) through the control logic. The setting of these two signals enables the system to flexibly extract the corresponding frame header information according to the currently received frame type, thereby improving the processing efficiency and flexibility. It should be noted that the receive frame type extraction enable signal can be configured by the user.

[0046] Specifically, when VNM and VNE are both 1, the frame header extraction object is the NVGRE tunnel frame; when VNM and VNE are both 0, the frame header extraction object is the traditional TCP / IP frame; when VNM is 0 and VNE is 1 or VNM is 1 and VNE is 0, the frame header extraction object is the VxLan tunnel frame. The control results are shown in Table 1 below.

[0047] Table 1

[0048] Serial number VNM VN Control Results 1 1 1 NVGRE tunnel frame 2 0 1 VxLan Tunnel Frame 3 1 0 VxLan Tunnel Frame 4 0 0 Traditional TCP / IP frame

[0049] Step 3: Extract the enable signal and the received frame type according to the received frame type, extract the TCP / IP frame header, VxLan tunnel frame header or NvGRE tunnel frame header, and obtain the TCP / IP frame header extraction content, VxLan tunnel frame header extraction content or NvGRE tunnel frame header extraction content.

[0050] That is, after determining the type of the received frame (TCP / IP frame, VxLan tunnel frame or NvGRE tunnel frame) and the value of the corresponding frame type extraction enable signal (VNM and VNE), the system enters the frame header extraction stage.

[0051] In one implementable manner, in combination with Table 1, the extraction of the enable signal and the received frame type according to the received frame type is performed to extract the TCP / IP frame header, the VxLan tunnel frame header, or the NvGRE tunnel frame header, as shown in the following:

[0052] a. When the received frame type is a TCP / IP frame, and the value of the VNM signal is 0, and the value of the VNE signal is 0, the TCP / IP frame header is extracted.

[0053] That is, when the received frame is identified as a TCP / IP frame, and the values ​​of the VNM signal and the VNE signal are both 0, the system determines that there is no need to process the VxLan or NvGRE tunnel frame, and therefore directly extracts the TCP / IP frame header.

[0054] In this implementation manner, when the TCP / IP frame header is extracted, the extracted content specifically includes:

[0055] {source IPv4 address, destination IPv4 address, source port address, destination port address}.

[0056] b. When the received frame type is an NvGRE tunnel frame, and the value of the VNM signal is 1, and the value of the VNE signal is 1, extract the NvGRE tunnel frame header.

[0057] That is, if the received frame is identified as an NvGRE tunnel frame, and the values ​​of the VNM signal and the VNE signal are both 1, the system extracts the frame header of the NvGRE tunnel frame.

[0058] In this implementation manner, when extracting the NvGRE tunnel frame header, the extracted content specifically includes:

[0059] {Flow_ID[7:0], L2_DA[47:0], VSID[23:0], VLAN_tag[15:0]}. For different NvGRE tunnel frames, the extracted content is unique, that is, the extracted content in different NvGRE tunnel frames is different and can be effectively distinguished.

[0060] The contents of L2_DA[47:0] and VLAN_tag[15:0] are included in the Outer_Ethernet_Header field of the NvGRE tunnel frame, and the contents of Flow_ID[7:0] and VSID[23:0] are included in the NvGRE_Header field of the NvGRE tunnel frame.

[0061] Specifically, the NvGRE tunnel frame format is shown in Table 2 below:

[0062] Table 2

[0063]

[0064] The format of Outer_UDP_Header is shown in Table 3 below. The destination port must be set to the NVGRE port number.

[0065] Table 3

[0066]

[0067] The NVGRE_Header format is shown in Table 4 below:

[0068] Table 4

[0069]

[0070] c. When the received frame type is a VxLan tunnel frame, the value of the VNM signal is 1, and the value of the VNE signal is 0, extract the VxLan tunnel frame header.

[0071] d. When the received frame type is a VxLan tunnel frame, the value of the VNM signal is 0, and the value of the VNE signal is 1, extract the VxLan tunnel frame header.

[0072] That is to say, when the received frame is a VxLan tunnel frame, there are two cases according to the values ​​of the VNM and VNE signals: if the VNM signal is 1 and the VNE signal is 0, the system performs a VxLan tunnel frame header extraction operation. If the VNM signal is 0 and the VNE signal is 1, the system performs a VxLan tunnel frame header extraction operation.

[0073] In this implementation, when extracting the VxLan tunnel frame header, the extracted content specifically includes:

[0074] {L2_DA[47:0], VNID[23:0], VLAN_tag[15:0]}. For different VxLan tunnel frames, this extracted content is unique, that is, the above-mentioned extracted content in different VxLan tunnel frames is different and can be effectively distinguished.

[0075] Among them, the L2_DA[47:0] and VLAN_tag[15:0] contents are included in the Outer_Ethernet_Header field of the VxLan tunnel frame, and the VNID[23:0] contents are included in the VxLan_Header field of the VxLan tunnel frame.

[0076] Specifically, the VxLan tunnel frame format is shown in Table 5 below.

[0077] Table 5

[0078]

[0079] The format of Outer_UDP_Header is shown in Table 6 below. The destination port must be set to the VxLan port number.

[0080] Table 6

[0081]

[0082] The VxLan_Header format is shown in Table 7 below.

[0083] Table 7

[0084]

[0085] In one implementable manner, when extracting the NvGRE tunnel frame header, the extracted length is 10B or 12B; when extracting the VxLan tunnel frame header, the extracted length is 9B or 11B.

[0086] Step 4: Perform hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content or the NvGRE tunnel frame header extraction content to obtain a hash calculation result.

[0087] That is, after obtaining the TCP / IP frame header extraction content, VxLan tunnel frame header extraction content or NvGRE tunnel frame header extraction content, the extracted frame header information is hashed according to a preset hash algorithm (such as MD5, SHA-1, etc.) to obtain a hash calculation result. Different frames are mapped to different processor cores through hash calculation, thereby avoiding overloading of a single processor core.

[0088] For VxLan tunnel frames, the hash calculation objects are L2_DA, VNID, and VLAN_tag; for NvGRE tunnel frames, the hash calculation objects are flow_ID, L2_DA, VSID, and VLAN_tag.

[0089] Step 5: Complete the mapping of processor cores according to the hash calculation result and the load of the system multi-core processor.

[0090] That is to say, the system maps the processor cores according to the hash calculation results and the load of the system's multi-core processors. Specifically, the system first obtains the current load information of each processor core, and then selects a processor core with a relatively light load to process the currently received frame according to the hash calculation results, ensuring the overall data processing efficiency of the system and achieving the goal of load balancing.

[0091] The hash_result is calculated by hashing, and the data packet processing task is mapped to the corresponding DMA_channel_number of the system according to the result.

[0092] To summarize, the present invention effectively solves the problem that the existing RSS technology cannot achieve load balancing when processing VxLan / NVGRE tunnel frames by parsing the received frame type, controlling the received frame type to extract an enable signal, extracting the frame header, performing hash calculations, and completing the mapping of the processor core, thereby improving the network data processing capability of the multi-core processor.

[0093] In another embodiment of the present invention, a receiving end control device for VxLan / NvGRE tunnel frames is provided, which is used to implement a receiving end control method for VxLan / NvGRE tunnel frames in the above embodiment, specifically including a receiving frame parsing module (RCOE), a mode control module, a frame header extraction module, a Hash calculation module and a DMA channel selection module, and each module is configured as follows:

[0094] The receiving frame parsing module is used to parse the receiving frame type, and the receiving frame type includes TCP / IP frame, VxLan tunnel frame or NvGRE tunnel frame.

[0095] Specifically, the main function of the receiving frame parsing module is to determine whether the current receiving frame type is a traditional TCP / IP frame or a VxLan / NVGRE tunnel frame, and send the parsing result to the frame header extraction module.

[0096] The mode control module is used to control the reception frame type extraction enable signal, wherein the reception frame type extraction enable signal includes a VNM signal and a VNE signal, wherein the value of the VNM signal includes 1 or 0, and the value of the VNE signal includes 1 or 0.

[0097] Specifically, the main function of the mode control module is to control the enable signal of TCP / IP frame, VxLan tunnel frame or NvGRE tunnel frame, which mainly includes two signals, namely VNM signal and VNE signal. When VNM and VNE are both 1, the frame header extraction module processes the NvGRE tunnel frame; when VNM and VNE are both 0, the frame header extraction module processes the traditional TCP / IP frame; when VNM is 0 and VNE is 1 or VNM is 1 and VNE is 0, the frame header extraction module processes the VxLan tunnel frame.

[0098] A frame header extraction module is used to extract an enable signal and the received frame type according to the received frame type, and extract the TCP / IP frame header, VxLan tunnel frame header or NvGRE tunnel frame header to obtain the TCP / IP frame header extraction content, VxLan tunnel frame header extraction content or NvGRE tunnel frame header extraction content.

[0099] Specifically, the main function of the frame header extraction module is to extract the TCP / IP frame header or VxLan tunnel frame header or NvGRE tunnel frame according to the parsing results of the receiving frame parsing module and the control results of the mode control module, and send the extracted content to the Hash calculation module.

[0100] The hash calculation module is used to perform hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content or the NvGRE tunnel frame header extraction content to obtain a hash calculation result.

[0101] That is to say, the main function of the Hash calculation module is to complete the Hash result calculation of the extracted content and send the calculation result to the DMA channel selection module.

[0102] The DMA channel selection module is used to complete the mapping of the processor core according to the hash calculation result and the load condition of the system multi-core processor.

[0103] That is to say, the DMA channel selection module completes the mapping of the processor cores according to the output result of the Hash calculation module and the load of the system multi-core processor, thereby achieving dynamic load balancing.

[0104] According to the above scheme, the logic design of each module in the present invention is described in Verilog language, and it is integrated with other modules in the network controller to perform system-level verification. The verification results show that the present invention realizes the design function and the performance meets expectations.

[0105] The present invention can be used in a network controller with an RSS function, and is particularly suitable for a multi-processor system such as a server, a measurement and control system center, and a Linux multi-core platform that needs to balance the network data throughput rate according to the system load and network processing performance when the input frame is a VxLan / NVGRE tunnel frame.

[0106] All relevant contents of each step involved in the aforementioned embodiment of a method for controlling the receiving end of a VxLan / NvGRE tunnel frame can be referred to the functional description of the functional module corresponding to the receiving end control device for a VxLan / NvGRE tunnel frame in the embodiment of the present invention, and will not be repeated here. The division of modules in the embodiment of the present invention is schematic, which is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present invention can be integrated into a processor, or it can exist physically separately, or two or more modules can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of software functional modules.

[0107] In another embodiment of the present invention, a computer device is provided, the computer device including a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., which are the computing core and control core of the terminal, which are suitable for implementing one or more instructions, and are specifically suitable for loading and executing one or more instructions in a computer storage medium to implement a corresponding method flow or a corresponding function; the processor described in the embodiment of the present invention can be used for an operation of a receiving end control method for a VxLan / NvGRE tunnel frame.

[0108] In another embodiment of the present invention, the present invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device for storing programs and data. It can be understood that the computer-readable storage medium here can include both built-in storage media in the computer device and, of course, extended storage media supported by the computer device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the above-mentioned embodiment of a receiving end control method for VxLan / NvGRE tunnel frames.

[0109] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0111] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0113] In the present invention, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0114] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A receiving end control method for VxLan / NvGRE tunnel frames, characterized in that: include: Parsing a received frame type, where the received frame type includes a TCP / IP frame, a VxLan tunnel frame, or an NvGRE tunnel frame; Controlling a reception frame type extraction enable signal, wherein the reception frame type extraction enable signal includes a VNM signal and a VNE signal, wherein the value of the VNM signal includes 1 or 0, and the value of the VNE signal includes 1 or 0; Extract the TCP / IP frame header, the VxLan tunnel frame header, or the NvGRE tunnel frame header according to the received frame type extraction enable signal and the received frame type, and obtain the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content, or the NvGRE tunnel frame header extraction content; Performing hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content, or the NvGRE tunnel frame header extraction content to obtain a hash calculation result; The mapping of the processor cores is completed according to the hash calculation result and the load condition of the system multi-core processor.

2. A method for controlling a receiving end of a VxLan / NvGRE tunnel frame according to claim 1, characterized in that: The extraction of the TCP / IP frame header, the VxLan tunnel frame header or the NvGRE tunnel frame header according to the frame type extraction enable signal and the received frame type is specifically as follows: When the received frame type is a TCP / IP frame, and the value of the VNM signal is 0, and the value of the VNE signal is 0, extracting the TCP / IP frame header; When the received frame type is an NvGRE tunnel frame, and the value of the VNM signal is 1, and the value of the VNE signal is 1, extracting the NvGRE tunnel frame header; When the received frame type is a VxLan tunnel frame, the value of the VNM signal is 1, and the value of the VNE signal is 0, extract the VxLan tunnel frame header; When the received frame type is a VxLan tunnel frame, the value of the VNM signal is 0, and the value of the VNE signal is 1, the VxLan tunnel frame header is extracted.

3. A method for controlling a receiving end of a VxLan / NvGRE tunnel frame according to claim 2, characterized in that: When extracting the NvGRE tunnel frame header, the extracted content specifically includes: {Flow_ID[7:0], L2_DA[47:0], VSID[23:0], VLAN_tag[15:0]}.

4. A method for controlling a receiving end of a VxLan / NvGRE tunnel frame according to claim 2, characterized in that: When the VxLan tunnel frame header is extracted, the extracted content specifically includes: {L2_DA[47:0], VNID[23:0], VLAN_tag[15:0]}.

5. A method for controlling a receiving end of a VxLan / NvGRE tunnel frame according to claim 2, characterized in that: When the TCP / IP frame header is extracted, the extracted content specifically includes: {source IPv4 address, destination IPv4 address, source port address, destination port address}.

6. A method for controlling a receiving end of a VxLan / NvGRE tunnel frame according to claim 2, characterized in that: When extracting the NvGRE tunnel frame header, the extracted length is 10B or 12B.

7. A method for controlling a receiving end of a VxLan / NvGRE tunnel frame according to claim 2, characterized in that: When extracting the VxLan tunnel frame header, the extracted length is 9B or 11B.

8. A receiving end control device for VxLan / NvGRE tunnel frames, characterized in that: include: A receiving frame parsing module, used for parsing the receiving frame type, wherein the receiving frame type includes a TCP / IP frame, a VxLan tunnel frame or an NvGRE tunnel frame; A mode control module, used for controlling a received frame type extraction enable signal, wherein the received frame type extraction enable signal includes a VNM signal and a VNE signal, wherein the value of the VNM signal includes 1 or 0, and the value of the VNE signal includes 1 or 0; A frame header extraction module, used to extract an enable signal and the received frame type according to the received frame type, perform TCP / IP frame header extraction, VxLan tunnel frame header extraction or NvGRE tunnel frame header extraction, and obtain TCP / IP frame header extraction content, VxLan tunnel frame header extraction content or NvGRE tunnel frame header extraction content; A hash calculation module is used to perform hash calculation on the TCP / IP frame header extraction content, the VxLan tunnel frame header extraction content or the NvGRE tunnel frame header extraction content to obtain a hash calculation result; The DMA channel selection module is used to complete the mapping of the processor core according to the hash calculation result and the load condition of the system multi-core processor.

9. A device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements a receiving end control method for VxLan / NvGRE tunnel frames as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the processor, it implements a receiving end control method for VxLan / NvGRE tunnel frames as described in any one of claims 1 to 7.

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