A video histogram equalization processing circuit and chip

Abstract

The present invention discloses a video histogram equalization processing circuit and chip. The core processing circuit in the video histogram equalization processing circuit includes a frame synchronization unit, a pixel calculation unit, a pixel component counting unit, an accumulation unit, a ratio calculation unit and a mapping unit. The frame synchronization unit outputs a frame synchronization signal according to a synchronization signal and a clock signal, the pixel calculation unit calculates the total number of pixels in the current frame according to a data enable signal and a frame synchronization signal, the pixel component counting unit counts the current pixel value, the accumulation unit accumulates according to the data output by the pixel component counting unit, the ratio calculation unit calculates the ratio of the data output by the accumulation unit to the data output by the pixel calculation unit, and the mapping unit maps the input pixel value to a preset value according to the previous frame data output by the ratio calculation unit. The video histogram equalization processing circuit of the present invention can be integrated into a netlist and burned into a chip to realize the processing of dynamic video streams, and has the advantages of fast processing speed and high efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a video histogram equalization processing circuit and a chip. Background Art

[0002] Histogram equalization is a method in the field of image processing that uses image histogram to adjust contrast. Through this method, brightness can be better distributed on the histogram, thereby increasing the global contrast of the image.

[0003] The conventional histogram equalization method is to use software analysis for static images, analyze the original image and write out the processed static image. For dynamic video, the conventional histogram equalization method needs to convert the video into several frames of images and then process the images, which is a complicated process. Summary of the invention

[0004] The present invention provides a video histogram equalization processing circuit and chip to solve the problem that the processing method of using software analysis for static pictures in the prior art leads to a relatively complicated processing process.

[0005] According to one aspect of the present invention, a video histogram equalization processing circuit is provided, the video histogram equalization processing circuit comprises a core processing circuit, the core processing circuit comprises a frame synchronization unit, a pixel calculation unit, a pixel component counting unit, an accumulation unit, a ratio calculation unit and a mapping unit;

[0006] The frame synchronization unit receives a synchronization signal and a clock signal, and the frame synchronization unit is used to output a frame synchronization signal according to the synchronization signal and the clock signal;

[0007] The pixel calculation unit is connected to the frame synchronization unit, and the pixel calculation unit is used to calculate the total number of pixels in the current frame according to the input data enable signal and the frame synchronization signal;

[0008] The pixel component counting unit is connected to the frame synchronization unit, and the pixel component counting unit is used to count the current pixel value connected;

[0009] The accumulating unit is connected to the pixel component counting unit, and the accumulating unit is used to accumulate data according to the data output by the pixel component counting unit;

[0010] The ratio calculation unit is connected to the accumulation unit and the pixel calculation unit, and is used to calculate the ratio of the data output by the accumulation unit to the data output by the pixel calculation unit;

[0011] The mapping unit is connected to the ratio calculation unit, and is used for mapping the input pixel value to a preset value according to the last frame data output by the ratio calculation unit.

[0012] Optionally, the frame synchronization unit includes a first trigger, a NOT gate circuit and a first AND gate circuit, the input end of the first trigger is connected to the synchronization signal, the clock end of the first trigger is connected to the clock signal, the output end of the first trigger is connected to the input end of the NOT gate circuit, the first input end of the first AND gate circuit is connected to the output end of the NOT gate circuit, the second input end of the first AND gate circuit is connected to the input end of the first trigger, and the output end of the first AND gate circuit outputs the frame synchronization signal.

[0013] Optionally, the pixel calculation unit includes a first OR gate circuit, a first adder, a first data selector, a second trigger and a third trigger, the first input end of the first OR gate circuit is connected to the output end of the first AND gate circuit and the control end of the first data selector, the second input end of the first OR gate circuit is connected to the data enable signal, the clock end of the second trigger and the clock end of the third trigger are connected to the clock signal, the enable end of the second trigger and the enable end of the third trigger are connected to the output end of the first OR gate circuit, the input end of the second trigger is connected to the output end of the first data selector, the output end of the second trigger is connected to the input end of the third trigger and the first input end of the first adder, the output end of the third trigger is connected to the output end of the pixel calculation unit, the second input end of the first adder inputs logic 1, the first input end of the first data selector is connected to the output end of the first adder, and the second input end of the first data selector inputs logic 0.

[0014] Optionally, the pixel component counting unit includes a first judgment module, a second AND gate circuit, a second OR gate circuit, a second data selector, a second adder, a fourth trigger and a fifth trigger, wherein the first input end of the first judgment module is connected to the input end of the pixel component counting unit, the second input end of the first judgment module inputs a pixel value variable, the output end of the first judgment module is connected to the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected to the data enable signal, the output end of the second AND gate circuit is connected to the first input end of the second OR gate circuit, the second input end of the second OR gate circuit, the control end of the second data selector and the enable end of the fifth trigger are connected to the first input end of the second AND gate circuit. The enable end is connected to the output end of the frame synchronization unit, the first input end of the second data selector is connected to the output end of the second adder, the second input end of the second data selector inputs logic 0, the output end of the second data selector is connected to the input end of the fourth trigger, the output end of the second OR gate circuit is connected to the enable end of the fourth trigger, the output end of the fourth trigger is connected to the input end of the fifth trigger and the first input end of the second adder, the second input end of the second adder inputs logic 1, the clock end of the fourth trigger and the clock end of the fifth trigger are connected to the clock signal, and the output end of the fifth trigger is connected to the output end of the pixel component counting unit.

[0015] Optionally, the accumulation unit includes a second judgment module, a third data selector and a third adder, the first end of the second judgment module inputs the pixel value variable, the second end of the second judgment module inputs logic 0, the output end of the second judgment module is connected to the control end of the third data selector, the first input end of the third data selector is connected to the output end of the third adder, the second input end of the third data selector inputs logic 0, the output end of the third data selector is connected to the first input end of the third adder, the second input end of the third adder is connected to the pixel component counting unit, and the output end of the third adder is connected to the output end of the accumulation unit.

[0016] Optionally, the ratio calculation unit includes a left shift module, a subtractor, a fourth data selector, a fifth data selector, a sixth trigger, a seventh trigger, a third OR gate circuit, a fourth OR gate circuit, a third judgment module, a fourth judgment module and a fourth adder, the input end of the left shift module is connected to the output end of the third adder, the output end of the left shift module is connected to the first input end of the fourth data selector, the second input end of the fourth data selector is connected to the output end of the subtractor, the output end of the fourth data selector is connected to the input end of the sixth trigger, the output end of the sixth trigger is connected to the first input end of the subtractor, the second input end of the subtractor is connected to the output end of the pixel calculation unit, the first input end of the third OR gate circuit is connected to the control end of the fourth data selector and the input end of the pixel calculation unit, the second input end of the third OR gate circuit is connected to the output end of the third judgment module, the first input end of the third judgment module is connected to the output end of the sixth trigger, and the second input end of the third judgment module is connected to the pixel calculation unit. The output end of the unit, the output end of the third OR gate circuit is connected to the enable end of the sixth trigger, and the clock end of the sixth trigger is connected to the clock signal; the first input end of the fourth judgment module is connected to the output end of the sixth trigger, the second input end of the fourth judgment module is connected to the output end of the pixel calculation unit, the output end of the fourth judgment module is connected to the first input end of the fourth OR gate circuit, the second input end of the fourth OR gate circuit is connected to the input end of the pixel calculation unit and the control end of the fifth data selector, the output end of the fourth OR gate circuit is connected to the enable end of the seventh trigger, the output end of the seventh trigger is connected to the output end of the ratio calculation unit and the first input end of the fourth adder, the second input end of the fourth adder inputs logic 1, the output end of the fourth adder is connected to the first input end of the fifth data selector, the second input end of the fifth data selector inputs logic 0, the output end of the fifth data selector is connected to the input end of the seventh trigger, and the clock end of the seventh trigger is connected to the clock signal.

[0017] Optionally, the mapping unit includes a fifth judgment module, a sixth data selector, a seventh data selector, a first right shift module, an eighth trigger and a fifth adder, the first input end of the fifth judgment module inputs the pixel value variable, the second input end of the fifth judgment module inputs logic 0, the output end of the fifth judgment module is connected to the control end of the sixth data selector, the first input end of the sixth data selector is connected to the output end of the ratio calculation unit, the second input end of the sixth data selector inputs logic 0, the output end of the sixth data selector is connected to the input end of the eighth trigger, the enable end of the eighth trigger is connected to the pixel component counting unit, the clock end of the eighth trigger is connected to the clock signal, the output end of the eighth trigger is connected to the input end of the first right shift module and the first input end of the fifth adder, the output end of the first right shift module is connected to the second input end of the fifth adder, the output end of the fifth adder is connected to the first input end of the seventh data selector and the control end of the seventh data selector, the second input end of the seventh data selector inputs 255, and the output end of the seventh data selector is connected to the output end of the mapping unit.

[0018] Optionally, the core processing circuit also includes a contrast judgment unit, an eighth data selector and a ninth trigger, the contrast judgment unit is connected to the pixel component counting unit and the pixel calculation unit, the contrast judgment unit is used to judge the image contrast according to the data output by the pixel component counting unit and the data output by the pixel calculation unit; the control end of the eighth data selector is connected to the output end of the contrast judgment unit, the first input end of the eighth data selector is connected to the output end of the ratio calculation unit, the second input end of the eighth data selector is connected to the output end of the ninth trigger, the input end of the ninth trigger is connected to the input end of the pixel component counting unit, the clock end of the ninth trigger is connected to the clock signal, and the eighth data selector is used to select a conduction path according to the signal output by the contrast judgment unit.

[0019] Optionally, the video histogram equalization processing circuit also includes a first color space conversion unit, a second color space conversion unit, a ninth data selector, a tenth data selector, a tenth trigger and an eleventh trigger, the control end of the ninth data selector is connected to a mode selection signal, the first input end of the ninth data selector is connected to the input end of the first color space conversion unit, the second input end of the ninth data selector is connected to the output end of the first color space conversion unit, the output end of the ninth data selector is connected to the input end of the core processing circuit, and the ninth data selector is used to select a conduction path according to the mode selection signal; the input end of the first color space conversion unit is connected to a video stream signal, the first color space conversion unit is used to convert an RGB color space into a YUV color space, and the first color space conversion unit is used to convert an RGB color space into a YUV color space. The output end of the color space conversion unit is connected to the input end of the tenth trigger and the input end of the eleventh trigger, the output end of the tenth trigger, the output end of the eleventh trigger and the output end of the core processing circuit are connected to the input end of the second color space conversion unit, the second color space conversion unit is used to convert the YUV color space into the RGB color space, the clock end of the tenth trigger and the clock end of the eleventh trigger are connected to the clock signal; the first input end of the tenth data selector is connected to the output end of the core processing circuit, the second input end of the tenth data selector is connected to the output end of the second color space conversion unit, the control end of the tenth data selector is connected to the mode selection signal, and the tenth data selector is used to select a conduction path according to the mode selection signal.

[0020] According to another aspect of the present invention, a chip is provided, comprising the video histogram equalization processing circuit.

[0021] The technical solution of the embodiment of the present invention provides a video histogram equalization processing circuit, wherein the core processing circuit includes a frame synchronization unit, a pixel calculation unit, a pixel component counting unit, an accumulation unit, a ratio calculation unit and a mapping unit; the frame synchronization unit outputs a frame synchronization signal according to a synchronization signal and a clock signal, the pixel calculation unit calculates the total number of pixels in the current frame according to a data enable signal and the frame synchronization signal, the pixel component counting unit counts the current pixel value, the accumulation unit accumulates according to the data output by the pixel component counting unit, the ratio calculation unit calculates the ratio of the data output by the accumulation unit to the data output by the pixel calculation unit, and the mapping unit maps the input pixel value to a preset value according to the previous frame data output by the ratio calculation unit, so as to realize real-time output of the frame after histogram equalization processing, that is, to process the dynamic video stream, and at the same time, the video histogram equalization processing circuit can be integrated into a netlist and burned into the chip, and has the advantages of fast processing speed and high efficiency, and solves the problem that the processing method of using software analysis for static pictures in the prior art leads to a more complicated processing process.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a structural diagram of a video histogram equalization processing circuit provided by an embodiment of the present invention;

[0025] Figure 2 is a circuit diagram of a video histogram equalization processing circuit provided by an embodiment of the present invention;

[0026] Figure 3 is a circuit diagram of another video histogram equalization processing circuit provided by an embodiment of the present invention;

[0027] Figure 4 It is a schematic diagram of the structure of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or submodules is not necessarily limited to those steps or submodules that are clearly listed, but may include other steps or submodules that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] The embodiment of the present invention provides a video histogram equalization processing circuit. Figure 1 is a structural diagram of a video histogram equalization processing circuit provided by an embodiment of the present invention, such as Figure 1 As shown, the video histogram equalization processing circuit 10 includes a core processing circuit 100, and the core processing circuit 100 includes a frame synchronization unit 110, a pixel calculation unit 120, a pixel component counting unit 130, an accumulation unit 140, a ratio calculation unit 150 and a mapping unit 160; the frame synchronization unit 110 is connected to the synchronization signal i_vsync and the clock signal i_vclk, and the frame synchronization unit is used to output a frame synchronization signal pos_vsync according to the synchronization signal i_vsync and the clock signal i_vsync; the pixel calculation unit 120 is connected to the frame synchronization unit 110, and the pixel calculation unit 120 is used to calculate the total number of pixels in the current frame according to the input data enable signal i_de and the frame synchronization signal pos_vsync. The pixel component counting unit 130 is connected to the frame synchronization unit 110, and the pixel component counting unit 130 is used to count the current pixel value i_pixel that is connected. The accumulation unit 140 is connected to the pixel component counting unit 130, and the accumulation unit 140 is used to accumulate according to the data output by the pixel component counting unit 130; the ratio calculation unit 150 is connected to the accumulation unit 140 and the pixel calculation unit 120, and the ratio calculation unit 150 is used to calculate the ratio of the data output by the accumulation unit 140 to the data output by the pixel calculation unit 120; the mapping unit 160 is connected to the ratio calculation unit 150, and the mapping unit 160 is used to map the input pixel value to a preset value according to the previous frame data output by the ratio calculation unit 150.

[0031] In this embodiment, the video histogram equalization processing circuit 10 is a circuit for performing histogram equalization processing on dynamic video to enhance the contrast of the video. The core processing circuit 100 is the core circuit of the video histogram equalization processing circuit, which can process the chrominance and brightness of the dynamic video. The frame synchronization unit 110 is a unit for extracting frame synchronization information, which can improve the accuracy and efficiency of data transmission. The pixel calculation unit 120 is a unit for calculating the total number of pixels in the current frame, the pixel component counting unit 130 is a unit for counting the number of pixel components in the current frame, and the accumulation unit 140 is a unit for accumulating the data output by the pixel component counting unit 130. For example, the number of pixel values ​​​​of 0 is m, and the number of pixel values ​​​​of 1 is n. When the input pixel value is 1, the data output by the accumulation unit 140 is m+n. The ratio calculation unit 150 is a unit for calculating the ratio of the data output by the accumulation unit 140 to the total number of pixels in the current frame, and the mapping unit 160 is a unit for mapping the input pixel to a preset pixel.

[0032] In this embodiment, after the video stream signal is input to the core processing circuit 100, the frame synchronization unit 110 outputs the frame synchronization signal pos_vsync according to the synchronization signal i_vsync and the clock signal i_vsync, wherein the synchronization signal i_vsync is a signal that provides the same time reference to the frame synchronization unit, the synchronization signal can be a switch signal or a continuous pulse signal, the clock signal i_vsync is used for timing in the synchronization circuit, and has a fixed clock frequency, and the frame synchronization signal pos_vsync plays the role of frame synchronization in the logic circuit. The pixel calculation unit 120 calculates the total number of pixels in this frame according to the input data enable signal i_de and the frame synchronization signal pos_vsync, wherein the data enable signal i_de refers to a valid data transmission signal. The pixel component counting unit 130 counts the current pixel value i_pixel connected, the accumulation unit 140 accumulates the data output by the pixel component counting unit 130, the ratio calculation unit 150 calculates the ratio of the data output by the accumulation unit 140 to the data output by the pixel calculation unit 120, and the mapping unit 160 maps the input pixel value to a preset value according to the previous frame data output by the ratio calculation unit 150. For example, the input pixel value range is 100-200, and the preset value range of the mapping output is 0-255, so that the histogram distribution is more uniform, thereby improving the contrast of the video.

[0033] The technical solution of this embodiment provides a video histogram equalization processing circuit, and its core processing circuit includes a frame synchronization unit, a pixel calculation unit, a pixel component counting unit, an accumulation unit, a ratio calculation unit and a mapping unit; the frame synchronization unit outputs a frame synchronization signal according to a synchronization signal and a clock signal, the pixel calculation unit calculates the total number of pixels in the current frame according to a data enable signal and a frame synchronization signal, the pixel component counting unit counts the current pixel value, the accumulation unit accumulates according to the data output by the pixel component counting unit, the ratio calculation unit calculates the ratio of the data output by the accumulation unit to the data output by the pixel calculation unit, and the mapping unit maps the input pixel value to a preset value according to the previous frame data output by the ratio calculation unit, so as to realize real-time output of the frame after histogram equalization processing, that is, to process the dynamic video stream, and at the same time, the video histogram equalization processing circuit can be integrated into a netlist and burned into the chip, which has the advantages of fast processing speed and high efficiency, and solves the problem that the processing method of using software analysis for static pictures in the prior art leads to a more complicated processing process.

[0034] Figure 2 is a circuit diagram of a video histogram equalization processing circuit provided by an embodiment of the present invention, such as Figure 2 As shown, the frame synchronization unit 110 includes a first trigger Q1, a NOT gate circuit F and a first AND gate circuit Y1, the input terminal D of the first trigger Q1 is connected to the synchronization signal i_vsync, the clock terminal of the first trigger Q1 is connected to the clock signal i_vclk, the output terminal Q of the first trigger Q1 is connected to the input terminal of the NOT gate circuit F, the first input terminal of the first AND gate circuit Y1 is connected to the output terminal of the NOT gate circuit F, the second input terminal of the first AND gate circuit Y1 is connected to the input terminal D of the first trigger Q1, and the output terminal of the first AND gate circuit Y1 outputs the frame synchronization signal pos_vsync.

[0035] In this embodiment, the first trigger Q1 is a D trigger. In one cycle of the clock signal i_vclk, the first trigger Q1 collects and outputs the rising edge signal of the synchronization signal i_vsync. The NOT gate circuit F inverts the signal output by the first trigger Q1. The first AND gate circuit Y1 performs a logic AND operation on the signal output by the NOT gate circuit F and the synchronization signal i_vsync, and outputs a frame synchronization signal pos_vsync. The frame synchronization signal pos_vsync plays a role of frame synchronization in the logic circuit.

[0036] Continue to refer Figure 2The pixel calculation unit 120 includes a first OR gate circuit H1, a first adder J1, a first data selector X1, a second trigger Q2 and a third trigger Q3. The first input end of the first OR gate circuit H1 is connected to the output end of the first AND gate circuit Y1 and the control end of the first data selector X1. The second input end of the first OR gate circuit H1 is connected to the data enable signal i_de. The clock end of the second trigger Q2 and the clock end of the third trigger Q3 are connected to the clock signal i_vclk. The enable end EN of the second trigger Q2 and the enable end EN of the third trigger Q3 are connected to the output end of the first OR gate circuit H1. The input end D of the second trigger Q2 is connected to the output end of the first data selector X1. The output end Q of the second trigger Q2 is connected to the input end D of the third trigger Q3 and the first input end of the first adder J1. The output end Q of the third trigger Q3 is connected to the output end of the pixel calculation unit 120. The second input end of the first adder J1 inputs logic 1. The first input end of the first data selector X1 is connected to the output end of the first adder J1. The second input end of the first data selector X1 inputs logic 0.

[0037] In this embodiment, the data output by the pixel calculation unit 120 is represented by lock_ftotal, the second trigger Q2 adopts a D trigger, and the third trigger Q3 adopts a D trigger, which has the function of information latching. The first OR gate circuit H1 performs an OR operation on the input data enable signal i_de and the frame synchronization signal pos_vsync, and the output signal is used as the enable signal of the second trigger Q2. The pixel calculation unit 120 performs an accumulation operation on the input pixel number through the first adder J1, calculates the total number of pixels of the current frame and outputs it to the second trigger Q2. The second trigger Q2 transmits the total number of pixels of the current frame to the third trigger Q3. The third trigger Q3 latches the total number of pixels of the previous frame according to the frame synchronization signal pos_vsync, which is used as the total number of pixels for histogram equalization processing of the current frame.

[0038] Continue to refer Figure 2The pixel component counting unit 130 includes a first judgment module P1, a second AND gate circuit Y2, a second OR gate circuit H2, a second data selector X2, a second adder J2, a fourth trigger Q4 and a fifth trigger Q5. The first input end of the first judgment module P1 is connected to the input end of the pixel component counting unit 130, the second input end of the first judgment module P1 inputs the pixel value variable i, the output end of the first judgment module P1 is connected to the first input end of the second AND gate circuit Y2, the second input end of the second AND gate circuit Y2 is connected to the data enable signal i_de, the output end of the second AND gate circuit Y2 is connected to the first input end of the second OR gate circuit H2, the second input end of the second OR gate circuit H2, the control end of the second data selector X2 and the fifth trigger Q4 The enable terminal EN is connected to the output terminal of the frame synchronization unit 110, the first input terminal of the second data selector X2 is connected to the output terminal of the second adder J2, the second input terminal of the second data selector X2 inputs logic 0, the output terminal of the second data selector X2 is connected to the input terminal D of the fourth trigger Q4, the output terminal of the second OR gate circuit H2 is connected to the enable terminal EN of the fourth trigger Q4, the output terminal Q of the fourth trigger Q4 is connected to the input terminal D of the fifth trigger Q5 and the first input terminal of the second adder J2, the second input terminal of the second adder J2 inputs logic 1, the clock terminal of the fourth trigger Q4 and the clock terminal of the fifth trigger Q5 are connected to the clock signal i_vclk, and the output terminal of the fifth trigger Q5 is connected to the output terminal of the pixel component counting unit 130.

[0039] Exemplarily, the data output by the pixel component counting unit 130 is represented by num_pixel[i]. After being latched by the fifth trigger Q5, the latched data is represented by lock_num_pixel[i], where the value range of i is 0 to 255. When the first judgment module P1 judges that the current pixel value i_pixel is equal to the pixel value variable i, the first judgment module P1 outputs the current pixel value i_pixel, the second AND gate circuit Y2 performs an AND operation on the current pixel value i_pixel and the data enable signal i_de, the second OR gate circuit H2 performs an OR operation on the signal output by the second AND gate circuit Y2 and the frame synchronization signal pos_vsync, and the output signal is used as the enable signal of the fourth trigger Q4, the second data selector X2 outputs the number of pixel components calculated by the second adder J2 to the fourth trigger Q4, the fourth trigger Q4 outputs the number of pixel components, and the fifth trigger Q5 latches the number of pixel components of the previous frame output by the fourth trigger Q4. For example, if the value of the input pixel component of the current frame is equal to 0, then num_pixel[0] is incremented by 1; if the value of the input pixel component is equal to 1, then num_pixel[1] is incremented by 1, and so on. If the value of the input pixel component is equal to i, then num_pixel[i] is incremented by 1. This is used to calculate how many pixels in the current frame have values ​​0 to 255. num_pixel[i] is latched, and the frame synchronization signal pos_vsync is used to latch the 256 num_pixel[i] numbers of the previous frame, which are used as the pixel fractions for histogram equalization processing of the current frame.

[0040] Continue to refer Figure 2 The accumulation unit 140 includes a second judgment module P2, a third data selector X3 and a third adder J3. The first end of the second judgment module P2 inputs the pixel value variable i, the second end of the second judgment module P2 inputs logic 0, the output end of the second judgment module P2 is connected to the control end of the third data selector X3, the first input end of the third data selector X3 is connected to the output end of the third adder J3, the second input end of the third data selector X3 inputs logic 0, the output end of the third data selector X3 is connected to the first input end of the third adder J3, the second input end of the third adder J3 is connected to the pixel component counting unit 130, and the output end of the third adder J3 is connected to the output end of the accumulation unit 140.

[0041] Exemplarily, when the second judgment module P2 judges that the pixel value variable i is 0, the third data selector X3 outputs 0. When the second judgment module P2 judges that the pixel value variable i is not 0, the third data selector X3 transmits the number of input pixel components to the third adder J3, and the third adder J3 performs an accumulation operation. The accumulation unit 140 is used to accumulate the data output by the num_pixel[i] counter to calculate the numerator of the scattered pixel value output by the subsequent histogram equalization. The data output by the accumulation unit 140 is represented by value_pixel[i]. Then,

[0042] value_pixel[0] = num_pixel[0]

[0043] value_pixel[1] = num_pixel[0] + num_pixel[1],

[0044] value_pixel[2] = num_pixel[0] + num_pixel[1] + num_pixel[2]

[0045] …

[0046] value_pixel

[255] = num_pixel[0] + num_pixel[1] +… + num_pixel

[255] = lock_ftotal.

[0047] Continue to refer Figure 2The ratio calculation unit 150 includes a left shift module L, a subtractor S, a fourth data selector X4, a fifth data selector X5, a sixth trigger Q6, a seventh trigger Q7, a third OR gate circuit H3, a fourth OR gate circuit H4, a third judgment module P3, a fourth judgment module P4 and a fourth adder J4, the input end of the left shift module L is connected to the output end of the third adder J3, the output end of the left shift module L is connected to the first input end of the fourth data selector X4, the second input end of the fourth data selector X4 is connected to the output end of the subtractor S, and the output end of the fourth data selector X4 is connected to the output end of the subtractor S. The first input end of the third OR gate circuit H3 is connected to the input end D of the sixth trigger Q6, the output end Q of the sixth trigger Q6 is connected to the first input end of the subtractor S, the second input end of the subtractor S is connected to the output end of the pixel calculation unit 120, the first input end of the third OR gate circuit H3 is connected to the control end of the fourth data selector X4 and the input end of the pixel calculation unit 120, the second input end of the third OR gate circuit H3 is connected to the output end of the third judgment module P3, the first input end of the third judgment module P3 is connected to the output end Q of the sixth trigger Q6, the second input end of the third judgment module P3 is connected to the output end of the pixel calculation unit 120, the output end of the third OR gate circuit H3 is connected to the enable end EN of the sixth trigger Q6, and the clock end of the sixth trigger Q6 is connected to the clock signal i_vclk; the first input end of the fourth judgment module P4 is connected to the output end of the sixth trigger Q6, the second input end of the fourth judgment module P4 is connected to the output end of the pixel calculation unit 120, the output end of the fourth judgment module P4 is connected to the first input end of the fourth OR gate circuit H4, and the second input end of the fourth OR gate circuit H4 is connected to the input end of the pixel calculation unit 120 and the control end of the fifth data selector X5. The output end of the fourth OR gate circuit H4 is connected to the enable end EN of the seventh flip-flop Q7, the output end Q of the seventh flip-flop Q7 is connected to the output end of the ratio calculation unit 150 and the first input end of the fourth adder J4, the second input end of the fourth adder J4 inputs logic 1, the output end of the fourth adder J4 is connected to the first input end of the fifth data selector X5, the second input end of the fifth data selector X5 inputs logic 0, the output end of the fifth data selector X5 is connected to the input end D of the seventh flip-flop Q7, and the clock end of the seventh flip-flop Q7 is connected to the clock signal i_vclk.

[0048] In this embodiment, the left shift module L can shift the input data left by 12 bits, that is, the data value_pixel[i] output by the accumulation unit 140 is shifted left by 12 bits, latched by the frame synchronization signal pos_vsync, and then divided by the data lock_ftotal output by the pixel calculation unit 120 to obtain the percentage percent_value_pixel[i] of the data value_pixel[i] output by the accumulation unit 140 in the data lock_ftotal output by the pixel calculation unit 120, where percent_value_pixel

[255] = 100%. The left shift of 12 bits ensures that the 12 binary digits after the decimal point of the quotient in the division are retained. In addition, the timing of the divider is difficult to handle in chip design, so subtraction is used instead of division. The initial value of the remainder minus_value_pixel[i] is value_pixel[i] latched by the frame synchronization signal pos_vsync shifted left by 12 bits. The third judgment module P3 outputs a valid signal when it judges that the total number of pixels lock_ftotal is greater than or equal to the remainder minus_value_pixel[i]. The third OR gate circuit H3 performs an OR operation based on the signal output by the third judgment module P3 and the frame synchronization signal pos_vsync, and the output signal is used as the enable signal of the sixth trigger Q6. The fourth data selector X4 transmits the signal output by the subtractor S to the sixth trigger Q6, and the sixth trigger Q6 outputs the remainder minus_value_pixel. In the subtractor S, each time the remainder minus_value_pixel[i] is subtracted from lock_ftotal, the percentage percent_value_pixel[i] in the fourth adder J4 is increased by 1 until the remainder minus_value_pixel[i] is less than lock_ftotal (i.e., it is judged by the third judgment module P3 and the fourth judgment module P4).

[0049] Continue to refer Figure 2The mapping unit 160 includes a fifth judgment module P5, a sixth data selector X6, a seventh data selector X7, a first right shift module R1, an eighth trigger Q8 and a fifth adder J5, the first input terminal of the fifth judgment module P5 inputs the pixel value variable i, the second input terminal of the fifth judgment module P5 inputs logic 0, the output terminal of the fifth judgment module P5 is connected to the control terminal of the sixth data selector X6, the first input terminal of the sixth data selector X6 is connected to the output terminal of the ratio calculation unit 150, the second input terminal of the sixth data selector X6 is input with logic 0, and the output terminal of the sixth data selector X6 is connected to the input terminal of the eighth trigger Q8. The enable terminal EN of the eighth trigger Q8 is connected to the pixel component counting unit 130, the clock terminal of the eighth trigger Q8 is connected to the clock signal i_vclk, the output terminal Q of the eighth trigger Q8 is connected to the input terminal of the first right shift module R1 and the first input terminal of the fifth adder J5, the output terminal of the first right shift module R1 is connected to the second input terminal of the fifth adder J5, the output terminal of the fifth adder J5 is connected to the first input terminal of the seventh data selector X7 and the control terminal of the seventh data selector X7, the second input terminal of the seventh data selector X7 is input with 255, and the output terminal of the seventh data selector X7 is connected to the output terminal of the mapping unit 160.

[0050] In this embodiment, the value of i_pixel in the current frame is equal to i in 0~255, and the eighth trigger Q8 calculates the pixel value cal_pixel according to the percent_value_pixel of the previous frame output by the ratio calculation unit 150. If the current frame i_pixel is equal to 0, the pixel value cal_pixel calculated by the eighth trigger Q8 is also equal to 0. If the current frame i_pixel is not equal to 0, the pixel value cal_pixel calculated by the eighth trigger Q8 is equal to percent_value_pixel. The eighth trigger Q8 calculates the pixel value cal_pixel[12:0] [11:0] is the 12 binary bits after the decimal point of percent_value_pixel[i] in the previous step. The 1-8 bits [11:4] after the decimal point can be used as pixel values ​​of 0-255, and the 9-12 bits [3:0] can still be regarded as 4 decimal places. Calculate cal_pixel by shifting right by 4 bits through the first right shift module R1, and round off the decimal place [3] to obtain the adjusted pixel value modify_pixel. If the value of the adjusted pixel value modify_pixel is greater than 255, the modified pixel value out_pixel output by the seventh data selector X7 takes the value 255. If the value of the adjusted pixel value modify_pixel is not greater than 255, the modified pixel value out_pixel output by the seventh data selector X7 is equal to the adjusted pixel value modify_pixel. Wherein, [8] is 1, indicating that modify_pixel is greater than 255, and [8] is 0, indicating that the adjusted pixel value modify_pixel is not greater than 255.

[0051] Continue to refer Figure 2 The core processing circuit 100 also includes a contrast judgment unit 210, an eighth data selector X8 and a ninth trigger Q9. The contrast judgment unit 210 is connected to the pixel component counting unit 130 and the pixel calculation unit 120. The contrast judgment unit 210 is used to judge the image contrast according to the data output by the pixel component counting unit 130 and the data output by the pixel calculation unit 120; the control end of the eighth data selector X8 is connected to the output end of the contrast judgment unit 210, the first input end of the eighth data selector X8 is connected to the output end of the ratio calculation unit 150, the second input end of the eighth data selector X8 is connected to the output end Q of the ninth trigger Q9, the input end D of the ninth trigger Q9 is connected to the input end of the pixel component counting unit 130, the clock end of the ninth trigger Q9 is connected to the clock signal i_vclk, and the eighth data selector X8 is used to select a conduction path according to the signal output by the contrast judgment unit 210.

[0052] In this embodiment, the contrast judgment unit 210 includes a sixth judgment module P6, a second right shift module R2, a third right shift module R3, a fourth right shift module R4 and a sixth adder J6, wherein the second right shift module R2 is a module for shifting the input data right by one bit, the third right shift module R3 is a module for shifting the input data right by two bits, and the fourth right shift module R4 is a module for shifting the input data right by 3 bits. The sixth judgment module P6 judges the data output by the sixth adder J6 and the lock_num_pixel output by the pixel component counting unit. When one of the 256 lock_num_pixel[i] is greater than or equal to 87.5% of lock_ftotal, that is, when more than 87.5% of the pixel values ​​are the same value, it is assumed that the image of the previous frame is close to pure color, and the current frame is temporarily not subjected to histogram equalization processing, and the eighth data selector X8 selects the second input terminal to be connected with the output terminal. At this time, the output o_pixel of the current frame is equal to the input i_pixel. When any of the 256 lock_num_pixel[i] is less than 87.5% of lock_ftotal, the eighth data selector X8 selects the first input terminal and the output terminal to be connected. At this time, the output o_pixel of the current frame is equal to the modified pixel value out_pixel.

[0053] Figure 3 is a circuit diagram of another video histogram equalization processing circuit provided by an embodiment of the present invention, such as Figure 3As shown, the video histogram equalization processing circuit 10 also includes a first color space conversion unit 310, a second color space conversion unit 320, a ninth data selector X9, a tenth data selector X10, a tenth trigger Q10 and an eleventh trigger Q11, the control end of the ninth data selector X9 is connected to the mode selection signal i_yuv_mode, the first input end of the ninth data selector X9 is connected to the input end of the first color space conversion unit 310, the second input end of the ninth data selector X9 is connected to the output end of the first color space conversion unit 310, the output end of the ninth data selector X9 is connected to the input end of the core processing circuit 100, and the ninth data selector X9 is used to select a conduction path according to the mode selection signal i_yuv_mode. The input end of the first color space conversion unit 310 is connected to the video stream signal, and the first color space conversion unit 310 is used to convert the RGB color space into the YUV color space. The output end of the first color space conversion unit 310 is connected to the input end D of the tenth trigger Q10 and the input end D of the eleventh trigger Q11. The output end of the tenth trigger Q10, the output end of the eleventh trigger Q11 and the output end of the core processing circuit 100 are connected to the input end of the second color space conversion unit 320. The second color space conversion unit 320 is used to convert the YUV color space into the RGB color space. The clock end of the tenth trigger Q10 and the clock end of the eleventh trigger Q11 are connected to the clock signal i_vclk; the first input end of the tenth data selector X10 is connected to the output end of the core processing circuit 100, the second input end of the tenth data selector X10 is connected to the output end of the second color space conversion unit 320, the control end of the tenth data selector X10 is connected to the mode selection signal i_yuv_mode, and the tenth data selector X10 is used to select a conduction path according to the mode selection signal i_yuv_mode.

[0054] In this embodiment, the video histogram equalization processing circuit includes a first core processing circuit, a second core processing circuit and a third core processing circuit, the three core processing circuits are all input with a reset signal i_rstn, a clock signal i_vclk, a synchronization signal i_vsync and a data enable signal i_de, and the first core processing circuit is connected to the ninth data selector Q9. The mode selection signal i_yuv_mode is a static signal, and the value does not change during the video processing process. When the mode selection signal i_yuv_mode is 0, the ninth data selector X9 selects to process the input video stream signals i_r, i_g and i_b respectively. When the mode selection signal i_yuv_mode is 1, the ninth data selector X9 first converts i_r, i_g and i_b into y, u and v components through the first color space conversion unit 310, where y is the brightness component, and u and v are the chrominance components. The ninth data selector X9 selects to transmit the brightness component y to the core processing circuit, and converts the yuv color space processed by the core processing circuit back to the rgb color space through the second color space conversion unit 320, where the input video stream signal also includes a reset signal i_rstn. After the core processing circuit processes the color component, there will be a clock delay of one cycle, so the u and v components are output by the tenth trigger Q10 and the eleventh trigger Q11 respectively. The components delayed by one clock cycle are d1_u and d1_v, which can be synchronized and aligned with the y component processed by the core processing circuit. The tenth data selector X10 selects a conduction path according to the mode selection signal i_yuv_mode. When the mode selection signal i_yuv_mode is 0, the tenth data selector X10 will conduct the first input terminal and the output terminal (that is, it selects to output the video stream signal after processing the input video stream signals i_r, i_g and i_b). When the mode selection signal i_yuv_mode is 1, the tenth data selector X10 will conduct the second input terminal and the output terminal (that is, it selects to output the video stream signal after processing the brightness component y), where the output video stream signal is represented by o_r, o_g and o_b.

[0055] The embodiment of the present invention further provides a chip 20, Figure 4 is a schematic diagram of the structure of a chip provided by an embodiment of the present invention, such as Figure 4 As shown, the chip 20 includes a video histogram equalization processing circuit 10. The video histogram equalization processing circuit 10 is integrated into a netlist and burned into the chip, and performs histogram equalization processing on the dynamic video stream in the form of hardware, thereby improving the processing speed and efficiency.

[0056] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0057] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A video histogram equalization processing circuit, characterized in that: The video histogram equalization processing circuit comprises a core processing circuit, and the core processing circuit comprises a frame synchronization unit, a pixel calculation unit, a pixel component counting unit, an accumulation unit, a ratio calculation unit and a mapping unit; The frame synchronization unit receives a synchronization signal and a clock signal, and the frame synchronization unit is used to output a frame synchronization signal according to the synchronization signal and the clock signal; The pixel calculation unit is connected to the frame synchronization unit, and the pixel calculation unit is used to calculate the total number of pixels in the current frame according to the input data enable signal and the frame synchronization signal; The pixel component counting unit is connected to the frame synchronization unit, and the pixel component counting unit is used to count the current pixel value connected; The accumulating unit is connected to the pixel component counting unit, and the accumulating unit is used to accumulate data according to the data output by the pixel component counting unit; The ratio calculation unit is connected to the accumulation unit and the pixel calculation unit, and is used to calculate the ratio of the data output by the accumulation unit to the data output by the pixel calculation unit; The mapping unit is connected to the ratio calculation unit, and is used to map the input pixel value to a preset value according to the previous frame data output by the ratio calculation unit; Wherein, the frame synchronization unit comprises a first trigger, a NOT gate circuit and a first AND gate circuit, the input end of the first trigger is connected to the synchronization signal, the clock end of the first trigger is connected to the clock signal, the output end of the first trigger is connected to the input end of the NOT gate circuit, the first input end of the first AND gate circuit is connected to the output end of the NOT gate circuit, the second input end of the first AND gate circuit is connected to the input end of the first trigger, and the output end of the first AND gate circuit outputs the frame synchronization signal; The pixel calculation unit includes a first OR gate circuit, a first adder, a first data selector, a second trigger and a third trigger. The first input end of the first OR gate circuit is connected to the output end of the first AND gate circuit and the control end of the first data selector. The second input end of the first OR gate circuit is connected to the data enable signal. The clock end of the second trigger and the clock end of the third trigger are connected to the clock signal. The enable end of the second trigger and the enable end of the third trigger are connected to the output end of the first OR gate circuit. The input end of the second trigger is connected to the output end of the first data selector. The output end of the second trigger is connected to the input end of the third trigger and the first input end of the first adder. The output end of the third trigger is connected to the output end of the pixel calculation unit. The second input end of the first adder inputs logic 1. The first input end of the first data selector is connected to the output end of the first adder. The second input end of the first data selector inputs logic 0.

2. The video histogram equalization processing circuit according to claim 1, characterized in that: The pixel component counting unit comprises a first judgment module, a second AND gate circuit, a second OR gate circuit, a second data selector, a second adder, a fourth trigger and a fifth trigger, wherein the first input end of the first judgment module is connected to the input end of the pixel component counting unit, the second input end of the first judgment module inputs a pixel value variable, the output end of the first judgment module is connected to the first input end of the second AND gate circuit, the second input end of the second AND gate circuit is connected to the data enable signal, the output end of the second AND gate circuit is connected to the first input end of the second OR gate circuit, the second input end of the second OR gate circuit, the control end of the second data selector and the enable end of the fifth trigger are connected The output end of the frame synchronization unit is connected to the first input end of the second data selector, the output end of the second data selector is connected to the output end of the second adder, the second input end of the second data selector inputs logic 0, the output end of the second data selector is connected to the input end of the fourth trigger, the output end of the second OR gate circuit is connected to the enable end of the fourth trigger, the output end of the fourth trigger is connected to the input end of the fifth trigger and the first input end of the second adder, the second input end of the second adder inputs logic 1, the clock end of the fourth trigger and the clock end of the fifth trigger are connected to the clock signal, and the output end of the fifth trigger is connected to the output end of the pixel component counting unit.

3. The video histogram equalization processing circuit according to claim 2, characterized in that: The accumulation unit includes a second judgment module, a third data selector and a third adder, the first end of the second judgment module inputs the pixel value variable, the second end of the second judgment module inputs logic 0, the output end of the second judgment module is connected to the control end of the third data selector, the first input end of the third data selector is connected to the output end of the third adder, the second input end of the third data selector inputs logic 0, the output end of the third data selector is connected to the first input end of the third adder, the second input end of the third adder is connected to the pixel component counting unit, and the output end of the third adder is connected to the output end of the accumulation unit.

4. The video histogram equalization processing circuit according to claim 3, characterized in that: The ratio calculation unit includes a left shift module, a subtractor, a fourth data selector, a fifth data selector, a sixth trigger, a seventh trigger, a third OR gate circuit, a fourth OR gate circuit, a third judgment module, a fourth judgment module and a fourth adder, wherein the input end of the left shift module is connected to the output end of the third adder, the output end of the left shift module is connected to the first input end of the fourth data selector, the second input end of the fourth data selector is connected to the output end of the subtractor, the output end of the fourth data selector is connected to the input end of the sixth trigger, the output end of the sixth trigger is connected to the first input end of the subtractor, the second input end of the subtractor is connected to the output end of the pixel calculation unit, the first input end of the third OR gate circuit is connected to the control end of the fourth data selector and the input end of the pixel calculation unit, the second input end of the third OR gate circuit is connected to the output end of the third judgment module, the first input end of the third judgment module is connected to the output end of the sixth trigger, the second input end of the third judgment module is connected to the output end of the pixel calculation unit, the output end of the third OR gate circuit is connected to the enable end of the sixth trigger, and the clock end of the sixth trigger is connected to the clock signal; The first input end of the fourth judgment module is connected to the output end of the sixth trigger, the second input end of the fourth judgment module is connected to the output end of the pixel calculation unit, the output end of the fourth judgment module is connected to the first input end of the fourth OR gate circuit, the second input end of the fourth OR gate circuit is connected to the input end of the pixel calculation unit and the control end of the fifth data selector, the output end of the fourth OR gate circuit is connected to the enable end of the seventh trigger, the output end of the seventh trigger is connected to the output end of the ratio calculation unit and the first input end of the fourth adder, the second input end of the fourth adder inputs logic 1, the output end of the fourth adder is connected to the first input end of the fifth data selector, the second input end of the fifth data selector inputs logic 0, the output end of the fifth data selector is connected to the input end of the seventh trigger, and the clock end of the seventh trigger is connected to the clock signal.

5. The video histogram equalization processing circuit according to claim 4, characterized in that: The mapping unit includes a fifth judgment module, a sixth data selector, a seventh data selector, a first right shift module, an eighth trigger and a fifth adder. The first input end of the fifth judgment module inputs the pixel value variable, the second input end of the fifth judgment module inputs logic 0, the output end of the fifth judgment module is connected to the control end of the sixth data selector, the first input end of the sixth data selector is connected to the output end of the ratio calculation unit, the second input end of the sixth data selector inputs logic 0, the output end of the sixth data selector is connected to the input end of the eighth trigger, the enable end of the eighth trigger is connected to the pixel component counting unit, the clock end of the eighth trigger is connected to the clock signal, the output end of the eighth trigger is connected to the input end of the first right shift module and the first input end of the fifth adder, the output end of the first right shift module is connected to the second input end of the fifth adder, the output end of the fifth adder is connected to the first input end of the seventh data selector and the control end of the seventh data selector, the second input end of the seventh data selector inputs 255, and the output end of the seventh data selector is connected to the output end of the mapping unit.

6. The video histogram equalization processing circuit according to claim 2, characterized in that: The core processing circuit also includes a contrast judgment unit, an eighth data selector and a ninth trigger. The contrast judgment unit is connected to the pixel component counting unit and the pixel calculation unit, and is used to judge the image contrast according to the data output by the pixel component counting unit and the data output by the pixel calculation unit; the control end of the eighth data selector is connected to the output end of the contrast judgment unit, the first input end of the eighth data selector is connected to the output end of the ratio calculation unit, the second input end of the eighth data selector is connected to the output end of the ninth trigger, the input end of the ninth trigger is connected to the input end of the pixel component counting unit, the clock end of the ninth trigger is connected to the clock signal, and the eighth data selector is used to select a conduction path according to the signal output by the contrast judgment unit.

7. The video histogram equalization processing circuit according to claim 1, characterized in that: It also includes a first color space conversion unit, a second color space conversion unit, a ninth data selector, a tenth data selector, a tenth trigger and an eleventh trigger, wherein the control end of the ninth data selector is connected to a mode selection signal, the first input end of the ninth data selector is connected to the input end of the first color space conversion unit, the second input end of the ninth data selector is connected to the output end of the first color space conversion unit, the output end of the ninth data selector is connected to the input end of the core processing circuit, and the ninth data selector is used to select a conduction path according to the mode selection signal; The input end of the first color space conversion unit is connected to the video stream signal, the first color space conversion unit is used to convert the RGB color space into the YUV color space, the output end of the first color space conversion unit is connected to the input end of the tenth trigger and the input end of the eleventh trigger, the output end of the tenth trigger, the output end of the eleventh trigger and the output end of the core processing circuit are connected to the input end of the second color space conversion unit, the second color space conversion unit is used to convert the YUV color space into the RGB color space, and the clock end of the tenth trigger and the clock end of the eleventh trigger are connected to the clock signal; The first input end of the tenth data selector is connected to the output end of the core processing circuit, the second input end of the tenth data selector is connected to the output end of the second color space conversion unit, the control end of the tenth data selector is connected to the mode selection signal, and the tenth data selector is used to select a conduction path according to the mode selection signal.

8. A chip, characterized in that: The invention comprises the video histogram equalization processing circuit as described in any one of claims 1 to 7.

Images