Image sensor

Abstract

An image sensor may include: a pixel array including a plurality of first pixels configured to receive light and output a plurality of first pixel signals; a row driver coupled to the plurality of first pixels and configured to apply a preset voltage to the plurality of first pixels; and an image signal processor configured to: obtain first state codes according to a plurality of second pixel signals received from the plurality of first pixels based on a preset voltage applied to the plurality of first pixels, each first state code relating to one of the plurality of first pixels; and processing the plurality of first pixel signals based on the first state code.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0096393 filed on July 24, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an image sensor. Background Art

[0004] An image sensor is a device for capturing a two-dimensional or three-dimensional image of an object. The image sensor generates an image of the object using a photoelectric conversion element that reacts according to the intensity of light reflected from the object.

[0005] As the demand for image sensors with improved performance increases in various fields, complementary metal oxide semiconductor (CMOS) image sensors using unit pixels made of CMOS have been widely used. On the other hand, as the pixel density in the image sensor increases and the size of the image sensor decreases, the size of the pixel also decreases and the manufacturing process becomes more and more complicated. Therefore, dark current may occur, which is an undesirable current integrated as an electric charge in the photoelectric element of the pixel in the image sensor. The increase in dark current may cause problems such as degradation of the performance of the element and a decrease in the charge storage capacity of the element. Summary of the invention

[0006] The present disclosure provides an apparatus and method for correcting a dark shadow existing in image data and a dark current level difference between a light receiving area and a shadow area.

[0007] According to one aspect of an example embodiment, an image sensor may include: a pixel array including a plurality of first pixels, the plurality of first pixels being configured to receive light and output a plurality of first pixel signals; a row driver coupled to the plurality of first pixels and configured to apply a preset voltage to the plurality of first pixels; and an image signal processor configured to: obtain a first state code based on a plurality of second pixel signals received from the plurality of first pixels based on the preset voltage applied to the plurality of first pixels, each first state code being associated with one of the plurality of first pixels; and process the plurality of first pixel signals based on the first state code.

[0008] The plurality of first pixels may include at least one first temperature monitoring pixel. The image sensor may be configured to: measure first dark current codes of the plurality of first pixels based on the plurality of second pixel signals; and generate a first compensation table based on a first temperature state code associated with the at least one first temperature monitoring pixel and a corresponding first dark current code corresponding to the first temperature state code, the first compensation table including first information about at least one of the first temperature state code, the corresponding first dark current code, the first state code, and the first dark current code.

[0009] The image sensor may be configured to generate first image data based on a plurality of first pixel signals when operating in an image sensing mode. The image signal processor may be configured to determine a first dark current code corresponding to a first state code based on a first compensation table; and compensate the first image data based on the first dark current code.

[0010] The image signal processor may be configured to compensate the first image data during the vertical blank period based on the pixel array not outputting the plurality of first pixel signals.

[0011] The pixel array may further include a plurality of second pixels located in the light shielding area. The plurality of second pixels may include at least one second temperature monitoring pixel. The image signal processor may be configured to perform: obtaining a second state code based on a third pixel signal received from the plurality of second pixels based on a preset voltage applied to the plurality of second pixels, each second state code being associated with one of the plurality of second pixels; measuring a second dark current code associated with the plurality of second pixels based on the third pixel signal; and generating a second compensation table based on at least one second state code of the second state code of at least one second temperature monitoring pixel and a second dark current code of at least one second temperature monitoring pixel, the second compensation table containing second information about the second state code and the second dark current code corresponding to the second state code.

[0012] The image sensor may be configured to generate first image data based on a plurality of first pixel signals when operating in an image sensing mode. The image signal processor may be configured to update the first dark current code in the first compensation table with the second dark current code based on a difference between the second dark current code and the first dark current code in the first compensation table.

[0013] The image signal processor may be configured to update the second compensation table during the vertical blank period based on the pixel array not outputting the plurality of first pixel signals.

[0014] The image sensor may further include: a temperature monitoring circuit located below the pixel array and configured to measure a temperature value of at least one first temperature monitoring pixel and send the temperature value to the image signal processor.

[0015] The plurality of first pixels may be divided into a plurality of pixel groups, and each pixel group in the plurality of pixel groups includes at least one first pixel. The image signal processor may be configured to: measure a third dark current code associated with a representative pixel based on a plurality of second pixel signals received from a representative pixel in each pixel group in the plurality of pixel groups, and generate a third compensation table based on at least one of a temperature value of the representative pixel, a third state code of the representative pixel, and a third dark current code, the third compensation table containing third information about the third state code and a third dark current code corresponding to the third state code. The image sensor may be configured to: generate second image data based on a plurality of first pixel signals when operating in an image sensing mode; obtain a third state code associated with at least one first pixel in each pixel group in the plurality of pixel groups; and determine a third dark current code associated with each first pixel in the plurality of first pixels based on the third compensation table, and compensate the second image data based on the third dark current code.

[0016] The plurality of first pixels include: a reset transistor coupled between a first node and a voltage line and configured to supply a reset voltage and be controlled by a reset control signal; a gain control transistor coupled between the first node and a second node and configured to be controlled by a gain control signal; and a drive transistor configured to transmit a pixel voltage corresponding to a voltage of the second node as a plurality of second pixel signals to an image signal processor. The row driver includes: a reset voltage generation module configured to generate a reset voltage; and a gain control signal generation module configured to generate a gain control signal.

[0017] Based on the reset voltage being a first voltage, the reset control signal having a first reset control level, and the gain control signal having a first gain control level, the second node may have a first voltage value. Based on the reset voltage being a second voltage lower than the first voltage, the reset control signal having a first reset control level, and the gain control signal having a second gain control level lower than the first gain control level, the second node may have a second voltage value. Based on the reset voltage being a third voltage higher than the first voltage, the reset control signal having a first reset control level, and the gain control signal having a second gain control level, the second node may have a third voltage value. The image signal processor may be configured to obtain a first state code based on a first pixel voltage corresponding to the first voltage value and a third pixel voltage corresponding to the third voltage value.

[0018] Based on the reset voltage being a third voltage higher than the first voltage, the reset control signal having a second reset control level lower than the first reset control level, and the gain control signal having a second gain control level, the second node may have a fourth voltage value. The image signal processor may be configured to obtain a first state code based on a first pixel voltage corresponding to the first voltage value and a fourth pixel voltage corresponding to the fourth voltage value.

[0019] Based on the reset voltage being a first voltage, the reset control signal having a first reset control level, and the gain control signal having a first gain control level, the second node may have a first voltage value. Based on the reset voltage being a second voltage higher than the first voltage, the reset control signal having a first reset control level, and the gain control signal having a first gain control level, the second node may have a second voltage value. Based on the reset voltage being a second voltage, the reset control signal having a second reset control level lower than the first reset control level, and the gain control signal having a first gain control level, the second node may have a third voltage value. Based on the reset voltage being a first voltage, the reset control signal having a first reset control level, and the gain control signal having a first gain control level, the second node may have a fourth voltage value. The image signal processor may be configured to obtain a first state code based on a third pixel voltage corresponding to the third voltage value and a fourth pixel voltage corresponding to the fourth voltage value.

[0020] Based on the reset voltage being the first voltage, the reset control signal having the second reset control level, and the gain control signal having the first gain control level, the second node may have a fifth voltage value. The image signal processor may be configured to obtain a first state code based on a third pixel voltage corresponding to the third voltage value and a fifth pixel voltage corresponding to the fifth voltage value.

[0021] The plurality of first pixels may include: a reset transistor coupled between a pixel power supply voltage line and a first node and configured to be controlled by a reset control signal; a gain control transistor coupled between the first node and a second node and configured to be controlled by a gain control signal; and a drive transistor configured to transmit a pixel voltage corresponding to a voltage of the second node as a plurality of second pixel signals to an image signal processor. The row driver may include a gain control signal generation module configured to generate a gain control signal.

[0022] Based on the reset control signal having a first reset control level and the gain control signal having a first gain control level, the second node may have a first voltage value. Based on the reset control signal having a second reset control level lower than the first reset control level and the gain control signal having a second gain control level lower than the first gain control level, the second node may have a second voltage value. Based on the reset control signal having a first reset control level and the gain control signal having a third gain control level lower than the first gain control level and higher than the second gain control level, the second node may have a third voltage value. The image signal processor may be configured to obtain a first state code based on a first pixel voltage corresponding to the first voltage value and a third pixel voltage corresponding to the third voltage value.

[0023] The plurality of first pixels may include: a reset transistor coupled between a pixel power supply voltage line and a first node and configured to be controlled by a reset control signal; a transfer transistor coupled between the first node and an optoelectronic element and configured to be controlled by a transfer signal; and a drive transistor configured to transfer a pixel voltage corresponding to a voltage of the first node as a plurality of second pixel signals to an image signal processor. The row driver may include: a reset signal generation module configured to generate a reset control signal; and a transfer signal generation module configured to generate a transfer signal.

[0024] Based on the reset control signal having a first reset control level and the transmission signal having a first transmission control level, the first node may have a first voltage value. Based on the reset control signal having a second reset control level lower than the first reset control level and the transmission signal having a second transmission control level lower than the first transmission control level, the first node may have a second voltage value. Based on the reset control signal having a third reset control level lower than the first reset control level and higher than the second reset control level and the transmission signal having the second transmission control level, the first node may have a third voltage value. The image signal processor may be configured to obtain a first state code based on a first pixel voltage corresponding to the first voltage value and a third pixel voltage corresponding to the third voltage value.

[0025] According to one aspect of an example embodiment, an operating method of an image sensor may include: performing a first state code measurement operation by receiving light and applying a preset voltage to a plurality of first pixels to output a plurality of first pixel signals; performing a first state code acquisition operation by obtaining a first state code according to a plurality of second pixel signals received from the plurality of first pixels based on the preset voltage applied to the plurality of first pixels, wherein each first state code is associated with one of the plurality of first pixels; performing a dark current code measurement operation on the plurality of first pixels based on the plurality of second pixel signals; and generating a first compensation table based on the first state code and the first dark current code, the first compensation table containing first information about the first state code and the first dark current code corresponding to the first state code.

[0026] The operating method of the image sensor may further include: performing a first state code obtaining operation when generating first image data based on a plurality of first pixel signals, determining a first dark current code based on a first compensation table, and compensating the first image data based on the first dark current code.

[0027] An image sensor according to some embodiments may compensate for dark shadows and dark current level differences. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a diagram showing a conceptual layout of an image sensor according to an embodiment.

[0030] Figure 2 is a block diagram of an image sensor according to an embodiment.

[0031] Figure 3 is a flow chart showing how an image sensor generates image data according to an embodiment.

[0032] Figure 4 is a flowchart showing how an image sensor according to an embodiment generates a compensation table.

[0033] Figure 5 is a flow chart showing how an image sensor compensates an image signal according to an embodiment.

[0034] Figure 6 is a diagram showing rows depending on the operation of the image sensor according to the embodiment.

[0035] Figure 7 is a diagram showing a pixel array according to an embodiment.

[0036] Figure 8is a circuit diagram showing an image sensor according to an embodiment.

[0037] Fig. 9 It shows that according to Figure 8 A timing diagram of the operation of the image sensor.

[0038] Fig.10 It shows that according to Fig. 9 A diagram of the image sensor circuit during operation of the image sensor.

[0039] Fig.11 It shows that according to Figure 8 A timing diagram of the operation of the image sensor.

[0040] Fig.12 It shows that according to Fig.11 A diagram of the image sensor circuit during operation of the image sensor.

[0041] Fig.13 is a circuit diagram showing an image sensor according to an embodiment.

[0042] Fig.14 It shows that according to Fig.13 A timing diagram of the operation of the image sensor.

[0043] Fig.15 It shows that according to Fig.13 A diagram of the image sensor circuit during operation of the image sensor.

[0044] Fig.16 is a circuit diagram showing an image sensor according to an embodiment.

[0045] Fig.17 It shows that according to Fig.16 A timing diagram of the operation of the image sensor.

[0046] Fig.18 It shows that according to Fig.17 A diagram of the image sensor circuit during operation of the image sensor.

[0047] Fig.19 It shows that according to Fig.16 A timing diagram of the operation of the image sensor.

[0048] Fig. 20 It shows that according to Fig.19 A diagram of the image sensor circuit during operation of the image sensor.

[0049] Fig.21 is a diagram illustrating a state code and a dark current code depending on a temperature value in an image sensor according to an embodiment.

[0050] Fig. 22 is a diagram illustrating dark current codes of a light receiving area and a shadow area depending on a state code in an image sensor according to an embodiment.

[0051] Fig.23 is a diagram illustrating a dark current code of a shaded area depending on a state code in an image sensor according to an embodiment.

[0052] Fig.24 is a diagram illustrating dark current codes of a light receiving area and a shadow area depending on a state code in an image sensor according to an embodiment.

[0053] Fig.25 is a block diagram showing an electronic device according to an embodiment.

[0054] Fig.26 is a block diagram showing an electronic device according to an embodiment.

[0055] Fig. 27 is a block diagram showing a vehicle according to an embodiment. DETAILED DESCRIPTION

[0056] The embodiments described herein are non-limiting example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. As used herein, the expression "at least one of..." modifies the entire list of elements after a list of elements without modifying the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0057] In the following detailed description, only examples of the present disclosure are shown and described by way of illustration only. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0058] Therefore, the drawings and descriptions should be considered illustrative in nature and not restrictive. Throughout the specification, similar reference numerals represent similar elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, operations may be divided, and some operations may not be performed.

[0059] In addition, unless an explicit expression such as "a", "an" or "single" is used, an expression written in the singular form may be understood as a singular form or a plural form. Terms including ordinal numbers such as first and second are used to describe various constituent elements, but the constituent elements are not limited by these terms. These terms are used only to distinguish one constituent element from other constituent elements.

[0060] Figure 1 is a diagram showing a conceptual layout of an image sensor according to an embodiment.

[0061] The image sensor 100 is a device for converting light received from the outside into an electrical signal. Figure 1 As shown, the image sensor 100 may include a first chip 110 and a second chip 130 that are stacked. Figure 1 , it is shown that the first chip 110 and the second chip 130 are stacked in a vertical direction; however, the first chip 110 and the second chip 130 may be formed as one chip.

[0062] In the first chip 110, a plurality of pixels may be arranged in a two-dimensional array structure. The first chip 110 may include a light receiving area 111 and a shadow area 113. The light receiving area 111 may be an area for acquiring an image to be displayed on a screen. The shadow area 113 may be an area for shielding light. Figure 1 , a shadow region 113 is shown to be formed along the edge of the light receiving region 111; however, the shadow region is not limited thereto. In addition, the shadow region 113 can be deformed into various shapes and sizes. In the light receiving region 111 and the shadow region 113, a plurality of unit pixel regions can be formed into a two-dimensional array (e.g., in the form of a matrix). A plurality of unit pixel regions can generate pixel signals.

[0063] In the light receiving area 111, a plurality of pixels (e.g., active pixels) may be arranged. The pixels in the light receiving area 111 may receive light to generate an active signal. In the shadow area 113, a plurality of pixels (e.g., optical black pixels) may be arranged. Since the pixels in the shadow area 113 perform photoelectric conversion in a shadow environment, the pixels in the shadow area 113 may generate an optical black signal corresponding to charges generated by other reasons other than light (such as dark current).

[0064] The second chip 130 may be electrically coupled to the first chip 110. The second chip 130 may include a circuit for processing a pixel signal generated by the first chip 110, and the like.

[0065] In addition, the second chip 130 may include a temperature monitoring circuit (TMC) 131. The TMC 131 may measure the temperature of the image sensor 100. In the drawings, it is shown that the TMC 131 is disposed in a region of the second chip 130 corresponding to the light receiving region 111 of the first chip 110; however, the TMC 131 may be disposed in a region of the second chip 130 corresponding to the shadow region 113 of the first chip 110. Alternatively or additionally, the TMC 131 may be arranged in a plurality of regions.

[0066] The temperature monitoring pixel (TMP) 115 may be disposed to correspond to the position of the TMC 131 in the second chip 130 .

[0067] The TMP 115 may be located in the first chip 110. When the first chip 110 and the second chip 130 are stacked in a vertical direction, the TMC 131 may measure the temperature of the TMP 115.

[0068] As the temperature increases, the magnitude of the dark current can increase. In order to compensate for the effects of the dark current, the pixel data value of the optical black area that is completely shielded from light (i.e., the black pixel value) can be used. When performing this dark current compensation, the difference between the dark current level of the active signal and the dark current level of the optical black signal can cause an offset of the pedestal level. The offset of the pedestal level can cause dark shadows. The difference between the dark current level of the optical black signal and the dark current level of the active signal can be due to an offset caused by a change in the manufacturing process or a difference in the structure. The offset of the pedestal level can vary based on the temperature.

[0069] When the pedestal level has an offset other than "0", a color distortion phenomenon such as reddish, bluish, greenish, etc. may occur in a low illumination area of ​​the image sensor 100. In addition, when the image sensor 100 synthesizes low illumination and high illumination images by a high dynamic range (HDR) method in a state where the pedestal level is not "0", problems such as color reproduction error, a decrease in the signal-to-noise ratio (SNR), etc. may be caused.

[0070] There is a grid offset surface (GOS) method for correcting dark shadows, which stores shadows in each area under multiple predetermined temperature conditions, and based on the stored information, predicts the shadow pattern of each pixel position according to the temperature, and uses the predicted shadow pattern. In the GOS method, based on the temperature value acquired by TMC 131, the shadow pattern required for the corresponding temperature can be predicted and used for correction. However, the shadow pattern according to the temperature collected for correction may not meet every operating scenario of the image sensor. When the step of storing the shadow pattern of each area according to multiple temperature conditions is a step of an EDS (electronic die sorting) process or a packaging process for determining whether there is a defect in the image sensor, the measured shadow pattern may be different from the shadow pattern of the image sensor in the step of actually using the image sensor. In addition, the method of storing the shadow pattern of each area according to multiple temperature conditions and using it for correction has the problem that the temperature distribution and dark current distribution of the image sensor according to various operating environments cannot be considered. In addition, there is a problem that this method cannot reflect the changes in the characteristics of the elements in the image sensor over time.

[0071] There is an optical black recovery (OBR) method for correcting the difference between the dark current level of the active signal and the dark current level of the optical black signal, which corrects the offset difference based on the correlation between the offset of the pedestal level of the active signal and the offset of the pedestal level of the optical black signal corresponding to each temperature condition. OBR can be performed in the automatic dark level compensation (ADLC) step. However, similar to the correction function of GOS, the OBR method also has problems, that is, the data collection step required for OBR correction and the collected data may not represent every operating environment of the sensor.

[0072] In addition, since the image sensor is usually exposed to light, the image signal of the light receiving area may include both the signal caused by the dark current and the signal caused by the light. Therefore, it is impossible to measure the dark current level and the internal temperature of the pixel in the light receiving area in real time.

[0073] However, the image sensor 100 according to the embodiment may correct the dark shadow and the difference between the dark current level of the active signal and the dark current level of the optical black signal in real time according to the dark current offset level difference between the light receiving area 111 and the shadow area 113 .

[0074] Figure 2 is a block diagram of an image sensor according to an embodiment.

[0075] like Figure 2 As shown, the image sensor 200 according to the embodiment may include a controller 210, a timing controller 220, a row driver 240, a pixel array 230, a readout circuit 260, a ramp signal generator 270, a data buffer 280, an image signal processor 290, and a TMC 295. In some embodiments, the image signal processor 290 may be located outside the image sensor 200. In some embodiments, the pixel array 230 may be on the first chip ( Figure 1 , and the controller 210, the timing controller 220, the row driver 240, the readout circuit 260, the ramp signal generator 270, the data buffer 280, the image signal processor 290, and the TMC 295 can be implemented in the second chip ( Figure 1 The method is implemented in the figure marked “130” in FIG.

[0076] The image sensor 200 may generate an image signal IMS by converting light received from the outside into an electrical signal, and the image signal IMS may be provided to the image signal processor 290 .

[0077] The image sensor 200 may be installed in an electronic device having an image or light sensing function. For example, the image sensor 200 may be installed in electronic devices such as cameras, smart phones, wearable devices, IoT (Internet of Things) devices, home appliances, tablet PCs (personal computers), personal digital assistants (PDAs), portable multimedia players (PMPs) navigation devices, drones, advanced driver assistance systems (ADAS), etc. In addition, the image sensor 200 may be installed in electronic devices incorporated as components in vehicles, furniture, manufacturing equipment, doors, various measuring devices, etc.

[0078] The controller 210 may control the respective constituent elements 220, 230, 240, 250, 260, 270, 280, 290, and 295 included in the image sensor 200. The controller 210 may control the operation timing of the respective constituent elements 220, 230, 240, 250, 260, 270, 280, 290, and 295 using control signals.

[0079] In some embodiments, the controller 210 may control the respective constituent elements 220, 230, 240, 250, 260, 270, 280, 290, and 295 included in the image sensor 200 so that the image sensor 200 operates in an image sensing mode or a state measurement mode. The image sensing mode may be a mode in which the image sensor 200 converts light received from the outside into an electrical signal. The state measurement mode may be a mode for measuring the state of an element in the pixel PX to correct a pedestal error in the image sensor 200.

[0080] When the image sensor 200 operates in the image sensing mode, the controller 210 may control the ramp signal generator 270 so as to adjust the reference signal RAMP generated by the ramp signal generator 270. When the image sensor 200 operates in the image sensing mode, the controller 210 may control the timing controller 220 to adjust the floating diffusion (FD) capacitance of the pixel circuit in the pixel array 230 through the row driver 240.

[0081] When the image sensor 200 operates in the state measurement mode, the controller 210 may control the row driver 240 and the image signal processor 290 to measure the state code of the pixel PX in the pixel array 230. The state code may represent the characteristics of the element in the pixel PX. For example, the state code of the pixel PX may be the threshold voltage of the transistor in the pixel PX. In some embodiments, the controller 210 may measure the dark current code of the pixel PX in the pixel array 230 by controlling the row driver 240. In some embodiments, the controller 210 may control the timing when the data buffer 280 outputs the data stored in the data buffer 280 to the image signal processor 290.

[0082] In some embodiments, the controller 210 may receive a mode signal indicating an imaging mode from the application processor, and generally control the image sensor 200 based on the received mode signal. For example, the application processor may determine the imaging mode of the image sensor 200 according to various scenarios (such as illumination in an imaging environment, a resolution setting of a user, a state of sensing or learning, etc.), and provide the determined result as a mode signal to the controller 210. The controller 210 may perform control so that a plurality of pixels in the pixel array 230 output pixel signals according to the imaging mode, and the pixel array 230 may output pixel signals of a plurality of individual pixels or pixel signals of some of the plurality of pixels, and the readout circuit 260 may sample and process the pixel signals received from the pixel array 230.

[0083] The timing controller 220 may generate a signal as a reference for the operation timing of the components of the image sensor 200. The timing controller 220 may control the timing of the row driver 240, the readout circuit 260, and the ramp signal generator 270. The timing controller 220 may provide a control signal to control the timing of the row driver 240, the readout circuit 260, and the ramp signal generator 270.

[0084] The pixel array 230 may include a plurality of pixels PX, and a plurality of row lines RL and a plurality of column lines CL respectively coupled to the plurality of pixels PX. In some embodiments, each pixel PX may include at least one photoelectric element (also referred to as an optical sensing device). The photoelectric element may detect incident light and convert the incident light into an electrical signal, i.e., a plurality of analog pixel signals, based on the amount of light. The level of the analog pixel signal output from the photoelectric element may increase as the amount of charge output from the photoelectric element increases. In other words, the level of the analog pixel signal output from the photoelectric element may increase as the amount of light entering the pixel array 230 increases. At the same time, as Figure 1 As shown, the pixel array 230 may include pixels arranged in the light receiving area 111 and pixels arranged in the shadow area 113. In addition, some of the plurality of pixels PX may be temperature monitoring pixels. Figure 2 In the embodiment, the first TMP 235 may be disposed in the light receiving area 231, and the second TMP 237 may be disposed in the shadow area 233. Figure 2 , it is shown that the pixel array 230 includes one TMP in the light receiving area 231 and one TMP in the shadow area 233; however, the present disclosure is not limited thereto, and the pixel array 230 may include a plurality of TMPs in the light receiving area 231 and a plurality of TMPs in the shadow area 233. In some embodiments, a TMC 295 may be provided below the first TMP 235 and the second TMP 237.

[0085] A plurality of row lines RL (RL1 to RLn-1) may extend in a first direction and be coupled to the pixels PX arranged along the first direction. For example, the plurality of row lines RL may transmit a control signal output from the row driver 240 to an element (e.g., a transistor) included in the pixel PX. Signal lines other than the row lines RL may be arranged along the first direction. A plurality of column lines CL (CL1 to CLm-1) may extend in a second direction intersecting the first direction and be coupled to the pixels PX arranged along the second direction. The column lines CL may transmit a pixel signal output from the pixel PX to the readout circuit 260.

[0086] In some embodiments, one pixel PX may include a plurality of sub-pixel groups. The sub-pixel groups may be arranged in the form of an M×N matrix (where M and N are integers greater than 2). The form of the M×N matrix may be in the form of M columns arranged along the arrangement direction of the column lines CL and N rows arranged along the arrangement direction of the row lines RL.

[0087] The row driver 240 may generate a control signal for driving the pixel array 230 in response to a control signal from the timing controller 220, and provide the control signal to a plurality of pixels PX of the pixel array 230 through a plurality of row lines RL. In some embodiments, the row driver 240 may control the pixels PX in the row line unit so that the pixels detect incident light. Each row line unit may include at least one row line RL.

[0088] In some embodiments, the row driver 240 may include a state code measurement module 250. The state code measurement module 250 may be coupled to a plurality of pixels PX via at least one row line RL. The state code measurement module 250 may perform a preset state code measurement operation based on the type of the coupled pixel PX. When the image sensor 200 operates in a state measurement mode, the state code measurement module 250 may perform a state code measurement operation. The state code measurement module 250 may apply a preset voltage to the pixel array 230 for the state code measurement operation. The pixel array 230 may generate a state signal as a pixel signal according to the voltage applied from the state code measurement module 250. The column line CL may transmit the state signal output from the pixel PX to the readout circuit 260.

[0089] The state code measurement module 250 may perform a dark current measurement operation. The state code measurement module 250 may apply a preset voltage to the pixel array 230 to measure dark currents from a plurality of optical black pixels located in the shadow area 233 and a plurality of active pixels located in the light receiving area 231. As described above, dark current may be a current caused by charges generated by reasons other than light. Therefore, when the image sensor 200 is operated in an image sensing mode or a state measurement mode, during a dark current measurement operation on the active pixels in the light receiving area 231, the state code measurement module 250 may not be able to distinguish between dark current and current generated by charges generated by light. On the contrary, when the image sensor 200 is operated in an image sensing mode or a state measurement mode, the optical black pixels in the shadow area 233 do not generate currents based on charges generated by light. Therefore, even when the image sensor 200 is operated in an image sensing mode, the state code measurement module 250 may perform a dark current measurement operation on the optical black pixels.

[0090] In some embodiments, the state code measurement module 250 may apply a preset voltage to the pixel array 230 to measure dark currents from a plurality of optical black pixels and a plurality of active pixels during the EDS process. In some embodiments, the state code measurement module 250 may measure dark currents from a plurality of optical black pixels when the image sensor 200 operates in a state measurement mode. The pixel array 230 may generate a dark current signal as a pixel signal according to the voltage applied from the state code measurement module 250. The column line CL may transmit the dark current signal output from the pixel PX to the readout circuit 260.

[0091] The readout circuit 260 can convert the pixel signal (or electrical signal) received from the pixel PX coupled to the selected row line RL among the plurality of pixels PX into a pixel value indicating the amount of light in response to the control signal from the timing controller 220. The readout circuit 260 can convert the pixel signal outputted by the corresponding column line CL into a pixel value. For example, the readout circuit 260 can convert the pixel signal into a pixel value by comparing the pixel signal with a ramp signal. The pixel value can be an image data item, each of which has a plurality of bits. Specifically, the readout circuit 260 may include a selector, a plurality of comparators, a plurality of counter circuits, and the like.

[0092] In some embodiments, the readout circuit 260 may convert a state signal (or electrical signal) received from a pixel PX coupled to a selected row line RL among a plurality of pixels PX into a state code in response to a control signal from the timing controller 220. Each state code may be state data having a plurality of bits. In some embodiments, the readout circuit 260 may convert a dark current signal (or electrical signal) into a dark current code. Each dark current code may be dark current data having a plurality of bits.

[0093] The ramp signal generator 270 can generate a reference signal RAMP and send it to the readout circuit 260. The ramp signal generator 270 may include a current source, a resistor, and a capacitor. The ramp signal generator 270 can adjust a ramp voltage, which is a voltage to be applied to the ramp resistor, by adjusting the current amplitude of the variable current source or the resistance value of the variable resistor. In this way, the ramp signal generator can generate a plurality of ramp signals that decrease or increase at a slope determined by the current amplitude of the variable current source or the resistance value of the variable resistor.

[0094] The data buffer 280 may store pixel values ​​of a plurality of pixels PX received from the readout circuit 260, the plurality of pixels PX being coupled to the selected column line CL. In addition, the data buffer 280 may store state codes of a plurality of pixels PX received from the readout circuit 260, the plurality of pixels PX being coupled to the selected column line CL. The data buffer 280 may output the stored pixel values, state codes, or dark current codes to the image signal processor 290 in response to an enable signal from the controller 210. For example, when the row driver 240 performs a state code measurement operation, the data buffer 280 may receive a state code from the readout circuit 260, and send the received state code value to the image signal processor 290. In some embodiments, the data buffer 280 may store a plurality of state codes received from the readout circuit 260 when the row driver 240 performs a state code measurement operation, and send the stored plurality of state codes to the image signal processor 290 after the row driver 240 completes the state code measurement operation.

[0095] The TMC 295 may measure the temperature of the image sensor 200, thereby generating a temperature value TEMP. Specifically, the TMC 295 may measure the temperature at a location where the TMC 295 is disposed. The TMC 295 may transmit the generated temperature value TEMP corresponding to the temperature to the image signal processor 290.

[0096] The image signal processor 290 may perform image signal processing on the image signal received from the data buffer 280. For example, the image signal processor 290 may receive a plurality of image signals IMS from the data buffer 280 and synthesize the received image signals IMS to generate one image. Here, the image signal IMS may be based on a pixel signal output from a pixel PX located in the light receiving area 231 in the image sensor 200.

[0097] The image signal processor 290 may compensate the plurality of received image signals IMS for dark current, thereby generating image data IDS.

[0098] In some embodiments, the image signal processor 290 may perform a status code calculation operation on a plurality of status codes received from the data buffer 280. The image signal processor 290 may obtain status codes associated with respective pixels PX in the pixel array 230. The status codes indicate the threshold voltages of transistors in the respective pixels PX in the pixel array 230. Figures 12 to 25 How the image signal processor 290 performs the state code calculation operation is described. When the state code measurement module 250 performs the state code measurement operation, the image signal processor 290 may receive the temperature value TEMP of the TMPs 235 and 237 located on the TMC 295 from the TMC 295 .

[0099] In some embodiments, the image signal processor 290 may receive a dark current code. When the status code measurement module 250 performs a dark current code measurement operation, the image signal processor 290 may receive a temperature value TEMP of the TMPs 235 and 237 located on the TMC 295 from the TMC 295 .

[0100] The image signal processor 290 may generate a compensation table based on the temperature value TEMP, the state code, and the dark current code. In some embodiments, the image signal processor 290 may generate a compensation table during the EDS process. For example, during the EDS process, when the image sensor 200 has a preset temperature value TEMP, the image signal processor 290 may calculate the state code according to the position of each pixel PX, and may receive a dark current code. The compensation table may include state codes and dark current codes associated with a plurality of individual pixels PX in the pixel array 230 according to the temperature value TEMP. Therefore, the image signal processor 290 may calculate the correlation between the state code and the dark current code of the pixel PX. For example, the compensation table may include information about the dark current code corresponding to the state code of the pixel PX. On the other hand, the correlation between the state code and the dark current code of the pixel in the light receiving area 231 may be different from the correlation between the state code and the dark current code of the pixel in the shadow area 233.

[0101] The image signal processor 290 may include a register for storing the compensation table. The register may be provided outside the image signal processor 290.

[0102] The image signal processor 290 may compensate for the dark current present in the image signal IMS based on a pre-stored compensation table. Specifically, the image signal processor 290 may determine a dark current code corresponding to a state code calculated for a pixel in the light receiving area 231. Therefore, the image signal processor 290 may apply the dark current code of each pixel PX to the received image signal. For example, the image signal processor 290 may generate image data IDS including a value obtained by subtracting the dark current code of each pixel PX from the image signal IMS.

[0103] In some embodiments, the image signal processor 290 may update a pre-stored compensation table. For example, when the state code of any pixel at any temperature value TEMP in the compensation table is different from the dark current code at the above temperature value TEMP, the image signal processor 290 may update the compensation table. For example, the image signal processor 290 may update the compensation table in the vertical blank period of the image sensor 200. In some embodiments, since the characteristics of the elements in the pixel PX may change over time, the image signal processor 290 may update the compensation table at predetermined intervals for accurate correction of the image signal. For example, the image signal processor 290 may update the compensation table in each vertical blank period of the image sensor 200, or may update the compensation table once every three vertical blank periods. However, the present disclosure is not limited thereto, and the image signal processor 290 may update the compensation table at any suitable interval. In some embodiments, when the image sensor 200 operates in the state measurement mode, the image signal processor 290 may re-measure the state code and dark current code associated with the pixel PX at the corresponding temperature value TEMP, and update the compensation table based on them.

[0104] In some embodiments, the image signal processor 290 may update the compensation table of the light receiving area 231 based on the compensation table of the pixels in the shadow area 233. For example, when the image sensor 200 operates in the image sensing mode, the image signal processor 290 may update the compensation table of the pixels in the light receiving area 231 based on the compensation table of the pixels in the shadow area 233.

[0105] In some embodiments, if there is a difference between the dark current code of the pixels in the light receiving area 231 and the dark current code of the pixels in the shadow area 233, the image signal processor 290 may update the compensation table of the pixels in the light receiving area 231. For example, the image signal processor 290 may update the compensation table of the pixels in the light receiving area 231 so that the average value of the dark current codes of the multiple pixels in the light receiving area 231 is equal to the average value of the dark current codes of the multiple pixels in the shadow area 233. Specifically, the image signal processor 290 may modify the dark current codes of the multiple pixels in the light receiving area 231 by multiplying the multiple pixels in the light receiving area 231 by a certain percentage so that the average value of the dark current codes of the multiple pixels in the light receiving area 231 is equal to the average value of the dark current codes of the multiple pixels in the shadow area 233.

[0106] Figure 3 is a flow chart showing how an image sensor generates image data according to an embodiment.

[0107] First, the image sensor 200 generates a compensation table ( S100 ).

[0108] In some embodiments, the step of generating the compensation table by the image sensor 200 can be performed in the EDS process step. Figure 4 Step S100 will be described.

[0109] Figure 4 is a flowchart showing how an image sensor according to an embodiment generates a compensation table.

[0110] Refer to Figure 4 , the status code measurement module 250 performs a status code measurement operation (S1001).

[0111] The state code measurement module 250 may sequentially apply a preset voltage according to the type of pixel PX. For example, the state code measurement module 250 may apply a preset voltage to the TMP 235. In this case, the TMP 235 may be an active pixel located in the light receiving area 231. In some embodiments, the state code measurement module 250 may apply a first voltage group to each transistor in the TMP 235, and apply a second voltage group to each transistor in the TMP 235 after a predetermined time, and apply a third voltage group to each transistor in the TMP 235 after a predetermined time. When the state code measurement module 250 performs the state code measurement operation, the TMC 295 may measure the temperature of the TMP 235 to generate a temperature value TEMP. For example, the TMP 235 may have a first temperature value.

[0112] Meanwhile, the status code measurement module 250 may perform a status code measurement operation on the TMP 237 located in the shadow area 233 .

[0113] The image signal processor 290 performs a status code calculation operation (S1003).

[0114] The image signal processor 290 may calculate the state code based on the code value acquired in step S100. For example, when the state code measurement module 250 applies the first voltage group to the TMP 235, the image signal processor 290 may calculate the state code related to the TMP 235 based on the first state signal output from the pixel array 230, when the state code measurement module 250 applies the second voltage group to the TMP 235, the image signal processor 290 may calculate the state code related to the TMP 235 based on the second state signal output from the pixel array 230, and when the state code measurement module 250 applies the third voltage group to the TMP 235, the image signal processor 290 may calculate the state code related to the TMP 235 based on the third state signal output from the pixel array 230. For example, the TMP 235 may have a first state code when having a first temperature value.

[0115] Subsequently, the state code measuring module 250 performs a dark current measuring operation ( S1005 ).

[0116] The state code measurement module 250 may apply a preset voltage to the pixel PX. For example, the state code measurement module 250 may apply a voltage of 0V to the TMP 235. When the state code measurement module 250 performs a dark current measurement operation, the TMC 295 may measure the temperature of the TMP 235 to generate a temperature value TEMP.

[0117] The image signal processor 290 receives the dark current code ( S1007 ).

[0118] In the EDS process step, since the image sensor 200 has not received light, the state code measurement module 250 may perform a dark current measurement operation, whereby the pixel array 230 may output a signal based on the dark current. Therefore, the image signal processor 290 may acquire a dark current code associated with the first temperature of the TMP 235. For example, the TMP 235 may have a first dark current code when having a first temperature value.

[0119] The image signal processor 290 generates a compensation table (S1009).

[0120] The compensation table may include a state code and a dark current code associated with each of the plurality of pixels PX in the pixel array 230 according to the temperature value TEMP. For example, when the TMP 235 has a first temperature value, the compensation table may include a first state code and a first dark current code.

[0121] When the image sensor 200 has various temperature conditions, the image signal processor 290 may generate a compensation table associated with one TMP 235 by performing steps S1001 to S1009 multiple times. For example, when the TMP 235 has a second temperature value different from the first temperature value, the compensation table may include a second state code and a second dark current code.

[0122] The image signal processor 290 may generate a compensation table associated with each pixel PX of the plurality of pixels PX, and calculate a formula associated with a relationship between the temperature value TEMP of the TMC 295 and the state code and a relationship between the temperature value TEMP of the TMC 295 and the dark current code. Based on this, the image signal processor 290 may derive a relationship between the state code and the dark current code.

[0123] On the other hand, the image signal processor 290 may generate a compensation table according to various temperature conditions with reference to each of the plurality of pixels PX. Although the plurality of pixels PX are located in one image sensor 200, the pixels PX may also have different temperatures depending on the structure of the image sensor 200. Therefore, the image signal processor 290 may apply different compensation values ​​according to the position of the pixel PX in the pixel array 230.

[0124] The image signal processor 290 may store the generated compensation table.

[0125] Refer again Figure 3 , the image sensor 200 generates an image signal (S200).

[0126] The image sensor 200 may convert light received from the outside into an electrical signal, thereby generating an image signal IMS. In this case, the image signal IMS may be based on a pixel signal output from a pixel in the light receiving area 231 in the image sensor 200 .

[0127] The image sensor 200 compensates the image signal (S300). Figure 5 Let's describe step S300.

[0128] Figure 5 is a flow chart showing how an image sensor compensates an image signal according to an embodiment.

[0129] Refer to Figure 5 , the status code measurement module 250 performs a status code measurement operation (S3001).

[0130] In some embodiments, the state code measurement module 250 may perform a state code measurement operation on an active pixel. For example, the state code measurement module 250 may perform a state code measurement operation on the TMP 235.

[0131] The image signal processor 290 performs a status code calculation operation (S3003).

[0132] For example, through calculation, the image signal processor 290 may determine that the TMP 235 has the first state code.

[0133] The image signal processor 290 compensates the image data based on the dark current code corresponding to the calculated state code based on the compensation table (S3005).

[0134] Specifically, the image signal processor 290 may read a dark current code corresponding to the state code calculated in step S100 from a compensation table stored in the image signal processor 290. In some embodiments, the image sensor 200 may compensate the image signal based on the compensation table generated in step S100. For example, when the TMP 235 has a first state code, the image signal processor 290 may read from the compensation table that the TMP 235 has a first dark current code. In addition, when the TMP 235 has a first state code, the image signal processor 290 may read from the compensation table that the TMP 235 has a first temperature value. The image signal processor 290 may generate compensated image data reflecting the first dark current code based on the image data output from the TMP 235 and included in the image signal. For example, the image signal processor 290 may generate compensated image data by subtracting the first dark current code from the image data or adding the first dark current code to the image data.

[0135] On the other hand, Figure 3 , it is shown that step S300 is performed after step S200; however, the present disclosure is not limited thereto, and step S300 may be performed first, and then step S200 may be performed. In the case where step S300 is performed first, the image signal processor 290 may acquire a compensation table in advance, and apply the compensation value to the sensed image data based on the acquired compensation table.

[0136] When the image sensor 200 performs the method of compensating the image signal IMS, also refer to Figure 6 .

[0137] Figure 6 is a diagram showing rows depending on the operation of the image sensor according to the embodiment.

[0138] Specifically, Figure 6 is a diagram showing row addresses read by the image sensor 200 over time. Specifically, Figure 6A plurality of scanning periods for driving a plurality of pixels PX in units of row lines are shown.

[0139] like Figure 2 As shown, the pixel array 230 may include a plurality of pixels PX. In some embodiments, the time required to drive a row line selected from a plurality of row lines RL and read an image signal from the pixel PX coupled to the selected row line may be defined as one horizontal period. The image sensor may operate in a rolling shutter manner to sequentially drive the plurality of row lines RL.

[0140] The first period P1 and the second period P2 may be periods during which the image sensor 200 performs image sensing on the pixel array 230 .

[0141] On the other hand, the frame period of the image sensor 200 may be defined as the time required to read the reset voltage and the pixel voltage from all pixels included in the pixel array 230. In some embodiments, one frame period may be equal to the product of the number of row lines RL and the horizontal period, or may be greater than the product of the number of row lines RL and the horizontal period. As the frame period of the image sensor is shortened, the image sensor can generate a greater number of image data items within the same period of time.

[0142] In one frame period, the image sensor 200 may generate one image data item. For example, the image sensor 200 may generate one image data item in the first period P1 and one image data item in the second period P2. The operation of the image sensor 200 in the second period P2 may be similar to the operation of the image sensor 200 in the first period P1.

[0143] On the other hand, between the period when the image sensor 200 generates one image data item and the period when the image sensor 200 generates the next image data item, there may be a third period P3. The third period P3 may be a vertical blank period. The vertical blank period may be a period when the image sensor 200 does not generate image data. The third period P3 may be a period when photocharges are accumulated in the photoelectric element of the pixel PX. In the third period P3, the image sensor 200 may perform operations required to generate image data.

[0144] In some embodiments, the image sensor 200 may perform operations required to compensate for the image data items generated in the first period P1 in the third period P3. For example, the image sensor 200 may perform a state code measurement operation and a state code calculation operation during the third period P3. The image sensor 200 may determine a dark current code based on the state code associated with each pixel PX determined in the third period P3, and compensate for the image data items generated in the first period P1 based on the dark current code.

[0145] In some embodiments, the image sensor 200 may perform operations required for generating image data in the second period P2 in the third period P3. For example, the image sensor 200 may perform a state code measurement operation and a state code calculation operation during the third period P3. The image sensor 200 may determine a dark current code based on the state code associated with each pixel PX determined in the third period P3, and compensate for the image data items generated in the second period P2 based on the dark current code.

[0146] In some embodiments, the image sensor 200 may perform compensation by applying the dark current code determined for each pixel PX in the third period P3 to a plurality of frame periods.

[0147] Figure 7 is a diagram showing a pixel array according to an embodiment.

[0148] As described above, the characteristics of the pixel PX can be determined through this process and can be obtained by the image sensor ( Figure 2 The temperature of the pixel PX is determined by the position of the pixel PX in FIG. 1 (reference numeral “200” in FIG. 1 ). Therefore, the state code and the dark current code of the respective pixels PX arranged close to each other may have similar values.

[0149] like Figure 7 As shown, the pixel array 730 may include a plurality of pixels. Figure 7 As shown, the pixel array 730 may include a plurality of pixel groups. Figure 2 ” in the figure mark “200”) can measure the state code and dark current code of a representative pixel in a pixel group. Thereafter, the image sensor 200 can generate a compensation table, which includes the state code and dark current code of the representative pixel. During image data compensation, the image sensor 200 can equally apply the state code and dark current code of the representative pixel in the pixel group including the corresponding pixel. In other words, the image sensor 200 can determine the dark current code corresponding to the state code of the corresponding pixel in the compensation table generated based on the state code and dark current code calculated according to the representative pixel, and use the determined dark current code to compensate the image data related to the corresponding pixel. Therefore, although the image sensor 200 does not measure the state code and dark current code of all pixels PX in the pixel array 730 in step S100, it can compensate the image data.

[0150] Figure 8 is a circuit diagram showing an image sensor according to an embodiment.

[0151] Specifically, Figure 8is a diagram showing one pixel PX1 in the pixel array 830 and a state code measurement module 850 coupled to the pixel PX1. The image sensor 800 according to the embodiment may further include a timing controller, a readout circuit, a data buffer, and the like.

[0152] Reference Figure 8 , the pixel PX1 may include photoelectric elements PD1 and PD2, a first capacitor C1, and a plurality of transistors. Figure 8 , it is shown that one pixel PX1 includes two photoelectric elements PD1 and PD2; however, the present embodiment is not limited thereto, and one pixel PX1 may include a plurality of photoelectric elements.

[0153] The cathode of the photoelectric element PD1 may be coupled to the third node N13 through the transmission transistor STX, and the anode of the photoelectric element PD1 may be grounded. In addition, the cathode of the photoelectric element PD2 may be coupled to the fifth node N15 through the transmission transistor LTX, and the anode of the photoelectric element PD2 may be grounded.

[0154] The plurality of transistors may include transfer transistors STX and LTX, a first transistor TSX, a first switch transistor SWX, a second switch transistor DSX, a reset transistor RX1, a gain control transistor DRX1, a drive transistor SF, and a select transistor SX1. The transistors STX, LTX, TSX, SWX, DSX, RX1, DRX1, and SX1 in the pixel PX1 may be responsive to the row driver ( Figure 2 The module 850 operates by controlling the control signals (eg, transmission control signals STG, LTG, TS, SW, and DRW, a selection signal SEL, a reset control signal RG1, and a first gain control signal DRG1) provided by the state code measurement module 850.

[0155] The transfer transistor STX may be coupled between the photoelectric element PD1 and the third node N13 and controlled by a transfer control signal STG. When the transfer transistor STX is turned on, charges generated by the photoelectric element PD1 may be transferred to the third node N13.

[0156] The transfer transistor LTX may be coupled between the photoelectric element PD2 and the fifth node N15 and controlled by the transfer control signal LTG. When the transfer transistor LTX is turned on, the charge generated by the photoelectric element PD2 may be transferred to the fifth node N15. The transfer transistor STX may be turned off in response to the deactivated transfer control signal STG, and the transfer transistor LTX may be turned off in response to the deactivated transfer control signal LTG. When the transfer transistors STX and LTX are turned off (i.e., during the exposure time), the photoelectric elements PD1 and PD2 may accumulate charge depending on the incident light.

[0157] In some embodiments, the pixel PX1 may include a plurality of floating diffusions. Each of the plurality of floating diffusions may have a predetermined capacitance and may store charges generated by the photoelectric elements PD1 and PD2. Each of the plurality of floating diffusions may have a parasitic capacitance. In some embodiments, the pixel PX1 may further include capacitors as passive elements, which are respectively coupled to the plurality of floating diffusions.

[0158] The charge generated by the photoelectric element PD1 may be accumulated in the first capacitor C1 by the first transistor TSX. The first transistor TSX may be controlled by a transmission control signal TS. The voltage of the third node N13 may be determined according to the charge accumulated in the first capacitor C1 and the charge generated by the photoelectric element PD1. As the magnitude of the capacitance of the first capacitor C1 increases, the conversion gain may decrease, and the conversion gain is the rate at which the charge is converted into a voltage. For example, as the capacitance of the first capacitor C1 increases, the conversion gain decreases, and as the capacitance decreases, the conversion gain increases.

[0159] One side of the first capacitor C1 is coupled to one end of the first transistor TSX, and the other side of the first capacitor C1 is coupled to the first node N11. The first node N11 may be coupled to a power supply voltage line supplying a power supply voltage VDD.

[0160] The first switch transistor SWX may be coupled between the third node N13 and the fourth node N14 and controlled by the transmission control signal SW When the first switch transistor SWX is turned on, the voltage of the third node N13 may be transmitted to the fourth node N14.

[0161] The reset transistor RX1 may be coupled between the fourth node N14 and a voltage line supplying a reset voltage VRD, and may be controlled by a reset control signal RG1. When the reset transistor RX1 is turned on by the reset control signal RG1, the reset voltage VRD may be applied to the fourth node N14, so that the fourth node N14 is reset. When the reset transistor RX1 is turned on, if the switch transistor SW1 and the gain control transistor DRX1 are turned on, both the fourth node N14 and the fifth node N15 may be reset to the reset voltage VRD. The reset voltage VRD may be a voltage generated from the reset voltage generating module 851.

[0162] The second switch transistor DSX may be coupled between the first node N11 and the second node N12 and controlled by a switch signal DSW. When the second switch transistor DSX is turned on, voltages of the first node N11 and the second node N12 may be the same.

[0163] The gain control transistor DRX1 may be coupled between the fourth node N14 and the fifth node N15 and turned on by the gain control signal DRG1. When the gain control transistor DRX1 is turned on, the fourth node N14 and the fifth node N15 may be coupled.

[0164] A gate of the driving transistor SF is coupled to the fifth node N15. The driving transistor SF may operate as a source follower amplifier for the voltage of the fifth node N15. The driving transistor SF may output a pixel voltage to the column line CL1 through the selection transistor SX1 in response to the voltage of the fifth node N15.

[0165] The selection transistor SX1 may be coupled between the drive transistor SF and the column line CL1 and may be controlled by the selection signal SEL. When the selection transistor SX1 is turned on, the pixel voltage output from the drive transistor SF may be output to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0166] The gain control transistor DRX1 may be coupled between the fourth node N14 and the fifth node N15 and controlled by the first gain control signal DRG1 .

[0167] The voltage of the fifth node N15 may depend on the charge accumulated in the photoelectric elements PD1 and PD2, and may be represented as the product of the charge accumulated in the photoelectric elements PD1 and PD2 and the conversion gain. The voltage of the fifth node N15 corresponding to the same amount of charge may be different depending on whether the first gain control signal DRG1 is active, and may vary according to the first gain control signal DRG1. In other words, when the first gain control signal DRG1 is passive, the pixel PX1 may have a high conversion gain (HCG), and when the first gain control signal DRG1 is active, the pixel PX1 may have a relatively low conversion gain (LCG). As described above, the pixel PX1 providing two different conversion gains may be referred to as a dual conversion gain (DCG) pixel.

[0168] The state code measurement module 850 may be coupled to the pixel PX1. The state code measurement module 850 may provide a reset voltage VRD to the second node N12 and provide a first gain control signal DRG1 to the gate of the gain control transistor DRX1. The row driver may also be coupled to the pixel PX1 to provide a power supply voltage VDD and a pixel power supply voltage VPIX.

[0169] Specifically, the state code measurement module 850 may include a reset voltage generation module 851, a gain control signal generation module 853, a first reset signal regulator 855, a second reset signal regulator 856, a first gain control regulator 857, and a second gain control regulator 858. Each of the state code measurement module 850, the reset voltage generation module 851, the gain control signal generation module 853, the first reset signal regulator 855, the second reset signal regulator 856, the first gain control regulator 857, and the second gain control regulator 858 may be physically implemented by an analog circuit and / or a digital circuit, which includes one or more of a logic gate, an integrated circuit, a microprocessor, a microcontroller, a memory circuit, a passive electronic component, an active electronic component, and the like.

[0170] The reset voltage generating module 851 may include a first reset voltage transistor RDX11, a second reset voltage transistor RDX12, and a third reset voltage transistor RDX13. The first reset voltage transistor RDX11 and the third reset voltage transistor RDX13 may be formed by a first type of transistor. The second reset voltage transistor RDX12 may be formed by a second type of transistor. For example, the first type of transistor may be a P-type transistor, and the second type of transistor may be an N-type transistor. The drain of the first reset voltage transistor RDX11, the drain of the second reset voltage transistor RDX12, and the drain of the third reset voltage transistor RDX13 may be coupled to the second node N12. The source of the first reset voltage transistor RDX11 may be coupled to the output terminal of the first reset signal regulator 855. The source of the second reset voltage transistor RDX12 may be coupled to the ground voltage. The source of the third reset voltage transistor RDX13 may be coupled to the output terminal of the second reset signal regulator 856.

[0171] The first reset signal regulator 855 may include an operational amplifier 8551 , a pass transistor VRDX11 , and a first resistor R11 .

[0172] A reference voltage V_REF11 may be provided to a first terminal of the operational amplifier 8551. The reference voltage V_REF11 may be generated based on the power supply voltage VDD. A second terminal of the operational amplifier 8551 may be coupled to an output node N_OUT11. The reference voltage V_REF11 may be determined by a voltage drop relative to the power supply voltage VDD caused by any resistor and any transistor. In some embodiments, the pass transistor VRDX11 may be a first type transistor. For example, the first type transistor may be a P-type transistor.

[0173] The first resistor R11 may be coupled in series between the output node N_OUT11 and the ground node of the first reset signal regulator 855. In other words, the voltage of the output node N_OUT11 may be input to the second terminal of the operational amplifier 8551 as the feedback voltage V_FB11.

[0174] The operational amplifier 8551 may amplify the difference between the reference voltage V_REF11 input to the first terminal and the feedback voltage V_FB11 input to the second terminal, and the output of the operational amplifier 8551 may be input to the gate of the pass transistor VRDX11 to drive the pass transistor VRDX11. The second terminal of the operational amplifier 8551 may be coupled to the output node N_OUT11 of the first reset signal regulator 855, and the feedback voltage V_FB11 may be the output voltage VRD1 of the first reset signal regulator 855.

[0175] The second reset signal regulator 856 may include the same configuration as that of the first reset signal regulator 855. The second reset signal regulator 856 may output an output voltage VRD2.

[0176] On the other hand, Figure 8 , it is shown that the first reset voltage VRD1 to be applied to the reset voltage generating module 851 is generated by the first reset signal regulator 855, and the second reset voltage VRD2 is generated by the second reset signal regulator 856; however, the present disclosure is not limited thereto, and the first reset voltage VRD1 and the second reset voltage VRD2 may be generated by one regulator. For example, when the regulator includes two resistors coupled in series, it may generate two different output voltages using a voltage drop caused by the resistors.

[0177] The gain control signal generating module 853 may include a first gain control transistor DRGX11, a second gain control transistor DRGX12, and a third gain control transistor DRGX13. The first gain control transistor DRGX11 and the third gain control transistor DRGX13 may be formed by a first type of transistor. The second gain control transistor DRGX12 may be formed by a second type of transistor. For example, the first type of transistor may be a P-type transistor, and the second type of transistor may be an N-type transistor. The drain of the first gain control transistor DRGX11, the drain of the second gain control transistor DRGX12, and the drain of the third gain control transistor DRGX13 may be coupled to the gate of the gain control transistor DRG1. The source of the first gain control transistor DRGX11 may be coupled to the output terminal of the first gain control regulator 857. The source of the second gain control transistor DRGX12 may be coupled to the ground voltage. The source of the third gain control transistor DRGX13 may be coupled to the output terminal of the second gain control regulator 858.

[0178] The first gain control regulator 857 may include an operational amplifier 8571 , a pass transistor VDRGX11 , and a first resistor R12 .

[0179] A reference voltage V_REF12 may be provided to a first terminal of the operational amplifier 8571. The reference voltage V_REF12 may be generated based on the power supply voltage VDD. A second terminal of the operational amplifier 8571 may be coupled to an output node N_OUT12. The reference voltage V_REF12 may be determined by a voltage drop relative to the power supply voltage VDD caused by any resistor and any transistor. In some embodiments, the pass transistor VDRGX11 may be a first type transistor. For example, the first type transistor may be a P-type transistor.

[0180] The first resistor R12 may be coupled in series between the output node N_OUT12 and the ground node of the first gain control regulator 857. In other words, the voltage of the output node N_OUT12 may be input to the second terminal of the operational amplifier 8571 as the feedback voltage V_FB12.

[0181] The operational amplifier 8571 may amplify the difference between the reference voltage V_REF12 input to the first terminal and the feedback voltage V_FB12 input to the second terminal, and the output of the operational amplifier 8571 may be input to the gate of the pass transistor VDRGX11 to drive the pass transistor VDRGX11. The second terminal of the operational amplifier 8571 may be coupled to the output node N_OUT12 of the first gain control regulator 857, and the feedback voltage V_FB12 may be the output voltage VDRG1 of the first gain control regulator 857.

[0182] The second gain control regulator 858 may include the same configuration as that of the first gain control regulator 857. The second gain control regulator 858 may output an output voltage VDRG2.

[0183] On the other hand, Figure 8 , it is shown that the first gain voltage VDRG1 to be applied to the gain control signal generating module 853 is generated by the first gain control regulator 857, and the second gain voltage VDRG2 is generated by the second gain control regulator 858; however, the present disclosure is not limited to this, and the first gain voltage VDRG1 and the second gain voltage VDRG2 can be generated by one regulator.

[0184] Fig. 9 It shows that according to Figure 8 A timing diagram of the operation of the image sensor. Fig.10 It shows that according to Fig. 9A diagram of the image sensor circuit during operation of the image sensor.

[0185] The reset voltage VRD may have a first reset voltage value VRD11, a second reset voltage value VRD12, and a third reset voltage value VRD13. In some embodiments, the first reset voltage value VRD11 may be a voltage applied to the second node N12 when the first reset voltage transistor RDX11 and the third reset voltage transistor RDX13 are turned on and the second reset voltage transistor RDX12 is turned off. The second reset voltage value VRD12 may be a voltage applied to the second node N12 when the first reset voltage transistor RDX11 is turned off and the second reset voltage transistor RDX12 and the third reset voltage transistor RDX13 are turned on. The third reset voltage value VRD13 may be a voltage applied to the second node N12 when the first reset voltage transistor RDX11 and the third reset voltage transistor RDX13 are turned off and the second reset voltage transistor RDX12 is turned on. In some embodiments, the first reset voltage value VRD11 may be a voltage value when the first reset voltage VRD1 is applied as the reset voltage VRD, and the third reset voltage value VRD13 may be a voltage value when the second reset voltage VRD2 is applied as the reset voltage VRD, and the second reset voltage value VRD12 may be a voltage value when the first reset voltage VRD1 and the second reset voltage VRD2 are applied together as the reset voltage VRD.

[0186] The reset transistor RX1 may be turned on when the reset control signal RG1 has a first reset control level RG11 , and may be turned off when the reset control signal RG1 has a second reset control level RG12 .

[0187] When the first gain control signal DRG1 has the first gain control level DRG11 and the second gain control level DRG12, the gain control transistor DRX1 may be turned on. In other words, the gain control transistor DRX1 may have a threshold voltage equal to or lower than the first gain control level DRG11 and the second gain control level DRG12.

[0188] In some embodiments, the first gain control level DRG11 may be a voltage applied to the gate of the gain control transistor DRX1 when the first gain control transistor DRGX11 and the third gain control transistor DRGX13 are turned on and the second gain control transistor DRGX12 is turned off. The second gain control level DRG12 may be a voltage applied to the gate of the gain control transistor DRX1 when the first gain control transistor DRGX11 is turned off and the second gain control transistor DRGX12 and the third gain control transistor DRGX13 are turned on. The third gain control level DRG13 may be a voltage applied to the gate of the gain control transistor DRX1 when the first gain control transistor DRGX11 and the third gain control transistor DRGX13 are turned off and the second gain control transistor DRGX12 is turned on.

[0189] The output voltage Vout may be a voltage at a fifth node N15 coupled to the gate of the driving transistor SF. A pixel voltage corresponding to the output voltage Vout may be transmitted to a readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0190] First, in the first period P1001 , the reset voltage VRD may have the second reset voltage value VRD12 , the reset control signal RG1 may have the first reset control level RG11 , and the first gain control signal DRG1 may have the first gain control level DRG11 .

[0191] Refer to Fig.10 , in the first period P1001, the first portion 801 may have Fig.10 The structure shown in (a).

[0192] The reset transistor RX1 may be turned on by the first gain control signal DRG1 at the first reset control level RG11, and the gain control transistor DRX1 may be turned on by the first gain control signal DRG1 at the first gain control level DRG11. Since the threshold voltage of the gain control transistor DRX1 is lower than the first gain control level DRG11, the gain control transistor DRX1 may be fully turned on. Therefore, the fourth node N14 and the fifth node N15 may have the second reset voltage value VRD12. In other words, the fourth node N14 and the fifth node N15 may be reset by the reset voltage VRD, thereby removing the charges stored in the fourth node N14 and the fifth node N15.

[0193] In the first period P1001, the output voltage Vout may have a first voltage value OUT11. In this case, the first voltage value OUT11 may be based on the second reset voltage value VRD12.

[0194] The first pixel voltage based on the first voltage value OUT11 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0195] In the second period P1003 , the reset voltage VRD may have a third reset voltage value VRD13 , the reset control signal RG1 may have a first reset control level RG11 , and the first gain control signal DRG1 may have a second gain control level DRG12 .

[0196] Reference Fig.10 In the second period P1003, the first part 801 may have Fig.10 The structure shown in (b).

[0197] The reset transistor RX1 may be turned on by the reset control signal RG1 at the first reset control level RG11, and the gain control transistor DRX1 may be turned on by the reset control signal RG1 at the second gain control level DRG12. Therefore, the fourth node N14 and the fifth node N15 may have a third reset voltage value VRD13. Here, the third reset voltage value VRD13 may be a value that is smaller than the second reset voltage value VRD12 by the threshold voltage of the gain control transistor DRX1. For example, when the second reset voltage value VRD12 is 2.4V and the threshold voltage of the gain control transistor DRX1 is 0.7V, the third reset voltage value VRD13 may be a value less than 1.7V.

[0198] The output voltage Vout may have a third voltage value OUT13. In this case, the third voltage value OUT13 may be based on a third reset voltage value VRD13.

[0199] The second pixel voltage based on the third voltage value OUT13 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0200] In the third period P1005 , the reset voltage VRD may have a first reset voltage value VRD11 , the reset control signal RG1 may have a first reset control level RG11 , and the first gain control signal DRG1 may have a second gain control level DRG12 .

[0201] Reference Fig.10 In the third period P1005, the first portion 801 may have Fig.10 The structure shown in (c).

[0202] The reset transistor RX1 may be turned on by the first reset control level RG11, and the gain control transistor DRX1 may be turned on by the second gain control level DRG12. On the other hand, as the reset voltage VRD increases from the third reset voltage value VRD13 to the first reset voltage value VRD11, the voltage to be applied to the fourth node N14 and the fifth node N15 may increase. In this case, the gain control transistor DRX1 may be located in the triode region. The triode region may be a region where, for the gain control transistor DRX1, when the value of the drain-source voltage is smaller than the value obtained by subtracting the threshold voltage from the gate-source voltage, as the drain-source voltage of the transistor increases, the drain current value increases. In other words, when the voltage of the fifth node N15 on the source side of the gain control transistor DRX1 is set to a low voltage and the gate voltage of the gain control transistor DRX1 is increased to the second gain control level DRG12, the voltage of the fifth node N15 on the source side of the gain control transistor DRX1 can be increased to a value obtained by subtracting the threshold voltage from the second gain control level DRG12.

[0203] Therefore, as the reset voltage VRD increases from the third reset voltage value VRD13 to the first reset voltage value VRD11, the output voltage Vout may increase from the third voltage value OUT13 to the second voltage value OUT12. Since the gain control transistor DRX1 is located in the triode region, the second voltage value OUT12 may be based on a value obtained by subtracting a threshold voltage of the gain control transistor DRX1 from the second gain control level DRG12.

[0204] A third pixel voltage based on a value obtained by subtracting the threshold voltage of the gain control transistor DRX1 from the second gain control level DRG12 may be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0205] On the other hand, in the third period P1005, the readout circuit can sample and process the third pixel voltage corresponding to the second voltage value OUT12. However, since the reset transistor RX1 and the gain control transistor DRX1 are turned on, the second voltage value OUT12 may be affected by the reset voltage VRD11 when the image sensor operates under high temperature conditions.

[0206] In the fourth period P1007 , the reset voltage VRD may have the first reset voltage value VRD11 , the reset control signal RG1 may have the second reset control level RG12 , and the first gain control signal DRG1 may have the second gain control level DRG12 .

[0207] Reference Fig.10In the fourth period P1007, the first portion 801 may have Fig.10 The structure shown in (d).

[0208] The reset transistor RX1 can be turned off by the second reset control level RG12, and the gain control transistor DRX1 can be turned on by the second gain control level DRG12. By turning off the reset transistor RX1, the second voltage value OUT12 is less likely to be affected by the reset voltage VRD11. Therefore, the readout circuit ( Figure 2 The reference numeral “260” in the figure can more accurately sample and process the third pixel voltage corresponding to the second voltage value OUT12.

[0209] Readout circuit ( Figure 2 The first pixel voltage may be sampled in the first period P1001 to obtain a first code value corresponding to the first voltage value OUT11 based on the second reset voltage value VRD12, and the first pixel voltage may be sampled in the third period P1005 and the fourth period P1007 to obtain a second code value corresponding to the second voltage value OUT12 based on a value obtained by subtracting the threshold voltage of the gain control transistor DRX1 from the second reset voltage value VRD12. The readout circuit ( Figure 2 The reference numeral "260" in the figure may be sent to the image signal processor ( Figure 2 ” in the figure (reference mark “290”) sends the acquired first code value and the acquired second code value.

[0210] Image Signal Processor ( Figure 2 ” in the figure mark “ 290 ”) calculates a state code by subtracting the first code value from the acquired second code value, the state code being a code value related to the threshold voltage of the gain control transistor DRX1.

[0211] Fig.11 It shows that according to Figure 8 A timing diagram of the operation of the image sensor. Fig.12 It shows that according to Fig.11 A diagram of the image sensor circuit during operation of the image sensor.

[0212] The reset voltage VRD may have a first reset voltage value VRD11 and a third reset voltage value VRD13. In some embodiments, the first reset voltage value VRD11 may be a voltage applied to the second node N12 when the first reset voltage transistor RDX11 and the third reset voltage transistor RDX13 are turned on and the second reset voltage transistor RDX12 is turned off. The third reset voltage value VRD13 may be a voltage applied to the second node N12 when the first reset voltage transistor RDX11 and the third reset voltage transistor RDX13 are turned off and the second reset voltage transistor RDX12 is turned on.

[0213] The reset transistor RX1 may be turned on when the reset control signal RG1 has a first reset control level RG11 , and may be turned off when the reset control signal RG1 has a second reset control level RG12 .

[0214] When the first gain control signal DRG1 has the first gain control level DRG11 and the second gain control level DRG12, the gain control transistor DRX1 may be turned on. In other words, the gain control transistor DRX1 may have a threshold voltage lower than the first gain control level DRG11 and the second gain control level DRG12.

[0215] The output voltage Vout may be a voltage applied to the fifth node N15 coupled to the gate of the driving transistor SF. A pixel voltage corresponding to the output voltage Vout may be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0216] First, in the first period P2001 , the reset voltage VRD may have the third reset voltage value VRD13 , the reset control signal RG1 may have the first reset control level RG11 , and the first gain control signal DRG1 may have the first gain control level DRG11 .

[0217] Refer to Fig.12 , in the first period P2001, the first portion 801 may have Fig.12 The structure shown in (a).

[0218] The reset transistor RX1 may be turned on by the first reset control level RG11, and the gain control transistor DRX1 may be turned on by the first gain control level DRG11. Since the threshold voltage of the gain control transistor DRX1 is lower than the first gain control level DRG11, the gain control transistor DRX1 may be fully turned on. Therefore, the fourth node N14 and the fifth node N15 may have the third reset voltage value VRD13. In other words, the fourth node N14 and the fifth node N15 may be reset by the reset voltage, so that the charges stored in the fourth node N14 and the fifth node N15 may be removed.

[0219] In the first period P1001, the output voltage Vout may have a third voltage value OUT13. In this case, the third voltage value OUT13 may be based on the third reset voltage value VRD13.

[0220] The first pixel voltage based on the third voltage value OUT13 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0221] Here, the third reset voltage value VRD13 may be a value smaller than a threshold voltage of the first gain control level DRG11 of the gain control transistor DRX1 .

[0222] In the second period P2003 , the reset voltage VRD may have a first reset voltage value VRD11 , the reset control signal RG1 may have a first reset control level RG11 , and the first gain control signal DRG1 may have a first gain control level DRG11 .

[0223] Reference Fig.12 In the second period P2003, the first part 801 may have Fig.12 The structure shown in (b).

[0224] The reset transistor RX1 may be turned on by the first reset control level RG11, and the gain control transistor DRX1 may be turned on by the first gain control level DRG11. Therefore, the voltage increased to have the first reset voltage value VRD11 may be applied to the fourth node N14 and the fifth node N15. On the other hand, since the gain control transistor DRX1 is located in the triode region, a voltage obtained by subtracting the threshold voltage of the gain control transistor DRX1 from the first gain control level DRG11 may be applied to the fourth node N14 and the fifth node N15. In other words, when the voltage of the fifth node N15 as the source side of the gain control transistor DRX1 is set to a low voltage and the voltage of the fourth node N14 as the drain side of the gain control transistor DRX1 is increased, the voltage of the fifth node N15 as the source side of the gain control transistor DRX1 may be increased to a value obtained by subtracting the threshold voltage from the first gain control level DRG11 as the gate voltage of the gain control transistor DRX1.

[0225] Therefore, as the reset voltage VRD increases from the third reset voltage value VRD13 to the first reset voltage value VRD11, the output voltage Vout may increase from the third voltage value OUT13 to the first voltage value OUT11. Since the gain control transistor DRX1 is located in the triode region, the first voltage value OUT11 may be a value obtained by subtracting a threshold voltage from the first gain control level DRG11.

[0226] A second pixel voltage based on a value obtained by subtracting the threshold voltage of the gain control transistor DRX1 from the first gain control level DRG11 may be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0227] In the third period P2005 , the reset voltage VRD may have a first reset voltage value VRD11 , the reset control signal RG1 may have a second reset control level RG12 , and the first gain control signal DRG1 may have a first gain control level DRG11 .

[0228] Reference Fig.12 In the third period P2005, the first part 801 may have Fig.12 The structure shown in (c).

[0229] The reset transistor RX1 can be turned off by the second reset control level RG12, and the gain control transistor DRX1 can be turned on by the first gain control level DRG11. By turning off the reset transistor RX1, the first voltage value OUT11 is less likely to be affected by the reset voltage VRD11. Therefore, the readout circuit ( Figure 2The reference numeral “ 260 ” in the figure can more accurately sample and process the third pixel voltage corresponding to the first voltage value OUT11.

[0230] In the fourth period P2007 , the reset voltage VRD may have a third reset voltage value VRD13 , the reset control signal RG1 may have a first reset control level RG11 , and the first gain control signal DRG1 may have a first gain control level DRG11 .

[0231] Reference Fig.12 In the fourth period P2007, the first part 801 may have Fig.12 The structure shown in (d).

[0232] The reset transistor RX1 may be turned on by the first reset control level RG11 , and the gain control transistor DRX1 may be turned on by the first gain control level DRG11 .

[0233] As the reset voltage VRD decreases from the first reset voltage value VRD11 to the third reset voltage value VRD13 , voltages to be applied to the fourth node N14 and the fifth node N15 may decrease.

[0234] The fourth node N14 and the fifth node N15 may be reset by the reset voltage VRD having the third reset voltage value VRD13 , and thus charges stored in the fourth node N14 and the fifth node N15 may be removed.

[0235] Therefore, the readout circuit ( Figure 2 ” in the figure (reference numeral “ 260 ”) may sample and process a fourth pixel voltage corresponding to the third voltage value OUT13 .

[0236] In the fifth period P2009 , the reset voltage VRD may have a third reset voltage value VRD13 , the reset control signal RG1 may have a second reset control level RG12 , and the first gain control signal DRG1 may have a first gain control level DRG11 .

[0237] Reference Fig.12 In the fifth period P2009, the first part 801 may have Fig.12 The structure shown in (e).

[0238] The reset transistor RX1 can be turned off by the second reset control level RG12, and the gain control transistor DRX1 can be turned on by the first gain control level DRG11. By turning off the reset transistor RX1, the third voltage value OUT13 is less likely to be affected by the reset voltage VRD13. Therefore, the readout circuit ( Figure 2The reference numeral “260” in the figure can more accurately sample and process the fifth pixel voltage corresponding to the third voltage value OUT13.

[0239] Readout circuit ( Figure 2 The reference numeral "260" in the figure) can obtain a first code value corresponding to the first voltage value OUT11 based on a value obtained by subtracting the threshold voltage from the first gain control level DRG11 by sampling the third pixel voltage in the third period P2005. In addition, the readout circuit ( Figure 2 The second code value corresponding to the third voltage value OUT13 can be obtained based on the third reset voltage value VRD13 by sampling the fourth pixel voltage in the fourth period P2007, or the second code value corresponding to the third voltage value OUT13 can be obtained based on the third reset voltage value VRD13 by sampling the fifth pixel voltage in the fifth period P2009. Figure 2 The reference numeral "260" in the figure may be sent to the image signal processor ( Figure 2 ” in the figure (reference mark “290”) sends the acquired first code value and the acquired second code value.

[0240] By subtracting the first code value from the acquired second code value, the image signal processor ( Figure 2 The state code can be calculated by the reference numeral "290" in the figure, which is a code value related to the threshold voltage of the gain control transistor DRX1. In this way, the image signal processor ( Figure 2 ' 290 ' in the figure) can calculate not only the state code but also the code related to the offset difference between the first gain control level DRG11 and the third reset voltage value VRD13.

[0241] Fig.13 is a circuit diagram showing an image sensor according to an embodiment.

[0242] Specifically, Fig.13 1 is a diagram showing one pixel PX2 in the pixel array 1330 and a state code measurement module 1350 coupled to the pixel PX2. The image sensor 800 according to the embodiment may further include a timing controller, a readout circuit, a data buffer, and the like.

[0243] The pixel PX2 may include a photoelectric element PD3 and a plurality of transistors. Fig.13 In FIG. 1 , it is shown that one pixel PX2 includes one photoelectric element PD3 ; however, the present embodiment is not limited thereto, and one pixel PX2 may include a plurality of photoelectric elements.

[0244] A cathode of the photo element PD3 may be coupled to the first node N21 through the transfer transistor LTX, and an anode of the photo element PD3 may be grounded.

[0245] The plurality of transistors may include a transfer transistor LTX, a reset transistor RX2, a gain control transistor DRX2, a drive transistor SF, and a selection transistor SX2. The transistors LTX, RX2, DRX2, and SX2 in the pixel PX2 may be responsive to the row driver ( Figure 2 The module 1300 operates based on the reference numeral “240” in the figure and control signals (eg, the transmission control signal LTG, the selection signal SEL, the reset control signal RG2, and the gain control signal DRG2) provided by the status code measurement module 1350.

[0246] The transfer transistor LTX may be coupled between the photoelectric element PD3 and the first node N21 and controlled by a transfer control signal LTG. When the transfer transistor LTX is turned on, the charge generated by the photoelectric element PD3 may be transferred to the first node N21. The transfer transistor LTX may be turned off in response to the deactivated transfer control signal LTG. When the transfer transistor LTX is turned off (i.e., during the exposure time), the photoelectric element PD3 may accumulate charge depending on the incident light.

[0247] In some embodiments, the pixel PX2 may include a plurality of floating diffusions. Each of the plurality of floating diffusions may have a predetermined capacitance and may store charges generated by the photoelectric element PD3. Each of the plurality of floating diffusions may have a parasitic capacitance. In some embodiments, the pixel PX2 may further include a capacitor as a passive element, which is respectively coupled to the plurality of floating diffusions.

[0248] The reset transistor RX2 may be coupled between the third node N23 and a voltage line supplying a pixel power supply voltage VPIX and may be controlled by a reset control signal RG2. When the reset transistor RX2 is turned on by the reset control signal RG2, the pixel power supply voltage VPIX may be applied to the third node N23 so that the third node N23 is reset. When the reset transistor RX2 is turned on, if the gain control transistor DRX2 is turned on, the first node N21 may be reset to the pixel power supply voltage VPIX.

[0249] The gain control transistor DRX2 may be coupled between the first node N21 and the third node N23 and turned on by the gain control signal DRG2. When the gain control transistor DRX2 is turned on, the first node N21 and the third node N23 may be coupled.

[0250] A gate of the driving transistor SF is coupled to the first node N21. The driving transistor SF may operate as a source follower amplifier for the voltage of the first node N21. The driving transistor SF may output a pixel voltage to the column line CL2 through the selection transistor SX2 in response to the voltage of the first node N21.

[0251] The selection transistor SX2 may be coupled between the drive transistor SF and the column line CL2 and may be controlled by the selection signal SEL. When the selection transistor SX2 is turned on, the pixel voltage output from the drive transistor SF may be output to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0252] The gain control transistor DRX2 may be coupled between the first node N21 and the third node N23 and controlled by a gain control signal DRG2 .

[0253] The state code measurement module 1350 may be coupled to the pixel PX2. The state code measurement module 1350 may provide a gain control signal DRG2 to the gate of the gain control transistor DRX2. A row driver may also be coupled to the pixel PX2 to provide a power supply voltage VDD and a pixel power supply voltage VPIX.

[0254] The state code measurement module 1350 may include a gain control signal generation module 1353 , a first gain control regulator 1357 , and a second gain control regulator 1358 .

[0255] The gain control signal generating module 1353 may include a first gain control transistor DRGX21, a second gain control transistor DRGX22, and a third gain control transistor DRGX23. The first gain control transistor DRGX21 and the third gain control transistor DRGX23 may be formed by a first type of transistor. The second gain control transistor DRGX22 may be formed by a second type of transistor. For example, the first type of transistor may be a P-type transistor, and the second type of transistor may be an N-type transistor. The drain of the first gain control transistor DRGX21, the drain of the second gain control transistor DRGX22, and the drain of the third gain control transistor DRGX23 may be coupled to the gate of the gain control transistor DRG2. The source of the first gain control transistor DRGX21 may be coupled to the output terminal of the first gain control regulator 1357. The source of the second gain control transistor DRGX22 may be coupled to the ground voltage. The source of the third gain control transistor DRGX23 may be coupled to the output terminal of the second gain control regulator 1358.

[0256] The first gain control regulator 1357 may include an operational amplifier 13571 , a pass transistor VDRGX11 , and a first resistor R12 .

[0257] A reference voltage V_REF22 may be provided to a first terminal of the operational amplifier 13571. The reference voltage V_REF22 may be generated based on the power supply voltage VDD. A second terminal of the operational amplifier 13571 may be coupled to an output node N_OUT22. The reference voltage V_REF22 may be determined by a voltage drop relative to the power supply voltage VDD caused by any resistor and any transistor. In some embodiments, the pass transistor VDRGX21 may be a first type transistor. For example, the first type transistor may be a P-type transistor.

[0258] The first resistor R22 may be coupled in series between the output node N_OUT22 and the ground node of the first gain control regulator 1357. In other words, the voltage of the output node N_OUT22 may be input to the second terminal of the operational amplifier 13571 as the feedback voltage V_FB22.

[0259] The operational amplifier 13571 may amplify the difference between the reference voltage V_REF22 input to the first terminal and the feedback voltage V_FB22 input to the second terminal, and the output of the operational amplifier 13571 may be input to the gate of the pass transistor VDRGX21 to drive the pass transistor VDRGX21. The second terminal of the operational amplifier 13571 may be coupled to the output node N_OUT22 of the first gain control regulator 1357, and the feedback voltage V_FB22 may be the output voltage VDRG1 of the first gain control regulator 1357.

[0260] The second gain control regulator 1358 may include the same configuration as that of the first gain control regulator 1357. The second gain control regulator 1358 may output an output voltage VDRG2.

[0261] On the other hand, Fig.13 , it is shown that a first gain voltage VDRG1 to be applied to a gain control signal generating module 1353 is generated by a first gain control regulator 1357, and a second gain voltage VDRG2 is generated by a second gain control regulator 1358; however, the present disclosure is not limited thereto, and the first gain voltage VDRG1 and the second gain voltage VDRG2 may be generated by one regulator.

[0262] Fig.14 It shows that according to Fig.13 A timing diagram of the operation of the image sensor. Fig.15 It shows that according to Fig.13 A diagram of the image sensor circuit during operation of the image sensor.

[0263] The reset transistor RX2 may be turned on when the reset control signal RG2 has a first reset control level RG21 , and may be turned off when the reset control signal RG2 has a second reset control level RG22 .

[0264] When the first gain control signal DRG2 has a first gain control level DRG21 and a second gain control level DRG22, the gain control transistor DRX2 may be turned on. In addition, when the first gain control signal DRG2 has a third gain control level DRG23, the gain control transistor DRX2 may be turned off. In other words, the gain control transistor DRX2 may have a threshold voltage equal to or lower than the first gain control level DRG21 and the second gain control level DRG22 and equal to or higher than the third gain control level DRG23.

[0265] In some embodiments, the first gain control level DRG21 may be a voltage applied to the gate of the gain control transistor DRX2 when the first gain control transistor DRGX21 and the third gain control transistor DRGX23 are turned on and the second gain control transistor DRGX22 is turned off. The second gain control level DRG22 may be a voltage applied to the gate of the gain control transistor DRX2 when the first gain control transistor DRGX21 is turned off and the second gain control transistor DRGX22 and the third gain control transistor DRGX23 are turned on. The third gain control level DRG23 may be a voltage applied to the gate of the gain control transistor DRX2 when the first gain control transistor DRGX21 and the third gain control transistor DRGX23 are turned off and the second gain control transistor DRGX22 is turned on.

[0266] The output voltage Vout may be a voltage at a first node N21 coupled to the gate of the driving transistor SF. A pixel voltage corresponding to the output voltage Vout may be transmitted to a readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0267] First, in the first period P3001 , the reset control signal RG2 may have the first reset control level RG21 , and the gain control signal DRG2 may have the first gain control level DRG21 .

[0268] Refer to Fig.15 In the first period P3001, the first part 1301 may have Fig.15 The structure shown in (a).

[0269] The reset transistor RX2 may be turned on by the first reset control level RG21, and the gain control transistor DRX2 may be turned on by the first gain control level DRG21. Since the threshold voltage of the gain control transistor DRX2 is lower than the first gain control level DRG21, the gain control transistor DRX2 may be fully turned on. Therefore, the first node N21 and the third node N23 may have the pixel power supply voltage VPIX. In other words, the first node N21 and the third node N23 may be reset by the reset voltage, thereby removing the charges stored in the first node N21 and the third node N23.

[0270] In the first period P3001, the output voltage Vout may have a first voltage value OUT11. In this case, the first voltage value OUT11 may be based on the pixel power supply voltage VPIX.

[0271] The first pixel voltage based on the first voltage value OUT11 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0272] In the second period P3003 , the reset control signal RG2 may have the second reset control level RG22 , and the gain control signal DRG2 may have the third gain control level DRG23 after a predetermined time from when the reset control signal RG2 transitions to the second reset control level RG22 .

[0273] Reference Fig.15 In the second period P3003, the first part 1301 may have Fig.15 The structure shown in (b).

[0274] The reset transistor RX2 may be turned off by the second reset control level RG22. Since the reset transistor RX2 and the gain control transistor DRX2 are turned on before the reset transistor RX2 is turned off, both the first node N21 and the third node N23 may have the pixel power supply voltage VPIX. Therefore, when the reset transistor RX2 and the gain control transistor DRX2 are turned off at the same time, due to the coupling phenomenon, the voltage of the first node N21 may only be reduced by a voltage smaller than the voltage that the first node should be reduced. Therefore, the image sensor 200 may sequentially control the reset control signal RG2 and the gain control signal DRG2 so that the gain control signal has the third gain control level DRG23 after a predetermined time from when the reset control signal is transferred to the second reset control level RG22. Since the gain control transistor DRX2 is turned off in a state where the reset transistor RX2 is turned off, the first node N21 and the third node N23 may have a lower voltage by coupling while being less affected by the pixel power supply voltage VPIX.

[0275] The gain control transistor DRX2 may be turned off by the third gain control level DRG23. Therefore, the first node N21 and the third node N23 may have the second reset control level RG22.

[0276] The output voltage Vout may have a third voltage value OUT23. In this case, the third voltage value OUT23 may be based on the pixel power supply voltage VPIX.

[0277] The second pixel voltage based on the third voltage value OUT23 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0278] In the third period P3005 , the reset control signal RG2 may have the first reset control level RG21 , and the gain control signal DRG2 may have the third gain control level DRG23 .

[0279] Reference Fig.15 In the third period P3005, the first part 1301 may have Fig.15 The structure shown in (c).

[0280] The reset transistor RX2 may be turned on by the first reset control level RG21, and the gain control transistor DRX2 may be turned off by the third gain control level DRG23. On the other hand, the reset transistor RX2 may be turned on so that the third node N23 is coupled to the pixel power supply voltage VPIX.

[0281] In the third period P3005 , after a predetermined time from when the reset control signal RG2 transitions to the first reset control level RG21 , the gain control signal DRG2 may be changed from the third gain control level DRG23 to the second gain control level DRG22 .

[0282] Since the gain control transistor DRX2, which is turned off by the third gain control level DRG23, is turned on by the second gain control level DRG22, the voltage applied to the first node N21 can be increased. In this case, the gain control transistor DRX2 can be located in the triode region. On the other hand, when the voltage of the first node N21 as the source side of the gain control transistor DRX2 is set to a low voltage and the gate voltage of the gain control transistor DRX2 is increased to the second gain control level DRG22, the voltage of the first node N21 as the source side of the gain control transistor DRX2 can be increased to a value obtained by subtracting the threshold voltage from the second gain control level DRG22 as the gate voltage of the gain control transistor DRX2.

[0283] Therefore, the output voltage Vout may increase from the third voltage value OUT23 to the second voltage value OUT22. Since the gain control transistor DRX2 is located in the triode region, the second voltage value OUT22 may be based on a value obtained by subtracting a threshold voltage of the gain control transistor DRX2 from the second gain control level DRG22.

[0284] The third pixel voltage based on the value obtained by subtracting the threshold voltage of the gain control transistor DRX2 from the second gain control level DRG22 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0285] On the other hand, in the third period P3005, the readout circuit can sample and process the third pixel voltage corresponding to the second voltage value OUT22. However, since the reset transistor RX2 and the gain control transistor DRX2 are turned on, the second voltage value OUT22 may be affected by the pixel power supply voltage VPIX when the image sensor operates under high temperature conditions.

[0286] In the fourth period P3007 , the reset control signal RG2 may have the second reset control level RG22 , and the gain control signal DRG2 may have the second gain control level DRG22 .

[0287] Reference Fig.15 In the fourth period P3007, the first part 1301 may have Fig.15 The structure shown in (d).

[0288] The reset transistor RX2 can be turned off by the second reset control level RG22, and the gain control transistor DRX2 can be turned on by the second gain control level DRG22. By turning off the reset transistor RX2, the second voltage value OUT22 is less likely to be affected by the pixel power supply voltage VPIX. Therefore, the readout circuit ( Figure 2 The reference numeral “260” in the figure can more accurately sample and process the third pixel voltage corresponding to the second voltage value OUT22.

[0289] Readout circuit ( Figure 2 The first pixel voltage may be sampled in the first period P3001 to obtain a first code value corresponding to the first voltage value OUT21 based on the pixel power supply voltage VPIX, and the third pixel voltage may be sampled in the fifth period P3009 and the sixth period P3011 to obtain a second code value corresponding to the second voltage value OUT22 based on a value obtained by subtracting the threshold voltage of the gain control transistor DRX2 from the second gain control level DRG22. The readout circuit ( Figure 2 The reference numeral "260" in the figure may be sent to the image signal processor ( Figure 2 ” in the figure (reference mark “290”) sends the acquired first code value and the acquired second code value.

[0290] By subtracting the first code value from the acquired second code value, the image signal processor ( Figure 2 The state code can be calculated by the reference numeral "290" in the figure, which is a code value related to the threshold voltage of the gain control transistor DRX2. In this way, the image signal processor ( Figure 2 ' 290 ' in the figure) can calculate not only the state code but also the code related to the offset difference between the pixel power supply voltage VPIX and the second gain control level DRG22.

[0291] Fig.16 is a circuit diagram showing an image sensor according to an embodiment.

[0292] Specifically, Fig.16 16 is a diagram showing one pixel PX3 in the pixel array 1630 and a state code measurement module 1650 coupled to the pixel PX3. The image sensor 1600 according to the embodiment may further include a timing controller, a readout circuit, a data buffer, and the like.

[0293] The pixel PX3 may include a photoelectric element PD4 and a plurality of transistors. Fig.16 In FIG. 1 , it is shown that one pixel PX3 includes one photoelectric element PD4 ; however, the present embodiment is not limited thereto, and one pixel PX3 may include a plurality of photoelectric elements.

[0294] A cathode of the photo element PD4 may be coupled to the first node N31 through the transfer transistor LTX, and an anode of the photo element PD4 may be grounded.

[0295] The plurality of transistors may include a transmission transistor LTX3, a reset transistor RX3, a drive transistor SF, and a selection transistor SX3. The transistors LTX3, RX3, and SX3 in the pixel PX3 may be responsive to a row driver ( Figure 2 The module 1600 operates based on the reference numeral “240” in the figure and control signals (eg, the transmission control signal LTG3, the selection signal SEL, and the reset control signal RG3) provided by the status code measurement module 1650.

[0296] The transfer transistor LTX3 may be coupled between the photoelectric element PD4 and the first node N31 and controlled by the transfer control signal LTG3. When the transfer transistor LTX3 is turned on, the charge generated by the photoelectric element PD4 may be transferred to the first node N31. The transfer transistor LTX3 may be turned off in response to the deactivated transfer control signal LTG3. When the transfer transistor LTX3 is turned off (i.e., during the exposure time), the photoelectric element PD4 may accumulate charge depending on the incident light.

[0297] In some embodiments, the pixel PX3 may include a plurality of floating diffusions. Each of the plurality of floating diffusions may have a predetermined capacitance and may be capable of storing charges generated by the photoelectric element PD4. Each of the plurality of floating diffusions may have a parasitic capacitance. In some embodiments, the pixel PX3 may further include a capacitor as a passive element, which is respectively coupled to the plurality of floating diffusions.

[0298] The reset transistor RX3 may be coupled between the first node N31 and a voltage line supplying a pixel power supply voltage VPIX and controlled by a reset control signal RG3. When the reset transistor RX3 is turned on by the reset control signal RG3, the pixel power supply voltage VPIX may be applied to the first node N31, so that the first node N31 is reset.

[0299] A gate of the driving transistor SF is coupled to the first node N31. The driving transistor SF may operate as a source follower amplifier for the voltage of the first node N31. The driving transistor SF may output a pixel voltage to the column line CL3 through the selection transistor SX3 in response to the voltage of the first node N31.

[0300] The selection transistor SX3 may be coupled between the drive transistor SF and the column line CL3 and may be controlled by the selection signal SEL. When the selection transistor SX3 is turned on, the pixel voltage output from the drive transistor SF may be output to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0301] The state code measurement module 1650 may be coupled to the pixel PX3. The state code measurement module 1650 may send a reset control signal RG3 to the gate of the reset transistor RX3 and a transmission control signal LTG3 to the gate of the transmission transistor LTX3. The row driver may also be coupled to the pixel PX3 to provide a power supply voltage VDD and a pixel power supply voltage VPIX.

[0302] Specifically, the state code measurement module 1650 may include a reset signal generation module 1651, a transmission signal generation module 1653, a first reset signal regulator 1655, a second reset signal regulator 1656, a first transmission control regulator 1657, and a second transmission control regulator 1658. Each of the state code measurement module 1650, the reset signal generation module 1651, the transmission signal generation module 1653, the first reset signal regulator 1655, the second reset signal regulator 1656, the first transmission control regulator 1657, and the second transmission control regulator 1658 may be physically implemented by an analog circuit and / or a digital circuit, which includes one or more of a logic gate, an integrated circuit, a microprocessor, a microcontroller, a memory circuit, a passive electronic component, an active electronic component, and the like.

[0303] The reset signal generating module 1651 may include a first reset signal transistor RGX31, a second reset signal transistor RGX32, and a third reset signal transistor RGX33. The first reset signal transistor RGX31 and the third reset signal transistor RGX33 may be formed by a first type of transistor. The second reset signal transistor RGX32 may be formed by a second type of transistor. For example, the first type of transistor may be a P-type transistor, and the second type of transistor may be an N-type transistor. The drain of the first reset signal transistor RGX31, the drain of the second reset signal transistor RGX32, and the drain of the third reset signal transistor RGX33 may be coupled to a third node N33. The source of the first reset signal transistor RGX31 may be coupled to an output terminal of the first reset signal regulator 1655. The source of the second reset signal transistor RGX32 may be coupled to a ground voltage. The source of the third reset signal transistor RGX33 may be coupled to an output terminal of the second reset signal regulator 1656.

[0304] The first reset signal regulator 1655 may include an operational amplifier 16551 , a pass transistor VRDX31 , and a first resistor R31 .

[0305] A reference voltage V_REF31 may be provided to a first terminal of the operational amplifier 16551. The reference voltage V_REF31 may be generated based on the power supply voltage VDD. A second terminal of the operational amplifier 16551 may be coupled to an output node N_OUT31. The reference voltage V_REF31 may be determined by a voltage drop relative to the power supply voltage VDD caused by any resistor and any transistor.

[0306] In some embodiments, the pass transistor VRDX31 may be a first type transistor. For example, the first type transistor may be a P-type transistor.

[0307] The first resistor R31 may be coupled in series between the output node N_OUT31 and the ground node of the first reset signal regulator 1655. In other words, the voltage of the output node N_OUT31 may be input to the second terminal of the operational amplifier 16551 as the feedback voltage V_FB31.

[0308] The operational amplifier 16551 may amplify the difference between the reference voltage V_REF31 input to the first terminal and the feedback voltage V_FB31 input to the second terminal, and the output of the operational amplifier 16551 may be input to the gate of the pass transistor VRDX31 to drive the pass transistor VRDX31. The second terminal of the operational amplifier 16551 may be coupled to the output node N_OUT31 of the first reset signal regulator 1655, and the feedback voltage V_FB31 may be the output voltage VRG1 of the first reset signal regulator 1655.

[0309] The second reset signal regulator 1656 may include the same configuration as that of the first reset signal regulator 1655. The second reset signal regulator 1656 may output an output voltage VRG2.

[0310] On the other hand, Fig.16 , it is shown that the first reset voltage VRG1 to be applied to the reset signal generating module 1651 is generated by the first reset signal regulator 1655, and the second reset voltage VRG2 is generated by the second reset signal regulator 1656; however, the present disclosure is not limited thereto, and the first reset voltage VRG1 and the second reset voltage VRG2 may be generated by one regulator. For example, when the regulator includes two resistors coupled in series, it may generate two different output voltages using a voltage drop caused by the resistors.

[0311] The transmission signal generating module 1653 may include a first transmission control transistor TGX31, a second transmission control transistor TGX32, and a third transmission control transistor TGX33. The first transmission control transistor TGX31 and the third transmission control transistor TGX33 may be formed by a first type of transistor. The second transmission control transistor TGX32 may be formed by a second type of transistor. For example, the first type of transistor may be a P-type transistor, and the second type of transistor may be an N-type transistor. The drain of the first transmission control transistor TGX31, the drain of the second transmission control transistor TGX32, and the drain of the third transmission control transistor TGX33 may be coupled to the gate of the transmission transistor LTX3. The source of the first transmission control transistor TGX31 may be coupled to the output terminal of the first transmission control regulator 1657. The source of the second transmission control transistor TGX32 may be coupled to the ground voltage. The source of the third transmission control transistor TGX33 may be coupled to the output terminal of the second transmission control regulator 1658.

[0312] The first transmission control regulator 1657 may include an operational amplifier 16571 , a pass transistor VDRGX31 , and a first resistor R32 .

[0313] A reference voltage V_REF32 may be provided to a first terminal of the operational amplifier 16571. The reference voltage V_REF32 may be generated based on the power supply voltage VDD. A second terminal of the operational amplifier 16571 may be coupled to an output node N_OUT32. The reference voltage V_REF32 may be determined by a voltage drop relative to the power supply voltage VDD caused by any resistor and any transistor. In some embodiments, the pass transistor VDRGX31 may be a first type transistor. For example, the first type transistor may be a P-type transistor.

[0314] The first resistor R32 may be coupled in series between the output node N_OUT32 and the ground node of the first transmission control regulator 1657. In other words, the voltage of the output node N_OUT32 may be input to the second terminal of the operational amplifier 16571 as the feedback voltage V_FB32.

[0315] The operational amplifier 16571 may amplify the difference between the reference voltage V_REF32 input to the first terminal and the feedback voltage V_FB32 input to the second terminal, and the output of the operational amplifier 16571 may be input to the gate of the pass transistor VDRGX31 to drive the pass transistor VDRGX31. The second terminal of the operational amplifier 16571 may be coupled to the output node N_OUT32 of the first transmission control regulator 1657, and the feedback voltage V_FB32 may be the output voltage VNTG1 of the first transmission control regulator 1657.

[0316] The second transmission control regulator 1658 may include the same configuration as that of the first transmission control regulator 1657. The second transmission control regulator 1658 may output an output voltage VNTG2.

[0317] On the other hand, Fig.16 , it is shown that the first transmission voltage VNTG1 to be applied to the transmission signal generating module 1653 is generated by the first transmission control regulator 1657, and the second transmission voltage VNTG2 is generated by the second transmission control regulator 1658; however, the present disclosure is not limited to this, and the first transmission voltage VNTG1 and the second transmission voltage VNTG2 can be generated by one regulator.

[0318] Fig.17 It shows that according to Fig.16 A timing diagram of the operation of the image sensor. Fig.18 It shows that according to Fig.17A diagram of the image sensor circuit during operation of the image sensor.

[0319] When the reset control signal RG3 has the first reset control level RG31 or the second reset control level RG32, the reset transistor RX3 may be turned on, and when the reset control signal RG3 has the third reset control level RG33, the reset transistor RX3 may be turned off. In addition, when the transmission control signal LTX3 has the first transmission control level LTX31 or the second transmission control level LTX32, the transmission transistor LTX3 may be turned on.

[0320] The output voltage Vout may be a voltage at a first node N31 coupled to the gate of the driving transistor SF. A pixel voltage corresponding to the output voltage Vout may be transmitted to a readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0321] First, in the first period P4001 , the reset control signal RG3 may have the first reset control level RG31 , and the transmission control signal LTX3 may have the first transmission control level LTX31 .

[0322] Refer to Fig.18 , in the first period P4001, the first portion 1601 may have Fig.18 The structure shown in (a).

[0323] The reset transistor RX3 can be turned on by the first reset control level RG31, and the transfer transistor LTX3 can be turned on by the first transfer control level LTX31. Since the threshold voltage of the reset transistor RX3 is lower than the first reset control level RG31, the reset transistor RX3 can be fully turned on. Therefore, the first node N31 can have the pixel power supply voltage VPIX. In other words, the first node N31 and the second node N32 can be reset by the reset voltage, thereby removing the charges stored in the first node N31 and the second node N32.

[0324] In the first period P4001, the output voltage Vout may have a first voltage value OUT11. In this case, the first voltage value OUT11 may be based on the pixel power supply voltage VPIX.

[0325] The first pixel voltage based on the first voltage value OUT11 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0326] In the second period P4003 , the reset control signal RG3 may have the third reset control level RG33 , and after a predetermined time from when the reset control signal RG3 transitions to the third reset control level RG33 , the transmission control signal LTX3 may have the second transmission control level LTX32 .

[0327] Reference Fig.18 , in the second period P4003, the first portion 1601 may have Fig.18 The structure shown in (b).

[0328] The reset transistor RX3 may be turned off by the third reset control level RG33. Since the reset transistor RX3 is turned on before the reset transistor RX3 is turned off, the first node N31 may have the pixel power supply voltage VPIX. Therefore, when the reset transistor RX3 is turned off, the voltage of the first node N31 may be reduced due to the coupling phenomenon. In this case, the output voltage Vout may have a second voltage value OUT32.

[0329] Thereafter, the reset control signal RG3 and the transmission control signal LTX3 may be sequentially controlled so that the transmission control signal has the second transmission control level LTX32 after a predetermined time from when the reset control signal is turned to the third reset control level RG33. Since the transmission transistor LTX3 is turned off in a state where the reset transistor RX3 is turned off, the first node N31 may have a lower voltage by coupling while being less affected by the pixel power supply voltage VPIX. In this case, the output voltage Vout may have a third voltage value OUT33.

[0330] The second pixel voltage based on the third voltage value OUT33 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0331] In the third period P4005 , the reset control signal RG3 may increase from the third reset control level RG33 to the second reset control level RG32 , and the transmission control signal LTX3 may have the second transmission control level LTX32 .

[0332] Reference Fig.18 , in the third period P4005, the first portion 1601 may have Fig.18 The structure shown in (c).

[0333] The reset transistor RX3 may be turned on by the second reset control level RG32 , and the transmission transistor LTX3 may be turned off by the second transmission control level LTX32 .

[0334] Since the reset transistor RX3 turned off by the third reset control level RG33 is turned on by the second reset control level RG32, the voltage applied to the first node N31 can be increased. In this case, the reset transistor RX3 can be located in the triode region. On the other hand, when the voltage of the first node N31 as the source side of the reset transistor RX3 is set to a low voltage and the gate voltage of the reset transistor RX3 is raised to the second reset control level RG32, the voltage of the first node N31 as the source side of the reset transistor RX3 can be raised to a value obtained by subtracting the threshold voltage from the second reset control level RG32 as the gate voltage of the reset transistor RX3.

[0335] Therefore, the output voltage Vout may increase from the third voltage value OUT33 to the second voltage value OUT32. Since the reset transistor RX3 is located in the triode region, the second voltage value OUT32 may be based on a value obtained by subtracting a threshold voltage of the reset transistor RX3 from the second reset control level RG32.

[0336] The third pixel voltage based on the value obtained by subtracting the threshold voltage of the reset transistor RX3 from the second reset control level RG32 can be transmitted to the readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0337] On the other hand, in the third period P4005, the readout circuit can sample and process the third pixel voltage corresponding to the second voltage value OUT32. However, since the reset transistor RX3 is turned on, the second voltage value OUT32 may be affected by the pixel power supply voltage VPIX when the image sensor operates under high temperature conditions.

[0338] In the fourth period P4007 , the reset control signal RG3 may have the third reset control level RG33 , and the transmission control signal LTX3 may have the second transmission control level LTX32 .

[0339] Reference Fig.18 , in the fourth period P4007, the first portion 1601 may have Fig.18 The structure shown in (d).

[0340] The reset transistor RX3 can be turned off by the third reset control level RG33, and the transfer transistor LTX3 can be turned off by the second transfer control level LTX32. By turning off the reset transistor RX3, the second voltage value OUT32 can be further less likely to be affected by the pixel power supply voltage VPIX. Therefore, the readout circuit ( Figure 2The reference numeral “260” in the figure can more accurately sample and process the third pixel voltage corresponding to the second voltage value OUT32.

[0341] Readout circuit ( Figure 2 The first pixel voltage may be sampled in the first period P4001 to obtain a first code value corresponding to the first voltage value OUT31 based on the pixel power supply voltage VPIX, and the third pixel voltage may be sampled in the third period P4005 and the fourth period P4007 to obtain a second code value corresponding to the second voltage value OUT32 based on a value obtained by subtracting the threshold voltage of the reset transistor RX3 from the second reset control level RG32. The readout circuit ( Figure 2 The reference numeral "260" in the figure may be sent to the image signal processor ( Figure 2 ” in the figure (reference mark “290”) sends the acquired first code value and the acquired second code value.

[0342] By subtracting the first code value from the acquired second code value, the image signal processor ( Figure 2 The state code can be calculated by the image signal processor ( 290 ) which is a code value related to the threshold voltage of the reset transistor RX3. Figure 2 ' 290 ' in the figure) can calculate not only the state code but also the code related to the offset difference between the pixel power supply voltage VPIX and the second reset control level RG32.

[0343] Fig.19 It shows that according to Fig.16 A timing diagram of the operation of the image sensor. Fig. 20 It shows that according to Fig.19 A diagram of the image sensor circuit during operation of the image sensor.

[0344] When the reset control signal RG3 has the first reset control level RG31 or the second reset control level RG32, the reset transistor RX3 may be turned on, and when the reset control signal RG3 has the third reset control level RG33, the reset transistor RX3 may be turned off. In addition, when the transmission control signal LTX3 has the first transmission control level LTX31 or the second transmission control level LTX32, the transmission transistor LTX3 may be turned on.

[0345] The output voltage Vout may be a voltage at a first node N31 coupled to the gate of the driving transistor SF. A pixel voltage corresponding to the output voltage Vout may be transmitted to a readout circuit ( Figure 2 ” in the figure (see reference numeral “260”).

[0346] exist Fig.19 The operation of the image sensor 1600 in the first period P5001, the second period P5003 and the third period P5005 may be the same as Fig.17 The operations of the image sensor 200 shown in the first period P4001, the second period P4003 and the third period P4005 are similar. Fig. 20 , in the first period P5001, the first portion 1601 may have Fig. 20 The structure shown in (a), and in the second period P5003, the first part 1601 may have Fig. 20 The structure shown in (b) of FIG. 1 , and in the third period P5005, the first portion 1601 may have Fig. 20 The structure shown in (c).

[0347] In this way, in the fourth period P5007, the transmission control signal LTX3 can have a first transmission control level LTX31, and after a predetermined time from when the transmission control signal LTX3 transitions to the first transmission control level LTX31, the reset control signal RG3 can change from the second reset control level RG32 to the first reset control level RG31.

[0348] Reference Fig. 20 , in the fourth period P5007, the first portion 1601 may have Fig. 20 The structure shown in (d).

[0349] The reset transistor RX3 can be turned off by the third reset control level RG33, and the transfer transistor LTX3 can be turned off by the second transfer control level LTX32. By turning off the reset transistor RX3, the second voltage value OUT32 can be further less likely to be affected by the pixel power supply voltage VPIX. Therefore, the readout circuit ( Figure 2 The reference numeral “260” in the figure can more accurately sample and process the third pixel voltage corresponding to the second voltage value OUT32.

[0350] Readout circuit ( Figure 2 The first pixel voltage may be sampled in the first period P5001 to obtain a first code value corresponding to the first voltage value OUT31 based on the pixel power supply voltage VPIX, and the third pixel voltage may be sampled in the third period P5005 and the fourth period P5007 to obtain a second code value corresponding to the second voltage value OUT32 based on a value obtained by subtracting the threshold voltage of the reset transistor RX3 from the second reset control level RG32. The readout circuit ( Figure 2 The reference numeral "260" in the figure may be sent to the image signal processor ( Figure 2 ” in the figure (reference mark “290”) sends the acquired first code value and the acquired second code value.

[0351] By subtracting the first code value from the acquired second code value, the image signal processor ( Figure 2 The state code can be calculated by the image signal processor ( 290 ) which is a code value related to the threshold voltage of the reset transistor RX3. Figure 2 ' 290 ' in the figure) can calculate not only the state code but also the code related to the offset difference between the pixel power supply voltage VPIX and the second reset control level RG32.

[0352] Fig.21 is a diagram illustrating a state code and a dark current code depending on a temperature value in an image sensor according to an embodiment.

[0353] The first graph 2001 is a graph showing a status code according to a temperature value TEMP acquired by the TMC 295 .

[0354] In some embodiments, the state code measurement module 250 may perform a preset state code measurement operation based on the type of the pixel PX coupled thereto. Thereafter, the image signal processor 290 may calculate a state code associated with each pixel PX based on the state signal received from the data buffer 280, and generate a first curve 2001 based on the temperature value TEMP received from the TMC 295.

[0355] The second curve 2003 is a graph showing the relationship between the TMC ( Figure 2 ” in the figure mark “295”) to obtain the curve of the dark current code of the temperature value TEMP.

[0356] In some embodiments, the state code measurement module 250 may perform a preset dark current measurement operation based on the type of pixel PX coupled thereto. Thereafter, the image signal processor 290 may receive the dark current code from the data buffer 280 and generate a second curve 2003 based on the temperature value TEMP received from the TMC 295 .

[0357] Fig. 22 is a diagram illustrating dark current codes of a light receiving area and a shadow area depending on a state code in an image sensor according to an embodiment.

[0358] The first curve 2005 is a curve showing a dark current code according to a state code of a pixel located in a shaded area 233 .

[0359] The second curve 2007 is a curve showing a dark current code according to a state code of a pixel located in the light receiving area 231 .

[0360] In some embodiments, the image signal processor 290 may obtain a state code according to the temperature value TEMP, and obtain a dark current code according to the temperature value TEMP. Based on them, the image signal processor 290 may calculate the correlation between the state code and the dark current code of the pixel PX.

[0361] Fig.23 is a diagram illustrating a dark current code of a shaded area depending on a state code in an image sensor according to an embodiment.

[0362] The first curve 2008 is a curve showing a dark current code according to a state code of a pixel located in a shaded area 233 .

[0363] Specifically, the first curve 2008 may be a curve showing the correlation between the state code and the dark current code acquired when the state code measurement module 250 performs the state code measurement operation and the dark current measurement operation on the pixels located in the shadow area 233 of the image sensor 200. In some embodiments, the first curve 2008 may be a curve showing the dark current code of the shadow area according to the state code in the image sensor 200 installed in the module or the characteristics of which vary over time.

[0364] The second curve 2009 is a curve showing a dark current code according to the state code of the pixel located in the shaded area 233 .

[0365] The second curve 2009 may be a curve showing the correlation between the state code and the dark current code acquired when the state code measurement module 250 performs the state code measurement operation and the dark current measurement operation on the pixels located in the shadow area 233 of the present image sensor 200. In some embodiments, the second curve 2009 may be a curve showing the dark current code of the shadow area according to the state code in the image sensor 200 in the EDS process step.

[0366] Image signal processor 290 may also calculate correlation between first curve 2008 showing actual characteristics of image sensor 200 and second curve 2009 showing ideal characteristics of image sensor 200. For example, first curve 2008 may be obtained by multiplying second curve 2009 by an arbitrary offset factor.

[0367] Fig.24 is a diagram illustrating dark current codes of a light receiving area and a shadow area depending on a state code in an image sensor according to an embodiment.

[0368] The first curve 2011 is a curve showing a dark current code according to a state code of a pixel located in a shadow area 233 .

[0369] In some embodiments, the first curve 2011 may be Fig.23 A first curve 2008 is shown.

[0370] The second curve 2013 is a curve showing a dark current code according to a state code of a pixel located in the light receiving area 231 .

[0371] In some embodiments, the image signal processor 290 may be configured to Fig. 22 The second curve 2007 shown is multiplied by an arbitrary offset factor to obtain the second curve 2013. Specifically, when the image sensor 200 operates in the image sensing mode, it is difficult to obtain an accurate dark current code for the pixels located in the light receiving area 231. To this end, the image signal processor 290 may use the pixels located in the shadow area 233 to obtain an offset factor indicating the correlation between the curve showing the ideal characteristics of the image sensor 200 and the curve showing the actual characteristics of the image sensor 200. In this case, the offset factor may be a factor reflecting the aging or characteristic change of the image sensor 200 over time.

[0372] Thereafter, for pixels located in the light receiving area 231, the image signal processor 290 may adjust the image sensor 200 by applying an offset factor to a curve (ie, Fig. 22 The second curve 2007 in FIG. 2 is used to obtain a curve reflecting the current characteristics of the image sensor 200.

[0373] Fig.25 is a block diagram showing an electronic device according to an embodiment.

[0374] Reference Fig.25 , the electronic device 30 may include a processor 31, a memory 32, a storage device 33, an image sensor 34, an I / O device 35, and a power supply 36, and the various components may communicate with each other through a bus. Here, the image sensor 34 may be a reference Figures 1 to 20 Even after the image sensor 34 is installed in the electronic device 30, the image sensor 34 can correct the dark shadow or the dark current level difference between the light receiving area and the shadow area according to the temperature of the pixel in the image sensor 34. In addition, the image sensor 34 is capable of correcting the change of the elements in the pixel over time. In addition, the image sensor 34 can correct the dark shadow and the dark current level difference in real time.

[0375] The processor 31 may perform specific calculations or tasks required for the operation of the electronic device 30. The memory 32 and the storage device 33 may store data required for the operation of the electronic device 30. For example, the processor 31 may include a microprocessor, a central processing unit (CPU), an application processor (AP), etc., and the memory 32 may include a volatile memory and / or a non-volatile memory, and the storage device 33 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The I / O device 35 may include input devices such as a keyboard, a keypad, a mouse, etc., and output devices such as a printer and a display. The power supply 36 may provide the operating voltage required for the operation of the electronic device 30.

[0376] Fig.26 is a block diagram showing an electronic device according to an embodiment.

[0377] Reference Fig.26 , the electronic device 40 according to the embodiment includes an image sensor 41, an image signal processor (ISP) 42, an application processor (AP) 43, a display device 44, a working memory 45, a storage device 46, a user interface 47, and a wireless transceiver 48. Here, the image sensor 41 and the image signal processor 42 can be respectively referred to as Figures 1 to 20 An image sensor and an image signal processor are described.

[0378] The image sensor 41 may generate image data (e.g., raw image data) based on the received light signal, and provide the image data to the image signal processor 42. The image signal processor 42 may perform image processing for changing the data format of the image data IDAT which is digital data on an image, image processing for improving image quality (such as noise removal, brightness adjustment, sharpness adjustment, etc.), and the like.

[0379] In some embodiments, image signal processor 42 may correct dark current level differences in the optical signal received from image sensor 41 in real time.

[0380] In the present disclosure, for the sake of convenience, it has been described that the image signal processor 42 is provided separately from the application processor 43; however, the present disclosure is not limited thereto. For example, the image signal processor 42 may not be configured with separate hardware or composed of hardware and software, but may exist as a subcomponent of the application processor 43.

[0381] The application processor 43 may control the overall operation of the electronic device 40 and may be provided in the form of a system on chip (SOC) for driving an application program, an operating system, etc. The application processor 43 may control the operation of the image signal processor 42 and may provide the display device 44 with image data generated and converted in the image signal processor 42 or store the image data in the storage device 46.

[0382] The working memory 45 may store programs and / or data processed or executed by the application processor 43. The storage device 46 may be implemented with a nonvolatile memory device such as a NAND flash memory, a resistive memory, etc., and, for example, the storage device 46 may be provided in the form of a memory card such as an MMC, an eMMC, an SD, or a micro SD, etc. The storage device 46 may store data and / or programs related to an execution algorithm for controlling an image processing operation of the image signal processor 42, and when the image processing operation is performed, the data and / or programs may be loaded into the working memory 45. For example, the working memory 45 or the storage device 46 may include a read-only memory (ROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. as a nonvolatile memory, and may include a static RAM (SRAM) and a dynamic RAM (DRAM) as a volatile memory; however, they are not limited to the examples listed above.

[0383] The user interface 47 may be implemented with various devices capable of receiving user input, such as a keyboard, a curtain key panel, a touch panel, a fingerprint sensor, and a microphone, etc. The user interface 47 may receive the user input and provide a signal corresponding to the received user input to the application processor 43. The wireless transceiver 48 may include a modem 48_1, a transceiver 48_2, and an antenna 48_3.

[0384] Fig. 27 is a block diagram showing a vehicle according to an embodiment.

[0385] like Fig. 27 As shown, the vehicle 50 may include an image sensor 51, a user I / F 52, a LIDAR sensor (light detection and ranging) 53, a RADAR (radio detection and ranging) sensor 54, an NPU (neural processing unit) 55, a CPU 56, and an ECU 57, and the ECU 57 may receive the steering angle of the vehicle and the speed of the vehicle from a steering wheel 58 and an engine 59. In addition, the vehicle 50 may also include a communication module, an input / output module, a security module, a power control device, etc., and may also include various types of control devices.

[0386] Here, the image sensor 51 may be a reference Figures 1 to 20 Description of the image sensor.

[0387] In some embodiments, the vehicle 50 can detect an object using information about the external environment acquired by a sensor (e.g., an image sensor 51, a LIDAR sensor 53, and / or a RADAR sensor 54). The sensors 51, 53, and 54 can capture images of objects, measure distances to the objects, and send them to a processor (e.g., a CPU 56, an NPU 55, and an ECU 57). In order for the sensors 51, 53, and 54 to detect an object, in addition to the above-mentioned sensors, a ToF (time of flight) sensor, an ultrasonic sensor, an infrared sensor, a geomagnetic sensor, a position sensor (e.g., GPS), an acceleration sensor, an air pressure sensor, a temperature / humidity sensor, a proximity sensor, a gyroscope sensor, and the like can be used.

[0388] The image sensor 51 can provide image or optical sensing, and can be, for example, a CMOS (complementary metal oxide semiconductor) image sensor. The image sensor 51 can acquire images or visual information about an object. For example, the image sensor 51 can be attached to the front side of the vehicle to capture driving images or measure the distance to an object located in front of the vehicle, etc. The location where the image sensor 51 is attached is not limited thereto, and the image sensor can be attached at various locations to achieve the intended purpose of obtaining information about an object.

[0389] The image sensor 51 may capture images of the environment around the vehicle 50. The vehicle 50 may include at least two image sensors for capturing images of a complete 360-degree view of the vehicle's surroundings. In an embodiment, the image sensor 51 may include a wide-angle lens. In an embodiment, the vehicle 50 may include four image sensors for the front, rear, left, and right sides of the vehicle; however, the present disclosure is not limited thereto, and a single image sensor 51 may capture images of the environment around the vehicle. The image sensor 51 may continuously capture images of the vehicle's surroundings to continuously provide the vehicle 50 with information about the vehicle's surroundings.

[0390] The image sensed by the image sensor 51 may be processed in the CPU 56 and / or the NPU 55. The CPU 56 may process the sensed image in a motion-based manner to detect an object, and the NPU 55 may process the sensed image in a shape-based manner to detect an object. The image sensor 51 may be attached to the front side of the vehicle to sense the external environment in front of the vehicle; however, it is not limited thereto, and the image sensor 51 may be attached to various surfaces of the vehicle to sense the external environment.

[0391] Here, the image sensor 51 may be a reference Figures 1 to 20The image sensor described above. Even after the image sensor 51 is installed in the vehicle 50, the image sensor 51 can correct the dark shadow or the dark current level difference between the light receiving area and the shadow area according to the temperature of the pixel in the image sensor 34. In addition, the image sensor 51 is capable of correcting the change of the elements in the pixel over time. In addition, the image sensor 51 can correct the dark shadow and the dark current level difference in real time.

[0392] The user I / F 52 may include various electronic devices and mechanical devices included in a driver's seat, a passenger's seat, and the like, such as an instrument panel of the vehicle, a display indicating driving information, a navigation device, an air conditioning system, and the like.

[0393] The LIDAR sensor 53 can measure the distance to the object by emitting a laser pulse and receiving an echo of the laser pulse from the target object. The LIDAR sensor 53 may generally include a laser, a scanner, a receiver, and a positioning system. For the laser, light in the wavelength range of 600nm to 1000nm is generally used, but the wavelength range may be different depending on the purpose of the laser. The scanner can scan the sensed surroundings to quickly acquire information about the surroundings, and there may be several forms of scanners using multiple reflectors. The receiver can receive the laser pulse reflected from the target object, and sense and amplify the photons from the laser pulse. The positioning system can check the position coordinates and direction of the device equipped with the receiver to achieve a three-dimensional image. The LIDAR sensor 53 and the RADAR sensor 54 can be distinguished according to their effective measurement distance.

[0394] The RADAR sensor 54 can transmit electromagnetic waves and receive echoes of the electromagnetic waves from a target object to measure the distance to the object or identify the object, or measure the position and moving speed of the object, etc. The RADAR sensor 54 may include a transmitter and a receiver. The transmitter can generate and output electromagnetic waves, and the receiver can receive echoes from the target object and process the signal. The RADAR sensor 54 can perform transmission and reception through one antenna, but is not limited to this. The electromagnetic wave frequency band used in the RADAR sensor 54 can be a radio wave band or a microwave band, but can be changed depending on its purpose. In an embodiment, the LIDAR sensor 53 and the RADAR sensor 54 can be attached to the vehicle to help determine the relative position relationship between the vehicle and the object of interest. The RADAR sensor 54 can be classified as a long RADAR sensor or a short RADAR sensor.

[0395] The NPU 55 may receive input data and perform calculations using an artificial neural network and provide output data based on the calculation results. The NPU 55 may be a processor optimized for simultaneous matrix operations and capable of processing multiple calculations in real time and deriving optimal values ​​through self-learning based on accumulated data. The NPU 55 may be optimized for simultaneous matrix operations to be able to process multiple calculations in real time and derive the local maximum at the current drive parameter through self-learning based on accumulated data.

[0396] In an embodiment, the NPU 55 may be a dedicated processor that executes deep learning type algorithms. For example, the NPU 55 is capable of performing arithmetic processing based on various types of networks such as CNN (convolutional neural network), R-CNN (region with convolutional neural network), RPN (region proposal network), RNN (recursive neural network), full convolution network, LSTM (long short-term memory) network, classification network, etc. However, the NPU is not limited thereto and is capable of performing various arithmetic processing that simulates human neural networks.

[0397] The NPU 55 may receive a driving image from the image sensor 51 and perform shape-based object detection based on the driving image. The NPU 55 may recognize each of a plurality of objects in the driving image by extracting features of the plurality of objects and performing self-learning based on accumulated data. For example, the NPU 55 may extract objects serving as driving criteria such as vehicles, pedestrians, traffic lights, lanes, etc., even from a single driving image based on features determined using accumulated data as learning materials.

[0398] The CPU 56 controls the overall operation of the vehicle 50. The CPU 56 may include a single processor core, or may include a plurality of processor cores. The CPU 56 may process or execute programs and / or data stored in the memory. For example, the CPU 56 may control the functions of the NPU 55 and the ECU 57 by executing programs stored in the memory.

[0399] The CPU 56 may acquire the steering angle and the vehicle speed from the ECU 57. The steering angle may be determined by the driver's operation of the steering wheel 58, and is processed by the ECU 57 that controls the operation of the steering control unit, and is provided to the CPU 56. The vehicle speed may be measured based on at least one of the driver's stepping (e.g., operation of the accelerator), the rotation speed of the engine 59, and the wheel speed measured by the wheel sensor, and may be processed in the ECU 57 that controls the vehicle speed, and is provided to the CPU 56.

[0400] In addition, the CPU 56 can determine the relative positional relationship between the vehicle and surrounding vehicles, and can issue a command to maintain the number of revolutions of the engine 59 for cruising to keep a certain distance from surrounding vehicles according to a predetermined driving plan, and when the vehicle is below a threshold distance from surrounding vehicles, or when surrounding vehicles cut in, can issue a command to adjust the steering wheel 58 to the left or right to change the steering angle to perform an evasive maneuver. Fig. 27 , a steering wheel 58 and an engine 59 are illustrated as components related to a steering angle and a vehicle speed; however, the present disclosure is not limited thereto, and the steering angle and the vehicle speed may be determined by various vehicle components.

[0401] The CPU 56 may perform object detection on the driving image in a motion-based manner. The motion-based manner is a method of detecting the degree of motion of an object over time to determine its relative motion. The driving image may be continuously acquired in frames by the image sensor 51. For example, each frame may be acquired at a rate of 60fps (frames per second). In this case, the CPU 56 may detect the motion over time between the image frames acquired every 1 / 60 second. In the motion-based manner, optical flow and the like may be included, and optical flow refers to the distribution of the motion vector of an object.

[0402] The CPU 56 may auxiliary use the distance to the object acquired from the LIDAR sensor 53 and the RADAR sensor 54 in addition to the image sensor 51 to maintain a stable driving state of the vehicle. In addition, the CPU 56 may issue a command in response to the driver's operation of the user I / F 52 to adjust the conditions inside and outside the vehicle.

[0403] The ECU 57 may be an electronic control unit configured to control the overall operation or a portion of the operation of the vehicle. The ECU 57 may control the operation of the vehicle according to vehicle parameters based on the operation of the internal combustion engine, the operation of one or more electric motors, the operation of a semi-automatic gearbox (SAGB) or an automatic gearbox (AGB), and the control of other drives via a CAN (Controller Area Network) multiplexed bus.

[0404] ECU 57 can electronically control the vehicle's engine, actuators of the steering control device, gear shift control system, anti-lock braking system, airbag control system, etc. through a computer, and can provide the vehicle 50 with the vehicle speed based on the engine speed or the wheel speed measured by the wheel sensor, and can provide the vehicle 50 with the vehicle's steering angle from the steering control device.

[0405] In an embodiment, the ECU 57 may control the state of the steering wheel 58 and the engine 59 in response to commands issued by the CPU 56 and the NPU 55. In an embodiment, the ECU 57 may accelerate or decelerate the vehicle in response to commands issued by the CPU 56 and the NPU 55, and may provide a signal to the engine 59 to increase or decrease the engine speed for acceleration or deceleration. In addition, when the distance to the surrounding vehicles is below a threshold distance, or when the surrounding vehicles cut in, the ECU 57 may adjust the steering wheel 58 to the left or right to perform an evasive maneuver according to a predetermined driving plan.

[0406] According to an embodiment of the present disclosure, the CPU 56 or the ECU 57 may check for defects in the ramp signal RML to turn off the automatic driving mode of the vehicle 50. For example, the CPU 56 or the ECU 57 may detect defects in the ramp signal RML based on the image sensor 51 when the vehicle is traveling in the automatic driving mode, and the driver immediately changes the driving mode from the automatic driving mode to the manual driving mode, thereby ensuring the safety of the user. For example, the vehicle 50 may detect defects in the ramp signal RML and stop the driving assist function based on the ramp signal RML, thereby ensuring the safety of the driver or the user.

[0407] In the drawings, it is shown that the ECU 57 is provided in the vehicle separately from the CPU 56; however, the present disclosure is not limited thereto, and the vehicle control function of the ECU 57 may be assigned to the CPU 56 and executed in the CPU, and in this case, the CPU 56 may be understood to have at least two processor cores. Fig. 27 , it is shown that the ECU 57 is a component separate from the CPU 56 ; however, it is not limited thereto, and the ECU 57 may be included in the CPU 56 .

[0408] The vehicle 50 may also include a communication module. The communication module may send data to the outside of the vehicle 50 and receive data from the outside of the vehicle 50. For example, the communication module may perform communication with an object outside the vehicle 50. In this case, the communication module may perform communication in a V2X (vehicle to everything) manner. For example, the communication module may perform communication in a V2V (vehicle to vehicle) manner, a V2I (vehicle to infrastructure) manner, a V2P (vehicle to pedestrian) manner, and a V2N (vehicle to mobile device) manner. However, the communication module is not limited thereto, and data may be sent and received in various known communication modes. For example, the communication module may perform communication by, for example, 3G, 4G (LTE), 5G, Wi-Fi, BLE (low energy Bluetooth), Zigbee, NFC (near field communication), and ultrasonic communication methods, and may perform both short-range communication and long-range communication.

[0409] While certain example embodiments have been particularly shown and described herein, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: a pixel array including a plurality of first pixels configured to receive light and output a plurality of first pixel signals; a row driver coupled to the plurality of first pixels and configured to apply a preset voltage to the plurality of first pixels; as well as An image signal processor configured to: obtaining first state codes, each first state code being associated with one of the plurality of first pixels, based on a plurality of second pixel signals received from the plurality of first pixels based on the preset voltage applied to the plurality of first pixels; as well as The plurality of first pixel signals are processed based on the first state code.

2. The image sensor according to claim 1, wherein: The plurality of first pixels include at least one first temperature monitoring pixel, and Wherein, the image sensor is configured as: measuring a first dark current code of the plurality of first pixels based on the plurality of second pixel signals; and A first compensation table is generated based on a first temperature state code associated with the at least one first temperature monitoring pixel and a corresponding first dark current code corresponding to the first temperature state code, the first compensation table including first information about at least one of the first temperature state code, the corresponding first dark current code, the first state code, and the first dark current code.

3. The image sensor according to claim 2, wherein: The image sensor is configured to: when operating in an image sensing mode, generate first image data based on the plurality of first pixel signals, and Wherein, the image signal processor is configured as: determining a first dark current code corresponding to the first state code based on the first compensation table; and The first image data is compensated based on the first dark current code.

4. The image sensor according to claim 3, wherein: The image signal processor is configured to compensate the first image data during a vertical blanking period based on the pixel array not outputting the plurality of first pixel signals.

5. The image sensor according to claim 2, wherein: The pixel array further includes a plurality of second pixels located in the light shielding area. Wherein, the plurality of second pixels include at least one second temperature monitoring pixel, Wherein, the image signal processor is configured to perform: obtaining second state codes, each second state code being associated with one of the plurality of second pixels, according to third pixel signals received from the plurality of second pixels based on the preset voltage applied to the plurality of second pixels, measuring a second dark current code associated with the plurality of second pixels based on the third pixel signal, and A second compensation table is generated based on at least one of the second state codes of the at least one second temperature monitoring pixel and a second dark current code of the at least one second temperature monitoring pixel, the second compensation table including second information about the second state code and the second dark current code corresponding to the second state code.

6. The image sensor according to claim 5, wherein: The image sensor is configured to: when operating in an image sensing mode, generate first image data based on the plurality of first pixel signals, and Wherein, the image signal processor is configured as: Based on a difference between the second dark current code and the first dark current code in the first compensation table, the first dark current code in the first compensation table is updated with the second dark current code.

7. The image sensor according to claim 6, wherein: The image signal processor is configured to update the second compensation table during a vertical blanking period based on the pixel array not outputting the plurality of first pixel signals.

8. The image sensor according to claim 2, further comprising: The temperature monitoring circuit is located below the pixel array and is configured to measure a temperature value of the at least one first temperature monitoring pixel and send the temperature value to the image signal processor.

9. The image sensor according to claim 2, wherein: The plurality of first pixels are divided into a plurality of pixel groups, and each of the plurality of pixel groups includes at least one first pixel, The image signal processor is configured to measure a third dark current code associated with the representative pixel based on the plurality of second pixel signals received from the representative pixel in each of the plurality of pixel groups, and generate a third compensation table based on at least one of the temperature value of the representative pixel, the third state code of the representative pixel and the third dark current code, wherein the third compensation table contains third information about the third state code and the third dark current code corresponding to the third state code, and Wherein, the image sensor is configured as: generating second image data based on the plurality of first pixel signals when operating in an image sensing mode, obtaining a third state code associated with the at least one first pixel of each pixel group in the plurality of pixel groups, and A third dark current code associated with each of the plurality of first pixels is determined based on the third compensation table, and the second image data is compensated based on the third dark current code.

10. The image sensor according to claim 1, wherein: The plurality of first pixels include: a reset transistor coupled between a first node and a voltage line and configured to supply a reset voltage and be controlled by a reset control signal; a gain control transistor coupled between the first node and a second node and configured to be controlled by a gain control signal; and a drive transistor configured to transmit a pixel voltage corresponding to a voltage of the second node as the plurality of second pixel signals to the image signal processor, and The row driver includes: a reset voltage generating module configured to generate the reset voltage; and a gain control signal generating module configured to generate the gain control signal.

11. The image sensor according to claim 10, wherein: Based on the reset voltage being the first voltage, the reset control signal having the first reset control level, and the gain control signal having the first gain control level, the second node has a first voltage value, wherein, based on the reset voltage being a second voltage lower than the first voltage, the reset control signal having the first reset control level, and the gain control signal having a second gain control level lower than the first gain control level, the second node has a second voltage value, wherein, based on the reset voltage being a third voltage higher than the first voltage, the reset control signal having the first reset control level, and the gain control signal having the second gain control level, the second node has a third voltage value, and The image signal processor is configured to obtain the first state code based on a first pixel voltage corresponding to the first voltage value and a third pixel voltage corresponding to the third voltage value.

12. The image sensor according to claim 11, wherein: The second node has a fourth voltage value based on the reset voltage being a third voltage higher than the first voltage, the reset control signal having a second reset control level lower than the first reset control level, and the gain control signal having the second gain control level, and The image signal processor is configured to obtain the first state code based on a first pixel voltage corresponding to the first voltage value and a fourth pixel voltage corresponding to the fourth voltage value.

13. The image sensor according to claim 10, wherein: Based on the reset voltage being the first voltage, the reset control signal having the first reset control level, and the gain control signal having the first gain control level, the second node has a first voltage value, wherein, based on the reset voltage being a second voltage higher than the first voltage, the reset control signal having the first reset control level, and the gain control signal having the first gain control level, the second node has a second voltage value, wherein, based on the reset voltage being the second voltage, the reset control signal having a second reset control level lower than the first reset control level, and the gain control signal having the first gain control level, the second node has a third voltage value, wherein, based on the reset voltage being the first voltage, the reset control signal having the first reset control level, and the gain control signal having the first gain control level, the second node has a fourth voltage value, and The image signal processor is configured to obtain the first state code based on a third pixel voltage corresponding to the third voltage value and a fourth pixel voltage corresponding to the fourth voltage value.

14. The image sensor according to claim 13, wherein: Based on the reset voltage being the first voltage, the reset control signal having the second reset control level, and the gain control signal having the first gain control level, the second node has a fifth voltage value, and The image signal processor is configured to obtain the first state code based on a third pixel voltage corresponding to the third voltage value and a fifth pixel voltage corresponding to the fifth voltage value.

15. The image sensor according to claim 1, wherein: The plurality of first pixels include: a reset transistor coupled between a pixel power supply voltage line and a first node and configured to be controlled by a reset control signal; a gain control transistor coupled between the first node and a second node and configured to be controlled by a gain control signal; and a drive transistor configured to transmit a pixel voltage corresponding to a voltage of the second node as the plurality of second pixel signals to the image signal processor, and The row driver comprises a gain control signal generating module, and the gain control signal generating module is configured to generate the gain control signal.

16. The image sensor according to claim 15, wherein: Based on the reset control signal having a first reset control level and the gain control signal having a first gain control level, the second node has a first voltage value, wherein, based on the reset control signal having a second reset control level lower than the first reset control level, and the gain control signal having a second gain control level lower than the first gain control level, the second node has a second voltage value, wherein, based on the reset control signal having the first reset control level and the gain control signal having a third gain control level lower than the first gain control level and higher than the second gain control level, the second node has a third voltage value, and The image signal processor is configured to obtain the first state code based on a first pixel voltage corresponding to the first voltage value and a third pixel voltage corresponding to the third voltage value.

17. The image sensor according to claim 1, wherein: The plurality of first pixels include: a reset transistor coupled between a pixel power supply voltage line and a first node and configured to be controlled by a reset control signal; a transfer transistor coupled between the first node and an optoelectronic element and configured to be controlled by a transfer signal; and a drive transistor configured to transfer a pixel voltage corresponding to a voltage of the first node as the plurality of second pixel signals to the image signal processor, and The row driver includes: a reset signal generating module configured to generate the reset control signal; and a transmission signal generating module configured to generate the transmission signal.

18. The image sensor according to claim 17, wherein: Based on the reset control signal having a first reset control level and the transmission signal having a first transmission control level, the first node has a first voltage value, wherein, based on the reset control signal having a second reset control level lower than the first reset control level, and the transmission signal having a second transmission control level lower than the first transmission control level, the first node has a second voltage value, wherein, based on the reset control signal having a third reset control level lower than the first reset control level and higher than the second reset control level, and the transmission signal having the second transmission control level, the first node has a third voltage value, and The image signal processor is configured to obtain the first state code based on a first pixel voltage corresponding to the first voltage value and a third pixel voltage corresponding to the third voltage value.

19. A method for operating an image sensor, comprising: performing a first state code measuring operation by receiving light and applying a preset voltage to a plurality of first pixels to output a plurality of first pixel signals; performing a first state code obtaining operation by obtaining first state codes according to a plurality of second pixel signals received from the plurality of first pixels based on a preset voltage applied to the plurality of first pixels, wherein each first state code is associated with one of the plurality of first pixels; performing a dark current code measurement operation on the plurality of first pixels based on the plurality of second pixel signals; and A first compensation table is generated based on the first state code and a first dark current code, the first compensation table containing first information about the first state code and a first dark current code corresponding to the first state code.

20. The method for operating the image sensor according to claim 19, further comprising: When first image data is generated based on the plurality of first pixel signals, the first state code obtaining operation is performed, and the first dark current code is determined based on the first compensation table, and the first image data is compensated based on the first dark current code.

Images