Pixel driving circuit, driving method thereof and display panel

Abstract

The invention discloses a pixel driving circuit, a driving method thereof and a display panel. The pixel driving circuit comprises a first reset module (110), a driving module (130), a coupling module (200) and a first switch module (190), the first reset module (110) is connected with a first node, a first initialization signal end and a reset signal end, and the first reset module (110) is used for writing a first initialization signal into the first node in response to a signal of the reset signal end; the driving module (130) is connected with the first node, the second node and the third node, and the driving module (130) is used for providing a driving current for the third node under the action of a voltage difference between the first node and the second node; the coupling module (200) is connected with a first node and a preset node, and the coupling module (200) is used for coupling the voltage variation of the first node to the preset node and coupling the voltage variation of the preset node to the first node; the first switch module (190) is connected with a constant voltage end, a preset node and a switch signal end, and the first switch module (190) is used for responding to signal conduction of the switch signal end so as to utilize the constant voltage end to stabilize the voltage of the preset node or responding to signal turn-off of the switch signal end so as to control the preset node to float. The pixel driving circuit can reset the first node in the holding frame so that the potential of the first node is the same as the potential before resetting, thereby eliminating or weakening the problem of non-uniform brightness caused by the working state difference of the driving module (130) in the refresh frame and the holding frame, and improving the flicker problem of the display panel under low-frequency driving.

Description

Pixel driving circuit and driving method thereof, and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] In display technology, low frequencies help reduce system power consumption and improve display battery life. However, low frequencies are more prone to flickering.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a pixel driving circuit and a driving method thereof, and a display panel.

[0006] According to one aspect of the present disclosure, a pixel driving circuit is provided, including: a first reset module, connected to a first node, a first initialization signal terminal and a reset signal terminal, the first reset module being used to write the first initialization signal to the first node in response to a signal from the reset signal terminal; a driving module, connected to the first node, a second node and a third node, the driving module providing a driving current to the third node based on the voltages of the first node and the second node; a coupling module, connected to the first node and a preset node, the coupling module being used to couple a voltage change of the first node to the preset node and to couple a voltage change of the preset node to the first node; a first switching module, connected to a constant voltage terminal, the preset node and a switching signal terminal, the first switching module being used to turn on in response to a signal from the switching signal terminal to stabilize the preset node using the constant voltage terminal or to turn off in response to a signal from the switching signal terminal to control the preset node to float.

[0007] In an exemplary embodiment of the present disclosure, the constant voltage terminal is a first power supply terminal; the pixel driving circuit also includes: a first transmission module, connecting the first node, the third node and the gate signal terminal, and the first transmission module is used to respond to the signal of the gate signal terminal to turn on or off the connection between the first node and the third node.

[0008] In an exemplary embodiment of the present disclosure, the reset signal terminal includes a first reset signal terminal, and the first reset module is connected to the first reset signal terminal; the gate signal terminal includes a first gate signal terminal, and the first transmission module is connected to the first gate signal terminal; wherein, the conduction level of the first reset module and the first transmission module is opposite to the conduction level polarity of the driving module.

[0009] In an exemplary embodiment of the present disclosure, the first reset module includes: a first transistor, a first electrode connected to the first initialization signal terminal, a second electrode connected to the first node, and a gate connected to the first reset signal terminal, the first transistor being used to transmit the signal of the first initialization signal terminal to the first node in response to the signal of the first reset signal terminal; the first transmission module includes: a second transistor, a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the first gate signal terminal, the second transistor being used to connect the third node to the first node in response to the signal of the first gate signal terminal; the driving module includes: a driving transistor, a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the first node, the driving transistor providing a driving current to the third node based on the voltage between the first node and the second node; wherein the first transistor and the second transistor are both N-type transistors, and the driving transistor is a P-type transistor.

[0010] In an exemplary embodiment of the present disclosure, the reset signal terminal includes a second reset signal terminal, and the first reset module is connected to the second reset signal terminal; the gate signal terminal includes a first gate signal terminal and a second gate signal terminal, and the first transmission module is connected to the second gate signal terminal; the pixel driving circuit also includes: a second switch module, which is connected in series between the first node and the first reset module and connected to the first gate signal terminal, and the second switch module is at least used to respond to the signal of the first gate signal terminal to connect the first reset signal module to the first node to transmit the signal of the first initialization signal terminal to the first node; wherein, the on-levels of the first reset module and the first transmission module are the same as the on-level polarity of the driving module, and the on-level of the second switch module is opposite to the on-level polarity of the driving module.

[0011] In an exemplary embodiment of the present disclosure, the first reset module includes: a first transistor, having a first electrode connected to the first initialization signal terminal, a second electrode connected to the fourth node, and a gate connected to the first reset signal terminal, the first transistor being configured to transmit a signal from the first initialization signal terminal to the fourth node in response to a signal from the first reset signal terminal; the first transmission module includes: a second transistor, having a first electrode connected to the fourth node, a second electrode connected to the third node, and a gate connected to the first gate signal terminal, the second transistor being configured to conduct a connection between the third node and the fourth node in response to a signal from the first gate signal terminal; the second switch module includes: a tenth transistor, having a first electrode connected to the first node, a second electrode connected to the fourth node, and a gate connected to the first gate signal terminal, the tenth transistor being configured to conduct or disconnect the connection between the first node and the fourth node in response to a signal from the first gate signal terminal; the driving module includes: a driving transistor, having a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the first node, the driving transistor providing a driving current to the third node based on a voltage between the first node and the second node; wherein the first transistor, the second transistor, and the driving transistor are all P-type transistors, and the tenth transistor is an N-type transistor.

[0012] In an exemplary embodiment of the present disclosure, the constant voltage terminal is a first power supply terminal; the pixel driving circuit also includes: a first transmission module, which is connected in series between the first node and the first reset module and connected to the first gate signal terminal, the first transmission module and the first reset module are connected to a third node, and the first transmission module is at least used to respond to the signal of the first gate signal terminal to turn on the connection between the first reset module and the third node to transmit the signal of the first initialization signal terminal to the first node; wherein the reset signal terminal includes a second reset signal terminal, and the first reset circuit is connected to the second reset signal terminal; the conduction level of the first reset module is the same as the conduction level polarity of the driving module, and the conduction level polarity of the first transmission module is opposite to that of the driving module.

[0013] In an exemplary embodiment of the present disclosure, the first reset module includes: a first transistor, a first electrode connected to the first initialization signal terminal, a second electrode connected to the third node, and a gate connected to the first reset signal terminal, the first transistor being used to transmit the signal of the first initialization signal terminal to the third node in response to the signal of the first reset signal terminal; the first transmission module includes: a second transistor, a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the first gate signal terminal, the second transistor being used to connect the third node to the first node in response to the signal of the first gate signal terminal; the driving module includes: a driving transistor, a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the first node, the driving transistor providing a driving current to the third node based on the voltage between the first node and the second node; wherein, the first transistor and the driving transistor are both P-type transistors, and the second transistor is an N-type transistor.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a second reset module connected to the second node, a third initialization signal terminal and a scan signal terminal, the second reset module being configured to write the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal; a data write module connected to the second node, the data signal terminal and the second gate signal terminal, the data write module being configured to transmit the signal of the data signal terminal to the second node in response to the signal of the second gate signal terminal; a first light-emitting control module connected to the second node, the first power supply terminal and the enable signal terminal, the first light-emitting control module being configured to transmit the voltage signal of the first power supply terminal to the second node in response to the signal of the enable signal terminal; a second light-emitting control module connected to the third node, the anode of the light-emitting device and the enable signal terminal, the second light-emitting control module being configured to transmit the current signal of the third node to the anode of the light-emitting device in response to the signal of the enable signal terminal; and a third reset module connected to the anode of the light-emitting device, the second initialization signal terminal and the scan signal terminal, the third reset module being configured to transmit the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the scan signal terminal to reset the anode of the light-emitting device.

[0015] The second reset module includes: an eighth transistor, a first electrode connected to the third initialization signal terminal, a second electrode connected to the second node, and a gate connected to the scan signal terminal, the eighth transistor being used to transmit the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal to reset the second node; the data write module includes: a fourth transistor, a first electrode connected to the data signal terminal, a second electrode connected to the second node, and a gate connected to the second gate signal terminal, the fourth transistor being used to transmit the signal of the data signal terminal to the second node in response to the signal of the second gate signal terminal; the switch signal terminal includes a first switch signal terminal; the first light control module includes: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the enable signal terminal, the fifth transistor being used to transmit the voltage signal of the first power supply terminal to the second node in response to the signal of the enable signal terminal; the second light control module includes: a sixth transistor, having a first electrode connected to the third node, a second electrode connected to the anode of the light-emitting device, and a gate connected to the enable signal terminal, the sixth transistor being configured to transmit the current signal of the third node to the anode of the light-emitting device in response to the signal of the enable signal terminal; the third reset module comprising: a seventh transistor, having a first electrode connected to the second initialization signal terminal, a second electrode connected to the anode of the light-emitting device, and a gate connected to the scan signal terminal, the seventh transistor being configured to transmit the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the scan signal terminal to reset the anode of the light-emitting device; the first switch module comprising: a first switch transistor, having a first electrode connected to the preset node, a second electrode connected to the first power supply terminal, and a gate connected to the first switch signal terminal, the first switch transistor being configured to be turned on in response to the signal of the first switch signal terminal to stabilize the preset boundary using the voltage signal of the first power supply terminal, or to be turned off in response to the signal of the first switch signal terminal to control the preset node to float; the coupling module comprising: a storage capacitor, having a first electrode connected to the first node, and a second electrode connected to the preset node; wherein the first switch transistor and the fourth to eighth transistors are all P-type transistors.

[0016] In an exemplary embodiment of the present disclosure, the constant voltage terminal is a first power supply terminal; the pixel driving circuit further includes a first transmission module and a data writing module; the gate signal terminal includes a first gate signal terminal and a second gate signal terminal; the first transmission module is connected to the first node, the third node, and the first gate signal terminal, and is configured to connect or disconnect the first node and the third node in response to a signal from the first gate signal terminal; the data writing module is connected to the second node, the data signal terminal, and the second gate signal terminal, and is configured to transmit a signal from the data signal terminal to the second node in response to a signal from the second gate signal terminal; or the data writing module is connected to the preset node, the data signal terminal, and the second gate signal terminal, and is configured to transmit a signal from the data signal terminal to the preset node in response to a signal from the second gate signal terminal; wherein the conduction level of the first transmission module has a polarity opposite to that of the conduction level of the data writing module; the conduction level output by the second gate signal terminal overlaps with the conduction level output by the first gate signal terminal, and the duration covered by the conduction level output by the second gate signal terminal is within the duration covered by the conduction level output by the first gate signal terminal.

[0017] In an exemplary embodiment of the present disclosure, when the non-conduction level output by the switching signal terminal overlaps with the conduction level output by the reset signal terminal, the duration covered by the conduction level output by the reset signal terminal is within the duration covered by the non-conduction level output by the switching signal terminal.

[0018] In an exemplary embodiment of the present disclosure, the constant voltage terminal is a reference voltage terminal, and the second node is further connected to a first power supply terminal.

[0019] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a second reset module, connected between the second node and the third initialization signal terminal and connected to the scan signal terminal, the second reset module being used to transmit the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal to reset the second node; a first light-emitting control module, connected between the second node and the first power supply terminal and connected to the first enable signal terminal, the first light-emitting control module being used to transmit the voltage signal of the first power supply terminal to the second node in response to the signal of the first enable signal terminal.

[0020] In an exemplary embodiment of the present disclosure, the switch signal terminal includes a second switch signal terminal, and the second switch signal terminal multiplexes the enable signal terminal; the first switch module includes: a first sub-switch module, connected to the reference voltage terminal, the preset node and the enable signal terminal, and the first sub-switch module is at least used to respond to the signal of the enable signal terminal to be turned on to use the voltage signal of the reference voltage terminal to stabilize the preset node or to respond to the signal of the enable signal terminal to be turned off to control the preset node to float.

[0021] In an exemplary embodiment of the present disclosure, the reset signal terminal includes a second reset signal terminal, the switch signal terminal also includes a first switch signal terminal, and the first switch signal terminal multiplexes the second reset signal terminal; the enable signal terminal includes a first enable signal terminal and a second enable signal terminal, the second switch signal terminal multiplexes the second enable signal terminal, and the first sub-switch module is connected to the second enable signal terminal; the first switch module also includes: a second sub-switch module, connected to the reference voltage terminal, the preset node and the second reset signal terminal, the second sub-switch module is used to transmit the voltage signal of the reference voltage terminal to the preset node in response to the signal of the second reset signal terminal; wherein, the conduction level stage of the second reset signal terminal does not overlap with the conduction level stage of the second enable signal terminal.

[0022] In an exemplary embodiment of the present disclosure, a first transmission module is connected to the first node, the third node and the first gate signal terminal, and the first transmission module is used to turn on or off the connection between the first node and the third node in response to a signal from the first gate signal terminal; wherein the conduction level of the first transmission module and the first reset module has an opposite polarity to the conduction level of the driving module.

[0023] In an exemplary embodiment of the present disclosure, the reset signal end also includes a first reset signal end; the first reset module includes: a first transistor, a first electrode connected to the first initialization signal end, a second electrode connected to the first node, and a gate connected to the first reset signal end, and the first transistor is used to respond to the signal of the first reset signal end and transmit the signal of the first initialization signal end to the first node; the first transmission module includes: a second transistor, a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the first gate signal end, and the second transistor is used to respond to the signal of the first gate signal end to connect the third node with the first node; the driving module includes: a driving transistor, a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the first node, and the driving transistor provides a driving current to the third node based on the voltage between the first node and the second node; wherein, the first transistor and the second transistor are both N-type transistors, and the driving transistor is a P-type transistor.

[0024] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a data writing module, connected to the preset node, the data signal terminal and the second gate signal terminal, the data writing module is used to transmit the signal of the data signal terminal to the preset node in response to the signal of the second gate signal terminal; a second light-emitting control module, connected to the third node, the anode of the light-emitting device and the second enable signal terminal, the second light-emitting control module is used to transmit the driving current of the third node to the anode of the light-emitting device in response to the signal of the second enable signal terminal; a third reset module, connected to the anode of the light-emitting device, the second initialization signal terminal and the scan signal terminal, the third reset module is used to transmit the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the scan signal terminal to reset the anode of the light-emitting device.

[0025] In an exemplary embodiment of the present disclosure, the data writing module includes: a fourth transistor, a first electrode connected to the data signal terminal, a second electrode connected to the preset node, and a gate connected to the second gate signal terminal, the fourth transistor being configured to transmit the signal of the data signal terminal to the preset node in response to the signal of the second gate signal terminal; the second light-emitting control module includes: a sixth transistor, a first electrode connected to the third node, a second electrode connected to the anode of the light-emitting device, and a gate connected to the second enable signal terminal, the sixth transistor being configured to transmit the driving current of the third node to the anode of the light-emitting device in response to the signal of the second enable signal terminal; the third reset module includes: a seventh transistor, a first electrode connected to the second initialization signal terminal, a second electrode connected to the anode of the light-emitting device, and a gate connected to the scan signal terminal, the seventh transistor being configured to transmit the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the scan signal terminal to reset the anode of the light-emitting device; the first sub-switch module includes: a first switching transistor, a first electrode connected to the reference voltage terminal, a second electrode connected to the preset node, and a gate connected to the enable signal terminal, the first switching transistor being configured to be turned on in response to the signal of the second enable signal terminal to utilize the voltage signal of the reference voltage terminal The preset node is stabilized or turned off in response to the signal of the second enable signal terminal to control the preset node to float; the second sub-switch module includes: a second switching transistor, a first electrode connected to the reference voltage terminal, a second electrode connected to the preset node, and a gate connected to the second reset signal terminal, the first switching transistor is used to transmit the voltage signal of the reference voltage terminal to the preset node in response to the signal of the second reset signal terminal; the coupling module includes: a storage capacitor, a first electrode connected to the first node, and a second electrode connected to the preset node; the second reset module includes: an eighth transistor, a first electrode connected to the second node, a second electrode connected to the third initialization signal terminal, and a gate connected to the scan signal terminal, the eighth transistor is used to transmit the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal to reset the second node; the first light-emitting control module includes: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the first enable signal terminal, the fifth transistor is used to transmit the voltage signal of the first power supply terminal to the second node in response to the signal of the first enable signal terminal; wherein the first switching transistor, the second switching transistor, and the fourth to eighth transistors are all P-type transistors.

[0026] According to a second aspect of the present disclosure, a driving method for a pixel driving circuit is further provided, for driving the pixel driving circuit described in any embodiment of the present disclosure, the driving method including a refresh frame stage and a hold frame stage, the driving method including: in the reset stage of the light-emitting frame, respectively controlling the switch signal terminal and the reset signal terminal to output a conduction level, the first switch module is turned on in response to the signal of the switch signal terminal to use the constant voltage terminal to stabilize the preset node, and the first reset module is turned on in response to the signal of the reset signal terminal to write the signal of the first initialization signal terminal to the first node; in the reset stage of the hold frame, respectively controlling the switch signal terminal to output a non-conduction level and the reset signal terminal to output a conduction level, the first switch module is turned on in response to the signal of the reset signal terminal In response to the signal of the switch signal terminal being turned off so that the preset node is floating, the first reset module is turned on in response to the signal of the reset signal terminal to write the signal of the first initialization signal terminal into the first node, and the coupling module couples the voltage change of the first node to the preset node; after the reset phase of the holding frame, the reset signal terminal is controlled to output a non-conduction level and the switch signal terminal is controlled to output a conduction level, the first reset module is turned off in response to the signal of the reset signal terminal so that the first node is floating, the first switch module is turned on in response to the signal of the switch signal terminal to stabilize the preset node using the constant voltage terminal, and the coupling module couples the voltage change of the preset node to the first node.

[0027] According to a third aspect of the present disclosure, a display panel is further provided, comprising the pixel driving circuit described in any embodiment of the present disclosure.

[0028] The pixel driving circuit provided by the present disclosure has a coupling module connecting a first node and a preset node, and a first switch module connecting the preset node and a constant power supply terminal. In the reset phase of the holding frame, the first switch module can be controlled to turn off to make the preset node float, and the first reset module can be controlled to write a first initialization signal to the first node. The coupling module couples the voltage change of the first node to the floating preset node, so that the bias voltage between the first node and the second node of the driving module in the reset phase of the refresh frame and the refresh phase of the holding frame is the same. At the same time, due to the presence of the first switch module, the first switch module can be controlled to turn on after the reset phase of the holding frame, and the coupling module is used to couple the voltage change of the preset node to the first node, so that the potential of the first node is the same as the potential before reset, thereby eliminating or reducing the problem of uneven brightness caused by the difference in working states of the driving module in the refresh frame and the holding frame, and improving the flicker problem of the display panel under low-frequency driving.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0031] FIG1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0032] FIG2 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure;

[0033] Figure 3 is a timing diagram of each node in Figure 2;

[0034] FIG4 is an equivalent circuit diagram of the pixel driving circuit of FIG2 during the reset phase of a refresh frame;

[0035] FIG5 is an equivalent circuit diagram of the pixel driving circuit in FIG2 during the data writing phase of the refresh frame;

[0036] FIG6 is an equivalent circuit diagram of the pixel driving circuit of FIG2 during the pre-light-emission bias phase of a refresh frame;

[0037] FIG7 is an equivalent circuit diagram of the pixel driving circuit in FIG2 during the light emitting phase of a refresh frame;

[0038] FIG8 is an equivalent circuit diagram of the pixel driving circuit in FIG2 during the frame reset stage;

[0039] FIG9 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure;

[0040] FIG10 is a timing diagram of each node in FIG9 ;

[0041] FIG11 is an equivalent circuit diagram of the pixel driving circuit of FIG9 during the reset phase of the refresh frame;

[0042] FIG12 is an equivalent circuit diagram of the pixel driving circuit in FIG9 during the refresh frame data writing phase;

[0043] FIG13 is an equivalent circuit diagram of the pixel driving circuit of FIG9 in the bias phase before the refresh frame light emission;

[0044] FIG14 is an equivalent circuit diagram of the pixel driving circuit in FIG9 during the light emitting stage;

[0045] FIG15 is an equivalent circuit diagram of the pixel driving circuit of FIG9 in the frame reset stage;

[0046] FIG16 is a schematic structural diagram of a pixel driving circuit according to yet another embodiment of the present disclosure;

[0047] FIG17 is a timing diagram of each node in FIG16;

[0048] FIG18 is an equivalent circuit diagram of the pixel driving circuit of FIG16 in the first reset phase of the refresh frame;

[0049] FIG19 is an equivalent circuit diagram of the pixel driving circuit of FIG16 during the second reset phase of the refresh frame;

[0050] FIG20 is an equivalent circuit diagram of the pixel driving circuit of FIG16 in the first reset stage of the hold frame;

[0051] FIG21 is an equivalent circuit diagram of the pixel driving circuit of FIG16 in the second reset stage of the hold frame;

[0052] FIG22 is a schematic structural diagram of a pixel driving circuit according to yet another embodiment of the present disclosure;

[0053] FIG23 is a timing diagram of each node of the pixel driving circuit shown in FIG22;

[0054] FIG24 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the reset phase of the refresh frame;

[0055] FIG25 is an equivalent circuit diagram of the pixel driving circuit in FIG22 during the refresh frame data writing phase;

[0056] FIG26 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the light emitting phase of a refresh frame;

[0057] FIG27 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the frame reset stage;

[0058] FIG28 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the frame light-emission maintenance phase;

[0059] FIG29 is a schematic structural diagram of a pixel driving circuit according to yet another embodiment of the present disclosure;

[0060] FIG30 is a timing diagram of each node of the pixel driving circuit shown in FIG29;

[0061] FIG31 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the reset phase of the refresh frame;

[0062] FIG32 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the refresh frame data writing phase;

[0063] FIG33 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the light emitting phase of a refresh frame;

[0064] FIG34 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the frame reset stage;

[0065] FIG35 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the frame light-emission maintenance stage;

[0066] FIG36 is a schematic structural diagram of a pixel driving circuit according to yet another embodiment of the present disclosure;

[0067] FIG37 is a timing diagram of each node in FIG36;

[0068] FIG38 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the reset phase of the refresh frame;

[0069] FIG39 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the data writing phase of the refresh frame;

[0070] FIG40 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the pre-light emission bias phase of a refresh frame;

[0071] FIG41 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the light emitting phase of a refresh frame;

[0072] FIG42 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the frame reset stage;

[0073] FIG43 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the pre-light emission bias phase of the hold frame;

[0074] FIG44 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the data writing phase of the hold frame. DETAILED DESCRIPTION

[0075] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0076] In related art, during long frame period driving, the hold frame does not reset the driver module 130, resulting in differences in the driver module's operating states between the hold frame and the refresh frame. This results in a difference in display brightness between the refresh frame and the hold frame, causing flicker. The pixel driver circuit disclosed herein is designed to address this issue.

[0077] The following is a unified description of the various signals involved in this disclosure:

[0078] The first initialization signal is the first initialization signal, the second initialization signal is the second initialization signal, the third initialization signal is the signal of the third initialization signal terminal Vinit3, and the data signal is the signal of the data signal terminal Vdata.

[0079] FIG1 is a schematic diagram of the structure of a pixel driving circuit according to an embodiment of the present disclosure. It should be understood that the pixel driving circuit may also include other circuit structures. The figure only shows a partial structure of the pixel driving circuit to exemplify the principle that the pixel driving circuit of the present disclosure can eliminate the difference in working states between the hold frame and the refresh frame. As shown in FIG1 , the pixel driving circuit may include a first reset module 110, a driving module 130, a coupling module 200 and a first switch module 190, wherein the first reset module 110 is connected to the first node N1, the first initialization signal terminal Vinit1 and the reset signal terminal Re, and the first reset module 110 is used to respond to the signal of the reset signal terminal Re and write the first initialization signal to the first node N1; the driving module 130 is connected to the first node N1, the second node N2 and the third node N3, and the driving module 130 is used to act on the voltage difference between the first node N1 and the second node N2 The driving current is provided to the third node N3 downward; the coupling module 200 is connected to the first node N1 and the preset node A, and the coupling module 200 is used to couple the voltage change of the first node N1 to the preset node A and couple the voltage change of the preset node A to the first node N1; the first switch module 190 is connected to the constant voltage terminal VM, the preset node A and the switch signal terminal SW, and the first switch module 190 is used to respond to the signal of the switch signal terminal SW to turn on to stabilize the preset node A using the constant voltage terminal VM or respond to the signal of the switch signal terminal SW to turn off to control the preset node A to float.

[0080] The pixel driving circuit provided by the present disclosure comprises a coupling module 200 connecting a first node N1 and a preset node A, and a first switch module 190 connecting the preset node A and a constant power supply terminal. During the reset phase of the hold frame, the first switch module 190 can be controlled to be turned off, leaving the preset node A floating, and the first reset module 110 can be controlled to write a first initialization signal to the first node N1. The coupling module 200 couples the voltage variation of the first node N1 to the floating preset node A, thereby ensuring that the bias voltage between the first node N1 and the second node N2 of the driver module 130 is the same during the reset phase of the refresh frame and the reset phase of the hold frame. Furthermore, due to the presence of the first switch module 190, the first switch module 190 can be controlled to be turned on after the reset phase of the hold frame, and the coupling module 200 couples the voltage variation of the preset node A to the first node N1, ensuring that the potential of the first node N1 is the same as that before the reset phase. This eliminates or reduces the problem of uneven brightness caused by the difference in the operating state of the driver module 130 between the refresh frame and the hold frame, thereby improving the flicker problem of the display panel under low-frequency driving.

[0081] The pixel driving circuit disclosed herein can be used for low-frequency long-frame cycle driving, i.e., refreshing a frame of data while maintaining it for multiple frames. The driving method of the pixel driving circuit disclosed herein can perform a reset in each hold frame so that the bias voltage of the driving module 130 in the hold frame is the same as the bias voltage in the refresh frame, allowing the pixel driving circuit to provide the same drive current in the hold frame and the refresh frame.

[0082] In the reset phase of the refresh frame, the reset signal terminal Re outputs a conduction level to control the first reset module 110 to be turned on, so that the first initialization signal can be transmitted to the first node N1 to reset the first node N1. During this process, the voltage of the second node N2 can be stabilized to VH, so that the voltage difference ΔV between the first node N1 and the second node N2 is A = Vinit1 - VH is the bias voltage of the driving module 130. The present disclosure can connect the second node N2 to a stable voltage source VH or write a stable voltage to the second node N2 through other reset circuits, so that the second node N2 has a stable voltage at this stage. The specific circuit can be found in the description of subsequent embodiments and will not be elaborated here.

[0083] During the driving process of the holding frame, the first node N1 is also reset. Specifically, the first reset module 110 transmits the first initialization signal to the first node N1 and controls the first switch module 190 to be turned off so that the preset node A is floating. In this way, the coupling module 200 can change the voltage of the first node N1 by ΔV N1 = Vinit1-V0 is coupled to the preset node A, where V0 is the voltage of the first node N1 before coupling, so that the voltage of the preset node A becomes VA=VM+(Vinit1-V0), where VM is the voltage provided by the constant voltage terminal VM. Similarly, during this process, the second node N2 can be stabilized at VH, so that the voltage difference between the first node N1 and the second node N2 is also ΔV A =Vinit1-VH, which is the bias voltage of the driving module 130. It can be seen that after the driving module is reset in the hold frame, the bias voltage of the driving module is the same as the bias voltage of the refresh frame, thereby eliminating the problem of display brightness difference between the refresh frame and the hold frame caused by the different bias voltages of the driving module 130.

[0084] At the same time, after the reset phase of the refresh frame ends, the first switch module 190 can be controlled to be turned on so that the preset node A is stabilized to VM by the constant voltage terminal VM. The voltage change of the preset node A is ΔV A=VM-(VM+(Vinit1-V0))=V0-Vinit1. At the same time, the first reset module 110 is turned off to make the first node N1 float. In this way, the coupling module 200 can preset the voltage change of the node A by ΔV A =V0-Vinit1 is coupled to the first node N1, so that the voltage of the first node N1 becomes VA=V0 again, so that after the reset phase of the holding frame, the first node N1 maintains the same voltage as before the reset, that is, the voltage of the first node N1 will not be changed, and the pixel driving circuit can maintain the original state to emit light.

[0085] The level output by a certain signal terminal described in the present disclosure as a conduction level can be understood as the level output by the signal terminal being able to conduct or activate the circuit structure connected to the signal terminal or to increase the voltage of the node connected to the signal terminal. Correspondingly, the level output by a certain signal terminal being a non-conduction level means that the level signal output by the signal terminal is able to shut down the circuit structure connected to the signal terminal or to lower the voltage of the node connected to the signal terminal.

[0086] The circuit structure and working principle of the pixel driving circuit disclosed in the present invention are described in detail below with reference to a specific circuit.

[0087] FIG2 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure. As shown in FIG2 , in an exemplary embodiment, the constant voltage terminal VM is the first power terminal VDD, that is, the preset node A is connected to the first power terminal VDD via the first switch module 190. The switch signal terminal SW may include a first switch signal terminal SW-P, the reset signal terminal Re may include a first reset signal terminal Re-N, and the cathode of the light-emitting device OLED may be connected to the second power terminal VSS. The pixel driving circuit may further include a second reset module 180, a first transmission module 120, a data writing module 140, a first light-emitting control module 150, a second light-emitting control module 160 and a third reset module 170, wherein the second reset module 180 is connected to the second node N2, the third initialization signal terminal Vinit3 and the scan signal terminal Scan, and the second reset module 180 can be used to write the third initialization signal to the second node N2 in response to the signal of the scan signal terminal Scan; the first transmission module 120 is connected to the first node N1, the third node N3 and the first gate signal terminal Gn-N, and the first transmission module 120 can be used to turn on or off the connection between the first node N1 and the third node N3 in response to the signal of the first gate signal terminal Gn-N. The data writing module 140 is connected to the second node N2, the data signal terminal Vdata and the second gate signal terminal Gn-P, and the data writing module 140 can be used to transmit the data signal to the second node N2 in response to the signal of the second gate signal terminal Gn-P; the first light-emitting control module 150 is connected to the second node N2, the first power supply terminal VDD and the enable signal terminal EM, and the first light-emitting control module 150 can be used to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM; the second light-emitting control module 160 is connected to the third node N3, the anode of the light-emitting device OLED and the enable signal terminal EM, and the second light-emitting control module 160 can be used to transmit the current signal of the third node N3 to the anode of the light-emitting device OLED in response to the signal of the enable signal terminal EM; the third reset module 170 is connected to the anode of the light-emitting device OLED, the second initialization signal terminal Vinit2 and the scan signal terminal Scan, and the third reset module 170 can be used to transmit the second initialization signal to the anode of the light-emitting device OLED in response to the signal of the scan signal terminal Scan to reset it.

[0088] The driving process of the pixel drive may include a refresh frame stage and a hold frame stage. The refresh frame may include a reset stage, a data writing stage, a pre-luminous bias stage and a luminous stage. The hold frame may include a reset stage, a pre-luminous bias stage and a luminous stage. That is, the hold frame does not need to write data, but instead maintains the data written in the refresh frame.

[0089] Among them, the first reset module 110, the second reset module 180 and the third reset module 170 can be turned on in the reset stage, the first reset module 110 can transmit the first initialization signal to the first node N1 to reset the first node N1, the second reset module 180 can transmit the third initialization signal to the second node N2 to reset the second node N2, and the third reset module 170 can transmit the second initialization signal to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED.

[0090] The first transmission module 120 and the data writing module 140 can be turned on in the data writing phase. In this phase, the driving module 130 is turned on under the voltage control of the first node N1, so that the data signal is written into the first node N1 through the data writing module 140, the driving module 130 and the first transmission module 120.

[0091] In the pre-light-emission bias stage, the second reset module 180 may be controlled to be turned on so as to transmit the third initialization signal to the second node N2 to reset the second node N2.

[0092] The first light emitting control module 150 and the second light emitting control module 160 can be turned on in the light emitting stage, thereby forming a current path between the first power supply terminal VDD and the second power supply terminal VSS, and the light emitting device OLED emits light under the action of the driving current provided by the driving module 130.

[0093] The first switch module 190 can be turned off during the reset phase of the holding frame and turned on in other phases. In this way, the preset node A can be controlled to float during the reset phase of the holding frame, so that the voltage change of the first node N1 can be coupled to the preset node A using the coupling module 200, so that after resetting the first node N1 during the reset phase of the holding frame, the voltage of the first node N1 in the holding frame will not be changed, that is, the working state of the driving module 130 will not be changed.

[0094] In an exemplary embodiment, the pixel driving circuit can be implemented by a transistor. Exemplarily, with continued reference to FIG2 , the first reset module 110 may include a first transistor T1, wherein a first electrode of the first transistor T1 is connected to the first initialization signal terminal Vinit1, a second electrode of the first transistor T1 is connected to the first node N1, and a gate of the first transistor T1 is connected to the first reset signal terminal Re-N. The first transistor T1 may be configured to transmit the first initialization signal to the first node N1 in response to a signal at the first reset signal terminal Re-N. The first transmission module 120 may include a second transistor T2, wherein a first electrode of the second transistor T2 is connected to the first node N1, a second electrode of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first gate signal terminal Gn-N. The second transistor T2 may be configured to conduct the connection between the third node N3 and the first node N1 in response to a signal at the first gate signal terminal Gn-N. The driving module 130 may include a driving transistor DT, wherein a first electrode of the driving transistor DT is connected to the second node N2, a second electrode of the driving transistor DT is connected to the third node N3, and a gate of the driving transistor DT is connected to the first node N1. The driving transistor DT may be configured to provide a driving current to the third node N3 using a voltage difference between the first node N1 and the second node N2. The first switching module 190 may include a first switching transistor Tsw1, wherein a first electrode of the first switching transistor Tsw1 is connected to a predetermined node A, a second electrode of the first switching transistor Tsw1 is connected to a first power supply terminal VDD, and a gate of the first switching transistor Tsw1 is connected to a first switching signal terminal SW-P. The first switching transistor Tsw1 may be configured to be turned on in response to a signal from the first switching signal terminal SW-P to regulate a predetermined voltage using a voltage signal from the first power supply terminal VDD, or to be turned off in response to a signal from the first switching signal terminal SW-P to control the predetermined node A to float.

[0095] The second reset module 180 may include an eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the third initialization signal terminal Vinit3, the second electrode is connected to the second node N2, and the gate is connected to the scan signal terminal Scan. The eighth transistor T8 can be used to respond to the signal of the scan signal terminal Scan to transmit the third initialization signal to the second node N2 to reset the second node N2.

[0096] The data writing module 140 may include a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the data signal terminal Vdata, a second electrode of the fourth transistor T4 is connected to the second node N2, and a gate of the fourth transistor T4 is connected to the second gate signal terminal Gn-P. The fourth transistor T4 can be used to transmit the data signal to the second node N2 in response to the signal of the second gate signal terminal Gn-P; the first light-emitting control module 150 may include a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the second node N2, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM. The fifth transistor T5 can be used to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM; the second light-emitting control module 160 may include a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the third node N3 , the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting device OLED, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, and the sixth transistor T6 can be used to transmit the current signal of the third node N3 to the anode of the light-emitting device OLED in response to the signal of the enable signal terminal EM; the third reset module 170 may include a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the second initialization signal terminal Vinit2, the second electrode of the seventh transistor T7 is connected to the anode of the light-emitting device OLED, and the gate of the seventh transistor T7 is connected to the scan signal terminal Scan, and the seventh transistor T7 can be used to transmit the second initialization signal to the anode of the light-emitting device OLED in response to the signal of the scan signal terminal Scan to reset it; the coupling module 200 may include a storage capacitor Cst, the first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode of the storage capacitor Cst is connected to the preset node A.

[0097] Among them, the first transistor T1 and the second transistor T2 can both be N-type transistors, for example, both can be N-type oxide transistors. In this way, the low leakage current characteristic of the oxide transistor can be used to reduce the leakage current of the first node N1. The leakage of the pixel driving circuit is mainly caused by the leakage of the first node N1. Therefore, by controlling the leakage current of the first node N1, the voltage holding rate of the pixel driving circuit during a long frame period can be effectively improved, avoiding the brightness difference between different data frames due to leakage. The driving transistor DT, the first switching transistor Tsw1, and the fourth transistor T4 to the eighth transistor T8 can all be P-type transistors, for example, all can be P-type low-temperature polysilicon transistors. The low-temperature polysilicon transistor has a high electron mobility, which is beneficial to reducing the overall power consumption of the pixel driving circuit. It should be understood that in other embodiments, the above-mentioned functional modules can also be implemented through other circuit structures.

[0098] Figure 3 is a timing diagram of each node in Figure 2. In the figure, Re-N represents the timing of the first reset signal terminal, Gn-N represents the timing of the first gate signal terminal, Gn-P represents the timing of the second gate signal terminal, Scan represents the timing of the scan signal terminal, SW-P represents the timing of the first switch signal terminal, and EM represents the timing of the enable signal terminal.

[0099] As shown in Figure 3, the driving process of the pixel drive may include a refresh frame and a hold frame. The refresh frame may include a reset stage, a data writing stage, a pre-luminescence bias stage and a luminescence stage. The hold frame may include a reset stage, a pre-luminescence bias stage and a luminescence stage.

[0100] During the reset phase t1 of the refresh frame, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 4 is an equivalent circuit diagram of the pixel driving circuit of Figure 2 during the reset phase of the refresh frame. As shown in Figure 4, the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the first switch transistor Tsw1 are turned on, and the other transistors are turned off. During this process, the first initialization signal is transmitted to the first node N1 to reset the first node N1, the second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED, and the third initialization signal is transmitted to the second node N2 to reset the second node N2, so that the voltage of the first node N1 becomes Vinit1, and the voltage of the second node N2 becomes Vinit3. The voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, and this voltage difference is the bias voltage Vgs of the driving transistor DT.

[0101] During the data writing phase t2 of the refresh frame, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a low-level signal, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 5 is an equivalent circuit diagram of the pixel driving circuit of Figure 2 during the data writing phase of the refresh frame. As shown in Figure 5, the second transistor T2, the fourth transistor T4, and the first switch transistor Tsw1 are turned on. At this time, the driving transistor DT is turned on under the control of the voltage difference between the first node N1 and the second node N2, i.e., the bias voltage. The data signal provided by the data signal terminal Vdata is transmitted to the first node N1. When the potential of the first node N1 becomes Vdata + Vth, Vth is the threshold voltage of the driving transistor DT, and the bias voltage Vgs of the driving transistor DT is 0. At this time, the driving transistor DT is turned off, and the threshold voltage Vth of the driving transistor DT is written to the first node N1. This process achieves threshold voltage compensation of the driving transistor DT.

[0102] During the pre-emission bias phase t3 of the refresh frame, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 6 is an equivalent circuit diagram of the pixel drive circuit of Figure 2 during the pre-emission bias phase of the refresh frame. As shown in Figure 6, the seventh transistor T7, the eighth transistor T8, and the first switch transistor Tsw1 are turned on, and the third initialization signal is transmitted to the second node N2 to reset the second node N2 before emitting light. At this time, the bias voltage of the drive transistor DT is Vgs = Vdata + Vth - Vinit3. In this exemplary embodiment, by using the third initialization signal to reset the second node N2 before emitting light, the drive transistor DT remains in a reset state, improving the hysteresis of the drive transistor DT and thus eliminating afterimages. It can be seen that in actual use, the hysteresis of the driving transistor DT will cause the characteristic response of the driving transistor DT to be slow. Before the light-emitting stage, this exemplary embodiment quickly resets the gate-source voltage of the driving transistor DT, which is conducive to accelerating the recovery speed of the driving transistor DT. Therefore, it will improve the hysteresis phenomenon of the driving transistor DT and enhance the hysteresis recovery speed.

[0103] In the light-emitting stage t4 of the refresh frame, the first reset signal terminal Re-N, the first gate signal terminal Gn-N, the first switch signal terminal SW-P, and the enable signal terminal EM all output low-level signals, and the second gate signal terminal Gn-P and the scan signal terminal Scan output high-level signals. Figure 7 is an equivalent circuit diagram of the pixel driving circuit in Figure 2 in the light-emitting stage of the refresh frame. As shown in Figure 7, the fifth transistor T5, the sixth transistor T6 and the first switch transistor Tsw1 are turned on, and a loop is formed from the first power supply terminal VDD to the second power supply terminal VSS. The light-emitting device OLED emits light under the action of the driving current provided by the driving transistor DT.

[0104] According to the current formula: I=1 / 2k(V GS -Vth) 2 (1)

[0105] The above V GS Substituting into formula (1), we can get the driving current: I=1 / 2k(Vdata-Vinit3) 2 (2)

[0106] It can be seen that the driving current is only related to Vdata and Vinit3, and has nothing to do with the voltage of the first voltage terminal Vdd (driving voltage), thereby achieving compensation of the threshold voltage and the driving voltage, so that the driving voltage at different positions in the driving circuit will not be affected by the voltage drop of the first power line itself.

[0107] During the reset phase t1' of the hold frame, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a high-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 8 is an equivalent circuit diagram of the pixel driving circuit of Figure 2 during the reset phase of the hold frame. As shown in Figure 8, the seventh transistor T7, the eighth transistor T8, and the first transistor T1 are turned on. The first switch transistor Tsw1 is turned off, causing the preset node A to float. At the same time, the first transistor T1 is turned on to write the first initialization signal to the first node N1. During this phase, the voltage change at the first node N1 is ΔVN1 = Vinit1 - (Vdata + Vth), so that the voltage at the preset node A becomes VA = VDD + Vinit1 - (Vdata + Vth). Moreover, in this stage, the voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, that is, the bias voltage Vgs of the driving transistor DT is Vinit1-Vinit3. It can be seen that the bias voltage of the driving transistor DT is the same as the bias voltage in the reset stage in the refresh frame, so that the driving transistor DT has the same bias voltage in the hold frame and the refresh frame, thereby eliminating or improving the display brightness difference between the refresh frame and the hold frame caused by the different bias voltages of the driving transistor DT.

[0108] As shown in FIG3 , after the reset phase of the hold frame ends, the first reset signal terminal Re-N outputs a low-level signal, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the output signals of the other signal terminals remain unchanged compared to the previous phase. At this time, the first switch transistor Tsw1 turns on, causing the voltage of the preset node A to return to VDD. The voltage change of the preset node A is ΔVA = VDD - [VDD + Vinit1 - (Vdata + Vth)] = (Vdata + Vth) - Vinit1. The first transistor T1 turns off, causing the first node N1 to float. The storage capacitor Cst couples the voltage change of the preset node A to the first node N1, causing the voltage of the first node N1 to return to Vdata + Vth, the same as the voltage before the reset. That is, in this exemplary embodiment, by adding a reset phase to the hold frame to reset the first node N1, while ensuring that the bias voltage of the drive transistor DT is the same as the bias voltage of the refresh frame, the voltage of the first node N1 in the hold frame is not changed.

[0109] During the pre-emission bias phase t3' of the hold frame, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. The eighth transistor T8 is turned on to transmit the third initialization signal to the second node N2. This process is identical to the pre-emission bias phase t3 of the refresh frame. The equivalent circuit diagram of this process is the same as that in FIG6 and will not be further described here.

[0110] During the light-emitting phase t4' of the hold frame, the first reset signal terminal Re-N, the first gate signal terminal Gn-N, the first switch signal terminal SW-P, and the enable signal terminal EM all output low-level signals, while the second gate signal terminal Gn-P and the scan signal terminal Scan output high-level signals. The fifth and sixth transistors T5 and T6, as well as the first switch transistor Tsw1, are turned on. This process is identical to the light-emitting phase of the refresh frame, and the light-emitting device OLED emits light under the drive current provided by the drive transistor DT. An equivalent circuit diagram of this process can be found in Figure 7 and will not be further described here.

[0111] In this exemplary embodiment, the hold frame adds a gate reset process for the drive transistor DT. The bias voltage Vgs applied to the drive transistor DT is consistent with the bias voltage during the reset phase t1 of the refresh frame. The bias voltages are all Vinit1-Vinit3, independent of the data signal Vdata voltage. This effectively resolves the incompatibility issues between different brightness levels or high and low grayscales. Furthermore, after the first node N1 acquires the threshold voltage of the drive transistor DT during the data write phase, the drive transistor DT is nearly cut off, minimizing the impact of this process on the state of the drive transistor DT. It can be seen that the pixel drive circuit and driving method of this exemplary embodiment can ensure consistent operating conditions during the refresh frame and the hold frame, thereby eliminating the brightness difference between the hold frame and the refresh frame and improving the flickering effect of low-frequency drive.

[0112] FIG9 is a schematic diagram of the structure of a pixel driving circuit according to another embodiment of the present disclosure. As shown in FIG9 , in an exemplary embodiment, the constant voltage terminal VM is the first power supply terminal VDD, that is, the preset node A is connected to the first power supply terminal VDD via the first switch module 190. The switch signal terminal SW may include a first switch signal terminal SW-P, the reset signal terminal Re may include a second reset signal terminal Re-P, and the cathode of the light-emitting device OLED may be connected to the second power supply terminal VSS. The pixel driving circuit may also include a second switch module 220. The second switch module 220 is connected in series between the first node N1 and the first reset module 110 and connected to the first gate signal terminal Gn-N. The second switch module 220 is at least configured to connect the first reset signal module to the first node N1 in response to a signal at the first gate signal terminal Gn-N to transmit a first initialization signal to the first node N1.

[0113] Comparing FIG2 and FIG9 , it can be seen that the pixel driving circuit in this exemplary embodiment differs from the pixel driving circuit shown in FIG2 in that a second switch module 220 is added between the first reset module 110 and the first node in this exemplary embodiment, and the conduction levels of the first reset module 110 and the first transmission module 120 in this exemplary embodiment are opposite in polarity to the conduction levels of the first reset module 110 and the first transmission module 120 in FIG2 . In this exemplary embodiment, the conduction levels of the first reset module 110 and the first transmission module 120 are the same as the conduction level of the driving module 130, and the conduction level of the second switch module 220 is opposite in polarity to the conduction level of the driving module 130. For example, the conduction levels of the first reset module 110, the first transmission module 120, and the driving module 130 can all be low, while the conduction level of the second switch module 220 can be high.

[0114] Exemplarily, the above-mentioned functional modules can be implemented by transistors. Specifically, the first reset module 110 may include a first transistor T1, the first transmission module 120 may include a second transistor T2, the driving module 130 may include a driving transistor DT, and the second switching module 220 may include a tenth transistor T10. The first transistor T1, the second transistor T2, and the driving transistor DT may all be P-type transistors, such as P-type low-temperature polysilicon transistors. The tenth transistor T10 may be an N-type transistor, such as an N-type oxide transistor. By configuring the tenth transistor T10 as an oxide transistor, the low leakage current characteristic of oxide transistors can be utilized to reduce the leakage current of the first node N1, thereby improving the voltage holding rate of the pixel driving circuit during long frame periods. The other transistors are all P-type transistors, which have high electron mobility and can reduce the power consumption of the pixel driving circuit. In this exemplary embodiment, because the additional tenth transistor T10 is an N-type transistor, the tenth transistor T10 can be utilized to reduce the leakage current of the first node N1. Therefore, the first transistor T1 and the second transistor T2 can be configured as P-type transistors, thereby further reducing the overall power consumption of the pixel driving circuit.

[0115] It should be understood that this exemplary embodiment can also have a coupling module 200, a data writing module 140, a first light-emitting control module 150, a second light-emitting control module 160, a third reset module 170, a second reset module 180 and a first switch module 190, and the above-mentioned functional modules can have the same structure as the corresponding functional modules in Figure 2, and will not be repeated here.

[0116] Figure 10 is a timing diagram of each node in Figure 9. In the figure, Re-P represents the timing of the second reset signal terminal, Gn-N represents the timing of the first gate signal terminal, Gn-P represents the timing of the second gate signal terminal, Scan represents the timing of the scan signal terminal, SW-P represents the timing of the first switch signal terminal, and EM represents the timing of the enable signal terminal.

[0117] As shown in Figure 10, the driving process of the pixel drive may include a refresh frame and a hold frame. The refresh frame may include a reset stage, a data writing stage, a pre-luminescence bias stage and a luminescence stage. The hold frame may include a reset stage, a pre-luminescence bias stage and a luminescence stage.

[0118] During the reset phase t1 of the refresh frame, the second reset signal terminal Re-P outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 11 is an equivalent circuit diagram of the pixel driving circuit of Figure 9 during the reset phase of the refresh frame. As shown in Figure 11, the first transistor T1, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the first switch transistor Tsw1 are turned on, and the other transistors are turned off. During this process, the first initialization signal is transmitted to the first node N1 to reset the first node N1, the second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED, and the third initialization signal is transmitted to the second node N2 to reset the second node N2, so that the voltage of the first node N1 becomes Vinit1, and the voltage of the second node N2 becomes Vinit3. The voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, and this voltage difference is the bias voltage Vgs of the driving transistor DT.

[0119] During the data writing phase t2 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a low-level signal, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 12 is an equivalent circuit diagram of the pixel driving circuit of Figure 9 during the data writing phase of the refresh frame. As shown in Figure 12, the second transistor T2, the fourth transistor T4, the tenth transistor T10, and the first switch transistor Tsw1 are turned on. At this time, the driving transistor DT is turned on under the control of the voltage difference between the first node N1 and the second node N2, i.e., the bias voltage. The data signal provided by the data signal terminal Vdata is transmitted to the first node N1. When the potential of the first node N1 becomes Vdata + Vth, Vth is the threshold voltage of the driving transistor DT, and the bias voltage Vgs of the driving transistor DT is 0. At this time, the driving transistor DT is turned off, and the threshold voltage Vth of the driving transistor DT is written to the first node N1. This process achieves threshold voltage compensation of the driving transistor DT.

[0120] During the pre-emission bias phase t3 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 13 is an equivalent circuit diagram of the pixel drive circuit of Figure 9 during the pre-emission bias phase of the refresh frame. As shown in Figure 13, the seventh transistor T7, the eighth transistor T8, and the first switch transistor Tsw1 are turned on, and the third initialization signal is transmitted to the second node N2 to reset the second node N2 and the anode of the light-emitting device OLED before emitting light. At this time, the bias voltage of the drive transistor DT is Vgs = Vdata + Vth - Vinit3. It should be understood that the pre-emission bias in this exemplary embodiment can also achieve the effects of improving the hysteresis of the drive transistor DT and eliminating afterimages as described in the above embodiments, and will not be repeated here.

[0121] During the light-emitting phase t4 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the first switch signal terminal SW-P and the enable signal terminal EM both output low-level signals. Figure 14 is an equivalent circuit diagram of the pixel drive circuit of Figure 9 during the light-emitting phase. As shown in Figure 14, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the first switch transistor Tsw1 are turned on, forming a loop from the first power supply terminal VDD to the second power supply terminal VSS. The light-emitting device OLED emits light under the driving current provided by the driving transistor DT. This process is similar to the light-emitting process of the circuit shown in Figure 2 and will not be repeated here.

[0122] During the reset phase t1' of the hold frame, the second reset signal terminal Re-P outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a high-level signal, and the enable signal terminal EM outputs a high-level signal. FIG15 is an equivalent circuit diagram of the pixel driving circuit of FIG9 during the reset phase of the hold frame. As shown in FIG15 , the first transistor T1, the tenth transistor T10, the seventh transistor T7, and the eighth transistor T8 are turned on, and the first switch transistor Tsw1 is turned off, thereby floating the preset node A. At the same time, the first transistor T1 and the tenth transistor T10 are turned on to write the first initialization signal to the first node N1. During this phase, the voltage change of the first node N1 is ΔVN1 = Vinit1 - (Vdata + Vth), so that the voltage of the preset node A becomes VA = VDD + Vinit1 - (Vdata + Vth). Moreover, in this stage, the voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, that is, the bias voltage Vgs of the driving transistor DT is Vinit1-Vinit3. It can be seen that the bias voltage of the driving transistor DT is the same as the bias voltage in the reset stage in the refresh frame, so that the driving transistor DT has the same bias voltage in the hold frame and the refresh frame, thereby eliminating or improving the display brightness difference between the refresh frame and the hold frame caused by the different bias voltages of the driving transistor DT.

[0123] As shown in FIG10 , in the second phase t2′ after the reset phase of the hold frame ends, the second reset signal terminal Re-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the output signals of the other signal terminals remain unchanged. At this time, the first switch transistor Tsw1 is turned on, causing the voltage of the preset node A to return to VDD. The voltage change of the preset node A is ΔVA = VDD - (VDD + Vinit1 - (Vdata + Vth)) = (Vdata + Vth) - Vinit1. Simultaneously, the first transistor T1 is turned off, causing the first node N1 to float. The storage capacitor Cst couples the voltage change of the preset node A to the first node N1, causing the voltage of the first node N1 to return to Vdata + Vth, the same as the voltage before the reset. This shows that in this exemplary embodiment, by adding a reset phase to the hold frame to reset the first node N1, while ensuring that the bias voltage of the drive transistor DT is the same as the bias voltage of the refresh frame, the voltage of the first node N1 in the hold frame remains unchanged.

[0124] Thereafter, the pre-light-emission bias phase t3' of the holding frame is the same as the pre-light-emission bias phase t3 of the refresh frame, and the light-emission phase t4' of the holding frame is the same as the light-emission phase t4 of the refresh frame, which will not be repeated here.

[0125] It can be seen that this exemplary embodiment can also achieve the same bias voltage for the driving transistor DT in the hold frame and the refresh frame by adding a second switch module 200 between the first node N1 and the first reset module 110 and coordinating the corresponding timing, thereby solving the problem of uneven display brightness between the hold frame and the refresh frame.

[0126] FIG16 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure. As shown in FIG16 , in an exemplary embodiment, the constant voltage terminal VM is the first power supply terminal VDD, that is, the preset node A is connected to the first power supply terminal VDD via the first switch module 190. The switch signal terminal SW may include a first switch signal terminal SW-P, the reset signal terminal Re may include a second reset signal terminal Re-P, and the cathode of the light-emitting device OLED may be connected to the second power supply terminal VSS. The first reset module 110 may also be connected to the first node N1 via the first transmission module 120. In this case, the first reset module 110 is connected to the third node N3, the first initialization signal terminal Vinit1, and the second reset signal terminal Re-P. The first transmission module 120 is connected between the first node N1 and the third node N3 and to the first gate signal terminal Gn-N. In this circuit structure, the conduction level of the first transmission module 120 has a polarity opposite to that of the conduction level of the driving module 103.

[0127] For example, the first transmission module 120 may include a second transistor T2, and the driving module 103 may include a driving transistor T3. The second transistor T2 may be an N-type transistor, such as an N-type oxide transistor, and the driving transistor DT may be a P-type transistor, such as a P-type low-temperature polysilicon transistor. In this case, by configuring the second transistor T2 as an oxide transistor, the leakage current of the first node N1 can be reduced, thereby improving the voltage holding ratio of the pixel driving circuit while simplifying the circuit structure.

[0128] As shown in Figure 16, the pixel driving circuit shown in this exemplary embodiment can also include a coupling module 200, a data writing module 140, a first light-emitting control module 150, a second light-emitting control module 160, a third reset module 170, a second reset module 180 and a first switch module 190, and the above-mentioned functional modules can have the same structure as the corresponding functional modules in Figure 2, and will not be repeated here.

[0129] FIG17 is a timing diagram of each node in FIG16 . In the diagram, Re-P represents the timing of the second reset signal terminal, Gn-N represents the timing of the first gate signal terminal, Gn-P represents the timing of the second gate signal terminal, Scan represents the timing of the scan signal terminal, SW-P represents the timing of the first switch signal terminal, and EM represents the timing of the enable signal terminal EM. Furthermore, the pixel driving process may include a refresh frame and a hold frame. The refresh frame may include a reset phase, a data write phase, a pre-emission bias phase, and a light-emitting phase, while the hold frame may include a reset phase, a pre-emission bias phase, and a light-emitting phase. Furthermore, because the first transistor T1 is connected to the third node N3 and the eighth transistor T8 is connected to the second node N2, it is necessary to stagger the reset of the second node N2 and the third node N3 to prevent a short circuit when the second node N2 and the third node N3 are reset simultaneously. Therefore, the reset phase in this exemplary embodiment may include a first reset phase and a second reset phase.

[0130] During the first reset phase t1 of the refresh frame, the second reset signal terminal Re-P outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 18 is an equivalent circuit diagram of the pixel driving circuit of Figure 16 during the first reset phase of the refresh frame. As shown in Figure 18, the first transistor T1, the second transistor T2, and the first switch transistor Tsw1 are turned on, and the other transistors are turned off. During this process, the first initialization signal is transmitted to the first node N1 to reset the first node N1, so that the voltage of the first node N1 becomes Vinit1.

[0131] During the second reset phase t2 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. FIG19 is an equivalent circuit diagram of the pixel driving circuit of FIG16 during the second reset phase of the refresh frame. As shown in FIG19 , the seventh transistor T7, the eighth transistor T8, and the first switch transistor Tsw1 are turned on, while the other transistors are turned off. A second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED. A third initialization signal is transmitted to the second node N2 to reset the second node N2, causing the voltage of the second node N2 to become Vinit3. As a result, the voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, which is the bias voltage Vgs of the drive transistor DT.

[0132] Thereafter, the pre-light-emission bias phase and the light-emission phase in the refresh frame correspond to the pre-light-emission bias phase and the light-emission phase of the driving method shown in FIG3 and have the same effects, which will not be described in detail here.

[0133] During the first reset phase t1' of the hold frame, the second reset signal terminal Re-P outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a high-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 20 is an equivalent circuit diagram of the pixel driving circuit of Figure 16 during the first reset phase of the hold frame. As shown in Figure 20, the first transistor T1 and the second transistor T2 are turned on, and the other transistors are turned off. During this process, the first initialization signal is transmitted to the first node N1 and the first node N1 is reset, so that the voltage of the first node N1 becomes Vinit1, and the voltage change of the first node N1 is ΔVN1 = Vinit1-(Vdata+Vth), and at this stage the first switching transistor Tsw1 is turned off to make the preset node A float, so that the storage capacitor Cst couples the voltage change ΔVN1 of the first node A to the preset node A, so that the voltage of the preset node A becomes VA = VDD+Vinit1-(Vdata+Vth).

[0134] During the second reset phase t2' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, the first switch signal terminal SW-P outputs a high-level signal, and the enable signal terminal EM outputs a high-level signal. Figure 21 is an equivalent circuit diagram of the pixel driving circuit of Figure 16 during the second reset phase of the hold frame. As shown in Figure 21, the seventh transistor T7 and the eighth transistor T8 are turned on, and the other transistors are turned off. The second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED. The third initialization signal is transmitted to the second node N2 to reset the second node N2, causing the voltage of the second node N2 to become Vinit3. As a result, the voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, which is the bias voltage Vgs of the driving transistor DT. It can be seen that the bias voltage of the driving transistor DT is the same as the bias voltage during the reset phase of the refresh frame, so that the driving transistor DT has the same bias voltage during the hold frame and the refresh frame, thereby eliminating or improving the display brightness difference between the refresh frame and the hold frame caused by the different bias voltages of the driving transistor DT. During this process, the first switching transistor Tsw1 is turned off, and the voltage of the preset node A is maintained at the previous stage.

[0135] Then, as shown in FIG. 17 , in the third stage t3′ after the second reset stage of the hold frame, the scan signal terminal Scan outputs a high-level signal, the first switch signal terminal SW-P outputs a low-level signal, and the output signals of the other signal terminals are the same as the output signals of the previous stage. At this time, the first switch transistor Tsw1 is turned on, so that the voltage of the preset node A returns to VDD. The voltage change of the preset node A is ΔVA = VDD - [VDD + Vinit1 - (Vdata + Vth)]. At the same time, the first node N1 is floating, and the storage capacitor Cst couples the voltage change of the preset node A to the first node N1. The voltage of the first node N1 returns to Vdata + Vth, which is the same as the voltage before the reset. That is, in this exemplary embodiment, by adding a reset stage to the hold frame to reset the first node N1, while achieving the same bias voltage of the drive transistor DT as the bias voltage of the refresh frame, the voltage of the first node N1 in the hold frame is not changed.

[0136] Similarly, the pre-light-emission bias phase and the light-emission phase of the maintenance frame correspond to the pre-light-emission bias phase and the light-emission phase of the refresh frame and have the same effects, and are not described in detail here.

[0137] FIG22 is a schematic diagram of the structure of a pixel driving circuit according to another embodiment of the present disclosure. As shown in FIG22 , in an exemplary embodiment, the constant voltage terminal VM is the reference voltage terminal Vref, that is, the preset node A is connected to the reference voltage terminal Vref via the first switch module 190. The switch signal terminal SW may include a second switch signal terminal, the reset signal terminal Re may include a first reset signal terminal Re-N and a second reset signal terminal Re-P, the cathode of the light-emitting device OLED may be connected to the second power supply terminal VSS, and the second node N2 may be directly connected to the first power supply terminal VDD. In this exemplary embodiment, the first switch module 190 may include a first sub-switch module 191, and the second switch signal terminal may be multiplexed with the enable signal terminal EM. That is, the first sub-switch module 191 is connected between the reference voltage terminal Vref and the preset node A and is also connected to the enable signal terminal EM. Thus, the first sub-switch module 191 can be turned on in response to a signal from the enable signal terminal EM to stabilize the preset node A using the voltage signal from the reference voltage terminal Vref, or turned off in response to a signal from the enable signal terminal EM to control the preset node A to float. In this exemplary embodiment, the first sub-switch module 191 can be turned on in the reset phase and the light-emitting phase respectively, so as to stabilize the preset node A using the reference voltage terminal Vref.

[0138] As shown in FIG22 , in an exemplary embodiment, the pixel driving circuit may further include a first transmission module 120, a data writing module 140, a second light emitting control module 160, and a third reset module 170. The first transmission module 120 connects the first node N1, the third node N3, and the first gate signal terminal Gn-N. The first transmission module 120 may be configured to connect or disconnect the first node N1 from the third node N3 in response to a signal at the first gate signal terminal Gn-N. The conduction levels of the first transmission module 120 and the first reset module 110 are opposite in polarity to the conduction level of the driving module 130. For example, if the conduction level of the driving module 130 is high, the conduction levels of the first transmission module 120 and the first reset module 110 may be low.

[0139] The data writing module 140 is connected to the preset node A, the data signal terminal Vdata and the second gate signal terminal Gn-P. The data writing module 140 can be used to transmit the signal of the data signal terminal Vdata to the preset node A in response to the signal of the second gate signal terminal Gn-P; the second light-emitting control module 160 is connected to the third node N3, the anode of the light-emitting device OLED and the enable signal terminal EM. The second light-emitting control module 160 can be used to transmit the driving current of the third node N3 to the anode of the light-emitting device OLED in response to the signal of the enable signal terminal EM; the third reset module 170 is connected to the anode of the light-emitting device OLED, the second initialization signal terminal Vinit2 and the scan signal terminal Scan. The third reset module 170 can be used to transmit the second initialization signal to the anode of the light-emitting device OLED in response to the signal of the scan signal terminal Scan to reset it.

[0140] In an exemplary embodiment, the first reset module 110 , the first transmission module 120 , the driving module 130 , the first sub-switch module 191 , the data writing module 140 , the second light emitting control module 160 and the third reset module 170 may all be implemented by transistors. As shown in Figure 22, the first reset module 110 may include a first transistor T1, a first electrode of the first transistor T1 is connected to the first initialization signal terminal Vinit1, a second electrode of the first transistor T1 is connected to the first node N1, and a gate of the first transistor T1 is connected to the first reset signal terminal Re-N. The first transistor T1 can be used to transmit the first initialization signal to the first node N1 in response to the signal of the first reset signal terminal Re-N; the first transmission module 120 may include a second transistor T2, a first electrode of the second transistor T2 is connected to the first node N1, a second electrode of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first gate signal terminal Gn-N. The second transistor T2 can be used to connect the third node N3 with the first node N1 in response to the signal of the first gate signal terminal Gn-N; the driving module 130 may include a driving transistor DT, a first electrode of the driving transistor DT is connected to the second node N2, a second electrode of the driving transistor DT is connected to the third node N3, and a gate of the driving transistor DT is connected to the first node N1. The driving transistor DT can be used to provide a driving current to the third node N3 using the voltage difference between the first node N1 and the second node N2. The driving transistor DT may be a P-type transistor, for example, a P-type low-temperature multi-transistor transistor. The first transistor T1 and the second transistor T2 may be N-type transistors, for example, N-type oxide transistors. Oxide transistors have a small leakage current. By configuring the first transistor T1 and the second transistor T2 as N-row transistors, the leakage current of the first node N1 can be reduced, thereby improving the data voltage retention rate of the pixel driving circuit. It should be understood that in other embodiments, the first reset module 110, the first transmission module 120, and the driving module 130 may also be implemented using other circuit structures.

[0141] The first sub-switch module 191 may include a first switch transistor Tsw1 , a first electrode of the first switch transistor Tsw1 connected to the reference voltage terminal Vref, a second electrode of the first switch transistor Tsw1 connected to the preset node A, and a gate of the first switch transistor Tsw1 connected to the enable signal terminal EM.

[0142] The data writing module 140 may include a fourth transistor T4, a first electrode of the fourth transistor T4 being connected to the data signal terminal Vdata, a second electrode of the fourth transistor T4 being connected to the preset node A, and a gate of the fourth transistor T4 being connected to the second gate signal terminal Gn-P. The fourth transistor T4 may be configured to transmit the signal of the data signal terminal Vdata to the preset node A in response to the signal of the second gate signal terminal Gn-P. The second light-emitting control module 160 may include a sixth transistor T6, a first electrode of the sixth transistor T6 being connected to the third node N3, a second electrode of the sixth transistor T6 being connected to the anode of the light-emitting device OLED, and a gate of the sixth transistor T6 being connected to the enable signal terminal EM. The sixth transistor T6 may be configured to transmit the driving current of the third node N3 to the anode of the light-emitting device OLED in response to the signal of the enable signal terminal EM. The third reset module 170 may include a seventh transistor T7, a first electrode of the seventh transistor T7 being connected to the second initialization signal terminal Vinit2, a second electrode of the seventh transistor T7 being connected to the anode of the light-emitting device OLED, and a gate of the seventh transistor T7 being connected to the scan signal terminal Scan. The seventh transistor T7 may be configured to transmit the second initialization signal to the anode of the light-emitting device OLED in response to the signal of the scan signal terminal Scan to reset the light-emitting device OLED. In this exemplary embodiment, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the first switch transistor Tsw1 may all be P-type transistors, thereby facilitating reduced overall power consumption of the pixel driving circuit. Furthermore, the coupling module 200 may include a storage capacitor Cst, wherein a first electrode of the storage capacitor Cst is connected to the first node N1, and a second electrode of the storage capacitor Cst is connected to a predetermined node A.

[0143] Figure 23 is a timing diagram of each node of the pixel driving circuit shown in Figure 22. In the figure, Re-N represents the timing of the first reset signal terminal, Gn-N represents the timing of the first gate signal terminal, Gn-P represents the timing of the second gate signal terminal, Scan represents the timing of the scan signal terminal, and EM represents the timing of the enable signal terminal. The driving process of this pixel driver can include a refresh frame and a hold frame. The refresh frame can include a reset phase, a data writing phase, and a light-emitting phase, and the hold frame can include a reset phase and a light-emitting phase.

[0144] As shown in FIG23 , during the reset phase t1 of the refresh frame, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and the enable signal terminal EM outputs a low-level signal. FIG24 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the reset phase of the refresh frame. As shown in FIG24 , the first transistor T1, the seventh transistor T7, and the first switch transistor Tsw1 are turned on, and the other transistors are turned off. During this process, the voltage at the preset node A is Vref, the first initialization signal is transmitted to the first node N1 to reset the first node N1, and the second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED. As a result, the voltage at the first node N1 becomes Vinit1, and the voltage difference between the first node N1 and the second node N2 is Vinit1-VDD, which is the bias voltage Vgs of the driving transistor DT.

[0145] During the data writing phase t2 of the refresh frame, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a low-level signal, the scan signal terminal Scan outputs a high-level signal, and the enable signal terminal EM outputs a high-level signal. FIG25 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the data writing phase of the refresh frame. As shown in FIG25 , the second transistor T2 and the fourth transistor T4 are turned on. At this time, the data signal provided by the data signal terminal Vdata is written to the preset node A. The driving transistor DT is turned on under the control of the voltage difference between the first node N1 and the second node N2, i.e., the bias voltage. When the potential of the first node N1 becomes VDD+Vth (Vth is the threshold voltage of the driving transistor DT), the bias voltage Vgs of the driving transistor DT is equal to 0. At this time, the driving transistor DT is turned off, and the threshold voltage Vth of the driving transistor DT is written to the first node N1.

[0146] During the light-emitting phase t3 of the refresh frame, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the enable signal terminal EM outputs a low-level signal. Figure 26 is an equivalent circuit diagram of the pixel driving circuit of Figure 22 during the light-emitting phase of the refresh frame. As shown in Figure 26, the first switching transistor Tsw1 and the sixth transistor T6 are turned on, and the reference voltage signal Vref is written to the preset node A. The voltage change of the preset node A is ΔVA = Vref - Vdata. At the same time, the first node N1 is floating, and the storage capacitor Cst couples the voltage change ΔVA of the preset node A to the first node N1, so that the voltage of the first node N1 becomes Vn1 = VDD + Vth + (Vref - Vdata). A loop is formed from the first power supply terminal VDD to the second power supply terminal VSS, and the light-emitting device OLED emits light under the driving current provided by the driving transistor DT.

[0147] According to the current formula: I=1 / 2k(V GS -Vth) 2 (1)

[0148] The above V GS Substituting into equation (1), we can get the drive current: I = 1 / 2k (Vref - Vdata) 2 (2)

[0149] It can be seen that the driving current is only related to the reference voltage Vref and the data voltage Vdata, and has nothing to do with the voltage of the first voltage terminal Vdd (driving voltage). Compensation of the threshold voltage and the driving voltage is achieved, so that the driving voltage at different positions in the driving circuit is not affected by the voltage drop of the first power line itself, thereby achieving IR drop compensation on the first power line.

[0150] During the reset phase t1' of the hold frame, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. FIG27 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the reset phase of the hold frame. As shown in FIG27 , the first transistor T1 and the seventh transistor T7 are turned on, and the other transistors are turned off. The preset node A is floating. At the same time, the first transistor T1 is turned on to write the first initialization signal to the first node N1. During this phase, the voltage change at the first node N1 is ΔVN1 = Vinit1 - [VDD + Vth + (Vref - Vdata)]. The storage capacitor Cst couples this voltage change to the preset node A, so that the voltage at the preset node A becomes VA = Vref + Vinit1 - [VDD + Vth + (Vref - Vdata)]. At this time, the voltage difference between the first node N1 and the second node N2 is Vinit1-VDD, that is, the bias voltage Vgs of the driving transistor DT is Vinit1-VDD. It can be seen that the bias voltage of the driving transistor DT is the same as the bias voltage in the reset stage in the refresh frame, so that the driving transistor DT has the same bias voltage in the hold frame and the refresh frame, thereby eliminating or improving the display brightness difference between the refresh frame and the hold frame caused by the different bias voltages of the driving transistor DT.

[0151] During the light-emitting phase t3' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the enable signal terminal EM outputs a low-level signal. FIG28 is an equivalent circuit diagram of the pixel driving circuit of FIG22 during the light-emitting phase of the hold frame. As shown in FIG28 , the first switching transistor Tsw1 and the sixth transistor T6 are turned on, the reference voltage signal Vref is written to the preset node A, and the voltage of the preset node A returns to Vref. The voltage change of the preset node A is ΔVA = Vref - [Vref + Vinit1 - [VDD + Vth + (Vref - Vdata)]] = [VDD + Vth + (Vref - Vdata)] - Vinit1. At the same time, the first node N1 is floating, and the storage capacitor Cst couples the voltage change ΔVA of the preset node A to the first node N1, so that the voltage of the first node N1 becomes VN1 = VDD + Vth + (Vref - Vdata), which is the same as the voltage in the light-emitting stage of the refresh frame. The light-emitting device OLED emits light under the action of the driving current provided by the driving transistor DT.

[0152] It can be seen that in the pixel driving circuit provided by this exemplary embodiment, by adding a gate reset process for the driving transistor DT during the hold frame, the bias voltage Vgs applied to the driving transistor DT is consistent with the bias voltage during the reset phase t1 of the refresh frame. Furthermore, the bias voltage is Vinit1-VDD, independent of the voltage of the data signal Vdata. This effectively resolves the incompatibility issues between different brightness levels or high and low grayscales. Furthermore, after the first node N1 acquires the threshold voltage of the driving transistor DT during the data write phase, the driving transistor DT is nearly cut off, and the impact of this process on the state of the driving transistor DT is minimized. Thus, the pixel driving circuit and driving method of this exemplary embodiment ensure consistent operating conditions during the refresh frame and the hold frame, thereby eliminating brightness differences between the hold frame and the refresh frame and improving the flickering effect of low-frequency driving.

[0153] FIG29 is a schematic diagram of the structure of a pixel driving circuit according to another embodiment of the present disclosure. As shown in FIG29 , in an exemplary embodiment, the constant voltage terminal VM is a reference voltage terminal Vref, that is, the preset node A is connected to the reference voltage terminal Vref via the first switch module 190. The switch signal terminal SW may include a first switch signal terminal and a second switch signal terminal, and the reset signal terminal Re may include a first reset signal terminal Re-N and a second reset signal terminal Re-P. The first switch signal terminal may be multiplexed with the second reset signal terminal Re-P, and the second switch signal terminal may be multiplexed with the enable signal terminal. The cathode of the light-emitting device OLED may be connected to the second power supply terminal VSS, and the second node N2 may be directly connected to the first power supply terminal VDD. The first switch module 190 may include a first sub-switch module 191 and a second sub-switch module 192. The first sub-switch module 191 is connected to the reference voltage terminal Vref, the first node N1, and the enable signal terminal EM. In this circuit structure, the first sub-switch module 191 can be turned on during the light-emitting phase, that is, in response to the signal of the enable signal terminal EM, it is turned on to use the voltage signal of the reference voltage terminal Vref to stabilize the preset node A, so that the coupling module 200 can couple the voltage change of the preset node A to the first node N1. The second sub-switch module 192 is connected to the reference voltage terminal Vref, the preset node A, and the second reset signal terminal Re-P. The second sub-switch module 192 can be turned on in response to the signal of the second reset signal terminal Re-P to stabilize the preset node A using the voltage signal of the reference voltage terminal Vref, or turned off in response to the signal of the second reset signal terminal Re-P to control the preset node A to float.

[0154] The difference from the circuit shown in Figure 22 is that this exemplary embodiment adds a second sub-switch module 192, which is turned on in the reset phase to use the reference voltage terminal Vref to stabilize the preset node A, and the first sub-switch module 191 can be turned on only in the light-emitting phase.

[0155] As shown in FIG29 , in this exemplary embodiment, the pixel driving circuit may also include a first transmission module 120, a data writing module 140, a second light-emitting control module 160, and a third reset module 170. The pixel driving circuit may also be implemented using transistors. It is noteworthy that the first reset module 110, the driving module 130, the first sub-switch module 191, the first transmission module 120, the data writing module 140, the second light-emitting control module 160, and the third reset module 170 in this exemplary embodiment may have the same circuit structure as the corresponding modules in FIG22 .

[0156] As shown in FIG. 29 , in this exemplary embodiment, the first sub-switch module 191 may include a first switching transistor Tsw1, and the second sub-switch module 192 may include a second switching transistor Tsw2. The second switching transistor Tsw2 may be a P-type transistor. A first electrode of the second switching transistor Tsw2 is connected to the reference voltage terminal Vref, a second electrode of the second switching transistor Tsw2 is connected to the preset node A, and a gate of the second switching transistor Tsw2 is connected to the second reset signal terminal Re-P. The second switching transistor Tsw2 may be configured to transmit a voltage signal from the reference voltage terminal Vref to the preset node A in response to a signal from the second reset signal terminal Re-P, thereby stabilizing the voltage of the preset node A using the reference voltage signal, or may be configured to be turned off in response to a signal from the second reset signal terminal Re-P to control the floating of the preset node A. In this circuit structure, the first switching transistor Tsw1 may be turned on during the light-emitting phase to couple the voltage change at the preset node A to the first node N1 via the coupling effect of the storage capacitor Cst.

[0157] Figure 30 is a timing diagram of each node of the pixel driving circuit shown in Figure 29. In the figure, Re-P represents the timing of the second reset signal terminal, Re-N represents the timing of the first reset signal terminal, Gn-N represents the timing of the first gate signal terminal, Gn-P represents the timing of the second gate signal terminal, Scan represents the timing of the scan signal terminal, and EM represents the timing of the enable signal terminal. The driving process of this pixel driver can include a refresh frame and a hold frame. The refresh frame can include a reset phase, a data writing phase, and a light-emitting phase, and the hold frame can include a reset phase and a light-emitting phase.

[0158] As shown in FIG30 , during the reset phase t1 of the refresh frame, the second reset signal terminal Re-P outputs a low-level signal, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. FIG31 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the reset phase of the refresh frame. As shown in FIG31 , the first transistor T1, the seventh transistor T7, and the second switch transistor Tsw2 are turned on, and the other transistors are turned off. During this process, the voltage at the preset node A is Vref, the first initialization signal is transmitted to the first node N1 to reset the first node N1, and the second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED. As a result, the voltage at the first node N1 becomes Vinit1, and the voltage difference between the first node N1 and the second node N2 is Vinit1-VDD, which is the bias voltage Vgs of the driving transistor DT.

[0159] During the data writing phase t2 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a low-level signal, the scan signal terminal Scan outputs a high-level signal, and the enable signal terminal EM outputs a high-level signal. FIG32 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the data writing phase of the refresh frame. As shown in FIG32, the second transistor T2 and the fourth transistor T4 are turned on. At this time, the data signal provided by the data signal terminal Vdata is written to the preset node A. The driving transistor DT is turned on under the control of the voltage difference between the first node N1 and the second node N2, i.e., the bias voltage. When the potential of the first node N1 becomes VDD+Vth (Vth is the threshold voltage of the driving transistor DT), the bias voltage Vgs of the driving transistor DT is equal to 0. At this time, the driving transistor DT is turned off, and the threshold voltage Vth of the driving transistor DT is written to the first node N1.

[0160] During the light-emitting phase t3 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the enable signal terminal EM outputs a low-level signal. Figure 33 is an equivalent circuit diagram of the pixel driving circuit of Figure 29 during the light-emitting phase of the refresh frame. As shown in Figure 33, the first switching transistor Tsw1 and the sixth transistor T6 are turned on, and the reference voltage signal Vref is written to the preset node A. The voltage change of the preset node A is ΔVA = Vref - Vdata. At the same time, the first node N1 is floating, and the storage capacitor Cst couples the voltage change ΔVA of the preset node A to the first node N1, so that the voltage of the first node N1 becomes Vn1 = VDD + Vth + (Vref - Vdata). A loop is formed from the first power supply terminal VDD to the second power supply terminal VSS, and the light-emitting device OLED emits light under the driving current provided by the driving transistor DT.

[0161] According to the current formula: I=1 / 2k(V GS -Vth) 2 (1)

[0162] The above V GS Substituting into equation (1), we can get the drive current: I = 1 / 2k (Vref - Vdata) 2 (2)

[0163] It can be seen that the driving current is only related to the reference voltage Vref and the data voltage Vdata, and has nothing to do with the voltage of the first voltage terminal Vdd (driving voltage). Compensation of the threshold voltage and the driving voltage is achieved, so that the driving voltage at different positions in the driving circuit is not affected by the voltage drop of the first power line itself, thereby achieving IR drop compensation on the first power line.

[0164] During the reset phase t1' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and the enable signal terminal EM outputs a high-level signal. FIG34 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the reset phase of the hold frame. As shown in FIG34, the first transistor T1 and the seventh transistor T7 are turned on, and the other transistors are turned off. The preset node A is floating. At the same time, the first transistor T1 is turned on to write the first initialization signal to the first node N1. During this phase, the voltage change at the first node N1 is ΔVN1 = Vinit1 - [VDD + Vth + (Vref - Vdata)]. The storage capacitor Cst couples this voltage change to the preset node A, so that the voltage of the preset node A becomes VA = Vref + Vinit1 - [VDD + Vth + (Vref - Vdata)]. At this time, the voltage difference between the first node N1 and the second node N2 is Vinit1-VDD, that is, the bias voltage Vgs of the driving transistor DT is Vinit1-VDD. It can be seen that the bias voltage of the driving transistor DT is the same as the bias voltage in the reset stage in the refresh frame, so that the driving transistor DT has the same bias voltage in the hold frame and the refresh frame, thereby eliminating or improving the display brightness difference between the refresh frame and the hold frame caused by the different bias voltages of the driving transistor DT.

[0165] During the light-emitting phase t3' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the enable signal terminal EM outputs a low-level signal. FIG35 is an equivalent circuit diagram of the pixel driving circuit of FIG29 during the light-emitting phase of the hold frame. As shown in FIG35 , the first switching transistor Tsw1 and the sixth transistor T6 are turned on, the reference voltage signal Vref is written to the preset node A, and the voltage of the preset node A returns to Vref. The voltage change of the preset node A is ΔVA = Vref - [Vref + Vinit1 - [VDD + Vth + (Vref - Vdata)]] = [VDD + Vth + (Vref - Vdata)] - Vinit1. At the same time, the first node N1 is floating, and the storage capacitor Cst couples the voltage change ΔVA of the preset node A to the first node N1, so that the voltage of the first node N1 becomes VN1 = VDD + Vth + (Vref - Vdata), which is the same as the voltage in the light-emitting stage of the refresh frame. The light-emitting device OLED emits light under the action of the driving current provided by the driving transistor DT.

[0166] It can be seen that in the pixel driving circuit provided by this exemplary embodiment, by adding a gate reset process for the driving transistor DT during the hold frame, the bias voltage Vgs applied to the driving transistor DT is consistent with the bias voltage during the reset phase t1 of the refresh frame. Furthermore, the bias voltage is Vinit1-VDD, independent of the voltage of the data signal Vdata. This effectively resolves the incompatibility issues between different brightness levels or high and low grayscales. Furthermore, after the first node N1 acquires the threshold voltage of the driving transistor DT during the data write phase, the driving transistor DT is nearly cut off, and the impact of this process on the state of the driving transistor DT is minimized. Thus, the pixel driving circuit and driving method of this exemplary embodiment ensure consistent operating conditions during the refresh frame and the hold frame, thereby eliminating brightness differences between the hold frame and the refresh frame and improving the flickering effect of low-frequency driving.

[0167] FIG36 is a schematic diagram of the structure of a pixel driving circuit according to another embodiment of the present disclosure. As shown in FIG36 , in an exemplary embodiment, the constant voltage terminal VM is a reference voltage terminal Vref, that is, the preset node A is connected to the reference voltage terminal Vref via the first switch module 190. The switch signal terminal SW may include a first switch signal terminal and a second switch signal terminal, the reset signal terminal Re may include a first reset signal terminal Re-N and a second reset signal terminal Re-P, and the enable signal terminal may include a first enable signal terminal EM1 and a second enable signal terminal EM2. The first switch signal terminal may multiplex the second reset signal terminal Re-P, and the second switch signal terminal may multiplex the second enable signal terminal EM2. The cathode of the light-emitting device OLED may be connected to the second power supply terminal VSS. The pixel driving circuit may further include a second reset module 180 and a first light emission control module 150. The second reset module 180 is connected between the second node N2 and the third initialization signal terminal Vinit3 and is also connected to the scan signal terminal Scan. The second reset module 180 may be configured to transmit the signal of the third initialization signal terminal Vinit3 to the second node N2 in response to the signal of the scan signal terminal Scan to reset the second node N2. The first light emission control module 150 is connected between the second node N2 and the first power supply terminal VDD and is also connected to the first enable signal terminal EM1. The first light emission control module 150 may be configured to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to the signal of the first enable signal terminal EM1. In addition, the pixel driving circuit may also include the entire structure of the pixel driving circuit shown in FIG. 29 , which will not be further described here.

[0168] As shown in FIG36 , in an exemplary embodiment, the pixel driving circuit can also be implemented using transistors. For example, the second reset module 180 may include an eighth transistor T8, wherein a first electrode of the eighth transistor T8 is connected to the second node N2, a second electrode of the eighth transistor T8 is connected to the third initialization signal terminal Vinit3, and a gate of the eighth transistor T8 is connected to the scan signal terminal Scan. The eighth transistor T8 can be configured to transmit the signal of the third initialization signal terminal Vinit3 to the second node N2 in response to the signal of the scan signal terminal Scan, thereby resetting the second node N2. The first light emission control module 150 may include a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the second node N2, and a gate of the fifth transistor T5 is connected to the first enable signal terminal EM1. The fifth transistor T5 can be configured to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to the signal of the first enable signal terminal EM1. In this exemplary embodiment, both the fifth transistor T5 and the eighth transistor T8 can be P-type transistors. The specific circuits of other modules in this exemplary embodiment can be seen in FIG29 and will not be described in detail here.

[0169] Figure 37 is a timing diagram of each node in Figure 36. In the figure, Re-P represents the timing of the second reset signal terminal Re-P, Re-N represents the timing of the first reset signal terminal, Gn-N represents the timing of the first gate signal terminal, Gn-P represents the timing of the second gate signal terminal, Scan represents the timing of the scan signal terminal, EM1 represents the timing of the first enable signal terminal, and EM2 represents the timing of the second enable signal terminal. The driving process of the pixel drive may include a refresh frame and a hold frame. The refresh frame may include a reset phase, a data writing phase, and a light-emitting phase, and the hold frame may include a reset phase and a light-emitting phase.

[0170] As shown in Figure 37, during the reset phase t1 of the refresh frame, the second reset signal terminal Re-P outputs a low-level signal, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and the first enable signal terminal EM1 and the second enable signal terminal EM2 both output high-level signals. Figure 38 is an equivalent circuit diagram of the pixel driving circuit of Figure 36 during the reset phase of the refresh frame. As shown in Figure 38, the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the second switch transistor Tsw2 are turned on, and the other transistors are turned off. During this process, the voltage at node A is preset to Vref. The first initialization signal is transmitted to the first node N1 to reset the first node N1, the second initialization signal is transmitted to the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED, and the third initialization signal is transmitted to the second node N2 to reset the second node N2, so that the voltage of the first node N1 becomes Vinit1, and the voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, which is the bias voltage Vgs of the driving transistor DT.

[0171] During the data writing phase t2 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a high-level signal, the second gate signal terminal Gn-P outputs a low-level signal, the scan signal terminal Scan outputs a high-level signal, the first enable signal terminal EM1 outputs a low-level signal, and the second enable signal terminal EM2 outputs a high-level signal. Figure 39 is an equivalent circuit diagram of the pixel driving circuit of Figure 36 during the data writing phase of the refresh frame. As shown in Figure 39, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. At this time, the data signal provided by the data signal terminal Vdata is written to the preset node A. The voltage of the second node N2 becomes VDD, and the driving transistor DT is turned on under the control of the voltage difference between the first node N1 and the second node N2, that is, the bias voltage. When the potential of the first node N1 becomes VDD+Vth (Vth is the threshold voltage of the driving transistor DT), the bias voltage Vgs of the driving transistor DT is 0. At this time, the driving transistor DT is turned off, so that the threshold voltage Vth of the driving transistor DT is written into the first node N1.

[0172] During the pre-emission bias phase t3 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and both the first enable signal terminal EM1 and the second enable signal terminal EM2 output high-level signals. Figure 40 is an equivalent circuit diagram of the pixel drive circuit of Figure 36 during the pre-emission bias phase of the refresh frame. As shown in Figure 40, the seventh transistor T7 and the eighth transistor T8 are turned on, and the third initialization signal resets the second node N2. It should be understood that the pre-emission bias phase in this exemplary embodiment can also achieve the effects of improving the hysteresis of the drive transistor DT and eliminating afterimages as described in the above embodiments, and will not be further described here.

[0173] During the light-emitting phase t4 of the refresh frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the first enable signal terminal EM1 and the second enable signal terminal EM2 both output low-level signals. Figure 41 is an equivalent circuit diagram of the pixel driving circuit of Figure 36 during the light-emitting phase of the refresh frame. As shown in Figure 41 , the first switching transistor Tsw1, the fifth transistor T5, and the sixth transistor T6 are turned on, and the reference voltage signal Vref is written to the preset node A. The voltage change at the preset node A is ΔVA = Vref - Vdata. At the same time, the first node N1 is floating, and the storage capacitor Cst couples the voltage change ΔVA at the preset node A to the first node N1. As a result, the voltage at the first node N1 becomes VN1 = VDD + Vth + (Vref - Vdata). A loop is formed from the first power supply terminal VDD to the second power supply terminal VSS, and the light-emitting device OLED emits light under the driving current provided by the driving transistor DT. This process is the same as the light-emitting process of the circuit shown in Figure 29 and will not be described in detail here.

[0174] During the reset phase t1' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a high-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and the first enable signal terminal EM1 and the second enable signal terminal EM2 both output high-level signals. Figure 42 is an equivalent circuit diagram of the pixel driving circuit of Figure 36 during the reset phase of the hold frame. As shown in Figure 42, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, and the other transistors are turned off. The preset node A is floated. At the same time, the first transistor T1 is turned on to write a first initialization signal to the first node N1. The voltage difference between the first node N1 and the second node N2 is Vinit1-Vinit3, which is the bias voltage Vgs of the drive transistor DT. It can be seen that the bias voltage of the drive transistor DT is the same as the bias voltage during the reset phase of the refresh frame. Therefore, the drive transistor DT has the same bias voltage during the hold frame and the refresh frame, thereby eliminating or improving the display brightness difference caused by the different bias voltages of the drive transistor DT between the refresh frame and the hold frame. During this phase, the voltage change of the first node N1 is ΔVN1=Vinit1-[VDD+Vth+(Vref-Vdata)]. The storage capacitor Cst couples this voltage change to the preset node A, so that the voltage of the preset node A becomes VA=Vref+Vinit1-[VDD+Vth+(Vref-Vdata)]=Vinit1-VDD-Vth+Vdata.

[0175] Then, as shown in FIG37 , the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, the first enable signal terminal EM1 outputs a low-level signal, and the second enable signal terminal EM2 outputs a high-level signal. As a result, the voltage of the second node N2 becomes VDD. At this time, the voltage difference between the first node N1 and the second node N2 is Vinit1-VDD, i.e., the bias voltage Vgs of the driving transistor DT = Vinit1-VDD.

[0176] During the pre-emission bias phase t3' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a low-level signal, and both the first enable signal terminal EM1 and the second enable signal terminal EM2 output high-level signals. Figure 43 is an equivalent circuit diagram of the pixel driving circuit of Figure 36 during the pre-emission bias phase of the hold frame. As shown in Figure 43, the seventh transistor T7 and the eighth transistor T8 are turned on, and the third initialization signal resets the second node N2.

[0177] During the light-emitting phase t4' of the hold frame, the second reset signal terminal Re-P outputs a high-level signal, the first reset signal terminal Re-N outputs a low-level signal, the first gate signal terminal Gn-N outputs a low-level signal, the second gate signal terminal Gn-P outputs a high-level signal, the scan signal terminal Scan outputs a high-level signal, and the first enable signal terminal EM1 and the second enable signal terminal EM2 both output low-level signals. FIG44 is an equivalent circuit diagram of the pixel driving circuit of FIG36 during the data writing phase of the hold frame. As shown in FIG44, the first switching transistor Tsw1, the fifth transistor T5, and the sixth transistor T6 are turned on, the reference voltage signal Vref is written to the preset node A, and the voltage of the preset node A returns to Vref. The voltage change of the preset node A is ΔVA = Vref - [Vref + Vinit1 - [VDD + Vth + (Vref - Vdata)]] = [VDD + Vth + (Vref - Vdata)] - Vinit1. At the same time, the first node N1 floats, and the storage capacitor Cst couples the voltage change ΔVA of the preset node A to the first node N1, so that the voltage of the first node N1 becomes Vn1 = VDD + Vth + (Vref - Vdata), which is the same as the voltage in the light-emitting stage of the refresh frame. The light-emitting device OLED emits light under the action of the driving current provided by the driving transistor DT.

[0178] The present disclosure also provides a display device, which may include the display panel described in any of the above embodiments.

[0179] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A pixel driving circuit, wherein: include: A first reset module, connected to the first node, the first initialization signal terminal and the reset signal terminal, the first reset module being used to write the first initialization signal into the first node in response to a signal from the reset signal terminal; A driving module connected to the first node, the second node and the third node, wherein the driving module provides a driving current to the third node based on the voltages of the first node and the second node; A coupling module, connecting the first node and a preset node, the coupling module being used to couple the voltage change of the first node to the preset node and vice versa; The first switch module is connected to the constant voltage terminal, the preset node and the switch signal terminal. The first switch module is used to respond to the signal of the switch signal terminal to turn on so as to stabilize the preset node using the constant voltage terminal, or respond to the signal of the switch signal terminal to turn off so as to control the preset node to float.

2. The pixel driving circuit according to claim 1, wherein: The constant voltage terminal is a first power supply terminal; The pixel driving circuit further includes: The first transmission module is connected to the first node, the third node and the gate signal terminal, and is used for switching on or off the connection between the first node and the third node in response to a signal from the gate signal terminal.

3. The pixel driving circuit according to claim 2, wherein: The reset signal terminal includes a first reset signal terminal, and the first reset module is connected to the first reset signal terminal; the gate signal terminal includes a first gate signal terminal, and the first transmission module is connected to the first gate signal terminal; The conduction level polarities of the first resetting module and the first transmission module are opposite to the conduction level polarity of the driving module.

4. The pixel driving circuit according to claim 3, wherein: The first reset module includes: A first transistor, a first electrode connected to the first initialization signal terminal, a second electrode connected to the first node, a gate connected to the first reset signal terminal, and the first transistor is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initialization signal terminal to the first One node; The first transmission module includes: a second transistor, a first electrode connected to the first node, a second electrode connected to the third node, a gate connected to the first gate signal terminal, and the second transistor is used to connect the third node to the first node in response to a signal at the first gate signal terminal; The driving module comprises: a driving transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first node, and the driving transistor provides a driving current to the third node based on a voltage between the first node and the second node; The first transistor and the second transistor are both N-type transistors, and the driving transistor is a P-type transistor.

5. The pixel driving circuit according to claim 2, wherein: The reset signal terminal includes a second reset signal terminal, and the first reset module is connected to the second reset signal terminal; the gate signal terminal includes a first gate signal terminal and a second gate signal terminal, and the first transmission module is connected to the second gate signal terminal; The pixel driving circuit further includes: A second switch module is serially connected between the first node and the first reset module and connected to the first gate signal terminal, and the second switch module is at least used to connect the first reset signal module to the first node in response to the signal of the first gate signal terminal to transmit the signal of the first initialization signal terminal to the first node; The conduction levels of the first resetting module and the first transmission module are of the same polarity as the conduction level of the driving module, and the conduction level of the second switching module is of opposite polarity to the conduction level of the driving module.

6. The pixel driving circuit according to claim 5, wherein: The first reset module includes: a first transistor, a first electrode connected to the first initialization signal terminal, a second electrode connected to the fourth node, a gate connected to the first reset signal terminal, and the first transistor is used to transmit the signal of the first initialization signal terminal to the fourth node in response to the signal of the first reset signal terminal; The first transmission module includes: a second transistor, a first electrode connected to the fourth node, a second electrode connected to the third node, The gate is connected to the first gate signal terminal, and the second transistor is used to connect the third node with the fourth node in response to the signal of the first gate signal terminal; The second switch module comprises: a tenth transistor, a first electrode connected to the first node, a second electrode connected to the fourth node, a gate connected to the first gate signal terminal, and the tenth transistor is used to turn on or off the connection between the first node and the fourth node in response to a signal at the first gate signal terminal; The driving module comprises: a driving transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first node, and the driving transistor provides a driving current to the third node based on a voltage between the first node and the second node; The first transistor, the second transistor and the driving transistor are all P-type transistors, and the tenth transistor is an N-type transistor.

7. The pixel driving circuit according to claim 1, wherein: The constant voltage terminal is a first power supply terminal; The pixel driving circuit further includes: A first transmission module is serially connected between the first node and the first reset module and connected to the first gate signal terminal. The first transmission module and the first reset module are connected to a third node. The first transmission module is at least used to respond to the signal of the first gate signal terminal to conduct the connection between the first reset module and the third node, so as to transmit the signal of the first initialization signal terminal to the first node; Wherein, the reset signal terminal includes a second reset signal terminal, and the first reset circuit is connected to the second reset signal terminal; The conduction level of the first reset module has the same polarity as the conduction level of the driving module, and the conduction level of the first transmission module has an opposite polarity to that of the driving module.

8. The pixel driving circuit according to claim 7, wherein: The first reset module includes: a first transistor, wherein a first electrode is connected to the first initialization signal terminal, a second electrode is connected to the third node, and a gate is connected to the first reset signal terminal, and the first transistor is used to transmit the signal of the first initialization signal terminal to the third node in response to the signal of the first reset signal terminal; The first transmission module includes: a second transistor, a first electrode connected to the first node, a second electrode connected to the third node, a gate connected to the first gate signal terminal, and the second transistor is used to connect the third node to the first node in response to a signal at the first gate signal terminal; The driving module comprises: a driving transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first node, and the driving transistor provides a driving current to the third node based on a voltage between the first node and the second node; The first transistor and the driving transistor are both P-type transistors, and the second transistor is an N-type transistor.

9. The pixel driving circuit according to claim 2 or 7, wherein: The pixel driving circuit further includes: A second reset module is connected to the second node, the third initialization signal terminal and the scan signal terminal, and the second reset module is used to write the signal of the third initialization signal terminal into the second node in response to the signal of the scan signal terminal; a data writing module connected to the second node, the data signal terminal and the second gate signal terminal, the data writing module being used for transmitting the signal of the data signal terminal to the second node in response to the signal of the second gate signal terminal; a first light-emitting control module connected to the second node, the first power supply terminal and the enable signal terminal, and configured to transmit a voltage signal of the first power supply terminal to the second node in response to a signal of the enable signal terminal; a second light-emitting control module connected to the third node, the anode of the light-emitting device and the enable signal terminal, and configured to transmit the current signal of the third node to the anode of the light-emitting device in response to the signal of the enable signal terminal; A third reset module is connected to the anode of the light-emitting device, the second initialization signal terminal and the scan signal terminal. The third reset module is used to respond to the signal of the scan signal terminal and transmit the signal of the second initialization signal terminal to the anode of the light-emitting device to reset the anode of the light-emitting device.

10. The pixel driving circuit according to claim 9, wherein: The second reset module includes: An eighth transistor, a first electrode connected to the third initialization signal terminal, a second electrode connected to the a second node, a gate of which is connected to the scan signal terminal, and the eighth transistor is used to transmit the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal to reset the second node; The data writing module comprises: a fourth transistor, a first electrode connected to the data signal terminal, a second electrode connected to the second node, a gate connected to the second gate signal terminal, and the fourth transistor is used to transmit the signal of the data signal terminal to the second node in response to the signal of the second gate signal terminal; The switch signal terminal includes a first switch signal terminal; The first light emitting control module comprises: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the enable signal terminal, the fifth transistor being used to transmit a voltage signal of the first power supply terminal to the second node in response to a signal of the enable signal terminal; The second light emitting control module comprises: a sixth transistor, wherein a first electrode is connected to the third node, a second electrode is connected to the anode of the light-emitting device, and a gate is connected to the enable signal terminal, and the sixth transistor is used to transmit the current signal of the third node to the anode of the light-emitting device in response to the signal of the enable signal terminal; The third reset module comprises: a seventh transistor, a first electrode connected to the second initialization signal terminal, a second electrode connected to the anode of the light-emitting device, and a gate connected to the scan signal terminal, the seventh transistor being used to transmit the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the scan signal terminal to reset the anode of the light-emitting device; The first switch module comprises: a first switch transistor, wherein a first electrode is connected to the preset node, a second electrode is connected to the first power supply terminal, and a gate is connected to the first switch signal terminal, and the first switch transistor is used to respond to a signal from the first switch signal terminal to conduct so as to stabilize the preset node using a voltage signal from the first power supply terminal, or to respond to a signal from the first switch signal terminal to shut down so as to control the preset node to float; The coupling module comprises: A storage capacitor, a first electrode connected to the first node, and a second electrode connected to the preset node; Among them, the first switch transistor, the fourth transistor to the eighth transistor are It is a P-type transistor.

11. The pixel driving circuit according to claim 1, wherein: The constant voltage terminal is a first power supply terminal; the pixel driving circuit further includes a first transmission module and a data writing module; the gate signal terminal includes a first gate signal terminal and a second gate signal terminal; The first transmission module is connected to the first node, the third node and the first gate signal terminal, and the first transmission module is used to turn on or off the connection between the first node and the third node in response to a signal from the first gate signal terminal; The data writing module is connected to the second node, the data signal terminal and the second gate signal terminal, and the data writing module is used to transmit the signal of the data signal terminal to the second node in response to the signal of the second gate signal terminal; or, the data writing module is connected to the preset node, the data signal terminal and the second gate signal terminal, and the data writing module is used to transmit the signal of the data signal terminal to the preset node in response to the signal of the second gate signal terminal; Wherein, the conduction level of the first transmission module is opposite in polarity to the conduction level of the data writing module; The conduction level output by the second gate signal terminal overlaps with the conduction level output by the first gate signal terminal, and the duration covered by the conduction level output by the second gate signal terminal is within the duration covered by the conduction level output by the first gate signal terminal.

12. The pixel driving circuit according to claim 1, wherein: When the non-conducting level output by the switch signal terminal overlaps with the conducting level output by the reset signal terminal, the duration covered by the conducting level output by the reset signal terminal is within the duration covered by the non-conducting level output by the switch signal terminal.

13. The pixel driving circuit according to claim 1, wherein: The constant voltage terminal is a reference voltage terminal, and the second node is also connected to the first power supply terminal.

14. The pixel driving circuit according to claim 13, wherein: The pixel driving circuit further includes: A second reset module is connected between the second node and the third initialization signal terminal and connected to the scan signal terminal, and the second reset module is used for transmitting the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal to reset the second node; The first light-emitting control module is connected between the second node and the first power supply terminal and connected to the first enable signal terminal. The first light-emitting control module is used to transmit the voltage signal of the first power supply terminal to the second node in response to the signal of the first enable signal terminal.

15. The pixel driving circuit according to claim 13 or 14, wherein: The switch signal terminal includes a second switch signal terminal, and the second switch signal terminal multiplexes an enable signal terminal; the first switch module includes: The first sub-switch module is connected to the reference voltage terminal, the preset node and the enable signal terminal. The first sub-switch module is at least used to respond to the signal of the enable signal terminal to be turned on to stabilize the preset node using the voltage signal of the reference voltage terminal, or to respond to the signal of the enable signal terminal to be turned off to control the preset node to float.

16. The pixel driving circuit according to claim 15, wherein: The reset signal terminal includes a second reset signal terminal, the switch signal terminal also includes a first switch signal terminal, and the first switch signal terminal multiplexes the second reset signal terminal; the enable signal terminal includes a first enable signal terminal and a second enable signal terminal, the second switch signal terminal multiplexes the second enable signal terminal, and the first sub-switch module is connected to the second enable signal terminal; The first switch module further includes: a second sub-switch module, connected to the reference voltage terminal, the preset node and the second reset signal terminal, the second sub-switch module being used for transmitting the voltage signal of the reference voltage terminal to the preset node in response to the signal of the second reset signal terminal; The conduction level phase of the second reset signal terminal does not overlap with the conduction level phase of the second enable signal terminal.

17. The pixel driving circuit according to claim 16, wherein: The pixel driving circuit further includes: a first transmission module, connected to the first node, the third node and a first gate signal terminal, the first transmission module being used to turn on or off the connection between the first node and the third node in response to a signal from the first gate signal terminal; The conduction levels of the first transmission module and the first reset module are opposite in polarity to the conduction level of the driving module.

18. The pixel driving circuit according to claim 17, wherein: The reset signal terminal also includes a first reset signal terminal; The first reset module includes: a first transistor, a first electrode connected to the first initialization signal terminal, a second electrode connected to the first node, a gate connected to the first reset signal terminal, and the first transistor is used to transmit the signal of the first initialization signal terminal to the first node in response to the signal of the first reset signal terminal; The first transmission module includes: a second transistor, a first electrode connected to the first node, a second electrode connected to the third node, a gate connected to a first gate signal terminal, and the second transistor is used to connect the third node to the first node in response to a signal at the first gate signal terminal; The driving module comprises: a driving transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first node, and the driving transistor provides a driving current to the third node based on a voltage between the first node and the second node; The first transistor and the second transistor are both N-type transistors, and the driving transistor is a P-type transistor.

19. The pixel driving circuit according to claim 17, wherein: The pixel driving circuit further includes: A data writing module, connected to the preset node, the data signal terminal and the second gate signal terminal, the data writing module is used to transmit the signal of the data signal terminal to the preset node in response to the signal of the second gate signal terminal; a second light-emitting control module, connected to the third node, the anode of the light-emitting device and the second enable signal terminal, the second light-emitting control module being used for transmitting the driving current of the third node to the anode of the light-emitting device in response to the signal of the second enable signal terminal; A third reset module is connected to the anode of the light-emitting device, the second initialization signal terminal and the scan signal terminal. The third reset module is used to respond to the signal of the scan signal terminal and transmit the signal of the second initialization signal terminal to the anode of the light-emitting device to reset the anode of the light-emitting device.

20. The pixel driving circuit according to claim 19, wherein: The data writing module comprises: A fourth transistor, a first electrode connected to the data signal terminal, a second electrode connected to the preset node point, the gate is connected to the second gate signal terminal, and the fourth transistor is used to transmit the signal of the data signal terminal to the preset node in response to the signal of the second gate signal terminal; The second light emitting control module comprises: a sixth transistor, wherein a first electrode is connected to the third node, a second electrode is connected to the anode of the light-emitting device, and a gate is connected to the second enable signal terminal, and the sixth transistor is used to transmit the driving current of the third node to the anode of the light-emitting device in response to the signal of the second enable signal terminal; The third reset module comprises: a seventh transistor, a first electrode connected to the second initialization signal terminal, a second electrode connected to the anode of the light-emitting device, and a gate connected to the scan signal terminal, the seventh transistor being used to transmit the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the scan signal terminal to reset the anode of the light-emitting device; The first sub-switch module comprises: a first switch transistor, wherein a first electrode is connected to a reference voltage terminal, a second electrode is connected to the preset node, and a gate is connected to the enable signal terminal, and the first switch transistor is used to respond to a signal from the second enable signal terminal to be turned on so as to stabilize the preset node using a voltage signal from the reference voltage terminal, or to respond to a signal from the second enable signal terminal to be turned off so as to control the preset node to float; The second sub-switch module includes: a second switch transistor, a first electrode connected to the reference voltage terminal, a second electrode connected to the preset node, a gate connected to the second reset signal terminal, and the first switch transistor is used to transmit the voltage signal of the reference voltage terminal to the preset node in response to the signal of the second reset signal terminal; The coupling module comprises: A storage capacitor, a first electrode connected to the first node, and a second electrode connected to a preset node; The second reset module includes: an eighth transistor, a first electrode connected to the second node, a second electrode connected to the third initialization signal terminal, and a gate connected to the scan signal terminal, the eighth transistor being used to transmit the signal of the third initialization signal terminal to the second node in response to the signal of the scan signal terminal to reset the second node; The first light emitting control module comprises: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the first enable signal terminal, the fifth transistor being used to transmit a voltage signal of the first power supply terminal to the second node in response to a signal of the first enable signal terminal; The first switch transistor, the second switch transistor, and the fourth transistor to the eighth transistor are all P-type transistors.

21. A driving method for a pixel driving circuit, wherein: Used to drive the pixel driving circuit according to any one of claims 1 to 20, the driving method comprising a refresh frame phase and a hold frame phase, the driving method comprising: In the reset phase of the light-emitting frame, the switch signal terminal and the reset signal terminal are respectively controlled to output a conduction level, the first switch module is turned on in response to the signal of the switch signal terminal to stabilize the preset node using the constant voltage terminal, and the first reset module is turned on in response to the signal of the reset signal terminal to write the signal of the first initialization signal terminal into the first node; In the reset phase of the holding frame, the switch signal terminal is controlled to output a non-conduction level and the reset signal terminal is controlled to output a conduction level, the first switch module is turned off in response to the signal of the switch signal terminal to make the preset node float, the first reset module is turned on in response to the signal of the reset signal terminal to write the signal of the first initialization signal terminal into the first node, and the coupling module couples the voltage change of the first node to the preset node; After the reset stage of the holding frame, the reset signal end is controlled to output a non-conduction level and the switch signal end is controlled to output a conduction level, the first reset module is turned off in response to the signal of the reset signal end to make the first node float, the first switch module is turned on in response to the signal of the switch signal end to stabilize the preset node using the constant voltage end, and the coupling module couples the voltage change of the preset node to the first node.

22. A display panel, wherein: A pixel driving circuit comprising the pixel driving circuit according to any one of claims 1 to 20.

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