Integrated Circuit Testability and Test Point Insertion Method, Device, Equipment, Medium

Abstract

The present application provides a method, apparatus, device, and medium for the testability of integrated circuits and test point insertion, which are applied to the field of integrated circuit testability design. First, it is judged the type of violation setting existing on the path (such as one or more combinations among "-from", "-through", and "-to"), and then according to different timing violation settings, different test point insertion strategies are adopted: for the "-from" and "-through" settings, test points are inserted after the last path that is not "-to", so as to use the test points to prevent the propagation of the X state backward; while for the "-to" setting, the relevant circuit nodes are masked (hidden or shielded) to control the X state from affecting subsequent tests. After inserting the test points, the derivation difficulty, running time, and the number of vectors of automatic test vector generation can be significantly reduced, and at the same time, the test coverage rate can be improved, having wide applicability and operability.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testability, and specifically relates to a method, device, equipment, and medium for integrated circuit testability and test point insertion. Background Art

[0002] With the continuous progress of integrated circuit (IC) manufacturing processes, the scale and integration of chips have been increasing day by day, making the testing of ICs particularly important. In integrated circuit design, the purpose of Design For Test (DFT) is to insert testable circuits during the design phase so that process or design defects in the chip can be efficiently detected during subsequent testing, thereby improving the ex-factory quality and reliability of the chip. In DFT design, the scan chain circuit (Scan) and Automatic Test Pattern Generation (ATPG) are two core components. The scan chain circuit allows test vectors and test results to be shifted inside the circuit, while ATPG is responsible for generating test vectors that can detect defects such as Stuck-At Faults (SAF) and Transition Faults (TF) in the circuit.

[0003] Important parameters for evaluating ATPG performance include the running duration of test vectors, test coverage, and the number of test vectors. However, in circuit design, there are timing violations, such as false paths or Multicycle Paths (MCP).

[0004] In ATPG testing, although DFT and ATPG can detect stuck-at and transition faults, for the timing violations in traditional circuit designs, these timing violation paths need to be processed additionally. If not handled properly, they will cause the indefinite state (X state) to propagate continuously in the circuit, increasing the difficulty of deriving test vectors, ultimately leading to an increase in test running time and the number of test vectors. At the same time, the test coverage will also decrease due to the propagation of the X state, increasing the difficulty of deriving test vectors and prolonging the test time.

[0005] Therefore, how to handle the timing violations in the design during the ATPG process has become an important technical challenge. Based on this, a new test technology solution is needed. Summary of the Invention

[0006] In view of this, the embodiments of the present specification provide an integrated circuit testability and test point insertion method, device, equipment, and medium, which adopt different test point insertion strategies for different violation paths, thereby avoiding the continuous propagation of indeterminate states (X states) in the circuit, thereby reducing the derivation difficulty of test vector generation, test running time, and the number of test vectors, etc. At the same time, the test coverage will also be significantly improved because it is not affected by the propagation of X states.

[0007] The embodiments of this specification provide the following technical solutions:

[0008] An integrated circuit test point insertion method, comprising:

[0009] Obtaining several timing violation paths of the circuit to be tested;

[0010] According to the capture path corresponding to each timing violation path in the test process, determine the path setting options of the capture path corresponding to each timing violation path; wherein the path setting options are used to characterize the path information of the capture path, and the path setting options include any of the following single options or a composite option of a combination of multiple options: -from, -through, -to, wherein -from is used to characterize the path starting point of the capture path, -through is used to characterize the path passing point of the capture path, and -to is used to characterize the path end point of the capture path;

[0011] A test point is inserted into each timing violation path, wherein the insertion process includes: if the capture path corresponding to the timing violation path contains more than one path setting options, a test point is inserted after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and the path setting option does not belong to the "-to" setting option, a test point is inserted after the timing violation path, otherwise the end point of the timing violation path is masked during automatic vector generation.

[0012] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0013] By inserting test points into the timing violation path in a targeted manner, the indeterminate state (X) on the violation path will not continue to propagate backward, so that the circuit can be fully tested to improve the test coverage. In addition, the propagation of the indeterminate state can be controlled and limited, which reduces the complexity of the automatic test pattern generation tool in deriving the test pattern. The specific insertion strategy depends on the different settings of the timing violation path ("-from", "-through", "-to"), which reduces the difficulty of ATPG derivation.

[0014] In addition, by inserting test points into the circuit, the test efficiency and quality of Transition ATPG for circuits with timing violations can be significantly improved. By precisely inserting test points to control the propagation of the floating state, the running time of ATPG and the number of test vectors are effectively reduced, and the test coverage is greatly improved at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 A test point circuit structure according to an embodiment of the present invention;

[0017] Figure 2 A method flow block diagram given according to different timing violations in an embodiment of the present invention;

[0018] Figure 3 A scan circuit according to an embodiment of the present invention;

[0019] Figure 4 A timing violation path according to an embodiment of the present invention;

[0020] Figure 5 For the Figure 4 timing violation path in;

[0021] Figure 6 A timing violation path according to an embodiment of the present invention;

[0022] Figure 7 For the Figure 6 timing violation path in;

[0023] Figure 8 A timing violation path according to an embodiment of the present invention;

[0024] Figure 9 For the Figure 8 timing violation path in;

[0025] Figure 10 A timing violation path according to an embodiment of the present invention;

[0026] Figure 11 A timing violation path according to an embodiment of the present invention;

[0027] Figure 12This is the solution to the timing violation path in the embodiments of the present invention for Figure 11 the timing violation path in

[0028] Figure 13 This is a timing violation path in the embodiments of the present invention;

[0029] Figure 14 This is a schematic diagram of a method for processing the testability of an integrated circuit in the present invention;

[0030] Figure 15 This is a schematic diagram of a device for inserting test points in an integrated circuit in the present invention;

[0031] Figure 16 This is a schematic diagram of a device for processing the testability of an integrated circuit in the present invention. Detailed implementation manners

[0032] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0034] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0035] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. The diagrams only show the components related to the present application, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0036] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0037] With the continuous progress of the manufacturing technology of integrated circuits (ICs for short), the scale and integration of chips have been significantly improved, which makes the testing of ICs crucial. Design for Test (DFT for short) is an important part of integrated circuit design. By embedding testable circuits in the design stage, it can effectively intercept chips with process or design defects, discover process problems, and thus improve the ex-factory quality and reliability of chips.

[0038] The combination of a scan chain circuit (Scan) and Automatic Test Pattern Generation (ATPG for short) can detect defects such as stuck-at faults (SAF for short) and transition faults (TF for short) in a circuit. The evaluation parameters of ATPG include the running time of test patterns, test coverage, and the number of test patterns. The goal is to generate a smaller number of test patterns in a shorter running time while achieving a higher fault coverage (Test Coverage, Cov for short), that is, to complete the testing of ICs with a higher coverage.

[0039] However, if a timing exception is set at the functional front end of the circuit, that is, a false path or a multi-cycle path (MCP for short) is set, then when generating transition test vectors, it is necessary to read in the set timing exception to avoid errors in simulation.

[0040] In addition, although DFT and ATPG can detect stuck-at and transition faults, for timing violations in traditional circuit designs, these timing violation paths need to be processed separately. If not handled properly, they can cause the propagation of indeterminate states (X-states) in the circuit, increasing the difficulty of deriving test vectors, ultimately leading to an increase in test run time and the number of test vectors. At the same time, the test coverage will also decrease due to the propagation of X-states, increasing the difficulty of deriving test vectors and prolonging the test time. These paths need to be processed separately in ATPG testing. If they cannot be handled, they will be regarded as X-states and continue to propagate backward in the circuit, which will make the derivation of test patterns more difficult, ultimately leading to an increase in run time and the number of test patterns, while reducing the coverage rate. The coverage rate will also decrease as the X-state propagates. Therefore, how to handle timing exceptions in the design during ATPG has become a technical challenge.

[0041] In view of this, through in-depth research and improvement exploration of circuits with timing violations, it is found that:

[0042] On the one hand, in integrated circuit design, for the problem of test vector generation caused by such timing violation paths, a circuit structure with test points inserted can be used to solve it. Then, corresponding control signals are adopted for the test point circuit structure, so that the test point path or the original path can be selected in the test mode, thereby identifying and isolating the unstable states in the circuit and improving the accuracy and efficiency of testing.

[0043] On the other hand, by means of the test point insertion strategy, the accuracy and efficiency of chip testing can be improved, timing violations can be effectively handled during the design phase, the propagation of indeterminate states during the test process can be reduced, thereby optimizing the generation of test vectors, reducing the test cost, and enhancing the reliability of the chip.

[0044] On the third hand, after the test point path is activated, it can allow the test signal to directly enter the test point without being affected by the indeterminate states in the original path. This design helps to control and switch the signal path during the test process, enhancing the testability and fault detection ability of the integrated circuit.

[0045] Generally speaking, for the problem of test point insertion in the testability design of integrated circuits with timing violation paths, by inserting test points in the circuit, it can effectively shorten the run time of the transition ATPG for circuits with timing violations, reduce the number of required test vectors, and significantly improve the test coverage rate. These improvements not only optimize the test process, reduce the test cost, but also enhance the reliability of the chip.

[0046] Based on this, the embodiments of this specification propose a timing-based test point insertion processing idea: different insertion test point strategies are adopted for different violation situations.

[0047] There are usually two statements for setting Timing Exception. One is set_false_path, and the other is set_multicycle. Although both of these two statements will affect the values captured by Scan Cells during Transition ATPG, as long as they can effectively prevent the Scan Cells from capturing the X state of the violation path during Transition ATPG, for these two statements, the same strategy for inserting Test Points can be adopted.

[0048] In addition, there are usually three setting options for the Timing Exception setting statement, namely "-from", "-through", and "-to". Its settings are relatively flexible, and one or all three of them can be set. However, because the "-to" statement is relatively special, since it is set at the end of the Timing Exception path and the ATPG tool will not propagate the X state further backward, there is no need to add Test Point control. Only mask the end point during ATPG testing to not test the transition fault (hide or mask); while for "-from" and "-through", the method of this application needs to be adopted to insert Test Points to prevent the ATPG tool from propagating the X state further backward.

[0049] Therefore, based on the statement characteristics of Timing Exception, for the process of inserting Test Points into the Timing Exception path, reference can be made to Figure 2 Illustration: First, determine whether there is a Timing Exception path. If there is, further determine whether there is only one option for the Timing Exception path setting; if there is only one statement, it is necessary to determine whether it is the "-to" statement. If it is not the "-to" statement, that is, "-from" or "-through" or a combination of the two, then insert the Test Point after the circuit where Timing Exception is set; for the case of only one "-to", then mask the circuit of Timing Exception so that the data it captures is X but the data for the shift operation is controllable. If there are multiple statements, then insert the Test Point after the path set by the last non-"-to" statement.

[0050] By inserting test points in integrated circuit design, the signals propagated from the starting control point can be effectively controlled. These test points serve as key positions for signal monitoring, ensuring that during the automatic test pattern generation (ATPG) process, the floating state (X-state) signals are effectively managed and prevented from further propagating to the subsequent parts of the circuit.

[0051] In addition, inserting test points avoids the inaccuracy of test results and the difficulty of fault diagnosis that may be caused by floating state signals, and can ensure that only stable and reliable signals are transmitted to the subsequent stages of the circuit, thereby improving the efficiency and accuracy of the automatic test pattern generation process, and at the same time enhancing the overall test coverage and fault detection ability of the circuit.

[0052] In summary, the present application can reduce the running time of Transition ATPG for circuits with Timing Exception, reduce the number of patterns of Transition ATPG, improve the coverage rate of Transition ATPG, has wide applicability, and the technical implementation is clear and has strong operability.

[0053] The following is a schematic illustration with reference to the accompanying drawings.

[0054] Reference Figure 1 For illustration, an embodiment of this specification provides a circuit structure of a test point (Test Point), and the circuit structure of this test point (Test Point) includes: an up-chain scan cell (ScanCell), an AND gate (AND Gate), and a multiplexer (MUX).

[0055] First of all, the scan cell is the core part of the test circuit and is responsible for capturing and shifting test data during the test process. The SI (Scan Input) terminal of the scan cell ScanCell is connected to the output Q terminal of the previous up-chain register to form a scan link. Since the Scan cell is up-chained, its SI signal is controllable. During the shift stage, its value is the value shifted in, and during capture, it captures the value of its own Q terminal. This design enables the test data to be smoothly transmitted in the circuit, ensuring the accuracy and integrity of the test signal.

[0056] Also, the SE terminal (Scan Enable) of the Scan Cell serves as the enable control for the Scan Cell. The SE terminal is connected to the ScanEnable signal. During the shift operation phase, the SE signal is at a high level '1', and during capture, it is at a low level '0', allowing data to be shifted in from the previous register. During the Capture operation phase, the SE signal is at a low level, and at this time, the Scan Cell captures the value of its own Q terminal. This mechanism ensures that the circuit can flexibly respond to different operation requirements during different test phases.

[0057] In addition, the input terminal D of the Scan Cell is connected to the output terminal of the AND gate; the output terminal Q of the Scan Cell is connected to one of the input terminals of the AND gate;

[0058] The AND gate is a logic gate, and its output terminal is at a high level only when both of its input terminals are at a high level. In this test circuit, one of the input terminals of the AND gate is connected to the output Q of the Scan Cell, and the other input terminal of the AND gate receives the TestMode signal or other control signals. When the TestMode signal is at a high level '1', a loop is formed from the Q of the register to the output of the AND gate and then to the Test Point terminal. The output Q of the ScanCell affects the Test Point terminal through the AND gate. This design allows the circuit to flexibly adjust the signal path according to the state of the control signal during the test mode, thereby improving the testability of the test.

[0059] Furthermore, the multiplexer (MUX) has the function of signal selection in the circuit and can select one from multiple inputs and transfer it to the output according to the selection signal. Among them, the S terminal of the multiplexer (MUX) is connected to the TpSelect signal, which is used to control which path the MUX selects for signal transfer. The I0 terminal is connected to TpIn, that is, the data input of the original path, and the I1 terminal is connected to the output terminal of the AND gate, that is, the data input of the test point path. By controlling the state of the TpSelect signal, the MUX can select to transfer the data of the original path (I0) or the test point path (I1) to the output. This selection mechanism enables the circuit to select different signal paths according to needs during the test process, thereby effectively controlling the flow of signals.

[0060] In addition, when dealing with timing violation paths, when the TpSelect signal is at a high level '1', the MUX selects the test point path, allowing the logical control signal from the Scan Cell to be transferred to the test point terminal through the AND gate, which can effectively prevent the propagation of the indeterminate state in the original path to the subsequent circuit. This control mechanism not only improves the accuracy of the test but also reduces the number of test vectors, thereby reducing the test cost.

[0061] Generally speaking,Figure 1 The test point circuit structure in effectively controls the signal path during the circuit test process. When dealing with timing violations, this structure can effectively control the propagation of the indeterminate state, improving the accuracy and efficiency of the test. This innovative design not only provides strong support for the testability of integrated circuits but also lays a foundation for subsequent circuit testing and fault diagnosis.

[0062] In some embodiments, during the testability design process, first, by analyzing the design data, all timing violation paths existing in the circuit to be tested are obtained. These paths may include false paths, multi-cycle paths, etc. They do not meet the standard timing requirements and need to be processed in subsequent tests to ensure the chip performance. A timing violation path refers to a path in the circuit design whose timing requirements are relaxed or ignored due to performance optimization or design requirements. If these paths are not properly processed, they will cause some problems during the automatic test pattern generation (ATPG) process, such as an increase in the number of test patterns, a decrease in test coverage, and an extension of the test running time.

[0063] Specifically, for the problems caused during the automatic test pattern generation (ATPG) process, first, several timing violation paths of the circuit to be tested are obtained. That is, the first step is to determine whether there are timing violation paths in the circuit design. This step is the basis because only by confirming the existence of timing violations can corresponding measures be taken to handle them. Next, the process will adopt different handling methods for different types of timing violations.

[0064] Among them, two commonly used statements for setting timing violations are mentioned: set_false_path and set_multicycle. Both of these statements will affect the values captured by the scan cells (ScanCell) during Transition ATPG. A timing violation path refers to a path that does not meet the normal timing requirements due to specific reasons in the circuit design. If these paths are not properly handled, they will introduce errors during the test, resulting in inaccurate test results.

[0065] Furthermore, this method requires determining the path setting options corresponding to the capture path of each timing violation path during the test according to each timing violation path. The path setting options are a set of parameters used to characterize the path information of the capture path. The timing violation statements can set three options: -from, -through, and -to. These options can be set individually or all three at the same time.

[0066] Specifically, for each timing violation path, it is necessary to determine its corresponding capture path during the test process and set the corresponding path options accordingly to ensure the effectiveness and accuracy of the test. The capture path refers to the path through which the test vector is transmitted to the interior of the circuit through the scan chain and the signal is captured at a specific node during the test process. For each timing violation path, different path options, including -from, -through, and -to, can be set according to its starting point, passing points, and ending point in the capture path. Among them, the -from option is used to identify the starting point of the capture path, the -through option is used to identify the passing points in the path, and the -to option is used to identify the ending point of the path. These path options together represent the complete information of the capture path and provide an important basis for subsequent test point insertion and test strategy formulation.

[0067] For example, if a timing violation path starts from the clock input terminal of a Scan Cell, passes through the output terminal of a logic gate, and finally reaches the data input terminal of another Scan Cell, the corresponding path options may include -from, -through, and -to. In this way, when the ATPG generates vectors, it can meet the requirements of timing violations, thereby improving the accuracy and reliability of the test.

[0068] In addition, after determining the path setting options, the method enters the critical test point insertion processing stage. For each timing violation path, if its corresponding capture path contains more than one path setting option, then a test point is inserted after the last timing violation path that does not belong to the "-to" setting option. This is because the "-to" option is usually used to identify the ending point of the path, and after the ending point, the ATPG tool will no longer propagate the indeterminate state (X state) further backward, so no additional test point control is required.

[0069] It should be noted that if there is only one path setting option in the capture path corresponding to the timing violation path and this option does not belong to the "-to" setting option, then a test point is inserted after the timing violation path. Such processing can ensure that the signals starting from the path starting point or passing points can be effectively controlled and observed during the test, thereby improving the accuracy and efficiency of the test.

[0070] Conversely, if the only path setting option is "-to", then the ending point of the timing violation path is masked because the masked path will not affect the test result, thus avoiding unnecessary test point insertion.

[0071] Different test point insertion methods are adopted for different settings. For the -to statement, since it is set at the end of the timing violation path and the ATPG tool will not propagate the indeterminate state (X state) further, there is no need to add test point control at the end position, which simplifies the processing flow, reduces unnecessary test point insertion, decreases the total number of test points, and avoids excessive circuit area occupation by test point insertion.

[0072] Then, if there is only one option for the timing violation path setting, the process will determine whether this option is a -to statement. If it is not a -to statement, i.e., it is a -from or -through, the test point will be inserted after the circuit where the timing violation is set. This processing method allows for more precise control of these paths during testing, thus improving the accuracy and efficiency of testing. For the case where there is only one -to, the circuit with the timing violation will be masked so that the captured data is X but the shifted data is controllable. This method can ensure that during testing, even at the end of the timing violation path, a certain degree of control over data flow can be maintained.

[0073] It should be noted that if there are multiple timing violation statements, the test point will be inserted after the path set by the last non -to statement. This processing method ensures that in the case of multiple timing violation paths, the test point can effectively control and observe the circuit state, thereby improving the test coverage.

[0074] Generally speaking, Figure 2 The presented process is a systematic method for inserting test points based on timing violations in circuit design to improve testability and coverage. This method ensures effective control and observation of the circuit state during testing by flexibly handling different timing violation settings.

[0075] Through this method, the timing violation paths in the integrated circuit can be effectively controlled and managed, reducing the propagation of indeterminate states during testing and decreasing the difficulty of the ATPG tool to derive the Transition pattern. This not only improves the Transition coverage, reduces the running time, but also decreases the number of patterns. At the same time, it has a minimal impact on the chip area, can reduce the number of test vectors, shorten the test running time, and improve the test coverage, thereby optimizing the entire test process, reducing the test cost, and ultimately enhancing the reliability of the chip.

[0076] Next, a circuit example is used to illustrate the way of inserting test points for different violation paths in this application.

[0077] As Figure 3As shown, the test circuit consists of four scan units (ScanCell), an AND gate, and combinational logic and sequential logic, etc. This circuit design is used to transfer data through different capture paths during the automatic test pattern generation (ATPG) test process to facilitate the testing and diagnosis of the circuit's functions and performance.

[0078] During the process of inserting test points, when determining the path setting options of the capture path corresponding to the timing violation path, first, determine the capture path and its path setting options corresponding to each timing violation path during the test process. These capture paths refer to the paths where test vectors propagate inside the circuit and are captured. Then, based on the capture process existing in the capture path, that is, the specific propagation nodes of the test vector in the circuit, determine the corresponding path option settings for each during the capture process.

[0079] In addition, these corresponding path setting options include "-from", "-through", and "-to", which are used to identify the starting point, passing point, and ending point of the capture path respectively.

[0080] Through analysis, in this circuit, data can be transmitted through three main capture paths:

[0081] The first capture path is from the D terminal of scancell1 to the Q terminal, then through combinational logic, and finally transmitted to the D terminal and Q terminal of scancell3.

[0082] The second capture path is that data is transmitted from the D terminal of scancell1 to the Q terminal, passes through the A terminal and Z terminal of the AND gate and1, and is transmitted to the D terminal and Q terminal of scancell4.

[0083] The third capture path is that data is transmitted from the D terminal of scancell2 to the Q terminal, then through the B terminal and Z terminal of the AND gate and1, and is transmitted to the D terminal and Q terminal of scancell4.

[0084] In summary, the design of these paths allows different parts of the circuit to be observed and controlled during the test process, thereby effectively detecting and isolating potential fault points. Each ScanCell in the circuit can be individually controlled in the test mode to capture and shift test data to detect stuck-at faults and transition faults.

[0085] Furthermore, for Figure 3 the three capture paths existing in the circuit structure, six different timing exception settings are formed, and these settings reflect different timing conditions that may exist in the circuit design.

[0086] The six types of timing violations that exist are set as follows:

[0087] Paths starting from the clock terminal (CP) of ScanCell1: set_false_path - from scancell1 / CP(1).

[0088] Paths passing through the output terminal (Z) of the AND gate and1: set_false_path - through and1 / Z(2).

[0089] Paths ending at the data terminals (D) of scancell3 and scancell4: set_false_path - to [list scancell3 / D scancell4 / D](3).

[0090] Paths that simultaneously start from the CP of scancell1 and pass through the Z of and1: set_false_path - from scancell1 / CP - through and1 / Z(4).

[0091] Paths starting from the CPs of scancell1 and scancell2: set_false_path - from [list scancell1 / CP scancell2 / CP](5).

[0092] Paths that start from the CP of scancell1, pass through the Z of and1, and end at the D of scancell4: set_false_path - from scancell1 / CP - through and1 / Z - to scancell4 / D(6).

[0093] These timing violation settings are for handling timing issues in the circuit. If a path is marked as a timing violation, it means that in normal timing analysis, this path may not meet the timing requirements, but it still needs to be considered during testing and verification. By inserting test points on these paths, it can ensure that data on these paths can be controlled and observed during testing, thereby improving the accuracy and efficiency of testing.

[0094] The following is a schematic illustration for these six cases.

[0095] For the setting of the (1)st Timing Exception, please refer to Figure 4 and Figure 5。The path of the Timing Exception is from scancell1 to scancell3 and scancell4, and it affects the subsequent circuits. According to Figure 2 's program flow block diagram, this statement only has "-from", so Test Point1 should be inserted after scancell1 to prevent the subsequent circuits from capturing X-state data from scancell1. For the specific insertion position of the Test Point, refer to Figure 5 。

[0096] Figure 4 and Figure 5 's settings, the timing violation path starts from the clock terminal (CP) of the scan cell ScanCell1 and extends to the scan cells ScanCell3 and ScanCell4.

[0097] In Figure 4 , since this timing violation path only contains one path setting option "-from", that is, starting from the CP of the scan cell scancell1, a test point needs to be inserted immediately after the scan cell scancell1.

[0098] Figure 5 illustrates the specific insertion position and method of the test point. By inserting a test point after the scan cell scancell1, it can be ensured that during the test process, any data transmitted from the scan cell scancell1 can be effectively controlled and monitored. For the timing violation path with only the -from option, the starting point of the timing violation path defined by the instruction set_false_path -from X, where X represents the starting point of this path. The timing violation path transmits from the D terminal to the Q terminal of the first scan cell ScanCell1, then through combinational logic to the D terminal and Q terminal of the third scan cell ScanCell3, and through the A terminal and Z terminal of the AND gate to the D terminal and Q terminal of the fourth scan cell ScanCell4. Insert a test point after the first scan cell ScanCell1.

[0099] For the setting of the second type of Timing Exception, please refer to Figure 6 and Figure 7 . Among them, the timing paths passing through and1 / Z are all Timing Exception paths. According to Figure 2 's program flow block diagram, this statement only has "-through", so Test Point2 should be inserted after and1. The specific solution is as Figure 7 shown.

[0100] This path passes through the output Z of the AND gate. In this configuration, any timing path passing through and1 / Z is defined as a timing violation, meaning that these paths may not meet the timing requirements in normal timing analysis, but still need to be specifically monitored during testing.

[0101] The path with timing violation is transmitted from the D terminal to the Q terminal of the first scan cell ScanCell1, then passes through the A terminal and Z terminal of the AND gate and is transmitted to the D terminal and Q terminal of the fourth scan cell ScanCell4;

[0102] Also, the path with timing violation is transmitted from the D terminal to the Q terminal of the second scan cell ScanCell2, then passes through the B terminal and Z terminal of the AND gate and is transmitted to the D terminal and Q terminal of the fourth scan cell ScanCell4, and a test point is inserted after the AND gate.

[0103] Among them, since this timing violation path only contains one path setup option "-through", indicating that it only affects the output terminal of the AND gate (i.e., and1), a test point needs to be inserted immediately after the AND gate. Such a design allows the path after the AND gate to be monitored during testing to ensure that any data transmitted from and1 / Z can be effectively controlled and observed.

[0104] Figure 7 It shows that the test point is precisely placed after the AND gate to capture and analyze the data transmitted from this point. This strategy helps to improve the accuracy of testing because it allows test engineers to observe and verify the transmission path of data after the AND gate and the impact of these paths on the subsequent circuit.

[0105] By inserting a test point after the AND gate, the propagation of indeterminate data backward can be prevented, thus avoiding possible test errors. This method also helps to reduce the number of test vectors required during the test pattern generation (ATPG) process, shorten the test time, and improve the test coverage. The insertion of the test point is a crucial step because it directly affects the generation of test vectors and the test coverage.

[0106] For the setting of the 3rd Timing Exception, please refer to Figure 8 and Figure 9 . This statement only has "-to". The values captured by scancell3 and scancell4 are both in the X state, but since the circuits behind these two scancell are not on the Timing Exception path, the X state will not continue to propagate backward. Therefore, these two scancell can be directly masked and not tested. The solution is as Figure 9 shown.

[0107] Since only the paths set with the "-to" option are considered, in this configuration, the endpoints of the timing violation paths are the data inputs (D) of the third scan cell scancell3 and the fourth scan cell scancell4. Since the endpoints of these paths are marked as timing violations, it means that in normal timing analysis, these paths may not meet the timing requirements. However, during the test process, since they are at the endpoints of the paths, the captured values will not propagate further backward. Therefore, the endpoints of these paths will not affect the subsequent circuit, and the X states on these paths will not propagate further, thus avoiding errors during the test process. This setting allows the designer to ignore the transition fault testing at the endpoints of the paths set with the "-to" option during the test process because they will not have a negative impact on the testing of the subsequent circuit.

[0108] Therefore, directly mask these two scan cells (scancell), where the mask operation is to not add test point control and ignore the data captured from these two scan cells during the automated vector generation process. This method can simplify the test process, reduce the number of required test vectors, and shorten the test time. By masking these paths, unnecessary testing of these paths during the ATPG process can be avoided, thus improving the test efficiency.

[0109] In addition, this method can also reduce the complexity that may occur during the test process because it avoids including paths in the test vectors that may cause errors. By focusing on the paths that are truly important, the test accuracy and reliability can be improved.

[0110] Generally speaking, Figure 8 and Figure 9 provide an effective strategy for dealing with the timing violation paths that are only set with the "-to" option. By identifying the endpoints of these paths and masking them, the test process can be optimized, and the test time and resource consumption can be reduced. This method helps to improve the test efficiency of integrated circuits while ensuring the accuracy and reliability of the test results. Through this strategy, potential problems can be effectively identified and isolated during the design and verification phases, thus improving the performance and reliability of the final product. This test point insertion method based on timing violation paths provides a practical solution for the design for testability of integrated circuits, helping to address the increasingly complex timing challenges.

[0111] For the setting of the 4th Timing Exception, please refer to Figure 10 . There is "-from" and "-through" in this statement. According to Figure 2For the program flow block diagram, if a Test Point is added after the last non "-to" option path, then a Test Point needs to be added after and1. The solution is the same as the (2)nd case, refer to the relevant schematic content described above. Figure 7 Related schematic content can be referred to.

[0112] Figure 10 The schematic path contains both "-from" and "-through" options. In this setting, the timing violation path starts from the clock terminal CP of the first scan cell ScanCell1, passes through the output terminal Z of the AND gate AND Gate1, and affects the subsequent circuit. Therefore, since the path setting contains "-from" and "-through" options but lacks the "-to" option, this means that the starting point and the passing points of the path need to be paid attention to during testing. The reason is that: containing -through and -from indicates that the data from the starting point and the data at the passing points will both propagate an indeterminate state, representing that the indeterminate state has no end point and will keep propagating. So, it is necessary to insert test points to control the end point of the X state and prevent it from propagating out.

[0113] Therefore, similar to the above Figure 7 , a test point can be added after the last non "-to" option path. Therefore, a test point needs to be added after and1 to ensure that the data starting from the first scan cell scancell1 and passing through AND1 / Z can be effectively controlled and monitored. Such a design allows test engineers to observe and verify the data transmission on this path during the testing process, while preventing the backward propagation of X state data, thereby improving the accuracy and efficiency of testing.

[0114] By inserting a test point after the AND gate, the backward propagation of indeterminate data can be prevented, thus avoiding possible test errors. In addition, this method also helps to reduce the number of test vectors required during the test vector generation ATPG process, shorten the test time, and improve the test coverage. The insertion of test points is a key step because it directly affects the generation of test vectors and the test coverage.

[0115] In summary, Figure 10 and Figure 7 demonstrate an effective strategy for handling timing violation paths containing "-from" and "-through" options. By inserting test points at key positions, the data flow in the circuit can be effectively controlled and monitored, thereby improving the quality and efficiency of testing. This method helps to improve the ex-factory quality of the chip, discover and fix potential problems during the design and verification phases, and ultimately improve the reliability and performance of the product. Through this meticulous circuit design and test point insertion strategy, the integrated circuit can maintain efficient and stable performance when facing complex timing challenges.

[0116] For the setting of the (5)th Timing Exception, please refer to Figure 11 . This statement only has "-from", and the data from both scancell1 and scancell2 are in the X state. According to Figure 2 's program flow block diagram, Test Points should be inserted after both scancell1 and scancell2 to prevent the subsequent circuit from capturing X-state data from scancell1 and scancell2. The solution is as Figure 12 shown.

[0117] In this setting, the starting points of the timing violation path are the clock terminals CP of the two scan cells, the first scan cell scanCell1 and the second scan cell scanCell2. And this path setting only includes the "-from" option and does not include the "-through" or "-to" options, which means that the data from the first scan cell scancell1 and the second scan cell scancell2 are both in the X state, that is, the indeterminate state. This state may cause errors during the test because the indeterminate data may affect the accuracy of the test results.

[0118] To solve this problem, it is necessary to insert test points after the first scan cell scancell1 and the second scan cell scancell2 to control and monitor the data transmitted from these two starting points.

[0119] Figure 12 Specific solutions are provided, showing how to insert test points after the first scan cell scancell1 and the second scan cell scancell2. By inserting test points after these two scan cells, it is possible to effectively prevent the subsequent circuit from capturing indeterminate data from the first scan cell scancell1 and the second scan cell scancell2. This strategy helps to improve the accuracy of the test because it allows test engineers to observe and verify the transmission paths of the data after it is transmitted from the first scan cell scancell1 and the second scan cell scancell2, as well as the impact of these paths on the subsequent circuit.

[0120] When implementing this test point insertion strategy, it is necessary to consider the overall structure and logic of the circuit. The insertion of test points should not interfere with the normal circuit operation, and at the same time, it is necessary to ensure that sufficient control and observation capabilities can be provided in the test mode. In addition, the design of the test points should also consider their impact on the circuit performance and area to ensure that while improving the testability, it will not have a negative impact on other aspects of the circuit.

[0121] In summary, Figure 11 and Figure 12Provides a clear guidance on how to handle timing violation paths with multiple starting points in integrated circuit design. By inserting test points at critical positions, the data flow in the circuit can be effectively controlled and monitored, thereby improving the quality and efficiency of testing. This method not only helps to improve the quality of chips leaving the factory, but also discovers and fixes potential problems during the design and verification phases, ultimately enhancing the reliability and performance of the product. Through this meticulous circuit design and test point insertion strategy, the integrated circuit can maintain efficient and stable performance in the face of complex timing challenges.

[0122] For the setting of the (6)th Timing Exception, please refer to Figure 13 . There are "-from", "-through", and "-to" in this statement. According to Figure 2 's program flow block diagram, add a TestPoint after the last option path that is not "-to". Therefore, its processing method is the same as that of the (4)th one, as Figure 7 shown.

[0123] The path contains complete path setting options such as "-from", "-through", and "-to". This configuration involves a path starting from the clock terminal CP of the first scan cell ScanCell1, passing through the output terminal Z of the AND gate AND Gate1, and finally reaching the data input terminal D of scan cell 4. This timing violation path contains all three path setting options, indicating that the starting point, passing points, and ending point of the path all need to be particularly concerned about.

[0124] In addition, since the path setting contains the "-to" option, this means that the ending point of the path will not continue to propagate the indeterminate state. Therefore, the main focus is on the starting point and passing points of the path.

[0125] According to Figure 2 's program flow block diagram, for this situation, a test point should be added after the last option path that is not "-to". Therefore, a test point needs to be added after and1 to ensure that the data starting from scancell1, passing through and1 / Z, and finally reaching scancell4 can be effectively controlled and monitored. Such a design allows test engineers to observe and verify the data transmission on this path during the testing process, while preventing the backward propagation of X-state data, thereby improving the accuracy and efficiency of testing.

[0126] Similar to Figure 7 shown, in this solution, the test point is precisely placed after the AND gate to capture and analyze the data outgoing from this point. This strategy helps to improve the accuracy of testing because it allows test engineers to observe and verify the data transmission path after AND gate 1 and the impact of these paths on the subsequent circuit.

[0127] Taking the setting of the first type as an example, the reason why this method can reduce the difficulty of ATPG derivation will be explained. When running ATPG in the conventional way, because a Timing Exception is set, the value captured at the A terminal of the AND gate is X, and this X will propagate backward. On the one hand, since the value captured at the A terminal is X and the Z port is also X, the A port and the Z port are untestable, and the value of the B port cannot be transmitted either, so the B port is also untestable. On the other hand, the ATPG tool needs to process the X states propagated subsequently, which requires a certain amount of time and the number of patterns. When using the method in this application, the Test Point can control the A terminal of and1 to 1, making the faults at the B and Z terminals testable, and the X states will not continue to propagate backward, reducing the difficulty of ATPG derivation patterns.

[0128] It should be noted that even if set_false_path is replaced with set_multicycle, the processing method of this application is still effective, indicating that the method of this application has wide applicability and can adapt to different timing violation settings.

[0129] To verify the effectiveness of this method, this application uses an actual project circuit, which contains 1.1 million registers and 293 timing violations.

[0130] Table 1 below shows the comparison results between the conventional method and this application.

[0131] Table 1 Comparison of Results between Conventional Method and the Method in the Patent

[0132]

[0133] In the case of Condition 1, that is, the coverage rate of Transition is limited to a maximum of 85%, the results show that the coverage rates of the two methods are similar, both around 85%. However, when using the method of this application, the running time of ATPG is reduced from 30 hours 2 minutes 45 seconds to 5 hours 51 minutes 13 seconds, and the number of test vectors is also reduced by 8,078. Under Condition 2, that is, the coverage rate limit is lifted, the coverage rate can be increased to 92.48%, and the running time and the number of test vectors are also significantly reduced. These results indicate that the method of this application can not only improve the coverage rate of Transition ATPG, reduce the running time, but also reduce the number of required test vectors, and the impact on the chip area is only 0.01%.

[0134] Table 1 shows the result comparison between the conventional method and the method of this application when performing ATPG in the Transition mode. These comparison results highlight the significant advantages of the method of this application in integrated circuit testing. Under Condition 1, that is, when the coverage rate of Transition is limited to a maximum of 85%, the ATPG running time using the method of this application is significantly reduced from 30 hours, 2 minutes, and 45 seconds to 5 hours, 51 minutes, and 13 seconds, a reduction of approximately 79.94%. At the same time, the number of test vectors is also reduced by 8,078, that is, a reduction of 88.55%. Although the coverage rates are similar due to the limitation, both being around 85%, the improvement in time and resource efficiency of the method of this application is obvious.

[0135] Under Condition 2, that is, when the coverage rate limit is lifted, this method not only increases the coverage rate to 92.48%, but also further reduces the running time and the number of test vectors. Specifically, the running time is reduced to 35 hours, 9 minutes, and 11 seconds, a reduction of approximately 9.89%, and the number of test vectors is reduced to 7,668, a reduction of approximately 22.18%. These data indicate that the method of this application effectively improves the efficiency and performance of testing without sacrificing the coverage rate.

[0136] In addition, although the insertion of test points may have a certain impact on the chip area, the area increase caused by the method of this application is only 0.01%, and this tiny increase can be almost ignored in practical applications. Generally speaking, the data in Table 1 strongly proves that when dealing with circuits containing timing violation paths, the method of this application not only improves the coverage rate of Transition ATPG, reduces the running time, but also reduces the number of test vectors, and at the same time has a minimal impact on the chip area, thus providing an efficient solution for the design for testability of integrated circuits.

[0137] The inventive method of this application significantly reduces the difficulty of the ATPG tool in deriving Transition test vectors by truncating the timing violation paths from the source and controlling the propagation of the X state. This method not only improves the test coverage rate, but also shortens the test running time, reduces the number of test vectors, and at the same time has a minimal impact on the chip area. Therefore, the method of this application is applicable to the Transition ATPG of circuits containing timing violation settings, providing an effective solution for the design for testability of integrated circuits. Through this method, designers can more effectively handle complex timing violation paths, improve the test quality and efficiency of the circuit, and thus improve the performance and reliability of the final product.

[0138] In some embodiments, the system reviews each timing violation path to determine whether a test point has been inserted, which can prevent duplicate insertion of test points on the same timing violation path. If the system determines that a test point already exists on a certain path, it will skip that path and not perform additional test point insertion. Conversely, if the system detects that a test point has not been inserted on a certain timing violation path, it will precisely insert a test point at an appropriate location according to the previously determined path setting options, such as "-from", "-through", or "-to".

[0139] In some embodiments, timing violation paths refer to those paths that are relaxed or ignored in standard timing analysis and are crucial for the performance and reliability of the circuit. These timing violation paths mainly include false paths and multi-cycle paths (abbreviated as MCP).

[0140] Specifically, a false path refers to a path that does not affect the timing performance in circuit design. They may be non-critical paths deliberately introduced due to design optimization, circuit structure peculiarities, or test requirements. In actual timing analysis, the timing requirements of these paths can be ignored to reduce the timing constraints in the design, thereby improving the flexibility and efficiency of the design. In circuit design, false paths are usually described using the set_false_path statement, which tells the timing analysis tool to ignore these specific paths and avoid their impact on the timing analysis results.

[0141] On the other hand, a multi-cycle path refers to a path that requires multiple clock cycles to complete data transmission during circuit operation. These paths usually involve complex logic operations or long-distance signal transmissions, so it is impossible to complete the stable propagation of data within one clock cycle. The existence of multi-cycle paths has an important impact on the performance and reliability of the circuit because they may cause data delays or timing conflicts. In circuit design, multi-cycle paths are usually described using the set_multicycle statement, which allows specifying the maximum number of clock cycles for the path, thus providing appropriate timing margins for these paths.

[0142] Generally speaking, false paths and multi-cycle paths are the two main types of timing violation paths. By using the set_false_path and set_multicycle statements, the characteristics of these paths can be precisely described, thereby optimizing the design process and test strategy while ensuring the circuit performance. The use of these statements enables designers to effectively manage and control timing violation paths in complex circuit designs, ensuring the reliability and efficiency of the circuit. Correctly handling these timing violation paths is crucial for improving the performance and reliability of integrated circuits because they directly affect the timing analysis, testing, and verification results of the circuit.

[0143] Based on the same inventive concept, after the test point insertion is completed, the testability design of the integrated circuit has been significantly improved. Therefore, this application also provides a method for processing the testability of an integrated circuit.

[0144] Refer to Figure 14 As shown in the figure, a method for processing the testability of an integrated circuit includes:

[0145] Step S202: Perform a serial scan chain operation on the circuit under test, where the circuit under test is a circuit under test that has completed test point insertion according to any of the integrated circuit test point insertion methods given in this application. The insertion process of the test points can refer to the foregoing examples and will not be elaborated here.

[0146] Step S204: After obtaining the serial chain result, an automated test vector can be generated according to the serial chain result.

[0147] Step S206: Carry out a preset integrated circuit test item according to the automated test vector.

[0148] It should be noted that the integrated circuit test item can be determined according to the circuit requirements and is not specifically limited.

[0149] Inserting test points for violation paths based on this application can reduce the derivation difficulty, running time, etc. of vector generation, and improve the coverage rate. Therefore, the generated vectors can be beneficial to the integrated circuit project test.

[0150] Based on the same inventive concept, this application also provides an integrated circuit test point insertion device corresponding to the foregoing method examples.

[0151] Refer to Figure 15 As shown in the figure, an integrated circuit test point insertion device includes:

[0152] A violation path module 101, configured to obtain a plurality of timing violation paths of the circuit under test;

[0153] A path setting module 103, configured to determine a path setting option for the capture path corresponding to each timing violation path during the test process according to each timing violation path; wherein, the path setting option is used to represent the path information of the capture path, and the path setting option includes any one of the following single options or a composite option of multiple options combined: -from, -through, -to, where -from is used to represent the starting point of the capture path, -through is used to represent the path passing point of the capture path, and -to is used to represent the end point of the capture path;

[0154] An insertion module 105 is used to perform test point insertion processing on each timing violation path. The insertion processing process includes: if the capture path corresponding to the timing violation path contains more than one path setting option, a test point is inserted after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and this path setting option does not belong to the "-to" setting option, a test point is inserted after the timing violation path, otherwise the end point of the timing violation path is masked during automated vector generation.

[0155] Based on the same inventive concept, the present application also provides an integrated circuit testability processing device corresponding to the foregoing method examples.

[0156] Reference Figure 16 Shown schematically, an integrated circuit testability processing device includes:

[0157] A scan module 301 is used to perform a serial scan chain on the circuit under test, where the circuit under test is a circuit under test that has completed test point insertion according to the integrated circuit test point insertion method described in any one of the embodiments of the present application;

[0158] A vector module 303 is used to generate automated test vectors according to the serial chain result;

[0159] A test module 305 is used to perform a preset integrated circuit test item according to the automated test vector.

[0160] Based on the same inventive concept, the present application also provides an electronic device, including:

[0161] At least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the integrated circuit test point insertion method described in any one of the embodiments of the present application, or the integrated circuit testability processing method described in any one of the embodiments of the present application.

[0162] Based on the same inventive concept, the present application also provides a computer storage medium, characterized in that the computer storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they execute: the integrated circuit test point insertion method described in any one of the embodiments of the present application, or the integrated circuit testability processing method described in any one of the embodiments of the present application.

[0163] In this specification, for the same or similar parts among various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the foregoing embodiments.

[0164] As described above, the foregoing are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An integrated circuit test point insertion method, characterized in that, Including: Obtain several timing violation paths of the circuit to be tested; Determine the path setting options of the capture path corresponding to each timing violation path during the test process; wherein, the path setting options are used to represent the path information of the capture path, and the path setting options include any one of the following single options or a composite option of multiple options: -from, -through, -to, where -from is used to represent the starting point of the capture path, -through is used to represent the path passing point of the capture path, and -to is used to represent the ending point of the capture path; Perform test point insertion processing on each timing violation path, where the insertion process includes: if the capture path corresponding to the timing violation path contains more than one path setting option, then insert a test point after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and this path setting option does not belong to the "-to" setting option, then insert a test point after the timing violation path, otherwise, mask the ending point of the timing violation path during automatic vector generation.

2. The integrated circuit test point insertion method according to claim 1, wherein When determining the path setting options of the capture path corresponding to each timing violation path, first determine the capture path existing for this timing violation path during the test process, and then determine the path setting option corresponding to each capture process according to the capture processes existing in the capture path.

3. The integrated circuit test point insertion method according to claim 1, wherein When inserting a test point, first determine whether a test point has been inserted for this timing violation path. If so, do not insert the test point repeatedly. If not, insert the test point.

4. The integrated circuit test point insertion method according to claim 1, characterized in that The types of timing violation paths include false paths or multi-cycle paths, where false paths are described using the set_false_path statement and multi-cycle paths are described using the set_multicycle statement.

5. The integrated circuit test point insertion method according to any one of claims 1-4, characterized in that The test points include scan cells, AND gates, and multiplexers (MUX); Among them, the connections of each terminal of the scan cell are as follows: the SI terminal is connected to the output Q terminal of the previous chained register, the SE terminal is connected to the ScanEnable signal, the input terminal D is connected to the output terminal of the AND gate, and the output terminal Q is connected to one input terminal of the AND gate; The other input terminal of the AND gate is connected to the TestMode for testing or other control signals, where the TestMode or other control signals have a value of 1 in the scan mode to form a loop from the Q of the scan cell to the output of the AND gate and then to the D terminal of the scan cell; The connections of each port of the multiplexer (MUX) are as follows: the S terminal is connected to the scan chip select signal TpSelect, the I0 terminal is connected to the original path, and the I1 terminal is connected to the output terminal of the AND gate to control the multiplexer (MUX) to select the test point path or the original path by controlling TpSelect.

6. A method for processing the testability of an integrated circuit, characterized in that, Including: Perform a serial scan chain operation on the circuit under test, where the circuit under test is the circuit under test that has completed test point insertion according to the integrated circuit test point insertion method described in any one of claims 1-5; Generate an automated test vector based on the serial chain result; Perform a preset integrated circuit test item according to the automated test vector.

7. An integrated circuit test point insertion device, characterized in that, Comprising: A violation path module for obtaining a plurality of timing violation paths of the circuit under test; A path setting module for determining a path setting option for the capture path corresponding to each timing violation path during the test process according to each timing violation path; wherein, the path setting option is used to represent the path information of the capture path, and the path setting option includes any one of the following individual options or a composite option of multiple option combinations: -from, -through, -to, where -from is used to represent the starting point of the capture path, -through is used to represent the path passing point of the capture path, and -to is used to represent the end point of the capture path; An insertion module for performing test point insertion processing on each timing violation path, where the insertion processing process includes: if the capture path corresponding to the timing violation path contains more than one path setting option, then insert a test point after the last timing violation path that does not belong to the "-to" setting option; if there is only one path setting option in the capture path corresponding to the timing violation path, and this path setting option does not belong to the "-to" setting option, then insert a test point after the timing violation path, otherwise mask the end point of the timing violation path during the generation of the automated vector.

8. An integrated circuit testability processing device, characterized in that Comprising: A scan module for performing a serial scan chain operation on the circuit under test, where the circuit under test is the circuit under test that has completed test point insertion according to the integrated circuit test point insertion method described in any one of claims 1-5; A vector module for generating an automated test vector based on the serial chain result; A test module for performing a preset integrated circuit test item according to the automated test vector.

9. An electronic device, characterized in that, Comprising: At least one processor; And a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the integrated circuit test point insertion method described in any one of claims 1-5, or the integrated circuit testability processing method described in claim 6.

10. A computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they execute: the integrated circuit test point insertion method described in any one of claims 1-5, or the integrated circuit testability processing method described in claim 6.

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