Data conversion circuit and computing device

Abstract

The application discloses a data conversion circuit and a computing device, and relates to the technical field of power consumption management. The computing device comprises a plurality of memories, a data conversion circuit and a processor. The data conversion circuit is used for obtaining the power of each memory by using an improved integrated circuit I3C protocol to obtain first power data, performing data conversion processing on the first power data to obtain second power data, and sending the second power data to the processor by using a first communication protocol. The computing device provided by the technical scheme of the application can accurately read the power of each memory in the plurality of memories to obtain first power data with high precision and strong anti-interference capability. Furthermore, when the first power data is subjected to data conversion processing, the first power data is not easily affected by factors such as noise and ground floating, high-precision second power data can be obtained, and the problem of system performance degradation caused by abnormality or loss of memory power can be avoided.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of power consumption management, and in particular to a data conversion circuit and a computing device. BACKGROUND

[0002] Generally, a server can monitor the power of a memory through a central processing unit (CPU) to perform power consumption management according to the power of the memory, so as to ensure long-time stable operation of the system. At present, for a CPU that does not support an improved inter integrated circuit (I3C) protocol, the power of the memory is mainly monitored through an externally-attached power sampling circuit.

[0003] However, affected by factors such as environmental interference and ground plane floating, when the power of the memory is monitored through the externally-attached power sampling circuit, the CPU can not be able to obtain the power of the memory, or the obtained power of the memory can be inaccurate, or even an exception can occur when the power of the memory is obtained, which will all affect the system performance of the server. SUMMARY

[0004] Embodiments of the present application provide a data conversion circuit and a computing device, which can effectively reduce the influence of factors such as environmental interference and ground plane floating on the power of the memory, and ensure that the obtained power of the memory is relatively accurate.

[0005] Embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, the embodiments of the present application provide a computing device, which includes a plurality of memories, a data conversion circuit and a processor; a first end of the data conversion circuit is coupled with each memory, and a second end of the data conversion circuit is coupled with the processor;

[0007] The data conversion circuit is configured to:

[0008] obtain the power of each memory by using an I3C protocol, to obtain first power data;

[0009] perform data conversion processing on the first power data, to obtain second power data;

[0010] send the second power data to the processor by using a first communication protocol;

[0011] The first communication protocol is different from the I3C protocol.

[0012] Based on the scheme, the power of each memory in the plurality of memories is obtained through the data conversion circuit to obtain first power data. Since the power of each memory is a digital power collected by the internal integrated circuit of the memory, the accuracy is high and the anti-interference ability is strong, so the accuracy of the obtained first power data is high and the anti-interference ability is strong. Furthermore, when the first power data is processed by data conversion, it is not easy to be affected by noise, ground floating and other factors, and high-precision second power data can be obtained. The total power of the plurality of memories is obtained by the data conversion circuit, which can not only ensure that the obtained power is accurate, but also avoid the problem of system performance degradation caused by abnormality or loss when obtaining the total power of the plurality of memories.

[0013] In a possible implementation, the data conversion circuit comprises a first data converter and a power regulator; a first end of the first data converter is a first end of the data conversion circuit, a second end of the first data converter is coupled with a first end of the power regulator, and a second end of the power regulator is a second end of the data conversion circuit.

[0014] The first data converter is configured to obtain the power of each memory by using the I3C protocol to obtain the first power data; process the first power data by data conversion to obtain gain data; and send the gain data to the power regulator by using the I2C protocol.

[0015] The power regulator is configured to process the gain data by data conversion to obtain second power data; and send the second power data to the processor by using the first communication protocol.

[0016] Based on the scheme, the power of each memory is obtained by the first data converter, and the first power data obtained is processed by data conversion to obtain gain data. In this way, the first power data in the I3C protocol format can be converted into the gain data in the I2C format which meets the input data format requirements of the power regulator by the first data converter, and the gain data corresponds to the power of each memory. Furthermore, the gain data is processed by data conversion through the power regulator to obtain the second power data in the first communication protocol format which corresponds to the total power of the plurality of memories. Therefore, the processor can determine the total power of the plurality of memories based on the second power data. When the first data converter and the power regulator are both inherent circuits or devices in the computing device, the power sampling circuit can be avoided to save cost.

[0017] In another possible implementation, the first data converter is a baseboard management controller which supports both the I3C protocol and the I2C protocol.

[0018] Based on the scheme, the first data converter can realize mutual conversion between data in the I3C protocol format and data in the I2C protocol format, that is, the gain data can be obtained by processing the first power data by data conversion.

[0019] In a further possible implementation, the first data converter is specifically configured to determine a total power of the plurality of memories based on the first power data; determine a gain coefficient based on the total power of the plurality of memories, the working voltage of the plurality of memories, and the equivalent voltage corresponding to the working current of the plurality of memories; and generate the gain data based on the gain coefficient.

[0020] Based on the scheme, the first data converter can determine the total power of the plurality of memories based on the first power data, and then determine the gain coefficient related to the total power of the plurality of memories based on the total power of the plurality of memories, the working voltage of the plurality of memories, and the equivalent voltage corresponding to the working current of the plurality of memories, thereby ensuring that the generated gain data corresponds to the total power of the plurality of memories.

[0021] In a further possible implementation, the third end of the power regulator is coupled to the first voltage source, and the fourth end of the power regulator is coupled to the second voltage source; the power regulator is specifically configured to determine a gain coefficient based on the gain data; and generate the second power data based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source. The first voltage is the same as the working voltage of the plurality of memories, and the second voltage is the same as the equivalent voltage corresponding to the working current of the plurality of memories.

[0022] Based on the scheme, since the first voltage is the same as the working voltage of the plurality of memories, and the second voltage is the same as the equivalent voltage corresponding to the working current of the plurality of memories, the power regulator can accurately determine the total power of the plurality of memories based on the gain coefficient in the gain data, the first voltage, and the second voltage, thereby obtaining the second power data with high precision.

[0023] In a further possible implementation, the first data converter includes a format converter and a second data converter; the first end of the format converter is the first end of the first data converter, and the second end of the format converter is coupled to the first end of the second data converter; and the second end of the second data converter is the second end of the first data converter.

[0024] The format converter is configured to obtain the power of each memory using the I3C protocol to obtain the first power data, perform data format conversion on the first power data to obtain third power data, and send the third power data to the second data converter using the I2C protocol.

[0025] The second data converter is configured to perform data conversion processing on the third power data to obtain gain data, and send the gain data to the power regulator using the I2C protocol.

[0026] Based on the scheme, when the second data converter only supports the I2C protocol and cannot simultaneously support the I3C protocol and the I2C protocol, a format converter is arranged between the second data converter and the plurality of memories. The power of each memory in the plurality of memories is obtained through the format converter, first power data in the I3C protocol format is obtained, and the first power data in the I3C protocol format is subjected to data format conversion to obtain third power data in the I2C protocol format that can be processed by the second data converter. Therefore, the third power data is subjected to data conversion processing by the second data converter, and gain data in the I2C protocol format can be obtained.

[0027] In another possible implementation, the second data converter is a baseboard management controller supporting the I2C protocol.

[0028] Based on the scheme, the second data converter can process the third power data in the I2C protocol format to obtain gain data in the I2C protocol format.

[0029] In a second aspect, the embodiments of the present application also provide a data conversion circuit, which comprises a first data converter and a power regulator; a first end of the first data converter is coupled with each memory in a plurality of memories in a computing device, a second end of the first data converter is coupled with a first end of the power regulator; a second end of the power regulator is coupled with a processor in the computing device.

[0030] The first data converter is configured to obtain power of each memory in the plurality of memories in the I3C protocol to obtain first power data, and to process the first power data to obtain gain data, and to send the gain data to the power regulator in the I2C protocol.

[0031] The power regulator is configured to process the gain data to obtain second power data, and to send the second power data to the processor in the first communication protocol; and the first communication protocol is different from the I3C protocol.

[0032] In a possible implementation, the first data converter comprises a format converter and a second data converter. A first end of the format converter is the first end of the first data converter; a second end of the format converter is coupled with a first end of the second data converter; and a second end of the second data converter is the second end of the first data converter.

[0033] The format converter is configured to obtain power of each memory in the plurality of memories in the I3C protocol to obtain first power data, to process the first power data to obtain third power data, and to send the third power data to the second data converter in the I2C protocol.

[0034] The second data converter is configured to process the third power data to obtain gain data.

[0035] In one possible implementation, the third terminal of the power regulator is coupled to a first voltage source, and the fourth terminal of the power regulator is coupled to a second voltage source; the power regulator is specifically used to: determine a gain coefficient based on gain data; and generate second power data based on the gain coefficient, a first voltage corresponding to the first voltage source, and a second voltage corresponding to the second voltage source; wherein the first voltage is the same as the operating voltage of the multiple memory modules, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memory modules.

[0036] Thirdly, embodiments of this application also provide a chip that includes the data conversion circuit described in the second aspect above. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of the structure of another computing device provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of the structure of another computing device provided in the embodiments of this application;

[0040] Figure 4 This is a schematic diagram of the structure of a data conversion circuit provided in an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of another data conversion circuit provided in an embodiment of this application;

[0042] Figure 6 This is a flowchart illustrating a data conversion method provided in an embodiment of this application;

[0043] Figure 7 This is a flowchart illustrating another data conversion method provided in an embodiment of this application;

[0044] Figure 8 This is a flowchart illustrating another data conversion method provided in an embodiment of this application;

[0045] Figure 9 This is a flowchart illustrating another data conversion method provided in an embodiment of this application;

[0046] Figure 10 This is a flowchart illustrating another data conversion method provided in the embodiments of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0048] To facilitate understanding of this application, the terms used in this application are explained below.

[0049] A computing device is an electronic device used to perform computing tasks. Computing devices can include personal computers, servers, embedded computers, and supercomputers, etc. This application uses a server as an example for illustrative purposes. The server in this application can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. When the aforementioned server is a server cluster or distributed system composed of multiple physical servers, the multiple physical servers can form a blockchain, with each physical server being a node on the blockchain. The physical type of the server can include rack servers, cabinet servers, high-density servers, graphics processing unit (GPU) servers, tower servers, blade servers, artificial intelligence (AI) servers, etc. This application does not limit the type of server in its embodiments.

[0050] The Board Management Controller (BMC) is a controller in a computing device that manages the motherboard. As an independent processor embedded in the computing device, the BMC can monitor the device's hardware and software information, health status, and operational status. It should be noted that the BMC can also be called an Integrated Lights-Out (iLO), an Integrated Dell Remote Access (IDRAC) card, a Hardware Device Management (HDM), an Integrated Management Module (IMM), etc. This application does not limit the name of the BMC in its embodiments.

[0051] A voltage regulator module (VRM) is a hardware component in computing devices that converts the DC voltage supplied by the power supply into a stable and adjustable voltage required by the various components inside the server, especially high-performance components such as the CPU and memory. Through its internal circuit design and control mechanisms, the VRM can dynamically adjust the output voltage according to the server's load and the processor's needs. The VRM's regulation capability ensures that the CPU and other high-performance components operate under efficient and stable conditions.

[0052] The I3C protocol is a new serial communication interface standard based on a master-slave architecture, compatible with the Inter-Integrated Circuit (I2C) protocol. The I3C protocol aims to address the limitations of the I2C bus and Serial Peripheral Interface (SPI) in terms of low power consumption, high performance, and high integration, making it particularly suitable for connecting and communicating between various sensors and peripherals.

[0053] The I2C protocol is a simple, bidirectional, two-wire synchronous serial bus. The I2C protocol has advantages such as fewer pins, simple hardware implementation, strong scalability, and support for multiple masters.

[0054] SVID (Serial Voltage Identification) is a protocol used by the CPU to dynamically adjust the output voltage of the VRM power supply. Primarily used in server and personal computer systems, SVID allows the CPU to dynamically adjust the VRM power supply output voltage in real time based on current load and performance requirements, thereby optimizing system performance, reducing power consumption, and extending hardware lifespan.

[0055] The Advanced Configuration and Power Interface (ACPI) protocol is an operating system power management and hardware configuration interface that defines a hardware abstraction interface between the system firmware (BIOS or UEFI) and the operating system. It assigns power management almost entirely to the BIOS, greatly limiting the operating system's ability to control power consumption.

[0056] Computing devices (such as servers) include multiple Dual-Inline-Memory-Modules (DIMMs), which can also be called memory modules or memory. Each memory module includes a Microcontroller Unit (MCU) and / or power sampling circuitry. The MCU and / or power sampling circuitry determine the digital power of the memory (a power value represented by a digital quantity) and store the digital power of the memory in the memory's power register.

[0057] Furthermore, if all memory modules support the I3C protocol, but the CPU does not, then the CPU cannot read the power consumption of each memory module; in other words, the CPU cannot directly read the memory power. Therefore, CPUs that do not support the I3C protocol need to use other methods to monitor memory power.

[0058] This application provides a computing device including multiple memory modules, a processor, and a data conversion circuit coupled between the memory modules and the processor. The data conversion circuit uses the I3C protocol to obtain the power of each memory module, resulting in first power data including the power of each memory module. It then performs data conversion processing on the first power data to obtain second power data, and finally sends the second power data to the processor using a first communication protocol. Since the power of each memory module obtained by this data conversion circuit is the digital power collected by the integrated circuits inside the memory modules, it has high accuracy and strong anti-interference capability. Therefore, when performing format conversion processing on the obtained first power data, it can effectively reduce the influence of factors such as noise and ground fluctuations, obtaining high-precision second power data and avoiding the impact on server system performance due to abnormal or lost memory power.

[0059] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 1 As shown, the computing device 10 includes multiple memory modules 101, a data conversion circuit 102, and a processor 103. A first terminal of the data conversion circuit 102 is coupled to each memory module 101, and a second terminal of the data conversion circuit 102 is coupled to the processor 103. The data conversion circuit 102 is used to obtain the power of each memory module 101 using the I3C protocol to obtain first power data; then, it performs data conversion processing on the first power data to obtain second power data; finally, it sends the second power data to the processor 103 using a first communication protocol. The first communication protocol is different from the I3C protocol.

[0060] For example, since each of the multiple memory modules 101 supports the I3C protocol, the data conversion circuit 102 also supports the I3C protocol. Therefore, the first terminal of the data conversion circuit 102 can be coupled to each memory module 101 via the I3C bus to enable the data conversion circuit 102 to obtain power from each memory module 101 using the I3C protocol.

[0061] The number of memory modules 101 in the plurality of memory modules 101 can be any value greater than or equal to 1. This application embodiment does not limit the number of memory modules 101 included in the plurality of memory modules 101. However, due to limitations imposed by factors such as memory capacity, number of slots, memory type and capacity, heat dissipation, and user budget and performance requirements, the computing device 10 typically includes a maximum of 8 memory modules. This application embodiment uses an example of a plurality of memory modules 101 including 8 memory modules 101 for illustrative purposes. It is understood that... Figure 1 The example shown here is only one instance of multiple memory units 101, including three memory units 101.

[0062] Each memory 101 may include an MCU and / or a power sampling circuit. The MCU or power sampling circuit can obtain the digital power of the memory 101 and store it in the power register of the memory 101. Thus, the data conversion circuit 102 can obtain the stored digital power from the power register of each memory 101 to obtain the first power data.

[0063] For example, the data conversion circuit 102 may simultaneously support the I3C protocol and the first communication protocol. The processor 103 may support the first communication protocol. Therefore, the second terminal of the data conversion circuit 102 may be coupled to the processor 103 via the first communication bus.

[0064] The first communication protocol can be any communication protocol other than the I3C protocol. The first communication bus can be a bus that supports the first communication protocol. In some examples, the first communication protocol can be the SVID protocol, and the first communication bus can be an SVID bus. In other examples, the first communication protocol can be the ACPI protocol, and the first communication bus can be an ACPI bus. This application does not limit the specific implementation of the first communication protocol and the first communication bus; this application uses the example of the first communication protocol being the SVID protocol and the first communication bus being an SVID bus for illustrative purposes.

[0065] Exemplarily, processor 103 may be a CPU in computing device 10 that supports a first communication protocol but does not support the I3C protocol. In some examples, processor 103 may be a CPU in computing device 10 that supports the SVID protocol but does not support the I3C protocol. In other examples, processor 103 may be a CPU in computing device 10 that supports the ACPI protocol but does not support the I3C protocol. This application embodiment uses a CPU that supports the SVID protocol but does not support the I3C protocol as an example for illustrative purposes.

[0066] The processor 103 may also be any other general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, transistor logic device, hardware component, or any combination thereof that does not support the I3C protocol in the computing device 10. The general-purpose processor may be a microprocessor or any conventional processor.

[0067] The data conversion circuit 102 can be any device or apparatus capable of implementing the above functions. In some examples, the data conversion circuit 102 can be a hardware component within the computing device 10. In other examples, the data conversion circuit 102 can be an FPGA or a Programmable Logic Device (CPLD) chip disposed within the computing device 10. This application embodiment does not limit the specific implementation of the data conversion circuit 102; this application embodiment uses the data conversion circuit 20 as an example of a hardware component within the computing device 10 for illustrative purposes. For example, the data conversion circuit 102 can be a VRM that simultaneously supports the I3C protocol and a first communication protocol.

[0068] The first power data can be power data in I3C protocol format. In some examples, the first power data may include multiple memory power data in I3C protocol format obtained by reading the power of each memory 101 in the plurality of memory 101. That is, the first power data may include multiple memory power data in I3C protocol format. For example, if the plurality of memory 101 includes 8 memory 101, then the first power data includes 8 memory power data in I3C protocol format.

[0069] It is understandable that in the memory power data of the I3C protocol format, the content of the data packet may include the memory power read, and the packet header and packet trailer may respectively include the first packet header and the first packet trailer corresponding to the I3C protocol format.

[0070] The second power data can be power data in the format of the first communication protocol. In some examples, the first communication protocol is the SVID protocol. The second power data can be total memory power data in the SVID protocol format. In the total memory power data in the SVID protocol format, the content of the data packet can include the total power of multiple memory locations, and the packet header and packet trailer can respectively include a second packet header and a second packet trailer corresponding to the SVID protocol format. Moreover, the second packet header is different from the first packet header, and the second packet trailer is different from the first packet trailer.

[0071] The data conversion circuit 102 uses the I3C protocol to obtain the power of each memory and obtains the first power data. This may include: the data conversion circuit 102 sends a power read request to each memory 101 using the I3C protocol, each memory 101 responds to the power read request, reads the digital power (memory power) stored in the power register, and converts the read memory power into memory power data in I3C protocol format and returns it to the data conversion circuit 102.

[0072] The data conversion circuit 102 performs data conversion processing on the first power data to obtain the second power data. This may include: the data conversion circuit 102 performs preset calculations and format conversions on each memory power data to obtain the second power data in the format of the first communication protocol, and sends the second power data to the processor 103 using the first communication protocol.

[0073] In the computing device provided in this application embodiment, since the power of each memory in the multiple memory modules obtained by the data conversion circuit is the digital power collected by the integrated circuit inside the memory, it has high accuracy and strong anti-interference capability. Therefore, the obtained first power data also has high accuracy and strong anti-interference capability. Furthermore, when performing data conversion processing on the first power data, it is not easily affected by factors such as noise and ground fluctuations, and can obtain high-precision second power data. This not only ensures that the obtained power of the multiple memory modules is relatively accurate, but also avoids the problem of system performance degradation due to abnormal or lost memory power.

[0074] In some embodiments, the data conversion circuit 102 may be a VRM that simultaneously supports the I3C protocol and the first communication protocol. If the VRM cannot simultaneously support the I3C protocol and the first communication protocol, but supports the I2C protocol and the first communication protocol, then the data conversion circuit 102 may include a BMC that simultaneously supports the I3C protocol and the I2C protocol, and a VRM that simultaneously supports the I2C protocol and the first communication protocol.

[0075] like Figure 2 As shown above, in the above Figure 1Based on the illustrated embodiment, the data conversion circuit 102 may include a first data converter 1021 and a power regulator 1022. The first terminal of the first data converter 1021 is the first terminal of the data conversion circuit 20 and is coupled to each of the plurality of memory 101; the second terminal of the first data converter 1021 is coupled to the first terminal of the power regulator 1022, the second terminal of the power regulator 1022 is the second terminal of the data conversion circuit 102 and is coupled to the processor 103.

[0076] The first data converter 1021 is used to obtain the power of each memory 101 in the plurality of memory 101 using the I3C protocol to obtain first power data; to perform data conversion processing on the first power data to obtain gain data; and to send the gain data to the power regulator 1022 using the I2C protocol.

[0077] For example, the first data converter 1021 can be a hardware component within the computing device 10 that simultaneously supports the I2C and I3C protocols. That is, the first data converter 1021 can convert data in I3C protocol format to data in I2C protocol format, or vice versa. In some examples, the first data converter 1021 can be a BMC that supports both I2C and I3C protocols. This application embodiment uses a BMC as an example to illustrate the concept.

[0078] For example, since the first data conversion circuit 1021 and each memory 101 both support the I3C protocol, the first end of the first data converter 1021 can be coupled to each memory 101 via the I3C bus to enable the first data conversion circuit 1021 to obtain power from each memory 101 using the I3C protocol.

[0079] The first data conversion circuit 1021 obtains the power of each memory 101 using the I3C protocol, and the implementation method of obtaining the first power data is similar to that of the data conversion circuit 102 obtaining the power of each memory 101 using the I3C protocol. The implementation method of obtaining the first power data is not described in detail here.

[0080] The power regulator 1022 can be a hardware component within the computing device 10 that simultaneously supports the I2C protocol and the first communication protocol. That is, the power regulator 1022 can convert data in I2C protocol format to data in the first communication protocol format, or vice versa. In some examples, the power regulator 1022 can be a VRM that simultaneously supports the I2C protocol and the first communication protocol. This application embodiment uses a VRM as an example for illustrative purposes.

[0081] In this embodiment of the application, the first data converter 1021 is specifically used to determine the total power of the plurality of memory 101s based on the first power data; determine the gain coefficient based on the total power of the plurality of memory 101s, the operating voltage of the plurality of memory 101s and the equivalent voltage corresponding to the operating current of the plurality of memory 101s; and generate gain data based on the gain coefficient.

[0082] The total power of the multiple memory modules 101 can be the sum of the power of each memory module 101. For example, the first data converter 1021 may include a first parsing module and an addition module. The first data converter 1021 determines the total power of the multiple memory modules 101 based on the first power data, which may include: the first data converter 1021 parses the power data of each memory module in the first power data using the first parsing module to obtain the power of each memory module 101; and then performs an addition operation on the power of each memory module 101 using the addition module to obtain the total power of the multiple memory modules 101.

[0083] The power of each memory 101 is obtained by parsing the power data of each memory in the first power data by the first parsing module. This can include: identifying the data packet content in each memory power data by the first parsing module (removing the packet header and packet tail in each memory power data) to obtain the power of each memory 101.

[0084] In this embodiment, the operating voltage of the multiple memory modules 101 can be the input voltage of the multiple memory modules 101, and can be denoted as Vin. The equivalent voltage corresponding to the operating current of the multiple memory modules 101 can be the voltage across the sampling resistor when the operating power supply corresponding to the input voltage Vin of the multiple memory modules 101 is connected in series with the sampling resistor of the multiple memory modules 101, and can be denoted as Visys. In some examples, the values ​​of Vin and Visys can be determined according to the actual hardware design of the multiple memory modules 101. For example, Vin can be 12V and Visys can be 3.3V. This embodiment does not limit the values ​​of Vin and Visys. This embodiment uses Vin as 12V and Visys as 3.3V as an example for illustrative explanation.

[0085] For example, the first data converter 1021 may further include a first multiplication module and a division module. The first data converter 1021 determines the gain coefficient based on the total power of the multiple memory modules 101, the operating voltage of the multiple memory modules 101, and the equivalent voltage corresponding to the operating current of the multiple memory modules 101. This may include: the first data converter 1021 calculating the product of the operating voltage Vin of the multiple memory modules 101 and the equivalent voltage Visys corresponding to the operating current of the multiple memory modules 101 through the first multiplication module to obtain the voltage coefficient Vin*Visys; and then calculating the quotient of the total power of the multiple memory modules 101 and the voltage coefficient Vin*Visys through the division module to obtain the gain coefficient Gain. The calculation of the gain coefficient Gain can be found in the following formula (1).

[0086] Gain=Pdim / (Vin*Visys) (1);

[0087] Where Pdim represents the total power of the multiple memory modules 101; Vin represents the operating voltage of the multiple memory modules 101; and Visys represents the equivalent voltage corresponding to the operating current of the multiple memory modules 101.

[0088] In this embodiment, since the equivalent voltages corresponding to the operating voltages and currents of the multiple memory modules can accurately reflect the actual operating conditions of the multiple memory modules, the gain coefficient determined based on the total power of the multiple memory modules, the operating voltages and currents of the multiple memory modules can not only accurately reflect the actual operating conditions of the multiple memory modules, but also correspond to the total power of the multiple memory modules.

[0089] Gain data can be in I2C protocol format. In I2C protocol format gain data, the packet content may include gain coefficients, and the packet header and trailer may each include a third packet header and trailer corresponding to the I2C protocol format. The third packet header may be different from both the first and second packet headers; the third packet trailer may also be different from both the first and second packet trailers.

[0090] For example, the first data converter 1021 may further include a first encoding module. The first data converter 1021 generates gain data based on gain coefficients, which may include: the first data converter 1021 encoding the gain coefficients through the first encoding module to obtain gain data in I2C protocol format.

[0091] Encoding the gain coefficients using the first encoding module to obtain gain data in the I2C protocol format may include: using the gain coefficients as the content of the data packet through the first encoding module, and adding the third header and third trailer corresponding to the I2C protocol format to the gain coefficients to obtain gain data in the I2C protocol format.

[0092] For example, since both the first data converter 1021 and the power regulator 1022 support the I2C protocol, the second end of the first data converter 1021 can be coupled to the first end of the power regulator 1022 via the I2C bus to support the power regulator 1022 in obtaining gain data using the I2C protocol.

[0093] The power regulator 1022 is used to perform data conversion processing on the gain data to obtain the second power data; and to send the second power data to the processor 103 using the first communication protocol.

[0094] For example, the power regulator 1022 may further include a third terminal and a fourth terminal. The third terminal of the power regulator 1022 is coupled to a first voltage source Vcc1; the fourth terminal of the power regulator 1022 is coupled to a second voltage source Vcc2. Specifically, the power regulator 1022 is used to determine a gain parameter coefficient based on gain data, and to generate second power data based on the gain parameter coefficient, a first voltage corresponding to the first voltage source, and a second voltage corresponding to the second voltage source.

[0095] For example, the power regulator 1022 may also include a second parsing module. The power regulator 1022 determines the gain coefficient based on the gain data, which may include: the power regulator 1022 parsing the gain data through the second parsing module to obtain the gain coefficient, and writing the gain coefficient into the corresponding gain register in the power regulator 1022.

[0096] The method of parsing the gain data through the second parsing module to obtain the gain coefficient is similar to the method of parsing the power data of each memory 101 in the first power data through the first parsing module to obtain the power of each memory 101. The embodiments of this application will not be described again here.

[0097] In this embodiment, based on the above formula (1), it is known that in order to determine the total power of the multiple memory modules 101 based on the gain coefficient Gain, the power regulator 1022 needs to obtain the operating voltage Vin of the multiple memory modules 101 and the equivalent voltage Visys corresponding to the operating current of the multiple memory modules 101. Based on this and the hardware limitations of the power regulator 1022, a first voltage source Vcc1 and a second power source Vcc2 can be input to the third terminal of the power regulator 1022. Moreover, the first voltage corresponding to the first voltage source Vcc1 is the same as the operating voltage Vin of the multiple memory modules 101, and the second voltage corresponding to the second voltage source Vcc2 is the same as the equivalent voltage Visys corresponding to the operating current of the multiple memory modules 101.

[0098] The power regulator 1022 generates second power data based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source. This may include: the power regulator 1022 performing a multiplication operation on the gain coefficient, the first voltage corresponding to the first voltage source Vcc1, and the second voltage corresponding to the second voltage source Vcc2 to obtain the total power Pdim of the multiple memory 101, and encoding the total power Pdim of the multiple memory 101 to obtain the second power data in the pre-first signal protocol format.

[0099] In some examples, the power regulator 1022 may include a second multiplication module. The power regulator 1022 performs a multiplication operation on the gain coefficient, the first voltage corresponding to the first voltage source Vcc1, and the second voltage corresponding to the second voltage source Vcc2 to obtain the total power Pdim of the multiple memory modules 101. This may include: the power regulator 1022 calculating the product of the gain coefficient Gain, the first voltage corresponding to the first voltage source Vcc1, and the second voltage corresponding to the second voltage source Vcc2 through the second multiplication module to obtain the total power Pdim of the multiple memory modules 101.

[0100] Since the first voltage is the same as the operating voltage Vin of the multiple memory modules 101, and the second voltage is the same as the equivalent voltage Visys corresponding to the operating current of the multiple memory modules 101, the product of the gain coefficient Gain, the operating voltage Vin of the multiple memory modules 101, and the equivalent voltage Visys corresponding to the operating current of the multiple memory modules 101 can be determined as the total power Pdim of the multiple memory modules 101. The calculation of the total power Pdim of the multiple memory modules 101 can be found in the following formula (2).

[0101] Pdim = Gain * Vin * Visys (2);

[0102] For example, taking the SVID protocol as the first communication protocol, the power regulator 1022 may further include a second encoding module. The power regulator 1022 encodes the total power Pdim of the multiple memory modules 101 to obtain second power data in the format of the first communication protocol. This may include: the power regulator 1022 encoding the total power Pdim of the multiple memory modules 101 through the second encoding module to obtain second power data in the format of the SVID protocol.

[0103] The power regulator 1022 encodes the total power Pdim of multiple memory modules 101 through the second encoding module to obtain second power data in SVID protocol format. This may include: the second encoding module using the total power Pdim of multiple memory modules 101 as the content of a data packet, and adding a second packet header and a second packet trailer corresponding to the SVID protocol format to the total power Pdim of multiple memory modules 101 to obtain second power data in SVID protocol format.

[0104] In the computing device provided in this application embodiment, the power of each memory in a plurality of memory modules is obtained through a first data converter, and the total power of the plurality of memory modules is determined based on the obtained first power data in I3C format. A gain coefficient is determined based on the total power of the plurality of memory modules, the operating voltage of the plurality of memory modules, and the equivalent voltage corresponding to the operating current of the plurality of memory modules. Therefore, gain data in I2C protocol format that conforms to the input data format requirements of the power regulator can be generated based on the gain coefficient, and this gain data corresponds to the total power of the plurality of memory modules. Furthermore, the power regulator performs data conversion processing on the gain data to obtain second power data in I2C protocol format corresponding to the total power of the plurality of memory modules. Thus, the processor can determine the total power of the plurality of memory modules based on the second power data. Moreover, when both the first data converter and the power regulator are inherent circuits or devices in the computing device, the addition of a power sampling circuit can be avoided, saving costs.

[0105] In some embodiments, the first data converter 1021 may be a BMC that supports both the I3C and I2C protocols. If the BMC cannot support both the I3C and I2C protocols but supports the I2C protocol, then the first data converter 1021 may include a format converter that supports both the I3C and I2C protocols and a BMC that only supports the I2C protocol.

[0106] like Figure 3 As shown above, in the above Figure 2 Based on the illustrated embodiment, the first data converter 1021 may include a format converter 301 and a second data converter 302. The first terminal of the format converter 301 is the first terminal of the first data converter 1021 and is coupled to each of the plurality of memory modules 101; the second terminal of the format converter 301 is coupled to the first terminal of the second data converter 302; the second terminal of the second data converter 302 is the second terminal of the first data converter 1021 and is coupled to the first terminal of the power regulator 1022.

[0107] The format converter 301 is used to obtain the power of each memory 101 in the multiple memory 101s using the I3C protocol to obtain first power data, convert the first power data into a data format to obtain third power data, and send the third power data to the second data converter 302 using the I2C protocol.

[0108] For example, the format converter 301 may be a hardware component that supports both the I3C and I2C protocols. That is, the format converter 301 can convert data in I3C protocol format to data in I2C protocol format, or vice versa.

[0109] For example, since both the format converter 301 and the multiple memory modules 101 support the I3C protocol, the first end of the format converter 301 can be coupled to each memory module 101 via the I3C bus to enable the format converter 301 to obtain power from each memory module 101 via the I3C protocol.

[0110] The third power data can be power data in I2C protocol format. Furthermore, if the first power data includes multiple memory power data in I3C protocol format, then the third power data will also include the same number of memory power data in I2C protocol format. It can be understood that the content (power) of the data packets in each memory power data in the I2C protocol format of the third power data is the same as the content (power) of the data packets in the corresponding memory power data in the I3C protocol format of the first power data.

[0111] The format converter 301 uses the I3C protocol to obtain the power of each memory 101 in multiple memory 101s, and the implementation method of obtaining the first power data is the same as... Figure 2 The first data converter 1021 uses the I3C protocol to obtain the power of each memory 101 in the multiple memory 101. The implementation method of obtaining the first power data is similar, and will not be described again in the embodiments of this application.

[0112] For example, the format converter 301 performs data format conversion on the first power data to obtain the third power data, which may include: performing data format conversion on the memory power data of each I3C protocol format in the first power data to obtain memory power data of I2C protocol format, and determining the memory power data of each I2C protocol format as the third power data.

[0113] The data format conversion of the memory power data in each I3C protocol format in the first power data can include: retaining the contents of the data packets in the memory power data of each I3C protocol format, converting the packet header from the first packet header to the third packet header, and converting the packet trailer from the first packet trailer to the third packet trailer.

[0114] The second data converter 302 is used to perform data conversion processing on the third power data to obtain gain data; and sends the gain data to the power regulator 1022 using the I2C protocol.

[0115] For example, the second data converter 302 may be a hardware component that only supports the I2C protocol. In some examples, the second data converter 302 may be a BMC that only supports the I2C protocol.

[0116] Since both the format converter 301 and the second data converter 302 support the I2C protocol, the second end of the format converter 301 can be coupled to the first end of the second data converter 302 via the I2C bus to enable the second data converter 302 to obtain third power data via the I2C protocol.

[0117] Similar to how the first data converter 1021 performs data conversion processing on the first power data to obtain gain data, the second data converter 302 performs data conversion processing on the third power data to obtain gain data, which may include: determining the total power of the multiple memory modules 101 based on the third power data; determining the gain coefficient based on the total power of the multiple memory modules 101, the operating voltage of the multiple memory modules 101, and the equivalent voltage corresponding to the operating current of the multiple memory modules 101; and generating gain data based on the gain coefficient.

[0118] The implementation method for determining the total power of multiple memory modules 101 based on the third power data is similar to the implementation method for determining the total power of multiple memory modules 101 based on the first power data. For details, please refer to [link to relevant documentation]. Figure 2 The embodiments shown are described in detail below. Further details of the embodiments in this application will not be repeated here.

[0119] In the computing device provided in this application embodiment, when the second data converter only supports the I2C protocol and cannot simultaneously support both the I3C and I2C protocols, a format converter is set between the second data converter and multiple memory modules. The format converter obtains the power of each memory module within the multiple memory modules, resulting in first power data in I3C protocol format. This first power data in I3C protocol format is then converted to a third power data in I2C protocol format that the second data converter can process. Therefore, by performing data conversion processing on the third power data using the second data converter, gain data in I2C protocol format can be obtained.

[0120] Based on the above embodiments, this application also provides a data conversion circuit. Figure 4 This is a schematic diagram of a data conversion circuit provided in an embodiment of this application. Figure 4 As shown, the data conversion circuit 40 includes a first data converter 401 and a power regulator 402; a first terminal of the first data converter 401 is coupled to each memory in a plurality of memory in a computing device, and a second terminal of the first data converter 401 is coupled to a first terminal of the power regulator 402; the second terminal of the power regulator 402 is coupled to a processor in a computing device.

[0121] The first data converter 401 is used to obtain the power of each memory using the I3C protocol to obtain the first power data; to perform data conversion processing on the first power data to obtain gain data; and to send the gain data to the power regulator 402 using the I2C protocol.

[0122] The power regulator 402 is used to perform data conversion processing on the gain data to obtain the second power data; and to send the second power data to the processor using a first communication protocol; wherein the first communication protocol is different from the I3C protocol.

[0123] In this embodiment of the application, the first data converter 401 can correspond to Figure 2 The first data converter 1021 in the illustrated embodiment. The power regulator 402 may correspond to... Figure 2 The power regulator 1022 in the illustrated embodiment.

[0124] like Figure 5 As shown above, in the above... Figure 4 Based on the illustrated embodiment, the first data converter 401 may include a format converter 4011 and a second data converter 4012. The first end of the format converter 4011 is the first end of the first data converter 401; the second end of the format converter 4011 is coupled to the first end of the second data converter 4012; and the second end of the second data converter 4012 is the second end of the first data converter 401.

[0125] The format converter 4011 is used to obtain the power of each memory using the I3C protocol to obtain the first power data, convert the data format of the first power data to obtain the third power data, and send the third power data to the second data converter 4012 using the I2C protocol.

[0126] The second data converter 4012 is used to perform data conversion processing on the third power data to obtain gain data.

[0127] In this embodiment of the application, the format converter 4011 can correspond to Figure 3 The format converter 301 in the illustrated embodiment. The second data converter 4012 can correspond to... Figure 3 The second data converter 302 in the illustrated embodiment.

[0128] In some examples, continue to refer to Figure 4 As shown, the third terminal of the power regulator 402 is coupled to the first voltage source Vcc1, and the fourth terminal of the power regulator 402 is coupled to the second voltage source Vcc2. The power regulator 402 is specifically used for: determining the gain coefficient based on the gain data; generating second power data based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source; wherein, the first voltage is the same as the operating voltage of the multiple memory modules, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memory modules.

[0129] Regarding the data conversion circuit in the above embodiments, the specific methods of each circuit and the corresponding beneficial effects have been described in detail in the corresponding embodiment section of the computing device section. Please refer to the implementation method and beneficial technical effects of the above exemplary computing device section, which will not be repeated here.

[0130] Corresponding to the embodiments of computing device 10, this application also provides an embodiment of a data conversion method, which can be applied to the computing device 10 provided in any of the above embodiments. For example... Figure 6 As shown, the data conversion method may include the following steps 601 to 603.

[0131] Step 601: Use the I3C protocol to obtain the power of each memory in multiple memory locations to obtain the first power data.

[0132] Step 602: Perform data conversion processing on the first power data to obtain the second power data.

[0133] Step 603: Send the second power data to the processor using the first communication protocol.

[0134] In some embodiments, reference Figure 7 As shown above, in the above Figure 6 Based on the illustrated embodiment, step 602 may include the following steps 6021 and 6022.

[0135] Step 6021: Perform data conversion processing on the first power data to obtain gain data;

[0136] Step 6022: Perform data conversion processing on the gain data to obtain the second power data.

[0137] In some embodiments, reference Figure 8 As shown above, in the above Figure 7 Based on the illustrated embodiment, step 6021 may include steps 801 to 803 as follows.

[0138] Step 801: Determine the total power of multiple memory modules based on the first power data.

[0139] Step 802: Determine the gain coefficient based on the total power of multiple memory modules, the operating voltage of multiple memory modules, and the equivalent voltage corresponding to the operating current of multiple memory modules.

[0140] Step 803: Generate gain data based on the gain coefficient.

[0141] In some embodiments, reference Figure 9 As shown above, in the above Figure 7 Based on the illustrated embodiment, step 6022 may include the following steps 901 and 902.

[0142] Step 901: Determine the gain coefficient based on the gain data.

[0143] Step 902: Generate second power data based on the gain coefficient, the first voltage, and the second voltage.

[0144] The first voltage is the same as the operating voltage of the multiple memory modules, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memory modules.

[0145] In some embodiments, reference Figure 10 As shown above, in the above Figure 7 Based on the illustrated embodiment, step 6021 may include the following steps 1001 and 1002.

[0146] Step 1001: Convert the data format of the first power data to obtain the third power data.

[0147] Step 1002: Perform data conversion processing on the third power data to obtain gain data.

[0148] Regarding the data conversion method in the above embodiments, the specific methods of each step and the corresponding beneficial effects have been described in detail in the corresponding embodiment section of the computing device section. Please refer to the implementation method and beneficial technical effects of the above exemplary computing device section, which will not be repeated here.

[0149] Furthermore, embodiments of this application may also provide a chip that may include the aforementioned data conversion circuit.

[0150] The embodiments described above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A computing device, characterized in that, The computing device includes multiple memory modules, a data conversion circuit, and a processor; a first terminal of the data conversion circuit is coupled to each of the memory modules, and a second terminal of the data conversion circuit is coupled to the processor. The data conversion circuit is used for: The power of each memory module is obtained using the improved integrated circuit I3C protocol to obtain the first power data; The first power data is processed by data conversion to obtain the second power data; The second power data is sent to the processor using a first communication protocol; wherein the first communication protocol is different from the I3C protocol.

2. The computing device according to claim 1, characterized in that, The data conversion circuit includes a first data converter and a power regulator; a first terminal of the first data converter is a first terminal of the data conversion circuit, a second terminal of the first data converter is coupled to a first terminal of the power regulator, and a second terminal of the power regulator is a second terminal of the data conversion circuit. The first data converter is configured to obtain the power of each memory using the I3C protocol to obtain the first power data; perform data conversion processing on the first power data to obtain gain data; and send the gain data to the power regulator using the integrated circuit I2C protocol. The power regulator is used to perform data conversion processing on the gain data to obtain the second power data; and to send the second power data to the processor using the first communication protocol.

3. The computing device according to claim 2, characterized in that, The first data converter is a baseboard management controller that supports the I3C protocol and the I2C protocol.

4. The computing device according to claim 2, characterized in that, The first data converter is specifically used for: Based on the first power data, the total power of the plurality of memory modules is determined; The gain coefficient is determined based on the total power of the multiple memory modules, the operating voltage of the multiple memory modules, and the equivalent voltage corresponding to the operating current of the multiple memory modules. The gain data is generated based on the gain coefficient.

5. The computing device according to claim 2, characterized in that, The third terminal of the power regulator is coupled to the first voltage source, and the fourth terminal of the power regulator is coupled to the second voltage source; the power regulator is specifically used for: Based on the gain data, determine the gain coefficient; The second power data is generated based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source. Wherein, the first voltage is the same as the operating voltage of the plurality of memory modules, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the plurality of memory modules.

6. The computing device according to claim 2, characterized in that, The first data converter includes: a format converter and a second data converter; the first end of the format converter is the first end of the first data converter, and the second end of the format converter is coupled to the first end of the second data converter; the second end of the second data converter is the second end of the first data converter. The format converter is used to obtain the power of each memory using the I3C protocol to obtain the first power data, convert the first power data into a data format to obtain the third power data, and send the third power data to the second data converter using the I2C protocol. The second data converter is used to perform data conversion processing on the third power data to obtain the gain data; and to send the gain data to the power regulator using the I2C protocol.

7. The computing device according to claim 6, characterized in that, The second data converter is a baseboard management controller that supports the I2C protocol but does not support the I3C protocol.

8. A data conversion circuit, characterized in that, The data conversion circuit includes a first data converter and a power regulator; a first terminal of the first data converter is coupled to each memory in a plurality of memory in a computing device, and a second terminal of the first data converter is coupled to a first terminal of the power regulator; the second terminal of the power regulator is coupled to a processor in the computing device. The first data converter is used to obtain the power of each memory using the I3C protocol to obtain first power data; perform data conversion processing on the first power data to obtain gain data; and send the gain data to the power regulator using the I2C protocol. The power regulator is used to perform data conversion processing on the gain data to obtain second power data; and to send the second power data to the processor using a first communication protocol; wherein the first communication protocol is different from the I3C protocol.

9. The data conversion circuit according to claim 8, characterized in that, The first data converter includes a format converter and a second data converter; the first end of the format converter is the first end of the first data converter; the second end of the format converter is coupled to the first end of the second data converter; the second end of the second data converter is the second end of the first data converter. The format converter is used to obtain the power of each memory using the I3C protocol to obtain the first power data, convert the first power data into a data format to obtain the third power data, and send the third power data to the second data converter using the I2C protocol. The second data converter is used to perform data conversion processing on the third power data to obtain the gain data.

10. The data conversion circuit according to claim 8, characterized in that, The third terminal of the power regulator is coupled to the first voltage source, and the fourth terminal of the power regulator is coupled to the second voltage source; the power regulator is specifically used for: Based on the gain data, determine the gain coefficient; The second power data is generated based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source. Wherein, the first voltage is the same as the operating voltage of the plurality of memory modules, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the plurality of memory modules.

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