Memory management method and storage device

Abstract

The present invention provides a memory management method and a storage device. The method comprises: sending a read instruction sequence to a memory module to instruct to read a first physical unit among the plurality of physical units; obtaining read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data; generating password information according to the error rate information; encrypting the original data according to the password information to generate encrypted data corresponding to the original data; and sending a write instruction sequence to the memory module to instruct to store the encrypted data into a second physical unit among the plurality of physical units. Thus, the data encryption efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] In today's digital age, with the rapid development of information technology and the increasing value of big data, data security has become a core element that cannot be ignored in storage system design. Traditional mechanical hard disk drives (HDDs) and early solid-state drives (SSDs) are particularly vulnerable to unauthorized access and data leakage due to the lack of built-in security mechanisms. Especially in emerging application scenarios such as cloud computing and edge computing, these traditional storage media cannot meet the strict requirements for data integrity and confidentiality.

[0003] In order to cope with the above challenges, data encryption has become one of the mainstream ways to protect sensitive information. Among them, hardware-based encryption solutions are favored because they can provide high performance and high security. In this context, solid-state drives (Encrypted SSDs) with powerful encryption functions have emerged. They not only inherit the high-speed reading and writing characteristics of traditional SSDs, but also integrate advanced encryption algorithms and key management strategies to provide users with a fast and secure data storage platform.

[0004] Therefore, developing and optimizing high-quality encrypted SSDs has become a key focus for technical personnel in the storage field. Summary of the invention

[0005] The present invention provides a memory management method and a storage device, which can improve the above-mentioned problem and enhance the data encryption efficiency of the storage device.

[0006] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: sending a read instruction sequence to the memory module to instruct the memory module to read a first physical unit among the multiple physical units; obtaining read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects the bit error rate of the read data; generating password information based on the error rate information; encrypting original data based on the password information to generate encrypted data corresponding to the original data; and sending a write instruction sequence to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the multiple physical units.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: send a read instruction sequence to the memory module to instruct the memory module to read a first physical unit among the plurality of physical units; obtain read data corresponding to the read instruction sequence from the memory module; perform error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects the bit error rate of the read data; generate password information according to the error rate information; encrypt the original data according to the password information to generate encrypted data corresponding to the original data; and send a write instruction sequence to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the plurality of physical units.

[0008] Based on the above, the present invention can effectively improve the problem that the random numbers traditionally used to encrypt data are not random enough, thereby improving the data encryption efficiency of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of generating password information according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of generating password information according to an embodiment of the present invention;

[0014] Figure 6 is a flowchart of a memory management method according to an embodiment of the present invention;

[0015] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0022] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc.

[0026] In one embodiment, the memory controller 123 may further include an encryption circuit 26. The encryption circuit 26 is connected to the memory control circuit 23 and is used to perform encryption and decryption on data to ensure the confidentiality of the data. For example, after a certain data (also referred to as the first data) is encrypted by the encryption circuit 26, a ciphertext corresponding to the first data may be formed. After the ciphertext is decrypted by the encryption circuit 26, a plaintext corresponding to the ciphertext (i.e., the first data) may be restored.

[0027] In one embodiment, the encryption circuit 26 may support a symmetric encryption algorithm, an asymmetric encryption algorithm, or other types of encryption / decryption algorithms. For example, the symmetric encryption algorithm may include AES (Advanced Encryption Standard)-256, etc., and the asymmetric encryption algorithm may include RSA (Rivest-Shamir-Adleman), etc., and the present invention is not limited thereto. In one embodiment, the memory controller 123 may also include other types of various circuit modules (such as a power management circuit, etc.), and the present invention is not limited thereto.

[0028] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0029] In one embodiment, a physical unit may include one or more physical erasing units. In addition, a physical unit may include multiple physical sub-units. For example, a physical sub-unit may include one or more physical programming units.

[0030] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0031] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0032] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0033] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0034] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0035] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0036] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0037] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0038] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0039] In one embodiment, the memory control circuit 23 may send a read instruction sequence to the memory module 122. The read instruction sequence may be used to instruct the memory module 122 to read at least one physical unit (also referred to as a first physical unit). For example, the first physical unit may include Figure 3 According to the read result of the memory module 122, the memory control circuit 23 can obtain the read data corresponding to the read instruction sequence from the memory module 122. For example, assuming that the first physical unit is Figure 3If the physical unit 301 (i) is read by the memory module 122, the read data may reflect the reading result of the physical unit 301 (i) by the memory module 122.

[0040] In one embodiment, after obtaining the read data, the memory control circuit 23 may perform error detection on the read data. The error detection is used to obtain error rate information of the read data. The error rate information may reflect the bit error rate (BER) of the read data. For example, the error rate information (i.e., bit error rate) may reflect the number of error bits in a preset number of the read data.

[0041] It should be noted that the error detection may be performed by the memory control circuit 23 or by the memory control circuit 23 in conjunction with the decoding circuit 25. However, in one embodiment, the error detection does not include error correction of the read data by the decoding circuit 25. For example, the error correction is used to correct errors (i.e., error bits) in the read data.

[0042] That is, in one embodiment, the memory control circuit 23 may only perform error detection on the read data to obtain the error rate information without performing the error correction on the read data, thereby saving power consumption of the storage device 12 .

[0043] In one embodiment, after obtaining the error rate information, the memory control circuit 23 may generate cryptographic information based on the error rate information. Taking the AES-256 encryption algorithm as an example, the cryptographic information may include private-key information and initialization sequence information. The private-key information may carry information about the key used to perform encryption in the AES-256 encryption algorithm. The initialization sequence information may carry information about the initialization sequence (also called initialization vector) used to perform encryption in the AES-256 encryption algorithm. It should be noted that the information content of the cryptographic information may vary depending on different encryption algorithms, and the present invention is not limited thereto.

[0044] In one embodiment, after obtaining the password information, the encryption circuit 26 may encrypt the data (also referred to as the original data) according to the password information to generate encrypted data corresponding to the original data. Taking the AES-256 encryption algorithm as an example, the encryption circuit 26 may encrypt the original data based on the AES-256 encryption algorithm according to the password information to generate the encrypted data. It should be noted that the encryption circuit 26 may also use other encryption algorithms to encrypt the original data, and the present invention is not limited thereto.

[0045] In one embodiment, after obtaining the encrypted data, the memory control circuit 23 may send a write instruction sequence to the memory module 122. The write instruction sequence may be used to instruct the memory module 122 to store the encrypted data in at least one physical unit (also referred to as the second physical unit). For example, assuming that the first physical unit is Figure 3 The second entity unit can be Figure 3 , and i is different from j. Alternatively, in one embodiment, i may be equal to j.

[0046] It should be noted that in the aforementioned embodiment, the correctness of each data read from the first physical unit (or the bit error rate) will be affected by the current operating state of the memory module 122. For example, the operating state includes the read voltage applied to the first physical unit, the length of time for applying the read voltage, the critical voltage distribution of multiple storage units in the first physical unit, the ambient temperature and / or the clock frequency, etc., and the type of the operating state is not limited thereto. Therefore, at different time points, based on the current operating state of the memory module 122, the read result for the first physical unit may be different. As a result, compared to a conventional pseudo-random number generator (PRNG) and / or a true random number generator (TRNG), the bit error rate of the read result can be closer to a true random number (i.e., it cannot be accurately predicted).

[0047] In one embodiment, the password information is obtained according to the bit error rate of the read data and the original data is encrypted based on the password information, which can improve the defects of the pseudo-random number generator (PRNG) and / or the true random number generator (TRNG), such as the random numbers generated are not random enough or even have regularity, thereby improving the subsequent data encryption efficiency and increasing the difficulty of cracking the encrypted data. As a result, the data storage security of the storage device 12 can be effectively improved.

[0048] In one embodiment, after obtaining the error rate information, the memory control circuit 23 may perform information processing (also referred to as first information processing) on ​​the error rate information to obtain reference information (also referred to as first reference information). In particular, the first reference information may conform to a preset data format, and the preset data format matches the encryption algorithm used to generate the password information. For example, assuming that the encryption algorithm is AES-256, the preset data format may match the AES-256 encryption algorithm. For example, the preset data format may be used to standardize the data length of the first reference information to a preset length to meet subsequent calculation requirements for the AES-256 encryption algorithm. Then, the memory control circuit 23 may generate the password information based on the first reference information.

[0049] Figure 4 is a schematic diagram of generating password information according to an embodiment of the present invention. Figure 4 , the memory control circuit 23 may obtain the error rate information 41. For example, the error rate information 41 may reflect the bit error rate of the read data read from the first physical unit. For example, the error rate information 41 may include a value or a data sequence to reflect the bit error rate of the read data.

[0050] After obtaining the error rate information 41, the memory control circuit 23 may perform information processing 401 (i.e., first information processing) on ​​the error rate information 41 to obtain reference information 42 (i.e., first reference information). For example, in the information processing 401, the memory control circuit 23 may perform logarithm (e.g., natural logarithm), absolute value, extract at least part of the value after the decimal point, remove at least part of the value after the decimal point, numerical unit conversion, polynomial operation, hash operation, or other custom processing on the error rate information 41. The specific operation details of the information processing 401 may be set according to the encryption algorithm adopted, and the present invention is not limited thereto. Based on the result of the information processing 401, the memory control circuit 23 may obtain the reference information 42. Similar to the error rate information 41, the reference information 42 may approach a true random number (i.e., it cannot be accurately predicted).

[0051] In one embodiment, after obtaining the reference information 42, the memory control circuit 23 may generate the password information 43 according to the reference information 42. For example, taking the AES-256 encryption algorithm as an example, the password information 43 may include key information 431 and initialization sequence information 432.

[0052] In one embodiment, the memory control circuit 23 may perform a data conversion (also referred to as a first data conversion) 411 on the reference information 42 to obtain key information 431. For example, the key information 431 may carry information about a key used to perform encryption in the encryption algorithm used by the encryption circuit 26. In addition, the memory control circuit 23 may perform another data conversion (also referred to as a second data conversion) 412 on the reference information 42 to obtain initialization sequence information 432. For example, the initialization sequence information 432 may carry information about an initialization sequence (or initialization vector) used to perform encryption in the encryption algorithm used by the encryption circuit 26.

[0053] In one embodiment, the data format (e.g., data length) of the key information 431 may be different from the data format (e.g., data length) of the initialization sequence information 432. For example, taking the AES-256 encryption algorithm as an example, the data lengths of the key information 431 and the initialization sequence information 432 used in the AES-256 encryption algorithm may be "256" bits and "128" bits, respectively. However, the data formats of the key information 431 and / or the initialization sequence information 432 may be adjusted according to practical needs, and the present invention is not limited thereto.

[0054] It should be noted that in Figure 4 In the embodiment of the present invention, the information processing 401, the first data conversion 411 and the second data conversion 412 can be set or configured according to the encryption algorithm used by the encryption circuit 26. Therefore, the information processing 401, the first data conversion 411 and the second data conversion 412 can be used to generate the reference information 42, the key information 431 and the initialization sequence information 432 that match the encryption algorithm used by the encryption circuit 26.

[0055] In one embodiment, the memory control circuit 23 may also obtain time information. The time information may reflect the average execution time of the erase operation for multiple physical units in the memory module 122. For example, the execution time of the erase operation performed on a physical unit refers to the time from the start of the erase operation on the physical unit until the erase operation ends or is completed. Then, the memory control circuit 23 may generate the password information according to the error rate information and the time information.

[0056] In one embodiment, the execution time of each erase operation performed by the memory module 122 is affected by the current operating state of the memory module 122. For example, the operating state includes the applied erase voltage, the length of time the erase voltage is applied, the critical voltage distribution of the erased memory cells, the ambient temperature and / or the clock frequency, etc., and the types of the operating state are not limited thereto. Therefore, at different time points, based on the current operating state of the memory module 122, the execution time of the erase operation performed may also be different.

[0057] In one embodiment, by combining the error rate information with the time information to generate the password information, the randomness of the password information can be further improved, thereby improving the subsequent data encryption efficiency and increasing the difficulty of cracking the encrypted data. Thus, the data storage security of the storage device 12 can be more effectively improved.

[0058] In one embodiment, the memory control circuit 23 may perform an erase operation on at least one of the plurality of physical units in the memory module 122. Figure 3 In an erase operation performed on the physical unit 301(k), the memory module 122 may apply an erase voltage to each memory cell (or physical sub-unit) in the physical unit 301(k). The erase operation (or the applied erase voltage) may be used to clear the data stored in the physical unit 301(k). In addition, in response to the erase operation performed, the memory control circuit 23 may update the time information.

[0059] In one embodiment, the memory control circuit 23 may continuously monitor the usage status of the memory module 122 to obtain the total execution time of the erase operation executed on each physical unit in the memory module 122. Then, the memory control circuit 23 may obtain (or update) the time information according to the total number of physical units in the memory module 122 and the total execution time. Thus, the obtained or updated time information may reflect the average execution time of the erase operation on the plurality of physical units in real time.

[0060] In one embodiment, it is assumed that at a certain time point, the total execution time of the erase operation performed on the multiple physical units in the memory module 122 is "22451 microseconds (micro second, us)", and the total number of physical units in the memory module 122 is "1727". The memory control circuit 23 can obtain (or update) the time information according to the total execution time (i.e., "22451 microseconds") and the total number of physical units (i.e., "1727"). For example, the obtained or updated time information can reflect that the average execution time of the erase operation on the multiple physical units is "374.18333333333333333333 seconds".

[0061] In one embodiment, after obtaining the time information, the memory control circuit 23 may perform information processing (also referred to as second information processing) on ​​the time information to obtain reference information (also referred to as second reference information). Similar to the first reference information, the second reference information also conforms to the preset data format. Taking the AES-256 encryption algorithm as an example, the preset data format can be used to standardize the data length of the second reference information to a preset length to meet the subsequent calculation requirements for the AES-256 encryption algorithm. Then, the memory control circuit 23 can generate the password information based on the first reference information and the second reference information. In this way, the randomness of the password information can be further improved.

[0062] Figure 5 is a schematic diagram of generating password information according to an embodiment of the present invention. Figure 5 After obtaining the error rate information 41, the memory control circuit 23 may perform information processing 401 on the error rate information 41 to obtain reference information 42. Figure 4 The embodiments of the present invention will not be repeated here.

[0063] In one embodiment, the memory control circuit 23 may obtain the time information 51. For example, the time information 51 may reflect the average execution time of the erase operation on the plurality of physical units. For example, the average execution time may be obtained based on the total execution time of at least one erase operation executed on the plurality of physical units in the past and the total number of the plurality of physical units (for example, the total execution time is divided by the total number). For example, the time information 51 may include a value or a data sequence to reflect the average execution time.

[0064] After obtaining the time information 51, the memory control circuit 23 may perform information processing 501 (i.e., second information processing) on ​​the time information 51 to obtain reference information 52 (i.e., second reference information). For example, in the information processing 501, the memory control circuit 23 may perform extraction of at least part of the value after the decimal point, removal of at least part of the value after the decimal point, value unit conversion, polynomial operation, hash operation, or other custom processing on the time information 51. The specific operation details of the information processing 501 may be set according to the encryption algorithm adopted, and the present invention is not limited thereto. According to the result of the information processing 501, the memory control circuit 23 may obtain the reference information 52. For example, assuming that the time information 51 includes "374.183333333333333333333 (seconds)", after extracting at least part of the value after the decimal point on the time information 51, the reference information 52 may include "18333333333333333333". Similar to the time information 51 , the reference information 52 may be close to a truly random number (ie, cannot be accurately predicted).

[0065] In one embodiment, after obtaining the reference information 42 and 52, the memory control circuit 23 may perform a scrambling process 502 on the reference information 42 and 52 to obtain the reference information 53 (i.e., the third reference information). For example, in the scrambling process 502, the memory control circuit 23 may perform an XOR operation on the data sequence in the reference information 42 (also referred to as the first data sequence) and the data sequence in 52 (also referred to as the second data sequence) to obtain the reference information 53. The reference information 53 may reflect the operation result of the XOR operation. For example, the data sequence in the reference information 53 (also referred to as the third data sequence) may include a plurality of bits. Each bit in the reference information 53 may reflect the operation result of performing the XOR operation on the bits at the corresponding positions in the reference information 42 and 52. It should be noted that the scrambling process 502 may also include logical addition or other types of logical operations, which are not limited by the present invention. In this way, the randomness of the cryptographic information may be further improved.

[0066] After obtaining the reference information 53, the memory control circuit 23 can generate the password information 54 according to the reference information 53. It should be noted that the operation details of generating the password information 54 according to the reference information 53 can be referred to Figure 4 In the embodiment of the invention, the description of generating the password information 43 according to the reference information 42 may be adjusted according to practical requirements, and the present invention is not limited thereto.

[0067] In one embodiment, as long as there is continuous data writing, physical unit erasure and / or physical unit rotation in the memory module 122, the error rate information and / or the time information will continue to change unexpectedly, so that the password information generated based on the error rate information and / or the time information will also continue to change unexpectedly. Thus, the randomness of the generated password information and the difficulty of cracking the encrypted data can be effectively improved. Thus, the data storage security of the storage device 12 can be effectively improved.

[0068] In one embodiment, before storing the encrypted data in the second physical unit, the memory control circuit 23 may encode the encrypted data with an error correction code (ECC) to generate error correction data. The error correction data may be used to correct errors (i.e., error bits) in the encrypted data. For example, the error correction data may carry error correction information (e.g., an error correction code) corresponding to the encrypted data.

[0069] In one embodiment, after obtaining the encryption data and the error correction data, the memory control circuit 23 may store the encryption data in a data area of ​​a physical subunit (also referred to as a first physical subunit) in the second physical unit. For example, the first physical subunit may include at least one physical programming unit in the second physical unit. In addition, the memory control circuit 23 may store the password information and the error correction data in a spare area in the first physical subunit.

[0070] In one embodiment, the memory control circuit 23 may read the encrypted data from the data area in the first entity subunit. In addition, the memory control circuit 23 may read the error correction data and the password information from the idle area in the first entity subunit. Then, the memory control circuit 23 may restore the encrypted data to the original data according to the error correction data and the password information. For example, the decoding circuit 25 may decode the encrypted data read from the data area according to the error correction data to try to correct the errors in the read encrypted data. Then, the encryption circuit 26 may decrypt the corrected encrypted data according to the password information to restore the original data.

[0071] In one embodiment, the memory control circuit 23 may also detect system events. The system events may include at least one of a power-on event, a power-on event, and other types of custom events. For example, the custom event may include that the usage status of the storage device 12 or the memory module 122 meets a specific condition (for example, the read count, write count, and / or erase count of the memory module 122 reaches a critical value), etc., and the present invention is not limited thereto. When the system event is detected, in response to the system event, the memory control circuit 23 may send the read instruction sequence to the memory module 122 to obtain the read data. Thereafter, the memory control circuit 23 may perform subsequent operations based on the read data. The relevant operation details have been described above and will not be repeated here. However, if the system event is not detected, the memory control circuit 23 may not send the read instruction sequence to the memory module 122 to save system resources.

[0072] In one embodiment, the memory control circuit 23 may also predetermine a plurality of physical units (also referred to as candidate physical units) in the memory module 122. For example, the plurality of candidate physical units may be dispersed in different memory regions in the memory module 122. For example, the memory region includes at least one of a die, a chip enable (CE) region, and a plane in the memory module 122.

[0073] In one embodiment, before sending the read instruction sequence to the memory module to obtain the read data, the memory control circuit 23 may select one of the candidate physical units as the first physical unit according to a rotation or other type of customized method. For example, the customized method may include selecting one of the non-adjacent physical units as the first physical unit each time, and the present invention is not limited thereto. After determining the first physical unit, the memory control circuit 23 may send the read instruction sequence to the memory module to obtain the read data.

[0074] In one embodiment, by distributing the multiple candidate physical units in different components of the memory module 122 (for example, different chips, different chip enable (CE) areas, and different planes), it is possible to avoid the randomness of the subsequently generated cryptographic information being reduced due to excessive data reading of a single or a small number of areas in the memory module 122.

[0075] Figure 6 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 6 In step S601, a read instruction sequence is sent to a memory module to instruct the memory module to read a first physical unit. In step S602, read data corresponding to the read instruction sequence is obtained from the memory module. In step S603, error detection is performed on the read data to obtain error rate information of the read data. The error rate information reflects the bit error rate of the read data. In step S604, password information is generated according to the error rate information. In step S605, original data is encrypted according to the password information to generate encrypted data corresponding to the original data. In step S606, a write instruction sequence is sent to the memory module to instruct the memory module to store the encrypted data in a second physical unit.

[0076] Figure 7 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 7 In step S701, time information is obtained, wherein the time information reflects the average execution time of the erase operation on multiple physical units. In step S702, the password information is generated according to the error rate information and the time information.

[0077] However, Figure 6 and 7 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 6 and 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 6 and7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0078] In summary, the memory management method and storage device proposed in the embodiments of the present invention can generate password information for encryption based on error rate information and / or time information, such as reflecting slight changes in the current operating state of the memory module in the password information based on the error rate information and / or the time information, so as to improve the randomness of the password information. In this way, the problem that the random numbers traditionally used for encrypting data are not random enough can be effectively improved, thereby improving the data encryption efficiency and data storage security of the storage device.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: Sending a read instruction sequence to the memory module to instruct the memory module to read a first physical unit among the plurality of physical units; Obtain read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data; Generate password information according to the error rate information; Encrypting the original data according to the password information to generate encrypted data corresponding to the original data; and A write command sequence is sent to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the plurality of physical units. 2 . The memory management method according to claim 1 , wherein the error detection does not include error correction of the read data.

3. The memory management method according to claim 1, wherein the step of generating the password information according to the error rate information comprises: Performing first information processing on the error rate information to obtain first reference information, wherein the first reference information conforms to a preset data format, and the preset data format matches an encryption algorithm used to generate the password information; as well as The password information is generated according to the first reference information.

4. The memory management method according to claim 1, wherein the step of generating the password information according to the error rate information comprises: Acquire time information, wherein the time information reflects an average execution time of an erase operation on the plurality of physical units; as well as The password information is generated according to the error rate information and the time information.

5. The memory management method according to claim 4, further comprising: performing the erase operation on at least one of the plurality of physical units; as well as In response to the erase operation, the time information is updated.

6. The memory management method according to claim 4, wherein the step of generating the password information according to the error rate information and the time information comprises: performing first information processing on the error rate information to obtain first reference information, wherein the first reference information conforms to a preset data format, wherein the preset data format matches an encryption algorithm used to generate the password information; Performing second information processing on the time information to obtain second reference information, wherein the second reference information complies with the preset data format; as well as The password information is generated according to the first reference information and the second reference information.

7. The memory management method according to claim 6, wherein the step of generating the password information according to the first reference information and the second reference information comprises: performing scrambling processing on the first reference information and the second reference information to obtain third reference information; as well as The password information is generated according to the third reference information.

8. The memory management method according to claim 1, wherein the step of sending the read instruction sequence to the memory module comprises: Detecting system events, wherein the system events include at least one of a boot event, a power-on event, and a custom event; as well as In response to the system event, the read command sequence is sent to the memory module.

9. The memory management method according to claim 1, further comprising: predetermining a plurality of candidate entity units among the plurality of entity units; and Before sending the read instruction sequence to the memory module, one of the candidate physical units is selected as the first physical unit in a rotation or customized manner. 10 . The memory management method according to claim 9 , wherein the plurality of candidate physical units are dispersed in different memory areas in the memory module, and the memory area comprises at least one of a die, a chip enable area, and a plane.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: Sending a read instruction sequence to the memory module to instruct the memory module to read a first physical unit among the plurality of physical units; Obtain read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data; Generate password information according to the error rate information; Encrypting the original data according to the password information to generate encrypted data corresponding to the original data; as well as A write command sequence is sent to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the plurality of physical units.

12. The memory device of claim 11, wherein the error detection does not include error correction of the read data.

13. The storage device according to claim 11, wherein the operation of the memory controller generating the password information according to the error rate information comprises: Performing first information processing on the error rate information to obtain first reference information, wherein the first reference information complies with a preset data format; as well as The password information is generated according to the first reference information.

14. The storage device according to claim 11, wherein the operation of the memory controller generating the password information according to the error rate information comprises: Acquire time information, wherein the time information reflects an average execution time of an erase operation on the plurality of physical units; as well as The password information is generated according to the error rate information and the time information.

15. The storage device according to claim 14, wherein the memory controller is further configured to: performing the erase operation on at least one of the plurality of physical units; and In response to the erase operation, the time information is updated.

16. The storage device according to claim 14, wherein the operation of the memory controller generating the password information according to the error rate information and the time information comprises: performing first information processing on the error rate information to obtain first reference information, wherein the first reference information conforms to a preset data format, wherein the preset data format matches an encryption algorithm used to generate the password information; Performing second information processing on the time information to obtain second reference information, wherein the second reference information complies with the preset data format; as well as The password information is generated according to the first reference information and the second reference information.

17. The storage device according to claim 16, wherein the operation of the memory controller generating the password information according to the first reference information and the second reference information comprises: Performing a scrambling operation on the first reference information and the second reference information to obtain third reference information; as well as The password information is generated according to the third reference information.

18. The storage device according to claim 11, wherein the operation of the memory controller sending the read command sequence to the memory module comprises: Detecting system events, wherein the system events include at least one of a boot event, a power-on event, and a custom event; as well as In response to the system event, the read command sequence is sent to the memory module.

19. The storage device according to claim 11, wherein the memory controller is further configured to: predetermining a plurality of candidate entity units among the plurality of entity units; and Before sending the read instruction sequence to the memory module, one of the candidate physical units is selected as the first physical unit in a rotation or customized manner. 20 . The memory device of claim 19 , wherein the plurality of candidate physical units are dispersed in different memory regions in the memory module, and the memory regions include at least one of a die, a chip enable region, and a plane.

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