Display device and driving method

Abstract

The present disclosure relates to a display device capable of stabilizing a threshold voltage of a driving transistor and a driving method of the display device. The display device may include a display area and a bezel area. The first switch and the second switch may be disposed in the bezel area. A first switch may be connected between the first voltage line and the first sub-pixel, and a second switch may be connected between the second voltage line and the first sub-pixel. During an initialization period, the first switch may be turned on to provide a first voltage to the first sub-pixel, and during an on period, the second switch may be turned on to provide a second voltage to the first sub-pixel.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices having displays, and more particularly, to display devices and methods of driving the display devices. Background Art

[0002] As the information society develops, various demands for display devices for displaying images increase. Recently, various types of display devices such as liquid crystal display (LCD) devices, organic light emitting diode (OLED) display devices, etc. have been developed and widely used.

[0003] In order to increase pixels per inch (PPI), which represents the number of pixels in 1 inch, it is desired to further increase the circuit integration of the display panel.

[0004] The display panel may include a driving transistor for driving the light emitting device.

[0005] When the driving transistor is driven, a body voltage may be supplied to the body of the driving transistor. In this case, a body effect may occur depending on the body voltage. Summary of the invention

[0006] In order to improve the circuit integration of the display panel, it is desirable to reduce the number of components disposed on the display panel.

[0007] Furthermore, when a bulk voltage is supplied to a driving transistor, a threshold voltage of the driving transistor may vary due to a bulk effect.

[0008] In order to solve these problems, one or more aspects of the present disclosure may provide a display device capable of stably controlling a threshold voltage of a driving transistor and a driving method of the display device.

[0009] One or more aspects of the present disclosure may provide a display device capable of enabling a circuit provided in a display panel to be configured with improved integration, and a driving method of the display device.

[0010] One or more aspects of the present disclosure may provide a display device capable of being driven with low power consumption by enabling a circuit provided in a display panel to be configured to have improved integration, and a driving method of the display device.

[0011] According to various aspects of the present disclosure, a display device can be provided, which includes: a display area, in which a plurality of sub-pixels including a first sub-pixel are arranged; a border area different from the display area; a plurality of voltage lines, which are arranged in the border area and include a first voltage line and a basic voltage line; and a first switch and a second switch arranged in the border area, wherein the first switch is electrically connected between the basic voltage line and the first sub-pixel, and the second switch is electrically connected between the first voltage line among the plurality of voltage lines and the first sub-pixel.

[0012] According to various aspects of the present disclosure, a driving method for a display device can be provided, the driving method comprising the following steps: an initialization step, in which a first switch arranged in a border area is turned on, and a first voltage is provided to a first sub-pixel arranged in a display area; and a light-emitting step, in which a second switch arranged in the border area is turned on, a second voltage is provided to the first sub-pixel, and the first sub-pixel emits light.

[0013] According to one or more aspects of the present disclosure, a display device capable of stably controlling a threshold voltage of a driving transistor and a driving method of the display device may be provided.

[0014] According to one or more aspects of the present disclosure, a display device and a driving method of the display device may be provided, which enable a circuit provided in a display panel to be configured to have improved integration.

[0015] According to one or more aspects of the present disclosure, a display device and a driving method of the display device can be provided, which can be driven with low power consumption by enabling a circuit provided in a display panel to be configured with improved integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the present disclosure, illustrate various aspects of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0017] Figure 1 An exemplary system configuration of a display device according to aspects of the present disclosure is shown;

[0018] Figure 2 An example equivalent circuit of a sub-pixel included in a display device according to aspects of the present disclosure is shown;

[0019] Figure 3An example equivalent circuit of a sub-pixel in a display device according to aspects of the present disclosure and an example structure of a driving transistor included in the sub-pixel are shown;

[0020] Figure 4 is an example graph showing a change in threshold voltage with body voltage in a display device according to aspects of the present disclosure;

[0021] Figure 5 and Figure 6 An example configuration of a display panel including at least one initialization transistor and at least one light emitting transistor in a display device according to aspects of the present disclosure is shown;

[0022] Figure 7 An example configuration of a display panel including the initialization transistor and the light emitting transistor in Embodiment 1 in a display device according to aspects of the present disclosure is shown;

[0023] Figures 8 to 15 shows exemplary driving timings of the initialization transistor and the light emitting transistor in Embodiment 1 in the display panel according to aspects of the present disclosure;

[0024] Fig.16 and Fig.17 1. The configuration of the initialization transistor and the light emitting transistor in Embodiment 2 in the display panel according to aspects of the present disclosure is shown;

[0025] Figures 18 to 26 shows exemplary driving timings of the initialization transistor and the light emitting transistor in Embodiment 2 in the display panel according to aspects of the present disclosure; and

[0026] Fig. 27 is an example flow chart of a driving method of a display device according to aspects of the present disclosure. DETAILED DESCRIPTION

[0027] Now will be referred to in detail the embodiment of the present disclosure, examples of which may be shown in the accompanying drawings, in the following description, the structures, embodiments, implementations, methods and operations described herein are not limited to one or more specific examples set forth herein, and may be changed as known in the art, unless otherwise stated. Unless otherwise stated, the same reference numerals always represent the same elements. The names of the various elements used in the following description are selected only for the convenience of writing this specification, and therefore may be different from those used in the actual product. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that the description may make the subject matter in some embodiments of the present disclosure unclear, the detailed description of the known functions and components incorporated herein will be omitted. The terms used herein, such as "including", "having", "containing", "consisting of", "consisting of ... "and "formed by ... "are generally intended to allow the addition of other components, unless the term is used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0028] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0029] When it is mentioned that a first element is "connected or coupled to", "contacts or overlaps", etc. a second element, it should be interpreted that not only the first element can be "directly connected or coupled to" or "directly contact or overlaps" the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled to", "contacts or overlaps", etc. each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are "connected or coupled to", "contacts or overlaps", etc. each other.

[0030] When time-related terms such as "after", "next", "next", "before", etc. are used to describe the processing or operation of an element or configuration, or the flow or steps in an operation, process, or manufacturing method, these terms can be used to describe non-sequential or non-sequential processes or operations unless the terms "directly" or "immediately" are used together.

[0031] Furthermore, when any dimension, relative dimension, etc. is mentioned, it should be considered that the numerical value of an element or feature, or corresponding information (e.g., degree, range, etc.) includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impact, noise, etc.), even when no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0032] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 An exemplary system configuration of the display device 100 according to aspects of the present disclosure is described.

[0034] Reference Figure 1 , the display device 100 may include a display panel 110 and at least one driving circuit for driving the display panel 110 .

[0035] The display panel 110 may include, for example, a silicon material. In an example where the display panel 110 includes a silicon material and an organic light emitting device such as an organic light emitting diode (OLED), the display panel 110 may be referred to as a silicon-based OLED (OLEDoS) panel. The display panel 110 may also include glass.

[0036] The display panel 110 may include a plurality of signal lines, such as a plurality of data lines DL and a plurality of gate lines GL, and include a plurality of sub-pixels SP. The display panel 110 may include a display area AA allowing an image to be displayed and a border area BA in which an image is not displayed. A plurality of sub-pixels SP for displaying an image may be disposed in the display area AA of the display panel 110. The driving circuit (120, 130, and 140) may be electrically connected to or mounted on the border area BA of the display panel 110. In addition, a pad portion to which at least one integrated circuit or at least one printed circuit board is connected may be disposed in the border area BA of the display panel 110.

[0037] The at least one driving circuit may include a data driving circuit 120 , a gate driving circuit 130 , etc., and further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130 .

[0038] The data driving circuit 120 may be a circuit for driving a plurality of data lines DL and may provide data signals to the plurality of data lines DL. The gate driving circuit 130 may be a circuit for driving a plurality of gate lines GL and may provide gate signals to the plurality of gate lines GL.

[0039] The gate driving circuit 130 may provide a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive the plurality of gate lines GL by sequentially providing the gate signal of an on-level voltage to the plurality of gate lines GL.

[0040] The controller 140 may provide the data control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may provide the gate control signal GCS to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0041] The controller 140 can start scanning pixels according to the corresponding timing set in each frame, convert the image data input from the external device or the external image providing source (for example, the host system) into the form of a data signal that can be read by the data driving circuit 120, and then provide the converted image data Data to the data driving circuit 120, and in accordance with the scanning of at least one pixel (or at least one pixel array) in the pixels, control the loading of the image data to the at least one pixel at the moment when the illumination of at least one corresponding light-emitting device of the at least one pixel is predetermined.

[0042] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 can receive timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, etc., generate several types of control signals (DCS, GCS, etc.), and output the generated signals to the data driving circuit 120 and the gate driving circuit 130.

[0043] The controller 140 may be implemented in a separate component from the data driving circuit 120 , or integrated with the data driving circuit 120 , such that the controller 140 and the data driving circuit 120 may be implemented in a single integrated circuit.

[0044] The data driving circuit 120 can drive the plurality of data lines DL by providing a data voltage corresponding to the image data Data received from the controller 140 to the plurality of data lines DL. The data driving circuit 120 may also be referred to as a source driving circuit. The data driving circuit 120 may include, for example, one or more source driver integrated circuits SDIC. Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, etc. In one or more embodiments, each source driver integrated circuit SDIC may further include an analog-to-digital converter ADC.

[0045] In one or more embodiments, each source driver integrated circuit SDIC can be connected to the display panel 110 using tape automated bonding (TAB) technology, or connected to a conductive pad such as a bonding pad of the display panel 110 using chip on glass (COG) technology or chip on panel (COP) technology, or implemented in the display panel 110 using chip on film (COF) technology.

[0046] In one or more embodiments, the gate driving circuit 130 may be connected to the display panel 110 using a tape automated bonding (TAB) technique, or connected to a conductive pad such as a bonding pad of the display panel 110 using a chip on glass (COG) technique or a chip on panel (COP) technique, or implemented in the display panel 110 using a chip on film (COF) technique. In one or more embodiments, the gate driving circuit 130 may be formed in the bezel area BA of the display panel 110 using a gate in panel (GIP) technique.

[0047] When a specific gate line is selected and driven by the gate driving circuit 130 , the data driving circuit 120 may convert the image data Data received from the controller 140 into a data voltage in an analog form and provide the converted data voltage to the plurality of data lines DL.

[0048] The data driving circuit 120 may be located in only one side or part (e.g., the upper edge or the lower edge) of the display panel 110, and / or may be electrically connected to only one side or part (e.g., the upper edge or the lower edge) of the display panel 110, but is not limited thereto. In one or more embodiments, according to a driving scheme, a panel design scheme, etc., the data driving circuit 120 may be located in at least two of the two sides or parts (e.g., the upper edge and the lower edge) of the display panel 110 or the four sides or parts (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110, and / or may be electrically connected to at least two sides or parts (e.g., the upper edge and the lower edge) of the display panel 110 or the four sides or parts (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110, but is not limited thereto.

[0049] The gate drive circuit 130 may be located in only one side or portion (e.g., the left edge or the right edge) of the display panel 110, and / or may be electrically connected to only one side or portion (e.g., the left edge or the right edge) of the display panel 110, but is not limited thereto. In one or more embodiments, according to a driving scheme, a panel design scheme, etc., the gate drive circuit 130 may be located in at least two of the two sides or portions (e.g., the left edge and the right edge) of the panel 110 or the four sides or portions (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the panel 110, and / or may be electrically connected to at least two of the two sides or portions (e.g., the left edge and the right edge) of the panel 110 or the four sides or portions (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the panel 110, but is not limited thereto.

[0050] The controller 140 may be a timing controller 140 used in a typical display technology, or a control device / equipment capable of additionally performing other control functions in addition to the typical functions of the timing controller. In one or more embodiments, the controller 140 may be one or more other control circuits different from the timing controller 140, or a circuit or component in a control device / equipment. The controller 140 may be implemented using various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, etc.

[0051] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, etc. The controller 140 may send and receive signals to and from the data driving circuit 120 via one or more predetermined interfaces. For example, such an interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc. The controller 140 may include a storage medium or one or more storage locations, such as one or more registers.

[0052] In one or more aspects, the display device 100 may be a self-luminous display with or without a backlight unit, such as an organic light emitting diode (OLED) display, a quantum dot (QD) display, a micro light emitting diode (M-LED) display, etc.

[0053] Figure 2 An example equivalent circuit of a sub-pixel SP included in the display device 100 according to aspects of the present disclosure is shown.

[0054] Reference Figure 2 , the display panel 110 may include a plurality of sub-pixels SP disposed on a substrate SUB. The display panel 110 may include a silicon material or a glass substrate.

[0055] Reference Figure 2 In one or more embodiments, each of the plurality of sub-pixels SP provided in the display panel 110 of the display device 100 may include a light emitting device ED, a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, a storage capacitor Cst, etc. Such a circuit structure in which one sub-pixel SP is configured with three transistors (3T: DRT, SCT, and SENT) and one capacitor (1C: CST) may be referred to as a "3T1C structure".

[0056] The light emitting device ED may include a pixel electrode PE, a common electrode CE, and a light emitting layer EL disposed between the pixel electrode PE and the common electrode CE. For example, the pixel electrode PE may be disposed in each sub-pixel SP, and the common electrode CE may be disposed in all or two or more of the plurality of sub-pixels SP. For example, the pixel electrode PE may be an anode, and the common electrode CE may be a cathode. In another example, the pixel electrode PE may be a cathode, and the common electrode CE may be an anode. In one or more embodiments, the light emitting device ED may be an organic light emitting diode (OLED), a light emitting device configured with quantum dots, a micro light emitting diode (μ-LED), a light emitting diode (LED) based on an inorganic material, and the like.

[0057] In an example where the light emitting device ED is an organic light emitting diode (OLED), the display panel 110 may be an OLED on silicon (OLEDoS) panel.

[0058] The driving transistor DRT may be a transistor for driving the light emitting device ED, and may include a first node N1, a second node N2, a third node N3, and the like.

[0059] The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to a source or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be a source or drain node of the driving transistor DRT. The second node N2 may be electrically connected to a source or drain node of the sensing transistor SENT and may also be connected to a pixel electrode PE of the light emitting device ED. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL for carrying a driving voltage EVDD.

[0060] The scanning transistor SCT may be controlled by a scanning signal SCAN and may be connected between the first node N1 of the driving transistor DRT and the data line DL. The scanning transistor SCT may be turned on or off by the scanning signal SCAN transmitted through the scanning signal line SCL as a type of gate line GL, and may control the electrical connection between the data line DL and the first node N1 of the driving transistor DRT.

[0061] The scan transistor SCT may be turned on by the scan signal SCAN having an on-level voltage and transfer the data voltage Vdata transmitted through the data line DL to the first node N1 of the driving transistor DRT.

[0062] The on-level voltage of the scan signal SCAN for turning on the scan transistor SCT may be a high-level voltage or a low-level voltage. The off-level voltage of the scan signal SCAN for turning off the scan transistor SCT may be a low-level voltage or a high-level voltage. In an example in which the scan transistor SCT is an n-type transistor, the on-level voltage may be a high-level voltage, and the off-level voltage may be a low-level voltage. In another example in which the scan transistor SCT is a p-type transistor, the on-level voltage may be a low-level voltage, and the off-level voltage may be a high-level voltage.

[0063] The sensing transistor SENT may be controlled by a sensing signal SENSE and may be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. The sensing transistor SENT may be turned on or off by a sensing signal SENSE carried by a sensing signal line SENL (which is another type of gate line GL) and controls the electrical connection between the second node N2 of the driving transistor DRT and the reference voltage line RVL.

[0064] The sensing transistor SENT may be turned on by the sensing signal SENSE having an on-level voltage and transfer the reference voltage Vref carried by the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0065] The on-level voltage of the sensing signal SENSE for turning on the sensing transistor SENT may be a high level voltage or a low level voltage. The off-level voltage of the sensing signal SENSE for turning off the sensing transistor SENT may be a low level voltage or a high level voltage. In an example where the sensing transistor SENT is an n-type transistor, the on-level voltage may be a high level voltage, and the off-level voltage may be a low level voltage. In another example where the sensing transistor SENT is a p-type transistor, the on-level voltage may be a low level voltage, and the off-level voltage may be a high level voltage.

[0066] In one or more embodiments, the display device 100 may further include a line capacitor Crv1 formed between the reference voltage line RVL and the ground GND, a sampling switch SAM for controlling the connection between the reference voltage line RVL and the analog-to-digital converter ADC, and a power switch SPRE for controlling the connection between the reference voltage line RVL and the reference voltage supply node Nref. The reference voltage Vref output from the power supply may be provided to the reference voltage source node Nref and then provided to the reference voltage line RVL through the power switch SPRE.

[0067] Furthermore, the sensing transistor SENT may be turned on by the sensing signal SENSE having an on-level voltage and thus transfer the voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL. Thus, charging of the line capacitor Crv1 formed between the reference voltage line RVL and the ground GND may be performed.

[0068] For example, when driving the corresponding sub-pixel SP to detect one or more characteristic values ​​of the sub-pixel SP, the function of the sensing transistor SENT that transmits the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used. In this example, the voltage transmitted to the reference voltage line RVL can be a voltage that determines the characteristic value of the sub-pixel SP or a voltage that includes the characteristic value of the sub-pixel SP.

[0069] Here, the characteristic value of the subpixel SP may be a characteristic value of the driving transistor DRT or the light emitting device ED. The characteristic value of the driving transistor DRT may include a threshold voltage and / or mobility of the driving transistor DRT. The characteristic value of the light emitting device ED may include a threshold voltage of the light emitting device ED.

[0070] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT may be an n-type transistor or a p-type transistor. Here, for ease of description, a discussion is provided based on an example in which each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is an n-type transistor.

[0071] The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst may store an amount of charge corresponding to the voltage difference between the two terminals and maintain the voltage difference between the two terminals for a predetermined frame time. As a result, the corresponding sub-pixel SP may emit light within the predetermined frame time.

[0072] The storage capacitor Cst may be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor such as a parasitic capacitor (eg, Cgs or Cgd) that may be formed between the gate node and the source node (or drain node) of the driving transistor DRT.

[0073] In an embodiment, the scan signal line SCL and the readout signal line SENL may be different gate lines GL. In this embodiment, the scan signal SCAN transmitted through the scan signal line SCL and the sense signal SENSE transmitted through the sense signal line SENL may be separate gate signals, and the respective turn-on and / or turn-off timings of the scan transistor SCT and the sense transistor SENT in one sub-pixel SP may be independent of each other. For example, according to design requirements, the turn-on and / or turn-off timing of the scan transistor SCT in one sub-pixel SP and the turn-on and / or turn-off timing of the sense transistor SENT may be the same as or different from each other.

[0074] In another embodiment, the scanning signal line SCL and the sensing signal line SENL may be the same gate line GL. For example, the gate node of the scanning transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP may be connected to one gate line GL. In this embodiment, the scanning signal SCAN transmitted through the scanning signal line SCL and the sensing signal SENSE transmitted through the sensing signal line SENL may be the same gate signal, and the respective turn-on and / or turn-off timings of the scanning transistor SCT and the sensing transistor SENT in one sub-pixel SP may be the same.

[0075] In one embodiment, the reference voltage line RVL may be provided in each column of the sub-pixels SP. In another embodiment, the reference voltage line RVL may be provided in every two or more columns of the sub-pixels SP. In the embodiment in which the reference voltage line RVL is provided in every two or more columns of the sub-pixels SP, a plurality of sub-pixels SP may receive the reference voltage Vref through one reference voltage line RVL.

[0076] Each driving transistor DRT included in a plurality of sub-pixels SP provided in the display panel 110 of the display device 100 may have one or more unique characteristic values. For example, the characteristic values ​​of the driving transistor DRT may include a threshold voltage, a mobility, and the like.

[0077] The characteristic value of each driving transistor DRT included in each of the plurality of sub-pixels SP may vary with the passage of driving time. The respective driving times of the sub-pixels SP may be different from each other. For example, the driving time of some of the plurality of sub-pixels SP may be different from the driving time of one or more other sub-pixels SP or other sub-pixels SP. Therefore, the characteristic value of the corresponding one or more driving transistors DRT of one or more sub-pixels SP in the plurality of sub-pixels SP may be different from the characteristic value of the corresponding one or more driving transistors DRT of one or more other sub-pixels SP.

[0078] Due to differences in characteristic values ​​between a plurality of driving transistors DRT provided in the display panel 110, a brightness difference between a plurality of sub-pixels SP provided on the display panel 110 may occur. Therefore, brightness non-uniformity of the display panel 110 may occur.

[0079] To solve this problem, in one or more embodiments, the display device 100 may provide a compensation function of performing a sensing drive on the sub-pixels SP of the display panel 110, detecting corresponding characteristic values ​​of the driving transistors DRT, and performing an operation for reducing the characteristic value difference between the driving transistors DRT.

[0080] Figure 3 An example equivalent circuit of a sub-pixel SP in the display device 100 according to aspects of the present disclosure and an example structure of a driving transistor DRT included in the sub-pixel SP are illustrated. Figure 4 is an example graph illustrating a change in a threshold voltage according to a bulk voltage in the display device 100 according to aspects of the present disclosure.

[0081] Reference Figure 3 In one or more embodiments, a sub-pixel SP provided in the display panel 110 of the display apparatus 100 may include a light emitting device ED, a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, a storage capacitor Cst, and the like. Figure 3 The sub-pixel SP shown may be substantially equal to Figure 2 However, Figure 2 The scanning transistor SCT and the sensing transistor SENT can be controlled by different signals from each other, which can be called dual scanning drive. Figure 3 The scanning transistor SCT and the sensing transistor SENT can be controlled by the same signal, which can be called single scanning drive. Figure 3 As shown, a gate node of the scan transistor SCT and a gate node of the sense transistor SENT may be electrically connected to a scan signal line SCL.

[0082] Figure 3 A cross-sectional view of a corresponding driving transistor DRT disposed in a partial region A3 of the sub-pixel SP is shown.

[0083] The driving transistor DRT may include a body 310 , a drain layer 320 , a source layer 330 , an active layer 340 , a gate insulating layer 350 , and a gate layer 360 .

[0084] The drain layer 320 , the source layer 330 , and the active layer 340 may be disposed on the body 310 .

[0085] The active layer 340 may be disposed between the drain layer 320 and the source layer 330 .

[0086] The gate insulating layer 350 may be disposed on the active layer 340 .

[0087] The gate layer 360 may be disposed on the gate insulating layer 350 .

[0088] The source layer 330 may be a source node, which may be Figure 2 The second node N2 is shown.

[0089] The drain layer 320 may be a drain node, which may be Figure 2 The third node N3 is shown.

[0090] A driving voltage EVDD may be supplied to the drain layer 320 .

[0091] The data voltage Vdata may be provided to the gate layer 360 .

[0092] A reference voltage Vref may be provided to the source layer 330 .

[0093] The driving current may flow from the drain electrode layer 320 to the source electrode layer 330 by the voltage charged in the storage capacitor Cst. Therefore, the driving current may flow along the active layer 340.

[0094] The driving transistor DRT may have one or more unique characteristics. The unique characteristics of the driving transistor DRT may include a threshold voltage Vth. The threshold voltage Vth of the driving transistor DRT may have an initial threshold voltage value Vt0. The threshold voltage Vth of the driving transistor DRT may have a value that varies based on external factors.

[0095] In addition, a body voltage may be supplied to the body 310. When such a body voltage is supplied to the body 310, a body effect may occur. The body effect may mean a phenomenon in which a threshold voltage of a transistor varies as a body voltage is supplied to the body of the transistor.

[0096] Figure 4 A graph showing how the threshold voltage varies as a function of the bulk voltage.

[0097] The threshold voltage Vth may be represented by the following equation: “Threshold voltage (Vth) = initial threshold voltage (Vt0) + body effect coefficient (a) * source body voltage (Vsb)”. The source body voltage Vsb may be a voltage value obtained by subtracting the voltage of the body 310 from the voltage of the source layer 330. The body effect coefficient (a) may be a coefficient obtained by experiment.

[0098] When the source-to-body voltage Vsb is small, the corresponding threshold voltage Vth may be the initial threshold voltage Vt0. However, when the source-to-body voltage Vsb increases, the corresponding threshold voltage Vth may increase.

[0099] When the threshold voltage Vth increases, image quality may be deteriorated depending on such increased threshold voltage Vth. Therefore, in order to compensate for the increased threshold voltage Vth, the display device 100 may need to unnecessarily increase the corresponding data voltage Vdata.

[0100] In particular, when the display panel 110 is an OLEDoS panel, the display device 100 may need to provide a body voltage to the body 310 to ensure stable driving of the corresponding driving transistor DRT. That is, in an example where an OLEDoS panel as the display panel 110 is used in the display device 100, a change in the threshold voltage caused by the body effect may be problematic for stable driving of the corresponding driving transistor DRT.

[0101] Furthermore, in an example using an OLEDoS panel, in order to achieve ultra-high resolution, each sub-pixel included in the display device 100 may need to have a size as small as a micro-level. In order to reduce the size of the sub-pixel, it is desirable to minimize elements included in the sub-pixel.

[0102] In order to solve these problems, aspects of the present disclosure may provide a display device 100 and a driving method of the display device 100 capable of stably controlling a threshold voltage of a driving transistor.

[0103] Aspects of the present disclosure may provide a display device 100 that enables a circuit provided in a display panel 110 to be configured to have an improved degree of integration, and a driving method of the display device 100 .

[0104] Aspects of the present disclosure may provide a display device 100 capable of being driven with low power consumption by enabling a circuit provided in the display panel 110 to be configured with improved integration, and a driving method of the display device 100 .

[0105] Figure 5 and Figure 6 An example configuration of a display panel 110 including at least one initialization transistor and at least one light emitting transistor in a display device 100 according to aspects of the present disclosure is described.

[0106] refer to Figure 5 , the display panel 110 may include a display area AA and a bezel area BA.

[0107] The display area AA may be an area where an image is allowed to be displayed, and the bezel area BA may be an area where an image is not displayed.

[0108] A plurality of sub-pixels SP may be disposed in the display area AA.

[0109] At least one driving circuit, at least one voltage line, at least one signal line, etc. for driving the plurality of sub-pixels SP may be disposed in the bezel area BA.

[0110] Figure 5 A partial area A5 of the display panel 110 is shown. The area A5 of the display panel 110 may include a portion of the display area AA and a portion of the bezel area BA.

[0111] Figure 5 Two initialization transistors, two light emitting transistors, and six sub-pixels SP disposed in the display area AA are shown.

[0112] A plurality of initialization transistors (eg, first and second initialization transistors 511 and 521 ) and a plurality of light emitting transistors (eg, first and second light emitting transistors 512 and 522 ) may be disposed in the bezel area BA.

[0113] Voltage lines for electrically connecting the plurality of initialization transistors to the sub-pixels SP may be provided in the bezel area BA and the display area AA.

[0114] Voltage lines for electrically connecting the plurality of light emitting transistors to the sub-pixels SP may be provided in the bezel area BA and the display area AA.

[0115] A plurality of gate lines GL may be disposed in the bezel area BA and the display area AA.

[0116] The first gate line GL1 may be electrically connected to the first subpixel Spa, the second subpixel SPb, and the third subpixel SPc. The subpixels SP connected to the first gate line GL1 may be referred to as a first column subpixel group.

[0117] The first voltage line VL1 may be electrically connected to the first subpixel Spa, the second subpixel SPb, and the third subpixel SPc.

[0118] The first voltage line VL1 may be electrically connected to the first initialization transistor 511 and the first light emitting transistor 512 .

[0119] The first initialization transistor 511 may be provided with a first initialization signal Init1 through a gate node thereof. The first initialization transistor 511 may be controlled by the first initialization signal Init1. The first initialization transistor 511 may be provided with a first voltage V1.

[0120] The first light emitting transistor 512 may provide a first light emitting signal Em1 through a gate node thereof. The first light emitting transistor 512 may be controlled by the first light emitting signal Em1. The first light emitting transistor 512 may be provided with a second voltage V2.

[0121] By controlling the first initialization signal Init1 and the first emission signal Em1, the first voltage V1 or the second voltage V2 may be supplied to the first subpixel Spa, the second subpixel SPb, and the third subpixel SPc. Since the first voltage V1 or the second voltage V2 may be supplied to the subpixel SP, the threshold voltage of the driving transistor DRT included in the subpixel SP may be stably controlled.

[0122] The second gate line GL2 may be electrically connected to the fourth sub-pixel SPd, the fifth sub-pixel SPe, and the sixth sub-pixel SPf. The sub-pixels SP connected to the second gate line GL2 may be referred to as a second column sub-pixel group. Figure 7 In the following description, the first row sub-pixel group, the second row sub-pixel group, and the third row sub-pixel group are described. In the description of the corresponding part, it can be expressed as "the first column sub-pixel group includes the first sub-pixel SP1". In addition, it can be expressed as "the second column sub-pixel group includes the second sub-pixel SP2, and the third column sub-pixel group includes the third sub-pixel SP3".

[0123] The second voltage line VL2 may be electrically connected to the fourth subpixel SPd, the fifth subpixel SPe, and the sixth subpixel SPf.

[0124] The second voltage line VL2 may electrically connect the second initialization transistor 521 and the second light emitting transistor 522 .

[0125] The second initialization transistor 521 may be provided with a second initialization signal Init2 from a gate node of the second initialization transistor 521. The second initialization transistor 521 may be controlled by the second initialization signal Init2. The second initialization transistor 521 may be provided with a first voltage V1.

[0126] The second light emitting transistor 522 may be provided with a second light emitting signal Em2 through a gate node of the second light emitting transistor 522. The second light emitting transistor 522 may be controlled by the second light emitting signal Em2. The second light emitting transistor 522 may be provided with a second voltage V2.

[0127] By controlling the second initialization signal Init2 and the second emission signal Em2, the first voltage V1 or the second voltage V2 may be supplied to the fourth subpixel SPd, the fifth subpixel SPe, and the sixth subpixel SPf. Since the first voltage V1 or the second voltage V2 may be supplied to the subpixel SP, the threshold voltage of the driving transistor DRT included in the subpixel SP may be stably controlled.

[0128] After the first initialization transistor 511 and the first light emitting transistor 512 are controlled during the first period, the second initialization transistor 521 and the second light emitting transistor 522 may be controlled during the second period.

[0129] The first column of sub-pixel groups may be controlled during a first period, and the second column of sub-pixel groups may be controlled during a second period.

[0130] During the first period, the driving transistor included in the first column sub-pixel group may be stably controlled, and during the first period, the storage capacitor included in the first column sub-pixel group is charged.

[0131] During the second period, the driving transistor included in the second column sub-pixel group may be stably controlled, and during the second period, the storage capacitor included in the second column sub-pixel group may be charged with a voltage for emitting light.

[0132] A structure in which one sub-pixel includes one light-emitting device and three transistors may be referred to as a “3T1C structure.” A structure in which one sub-pixel includes one light-emitting device and two transistors may be referred to as a “2T1C structure.” Figure 5 Each of the plurality of sub-pixels SP shown may include a driving transistor, a scanning transistor, a storage capacitor, a light emitting device, etc. Therefore, Figure 5 Each sub-pixel SP shown may have a “2T1C structure” or a “3T1C structure”.

[0133] Reference Figure 5 The initialization transistor and the light emitting transistor may be disposed in a portion of the frame area BA adjacent to any one of the upper edge, the lower edge, the left edge, and the right edge of the display area AA. For example, the initialization transistor and the light emitting transistor may be disposed in a portion of the frame area BA.

[0134] In another example, the initialization transistor and the light emitting transistor may be disposed in two or more portions of the bezel area BA. Figure 6 , the display panel 110 may include a display area AA, a first frame area BA1 and a second frame area BA2. The first frame area BA1 and the second frame area BA2 may be located at both sides of the display area AA.

[0135] Reference Figure 5 and Figure 6 , the first initialization transistor 511 , the first light emitting transistor 512 , the second initialization transistor 521 , and the second light emitting transistor 522 may be disposed in the first border area BA1 .

[0136] Reference Figure 6 , the third initialization transistor 531 , the third light emitting transistor 532 , the fourth initialization transistor 541 , and the fourth light emitting transistor 542 may be disposed in the second bezel area BA2 .

[0137] Figure 7An example configuration of the display panel 110 including the initialization transistor and the light emitting transistor in Embodiment 1 in the display device 100 according to aspects of the present disclosure is shown.

[0138] Figure 7 It is shown that by controlling the first initialization signal Init1 and the first light emitting signal Em1, the driving voltage EVDD or the base voltage EVSS can be provided to the first sub-pixel SP1. During the initialization period T_Init, the base voltage EVSS can be provided to the first sub-pixel SP1, and during the light emitting period T_Em, the driving voltage EVDD can be provided to the first sub-pixel SP1. As a result of this operation, the threshold voltage of the driving transistor DRT included in the first sub-pixel SP1 can be stably controlled. Figure 7 The first sub-pixel SP1 shown in FIG. Figure 5 The first sub-pixel SPa shown in FIG.

[0139] A plurality of sub-pixels SP may be disposed in the display area AA, and a driving circuit, a voltage line, a signal line, etc. for driving the sub-pixels SP may be disposed in the bezel area BA.

[0140] Figure 7 One sub-pixel SP disposed in the display area AA is shown. Figure 7 An initialization transistor 711, a light emitting transistor 712, a main base voltage line 750, and a main driving voltage line 760 disposed in the bezel area BA are shown.

[0141] Reference Figure 7 In one or more embodiments, the sub-pixel SP may include a light emitting device ED, a driving transistor DRT, a scanning transistor SCT, a storage capacitor Cst, and the like.

[0142] The driving transistor DRT may be a transistor for driving the light emitting device ED. The driving transistor DRT may be electrically connected between the second node N2 and the third node N3. A gate node of the driving transistor DRT may be electrically connected to or correspond to the first node N1.

[0143] The scan transistor SCT may be electrically connected between the data line DL and the first node N1. A gate node of the scan transistor SCT may be electrically connected to the first gate line GL1. A corresponding data voltage Vdata may be provided to a gate node of the driving transistor DRT by control of the scan transistor SCT.

[0144] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2. The storage capacitor Cst may be charged with a voltage of a certain level, and the subpixel SP may emit light at a predetermined brightness according to the voltage stored in the storage capacitor Cst.

[0145] The light emitting device ED may be electrically connected between the second node N2 and a basic voltage node N_EVSS. The basic voltage node (N_EVSS) may be a node to which a basic voltage EVSS is supplied. When the light emitting device ED is driven, an image may be displayed on the display panel 110.

[0146] The first initialization transistor 711 may be electrically connected between the main basic voltage line 750 and the auxiliary driving voltage line 770. The first initialization transistor 711 may be controlled by a first initialization signal Init1. The main basic voltage line 750 may be located in the bezel area BA. The main basic voltage line 750 may be a line for providing a basic voltage EVSS to the subpixel SP.

[0147] The first light emitting transistor 712 may be electrically connected between the main driving voltage line 760 and the auxiliary driving voltage line 770. The first light emitting transistor 712 may be controlled by the first light emitting signal Em1. The main driving voltage line 760 may be disposed in the frame area BA. The main driving voltage line 760 may be a line for providing a driving voltage EVDD to the sub-pixel SP.

[0148] Figure 7 The sub-pixel SP shown can be composed of Figures 8 to 15 In the following, reference will be made to Figures 8 to 15 describe Figure 7 The driving of the sub-pixel SP is shown.

[0149] Figures 8 to 15 The display panel 110 according to various aspects of the present disclosure is shown. Figure 7 Exemplary driving timing of the initialization transistor and the light-emitting transistor in Embodiment Mode 1 is shown.

[0150] The period of driving the sub-pixel SP may include an initialization period and a light emitting period.

[0151] refer to Figure 8 , a period of driving the sub-pixel SP may include a first initialization period T_Init1 and a first light emitting period T_Em1.

[0152] The first initialization period T_Init1 may be a period for preparing to make the sub-pixel SP emit light.

[0153] The first light emitting period T_Em1 may be a period in which the sub-pixel SP emits light.

[0154] The period of driving the subpixel SP may include a first period T1, a second period T2, a third period T3, a fourth period T4, a fifth period T5, and a sixth period T6. The nth period Tn may be a period from the (n-1)th moment to the nth moment. Here, n is a natural number of 1 or more. For example, referring to Figure 8 The second time period T2 may be a time period from the first time t1 to the second time t2. The fifth time period T5 may be a time period from the fourth time t4 to the fifth time t5.

[0155] The first period T1 may be a light emitting period before the first initialization period T_Init1 .

[0156] The second to fifth periods T2 to T5 may be included in the first initialization period T_Init1 .

[0157] The sixth period T6 may be the first light emitting period T_Em1.

[0158] The first light emitting signal EM1 may have a high level during the first period T1 and the sixth period T6. The first light emitting signal EM1 may have a low level during the second period T2 to the fifth period T5.

[0159] The first initialization signal Init1 may have a low level during the first period T1, the second period T2, the fifth period T5, and the sixth period T6. The first initialization signal Init1 may have a high level during the third period T3 and the fourth period T4.

[0160] The first scan signal Scan1 may have a low level during the first period T1, the second period T2, the fourth period T4, the fifth period T5, and the sixth period T6. The first scan signal Scan1 may have a high level during the third period T3.

[0161] During the second period T2 to the fifth period T5 , the data voltage Vdata may be supplied to the data line DL electrically connected to the first subpixel.

[0162] Reference Fig. 9 , the first period T1 may be a light emitting period before the first initialization period T_Init1. During the first period T1, the scanning transistor SCT may be turned off, the initialization transistor 711 may be turned off, and the light emitting transistor 712 may be turned on. Since the light emitting transistor 712 is turned on, the driving voltage EVDD may be provided to the drain node of the driving transistor DRT. Therefore, during the first period T1, the light emitting transistor 712 may be turned on, and the driving voltage EVDD may be provided to the driving transistor DRT.

[0163] Reference Fig.10, the second period T2 may be a period in which the supply of the driving voltage EVDD is interrupted and the storage capacitor Cst charged at a specific voltage level is discharged. During the second period T2, all the scanning transistors SCT, the initialization transistor 711, and the light emitting transistor 712 may be turned off. Since the initialization transistor 711 and the light emitting transistor 712 are turned off during the second period T2, a short circuit caused by the simultaneous supply of the driving voltage EVDD and the base voltage EVSS may be prevented.

[0164] Reference Fig.11 , the third period T3 may be a period in which the basic voltage EVSS is provided to the driving transistor DRT. During the third period T3, the scanning transistor SCT and the initialization transistor 711 may be turned on. During the third period T3, the light emitting transistor 712 may be turned off. During the third period T3, the basic voltage EVSS may be provided to the drain node of the driving transistor DRT, and when the voltage of the drain node is lower than the voltage of the source node, the voltage of the source node may be initialized with the basic voltage EVSS. During the third period T3, the source node of the driving transistor DRT may be initialized to the basic voltage EVSS, and at the same time, the data voltage Vdata may be provided to the gate node of the driving transistor DRT. When the data voltage Vdata is provided to the gate node of the driving transistor DRT, the storage capacitor Cst may be charged with the light emitting voltage.

[0165] Reference Fig.12 , the fourth period T4 may be a period for enabling the storage capacitor Cst to be stably charged at a specific voltage level. During the fourth period T4, the scanning transistor SCT and the light emitting transistor 712 may be turned off. During the fourth period T4, the initialization transistor 711 may be turned on. The scanning transistor SCT may be turned off before the initialization transistor 711 is turned off. If the scanning transistor SCT is turned off after the initialization transistor 711 is turned off, the source node of the driving transistor DRT may be affected by the diode threshold voltage (Diode Vth) and the thin film transistor threshold voltage (TFT Vth). When the scanning transistor SCT is turned off before the initialization transistor 711 is turned off, the voltage of the source node of the driving transistor DRT may be stably maintained.

[0166] Reference Fig.13, the fifth period T5 may be a period during which the supply of the driving voltage EVDD is interrupted and the storage capacitor Cst charged at a specific voltage level is discharged. During the fifth period T5, all of the scan transistors SCT, the initialization transistor 711, and the light emitting transistor 712 may be turned off. Since the initialization transistor 711 and the light emitting transistor 712 are turned off during the fifth period T5, a short circuit caused by the simultaneous supply of the driving voltage EVDD and the base voltage EVSS may be prevented.

[0167] Reference Fig.14 , the sixth period T6 may be a period in which the sub-pixel SP emits light. During the sixth period T6, the scanning transistor SCT may be turned off, the initialization transistor 711 may be turned off, and the light emitting transistor 712 may be turned on. Since the light emitting transistor 712 is turned on, the driving voltage EVDD may be provided to the drain node of the driving transistor DRT. Therefore, during the sixth period T6, the light emitting transistor 712 may be turned on, and the driving voltage EVDD may be provided to the driving transistor DRT.

[0168] As mentioned above, reference has been made Figures 8 to 14 The operation of the subpixels SP included in the first column subpixel group is described. After controlling the operation of the first column subpixel group, the second column subpixel group may be controlled. A portion of the period of operating the first column subpixel group and a portion of the period of operating the second column subpixel group may overlap each other.

[0169] About Fig.15 , the first sub-pixel SP1 may be included in the first column sub-pixel group (eg, Figure 5 The second subpixel SP2 may be a subpixel included in the first column subpixel group (eg, Figure 5 The first subpixel SP1 may be connected to the first gate line, the second subpixel SP2 may be connected to the second gate line, and the third subpixel SP3 may be connected to the third gate line. Fig.15 The first sub-pixel SP1 shown can be Figure 5 The first sub-pixels SPa shown are identical. Fig.15 The second sub-pixel SP2 shown can be Figure 5 The second sub-pixel SPb shown is the same.

[0170] refer to Fig.15 , the driving period of the first column sub-pixel group may include a first initialization period T_Init1 and a first light emission period T_Em1. Fig.15, the driving period of the second column sub-pixel group may include a second initialization period T_Init2 and a second light emitting period T_Em2.

[0171] During the first initialization period T_Init1, the data voltage Vdata may be a first data voltage provided to the first subpixel SP1 included in the first column subpixel group. During the first emission period T_em1, the first subpixel SP1 may emit light having brightness corresponding to the first data voltage. Fig.15 , when the first light emitting period T_Em1 is started, the second initialization period T_Init2 may also be started.

[0172] During the second initialization period T_Init2, the data voltage Vdata may be a second data voltage provided to the second subpixel SP2 included in the second column subpixel group. During the second emission period T_em2, the second subpixel SP2 may emit light having brightness corresponding to the second data voltage. Fig.15 , when the second light emitting period T_Em2 is started, the third initialization period may also be started.

[0173] During the third initialization period, the data voltage Vdata may be a third data voltage provided to the third subpixel SP3 included in the third column subpixel group. During the third light emission period, the third subpixel SP3 may emit light having brightness corresponding to the third data voltage.

[0174] Fig.16 and Fig.17 The configuration of the initialization transistor and the light emitting transistor in Embodiment 2 in the display panel according to aspects of the present disclosure is shown.

[0175] Fig.16 It is shown that the reference voltage Vref or the base voltage EVSS can be provided to the first sub-pixel SP1 by controlling the first initialization signal Init1 and the first light-emitting signal Em1. During the initialization period T_Init, the reference voltage Vref can be provided to the first sub-pixel SP1, and during the light-emitting period T_Em, the base voltage EVSS can be provided to the first sub-pixel SP1. As a result of this operation, the threshold voltage of the driving transistor DRT included in the first sub-pixel SP1 can be stably controlled.

[0176] A plurality of sub-pixels SP may be disposed in the display area AA, and a driving circuit, a voltage line, a signal line, etc. for driving the sub-pixels SP may be disposed in the bezel area BA.

[0177] Fig.16 One sub-pixel SP disposed in the display area AA is shown. Fig.16An initialization transistor, a light emitting transistor, a main reference voltage line 1650, and a main basic voltage line 1660 disposed in the bezel area BA are shown.

[0178] Reference Fig.16 In one or more embodiments, the sub-pixel SP may include a light emitting device ED, a driving transistor DRT, a scanning transistor SCT, a storage capacitor Cst, and the like.

[0179] The driving transistor DRT may be a transistor for driving the light emitting device ED. The driving transistor DRT may be electrically connected between the second node N2 and the third node N3. A gate node of the driving transistor DRT may be electrically connected to or correspond to the first node N1.

[0180] The scan transistor SCT may be electrically connected between the data line DL and the first node N1. A gate node of the scan transistor SCT may be electrically connected to the first gate line GL1. The data voltage Vdata may be provided to the gate node of the driving transistor DRT by the control of the scan transistor SCT.

[0181] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2. The storage capacitor Cst may be charged with a voltage of a certain level, and the subpixel SP may emit light at a predetermined brightness according to the voltage stored in the storage capacitor Cst.

[0182] The light emitting device ED may be electrically connected between the third node N3 and the driving voltage node N_EVDD. The driving voltage node N_EVDD may be a node to which the driving voltage EVDD is supplied. When the light emitting device ED is driven, an image may be displayed on the display panel 110.

[0183] The first initialization transistor 1611 may be electrically connected between the main reference voltage line 1650 and the auxiliary basic voltage line 1670. The first initialization transistor 1611 may be controlled by a first initialization signal Init1. The main reference voltage line 1650 may be located in the bezel area BA. The main reference voltage line 1650 may be a line for providing a reference voltage Vref to the subpixel SP.

[0184] The first light emitting transistor 1612 may be electrically connected between the main basic voltage line 1660 and the auxiliary basic voltage line 1670. The first light emitting transistor 1612 may be controlled by the first light emitting signal Em1. The main basic voltage line 1660 may be located in the bezel area BA. The main basic voltage line 1660 may be a line for providing a basic voltage EVSS to the sub-pixel SP.

[0185] Fig.16 The sub-pixel SP shown can be composed of Figures 18 to 24 The drive timing shown is driven. In the following, the Fig.16 The driving of the sub-pixel SP is shown.

[0186] Figures 18 to 26 The display panel 110 according to various aspects of the present disclosure is shown. Fig.16 Exemplary driving timing of the initialization transistor 1611 and the light-emitting transistor 1612 in Embodiment 2 is shown.

[0187] The period of driving the sub-pixel SP may include an initialization period and a light emitting period.

[0188] refer to Fig.18 , a period of driving the sub-pixel SP may include a first initialization period T_Init1 and a first light emitting period T_Em1.

[0189] The first initialization period T_Init1 may be a period for preparing to make the sub-pixel SP emit light.

[0190] The first light emitting period T_Em1 may be a period in which the sub-pixel SP emits light.

[0191] The period of driving the subpixel SP may include a first period T1, a second period T2, a third period T3, a fourth period T4, a fifth period T5, and a sixth period T6. The nth period Tn may be a period from the (n-1)th moment to the nth moment. Here, n is a natural number of 1 or more. For example, referring to Figure 8 The second time period T2 may be a time period from the first time t1 to the second time t2. The fifth time period T5 may be a time period from the fourth time t4 to the fifth time t5.

[0192] The first period T1 may be a light emitting period before the first initialization period T_Init1 .

[0193] The second to fifth periods T2 to T5 may be included in the first initialization period T_Init1 .

[0194] The sixth period T6 may be the first light emitting period T_Em1.

[0195] The first light emitting signal EM1 may have a high level during the first period T1 and the sixth period T6. The first light emitting signal EM1 may have a low level during the second period T2 to the fifth period T5.

[0196] The first initialization signal Init1 may have a low level during the first period T1, the second period T2, the fifth period T5, and the sixth period T6. The first initialization signal Init1 may have a high level during the third period T3 and the fourth period T4.

[0197] The first scan signal Scan1 may have a low level during the first period T1, the second period T2, the fourth period T4, the fifth period T5, and the sixth period T6. The first scan signal Scan1 may have a high level during the third period T3.

[0198] During the second period T2 to the fifth period T5 , the data voltage Vdata may be supplied to the data line DL electrically connected to the first subpixel.

[0199] Reference Fig.19 , the first period T1 may be a light emitting period before the first initialization period T_Init1. During the first period T1, the scanning transistor SCT may be turned off, the initialization transistor 1611 may be turned off, and the light emitting transistor 1612 may be turned on. Since the light emitting transistor 1612 is turned on, the basic voltage EVSS may be provided to the source node of the driving transistor DRT. Therefore, during the first period T1, the light emitting transistor 1612 may be turned on and the basic voltage EVSS may be provided to the driving transistor DRT.

[0200] refer to Fig. 20 , the second period T2 may be a period in which the supply of the base voltage EVSS is interrupted and the storage capacitor Cst charged at a specific voltage level is discharged. During the second period T2, all of the scan transistors SCT, the initialization transistor 1611, and the light emitting transistor 1612 may be turned off. Since the initialization transistor 1611 and the light emitting transistor 1612 are turned off during the second period T2, a short circuit caused by the simultaneous supply of the base voltage EVSS and the reference voltage Vref may be prevented.

[0201] refer to Fig.21 , the third period T3 may be a period in which the reference voltage Vref is provided to the driving transistor DRT. During the third period T3, the scanning transistor SCT and the initialization transistor 1611 may be turned on. During the third period T3, the light emitting transistor 1612 may be turned off. During the third period T3, the source node of the driving transistor DRT may be provided with the reference voltage Vref, and at the same time, the data voltage Vdata may be provided to the gate node of the driving transistor DRT. When the data voltage Vdata is provided to the gate node of the driving transistor DRT, the storage capacitor Cst may be charged with the light emitting voltage. A voltage equal to or corresponding to the voltage difference between the data voltage Vdata and the reference voltage Vref may be stored in the storage capacitor Cst.

[0202] Reference Fig. 22, the fourth period T4 may be a period for enabling the storage capacitor Cst to be stably charged at a specific voltage level. During the fourth period T4, the scanning transistor SCT and the light emitting transistor 1612 may be turned off. During the fourth period T4, the initialization transistor 1611 may be turned on. The scanning transistor SCT may be turned off before the initialization transistor 1611 is turned off. In the case where the data voltage Vdata is supplied to one end of the storage capacitor Cst and the reference voltage Vref is supplied to the other end of the storage capacitor Cst, the supply of the data voltage Vdata may be interrupted first.

[0203] refer to Fig.23 , the fifth period T5 may be a period in which the supply of the reference voltage Vref is interrupted and the storage capacitor Cst charged at a specific voltage level is discharged. During the fifth period T5, all of the scan transistors SCT, the initialization transistor 1611, and the light emitting transistor 1612 may be turned off. Since the initialization transistor 1611 and the light emitting transistor 1612 are turned off during the fifth period T5, a short circuit caused by the simultaneous supply of the base voltage EVSS and the reference voltage Vref may be prevented.

[0204] Reference Fig.24 , the sixth period T6 may be a period in which the sub-pixel SP emits light. During the sixth period T6, the scanning transistor SCT may be turned off, the initialization transistor 1611 may be turned off, and the light emitting transistor 1612 may be turned on. Since the light emitting transistor 1612 is turned on, the basic voltage EVSS may be provided to the source node of the driving transistor DRT. Therefore, during the sixth period T6, the light emitting transistor 1612 may be turned on and the basic voltage EVSS may be provided to the driving transistor DRT.

[0205] and Fig.16 The configuration is different, refer to Fig.17 , the gate node of the scan transistor SCT and the gate node of the first initialization transistor 1611 can be simultaneously controlled by one gate line. In this implementation, since the number of lines is reduced, the integration of circuits provided in the display panel 110 can be improved.

[0206] For example, based on Fig.25 The timing diagram shown is used to drive Fig.17 The sub-pixel SP shown. Fig.18 and Fig.25 , Fig.25 2 shows that the first scan signal Scan1 is used, but the first initialization signal Init1 is not used. Fig.17As shown, the gate node of the scan transistor SCT and the gate node of the first initialization transistor 1611 can be electrically connected to the first gate line GL1. In this example, the scan transistor SCT and the first initialization transistor 1611 can be simultaneously controlled by the first scan signal Scan1 provided through the first gate line GL1. The above features also apply to Figure 7 The gate node of the initialization transistor 711 and the gate node of the scanning transistor SCT are shown. That is, Figure 7 The gate node of the initialization transistor 711 and the gate node of the scan transistor SCT as shown may be electrically connected to the same gate line.

[0207] As mentioned above, reference has been made Figures 19 to 24 Describes the sub-pixel group included in the first column (eg, Figure 5 After controlling the operation of the first column subpixel group, the second column subpixel group (eg, Figure 5 A portion of a period during which the first column of subpixel groups are operated and a portion of a period during which the second column of subpixel groups are operated may overlap with each other.

[0208] About Fig.26 The discussion of the timing diagram of the first subpixel SP1 may be a subpixel included in the first column subpixel group, the second subpixel SP2 may be a subpixel included in the second column subpixel group, and the third subpixel SP3 may be a subpixel included in the third column subpixel group. The first subpixel SP1 may be connected to the first gate line, the second subpixel SP2 may be connected to the second gate line, and the third subpixel SP3 may be connected to the third gate line.

[0209] refer to Fig.26 , the driving period of the first column sub-pixel group may include a first initialization period T_Init1 and a first light emission period T_Em1. Fig.26 , the driving period of the second column sub-pixel group may include a second initialization period T_Init2 and a second light emitting period T_Em2.

[0210] During the first initialization period T_Init1, the data voltage Vdata may be a first data voltage supplied to the first subpixel SP1 included in the first column subpixel group. During the first emission period T_em1, the first subpixel SP1 may emit light having brightness corresponding to the first data voltage. Fig.26 , when the first light emitting period T_Em1 is started, the second initialization period T_Init2 may also be started.

[0211] During the second initialization period T_Init2, the data voltage Vdata may be a second data voltage provided to the second subpixel SP2 included in the second column subpixel group. During the second emission period T_em2, the second subpixel SP2 may emit light having brightness corresponding to the second data voltage. Fig.26 , when the second light emitting period T_Em2 is started, the third initialization period may also be started.

[0212] During the third initialization period, the data voltage Vdata may be a third data voltage provided to the third subpixel SP3 included in the third column subpixel group. During the third light emission period, the third subpixel SP3 may emit light having brightness corresponding to the third data voltage.

[0213] Fig. 27 is an example flowchart of a driving method of the display device 100 according to aspects of the present disclosure.

[0214] The driving method of the display device 100 may include an initialization step S2710 and a light emitting step S2720.

[0215] The initialization step S2710 may be a stage of preparing to make the sub-pixel SP emit light. During the initialization step S2710, a first voltage may be supplied to the driving transistor DRT included in the sub-pixel SP.

[0216] The light emitting step S2720 may be a stage in which the sub-pixel SP emits light. During the light emitting step S2720 after the initialization step S2710, a second voltage may be supplied to the driving transistor DRT included in the sub-pixel SP.

[0217] During the initialization step S2710, the driving transistor DRT may be supplied with a first voltage, and during the light emitting step S2720, the driving transistor DRT may be supplied with a second voltage. Therefore, the threshold voltage of the driving transistor DRT may be stably controlled, thereby improving the quality of the image displayed on the display panel 110.

[0218] The above-mentioned embodiment will be briefly described below.

[0219] According to the aspects described herein, a display device can be provided, comprising: a display area in which a plurality of sub-pixels including a first sub-pixel are arranged; a border area different from the display area; a plurality of voltage lines arranged in the border area and including at least one driving voltage line and at least one basic voltage line; and a first switch and a second switch arranged in the border area, the first switch being electrically connected between the basic voltage line and the first sub-pixel, and the second switch being electrically connected between a first voltage line among the plurality of voltage lines and the first sub-pixel.

[0220] The first subpixel may include a driving transistor for driving the light emitting device, a scanning transistor electrically connected between a first node that is or corresponds to a gate node of the driving transistor and a data line, and a storage capacitor electrically connected between a second node of the driving transistor and the first node. The first switch and the second switch may be electrically connected to the driving transistor.

[0221] The first voltage line may be a driving voltage line.

[0222] The first switch and the second switch may be electrically connected to a drain node of the driving transistor.

[0223] The light emitting device may be electrically connected between the second node and the base voltage node.

[0224] The first voltage line may be a reference voltage line to which a reference voltage is supplied.

[0225] The first switch and the second switch may be electrically connected to a source node of the driving transistor.

[0226] The light emitting device may be electrically connected between the third node of the driving transistor and the driving voltage node.

[0227] The gate line electrically connected to the gate node of the scan transistor may be electrically connected to the gate node of the initialization transistor serving as the second switch.

[0228] The driving period of the sub-pixel may include a light emitting period in which the light emitting device emits light and an initialization period in which the storage capacitor is charged with the data voltage. In the initialization period, the source node of the driving transistor may be initialized to a base voltage.

[0229] When the first switch is turned on, the second switch may be turned off, and when the second switch is turned on, the first switch may be turned off.

[0230] During a light emission period in which the first subpixel emits light, the light emission transistor as the second switch may be turned on, and during an initialization period before the light emission period, the initialization transistor as the first switch may be turned on.

[0231] During the initialization period, a base voltage may be supplied to the first sub-pixel, and during the light emission period, a driving voltage may be supplied to the first sub-pixel.

[0232] During a light emission period in which the first subpixel emits light, the light emission transistor as the first switch may be turned on, and during an initialization period before the light emission period, the initialization transistor as the second switch may be turned on.

[0233] During the initialization period, the reference voltage may be supplied to the first sub-pixel through the first voltage line, and during the light emitting period, the base voltage may be supplied to the first sub-pixel.

[0234] The first switch and the second switch may be disposed in a first bezel region, and the third switch and the fourth switch different from the first switch and the second switch may be disposed in a second bezel region different from the first bezel region.

[0235] A plurality of sub-pixels may be disposed on a silicon substrate.

[0236] According to the aspects described herein, a driving method for a display device can be provided, which includes an initialization step and a light-emitting step. In the initialization step, a first switch arranged in a border area is turned on, and a first voltage is supplied to a first sub-pixel arranged in a display area. In the light-emitting step, a second switch arranged in the border area is turned on, a second voltage is supplied to the first sub-pixel, and the first sub-pixel emits light.

[0237] In the initialization step, the base voltage may be supplied through the first switch, and in the light emitting step, the driving voltage may be supplied through the second switch.

[0238] In the initialization step, the reference voltage may be provided through the first switch, and in the light emitting step, the base voltage may be provided through the second switch.

[0239] The above description is given to enable those skilled in the art to make, use and practice the technical features of the present disclosure, and is provided as an example in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and accompanying drawings provide examples of the technical features of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.

[0240] CROSS-REFERENCE TO RELATED APPLICATIONS

[0241] This application claims the benefit of Korean Patent Application No. 10-2023-0098307 filed on July 27, 2023 in the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a display area, in which a plurality of sub-pixels including a first sub-pixel are arranged; a frame area different from the display area; a plurality of voltage lines, the plurality of voltage lines being disposed in the frame region and comprising a driving voltage line and a basic voltage line; and A first switch and a second switch are arranged in the frame area, in, The first switch is electrically connected between the base voltage line and the first sub-pixel; and The second switch is electrically connected between a first voltage line among the plurality of voltage lines and the first sub-pixel.

2. The display device according to claim 1, wherein: The first sub-pixel comprises: A driving transistor, wherein the driving transistor is used to drive the light emitting device; a scanning transistor electrically connected between a first node and a data line, wherein the first node is or corresponds to a gate node of the driving transistor; and a storage capacitor electrically connected between the first node and a second node of the driving transistor, and The first switch and the second switch are electrically connected to the driving transistor.

3. The display device according to claim 2, wherein: The first voltage line is the driving voltage line.

4. The display device according to claim 3, wherein: The first switch and the second switch are electrically connected to a drain node of the drive transistor.

5. The display device according to claim 4, wherein: The light emitting device is electrically connected between the second node and a base voltage node.

6. The display device according to claim 2, wherein: The first voltage line is a reference voltage line configured to be supplied with a reference voltage.

7. The display device according to claim 6, wherein: The first switch and the second switch are electrically connected to a source node of the drive transistor.

8. The display device according to claim 7, wherein: The light emitting device is electrically connected between a driving voltage node and a third node of the driving transistor.

9. The display device according to claim 2, wherein: A gate line electrically connected to a gate node of the scan transistor is electrically connected to a gate node of an initialization transistor serving as the second switch.

10. The display device according to claim 2, wherein: The driving period of the first subpixel includes a light emitting period and an initialization period, during which the light emitting device is configured to emit light, and during which the storage capacitor is configured to be charged with a data voltage, and During the initialization period, the source node of the driving transistor is initialized to a basic voltage.

11. The display device according to claim 1, wherein: When the first switch is turned on, the second switch is turned off, and when the second switch is turned on, the first switch is turned off.

12. The display device according to claim 11, wherein: During a light emission period in which the first subpixel is configured to emit light, the light emission transistor as the second switch is configured to be turned on, and during an initialization period before the light emission period, the initialization transistor as the first switch is configured to be turned on.

13. The display device according to claim 12, wherein: During the initialization period, a base voltage is supplied to the first sub-pixel, and during the light emitting period, a driving voltage is supplied to the first sub-pixel.

14. The display device according to claim 11, wherein: During a light emission period in which the first subpixel is configured to emit light, the light emission transistor as the first switch is configured to be turned on, and during an initialization period before the light emission period, the initialization transistor as the second switch is configured to be turned on.

15. The display device according to claim 14, wherein: During the initialization period, a reference voltage is supplied to the first sub-pixel through the first voltage line, and during the light emitting period, a base voltage is supplied to the first sub-pixel.

16. The display device according to claim 1, wherein: The first switch and the second switch are disposed in a first bezel region, and a third switch and a fourth switch different from the first switch and the second switch are disposed in a second bezel region different from the first bezel region.

17. The display device according to claim 1, wherein: The plurality of sub-pixels are disposed on a silicon substrate.

18. A method for driving a display device, the method comprising the following steps: Setting an initialization period, wherein during the initialization period, a first switch provided in the frame area is turned on and a first voltage is provided to a first sub-pixel provided in the display area; and A light emission period is set, wherein during the light emission period, a second switch provided in the frame area is turned on, a second voltage is supplied to the first sub-pixel, and the first sub-pixel emits light.

19. The driving method according to claim 18, wherein: During the initialization period, a base voltage is supplied through the first switch, and during the light emitting period, a driving voltage is supplied through the second switch.

20. The driving method according to claim 18, wherein: During the initialization period, a reference voltage is supplied through the first switch, and during the light emitting period, a base voltage is supplied through the second switch.

21. A display device, comprising: Display area; a frame area different from the display area; a plurality of sub-pixels, the plurality of sub-pixels being disposed in the display area and including a first sub-pixel; a plurality of voltage lines, the plurality of voltage lines being disposed in the frame region and comprising a driving voltage line and a basic voltage line; and A first switch and a second switch are arranged in the frame area, in, During a first period, the first switch is configured to provide a first voltage to the first subpixel using a first voltage line among the plurality of voltage lines; and During a second period, the second switch is configured to provide a second voltage to the first subpixel using a second voltage line among the plurality of voltage lines.

22. The display device according to claim 21, in, The first period and the second period are respectively an initialization period and a light emitting period; wherein the first switch and the second switch are connected to each other; and in, The first voltage is a base voltage, and the second voltage is a driving voltage; or The first voltage is a reference voltage, and the second voltage is a base voltage.

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