Repair sharing circuit, repair sharing method and memory

Abstract

The invention provides a repair sharing circuit and method and a memory, the circuit comprises a mode selection circuit and a repair control circuit, the repair control circuit comprises N control sub-circuits, and M control sub-circuits in the N control sub-circuits are used as a sharing circuit; the mode selection circuit performs latching processing according to a preset clock signal and an enable signal to generate a starting signal; the repair control circuit performs logic processing according to the starting signal and N state indication signals, N repair indication signals are output through N control sub-circuits, and the state indication signals are used for indicating whether repair resources corresponding to the control sub-circuits corresponding to the state indication signals are available or not; and when the starting signal is in the enabled state and a repair indication signal output by a first control sub-circuit in the shared circuit is in the enabled state, executing a first repair operation according to a repair resource corresponding to the first control sub-circuit. According to the invention, multiple repair operations can share repair resources, so that the circuit area is saved, and the cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a repair sharing circuit, a repair sharing method and a memory. Background Art

[0002] During the normal use of the memory, some storage rows and / or columns may fail. In order to extend the life of the memory when the storage rows and / or columns fail, the post-package repair (Post Package Repair, PPR) method is used to repair the storage rows and / or columns of the memory. Specifically, redundant storage rows and / or columns can be used to replace the failed storage rows and / or columns. The PPR method includes soft package repair (Soft PPR, SPPR) and hard package repair (Hard PPR, HPPR), wherein SPPR is a temporary repair and HPPR is a permanent repair. The repair performed after the memory is subjected to a built-in self-test (Memory Built-In Self-Test, MBIST) is called MBIST Post Package Repair (MPPR). Summary of the invention

[0003] Embodiments of the present disclosure provide a repair sharing circuit, a repair sharing method, and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a repair sharing circuit, including a mode selection circuit and a repair control circuit, wherein the repair control circuit includes N control subcircuits, M of the N control subcircuits are used as shared circuits, each of the control subcircuits corresponds to a repair resource, N and M are both integers greater than 0, and M is less than N, wherein:

[0005] The mode selection circuit is used to receive a preset clock signal and an enable signal, perform latch processing according to the preset clock signal and the enable signal, and generate a start signal;

[0006] The repair control circuit is used to receive the start signal and N status indication signals, perform logic processing according to the start signal and the N status indication signals, and output N repair indication signals through the N control subcircuits respectively, each of the status indication signals is used to indicate whether the repair resource corresponding to the corresponding control subcircuit is available;

[0007] Among them, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits.

[0008] In some embodiments, when the start signal is in a non-enabled state and the repair indication signal output by the second control sub-circuit in the repair control circuit is in an enabled state, a second repair operation is performed according to the repair resources corresponding to the second control sub-circuit, and the second control sub-circuit is any one of the N control sub-circuits.

[0009] In some embodiments, the remaining (NM) control subcircuits of the N control subcircuits are used as non-shared circuits, and the mode selection circuit includes a latch, wherein:

[0010] The first input end of the latch is used to receive the enable signal, the second input end of the latch is used to receive the preset clock signal, the output end of the latch is used to output the start signal, and the output end of the latch is respectively connected to each of the control sub-circuits in the non-shared circuit.

[0011] In some embodiments, the latch further includes a reset terminal, and the reset terminal is used to receive a reset signal, wherein:

[0012] The latch is used to control the start signal to be reset to a non-enabled state when the reset signal is in an enabled state.

[0013] In some embodiments, the latch includes a first NAND gate and a second NAND gate, wherein:

[0014] The first input terminal of the first NAND gate is used as the first input terminal of the latch to receive the enable signal;

[0015] The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate;

[0016] The output end of the first NAND gate serves as the output end of the latch, and is used to output the start signal, and the output end of the first NAND gate is connected to the first input end of the second NAND gate;

[0017] The second input end of the second NAND gate is used as the second input end of the latch to receive the preset clock signal;

[0018] The third input terminal of the second NAND gate serves as a reset terminal of the latch, and is used to receive the reset signal.

[0019] In some embodiments, the i-th control subcircuit is used to receive the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal; perform logic processing according to the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal to generate the i-th repair indication signal; wherein, i is an integer greater than 0 and less than or equal to N, and when i is greater than 0 and less than N, the output end of the i-th control subcircuit is connected to the i+1-th control subcircuit; if the i-th control subcircuit belongs to the shared circuit, the i-th first control signal is a preset signal, and if the i-th control subcircuit belongs to the non-shared circuit, the i-th first control signal is the start signal; when i is equal to 1, the first second control signal is a preset signal, and when i is greater than 1 and less than or equal to N, the i-th second control signal is the i-1-th repair indication signal;

[0020] Among them, when the i-th first control signal is in an enabled state and the i-th control sub-circuit belongs to the non-shared circuit, the i-th repair indication signal is in a disabled state; when the i-th first control signal is in an enabled state and the i-th control sub-circuit belongs to the shared circuit, or when the i-th first control signal is in a disabled state, if the i-th state indication signal is in an enabled state, the i-th second control signal is in a disabled state, and the repair command signal is in an enabled state, the i-th repair indication signal is in an enabled state.

[0021] In some embodiments, the i-th control subcircuit comprises a sampling circuit, a first logic subcircuit, a second logic subcircuit and a third logic subcircuit, wherein:

[0022] The sampling circuit is used to receive the i-th state indication signal and the preset clock signal, and perform sampling processing on the i-th state indication signal according to the preset clock signal to generate an i-th sampling indication signal; the state of the i-th sampling indication signal is opposite to the state of the i-th state indication signal;

[0023] The first logic subcircuit is configured to receive the i-th sampling indication signal and the i-th first control signal; perform logic processing according to the i-th sampling indication signal and the i-th first control signal to generate an i-th first intermediate signal; when the i-th first control signal is in an enabled state, the i-th first intermediate signal is in an enabled state, and when the i-th first control signal is in a disabled state, the state of the i-th first intermediate signal is the same as the state of the i-th sampling indication signal;

[0024] the second logic sub-circuit is configured to receive an i-th first intermediate signal and an i-th second control signal; perform logic processing according to the i-th first intermediate signal and the i-th second control signal to generate an i-th second intermediate signal; when the i-th first intermediate signal is in an enabled state, the i-th second intermediate signal is in a disabled state, and when the i-th first intermediate signal is in a disabled state, a state of the i-th second intermediate signal is opposite to a state of the i-th second control signal;

[0025] The third logic sub-circuit is used to receive the i-th second intermediate signal and the repair command signal; perform logic processing according to the i-th second intermediate signal and the repair command signal to generate the i-th repair indication signal; wherein, when the i-th second intermediate signal and the repair command signal are both in an enabled state, the i-th repair indication signal is in an enabled state, otherwise, the i-th repair indication signal is in a disabled state.

[0026] In some embodiments, in the i-th control subcircuit, the sampling circuit comprises a trigger, wherein:

[0027] The input end of the trigger is used to receive the i-th state indication signal;

[0028] The clock terminal of the trigger is used to receive the preset clock signal;

[0029] The output end of the trigger is used to output the i-th sampling indication signal.

[0030] In some embodiments, in the i-th control subcircuit, the first logic subcircuit includes an OR gate, the second logic subcircuit includes a NOR gate, and the third logic subcircuit includes an AND gate, wherein:

[0031] The first input end of the OR gate is connected to the output end of the sampling circuit, and is used to receive the i-th sampling indication signal; the second input end of the OR gate is used to receive the i-th first control signal; the output end of the OR gate is connected to the second input end of the NOR gate, and is used to output the i-th first intermediate signal;

[0032] The first input end of the NOR gate is used to receive the i-th second control signal; the second input end of the NOR gate is used to receive the i-th first intermediate signal; the output end of the NOR gate is connected to the second input end of the AND gate, and is used to output the i-th second intermediate signal;

[0033] The first input end of the AND gate is used to receive the repair command signal; the second input end of the AND gate is used to receive the i-th second intermediate signal; and the output end of the AND gate is used to output the i-th repair indication signal.

[0034] In some embodiments, N=4, M=1, the N control subcircuits include a first subcircuit, a second subcircuit, a third subcircuit, and a fourth subcircuit, and the first subcircuit serves as the shared circuit, and the second subcircuit, the third subcircuit, and the fourth subcircuit serve as the non-shared circuit; wherein:

[0035] The output end of the mode selection circuit is connected to the second sub-circuit, the third sub-circuit and the fourth sub-circuit respectively, and is used to send the start signal to the second sub-circuit, the third sub-circuit and the fourth sub-circuit.

[0036] In some embodiments, the repair sharing circuit further comprises:

[0037] A register circuit, used for setting the N state indication signals, and sending the N state indication signals to the N control sub-circuits respectively;

[0038] When the i-th state indication signal is in an enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit is available, where i is an integer greater than 0 and less than or equal to N.

[0039] In some embodiments, the first repair operation includes a test post-packaging repair (MPPR), and the second repair operation includes a hard post-packaging repair (HPPR).

[0040] In some embodiments, the preset clock signal is generated according to the repair command signal and the initial clock signal.

[0041] In a second aspect, an embodiment of the present disclosure provides a repair sharing method, which is applied to the repair sharing circuit as described in any one of the first aspects, and the method includes:

[0042] Receiving a preset clock signal and an enable signal through the mode selection circuit, performing latch processing according to the preset clock signal and the enable signal, and generating a start signal;

[0043] The repair control circuit receives the start signal and N status indication signals, performs logic processing according to the start signal and the N status indication signals, and outputs N repair indication signals respectively through the N control subcircuits, each of the status indication signals being used to indicate whether the repair resource corresponding to the corresponding control subcircuit is available;

[0044] Among them, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits.

[0045] In a third aspect, an embodiment of the present disclosure provides a memory, comprising a repair sharing circuit as described in any one of the first aspects.

[0046] The embodiments of the present disclosure provide a repair sharing circuit, a repair sharing method and a memory, wherein the repair sharing circuit includes a mode selection circuit and a repair control circuit, wherein the repair control circuit includes N control sub-circuits, wherein M of the N control sub-circuits are used as shared circuits, each control sub-circuit corresponds to a repair resource, N and M are both integers greater than 0, and M is less than N, wherein: the mode selection circuit is used to receive a preset clock signal and an enable signal, perform latch processing according to the preset clock signal and the enable signal, and generate a start signal; the repair control circuit is used to receive the start signal and N state indication signals, perform logic processing according to the start signal and the N state indication signals, and output N repair indication signals respectively through the N control sub-circuits, wherein each state indication signal is used to indicate whether the repair resource corresponding to the control sub-circuit corresponding to the control sub-circuit is available; wherein, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resource corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits. Thus, in the disclosed embodiment, the mode selection circuit latches the enable signal with the preset clock signal, obtains the start signal and sends it to the repair control circuit; if the start signal is in the enabled state, it indicates that the first repair operation needs to be controlled to be executed, thereby in combination with the status indication signal, the first control subcircuit in the shared circuit will output the repair indication signal in the enabled state to execute the first repair operation with the corresponding repair resources; if the start signal is in the disabled state, it indicates that the second repair operation needs to be controlled to be executed, thereby in combination with the status indication signal, the second control subcircuit in the repair control circuit will output the repair indication signal in the enabled state to execute the second repair operation with the corresponding repair resources; thereby, in the case of limited resources, the control of the enable signal allows the first repair operation and the second repair operation to share the repair resources, thereby facilitating the integration of the memory and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of the structure of a HPPR circuit provided by an embodiment of the present disclosure;

[0048] Figure 2A schematic diagram of a structure of a repair sharing circuit provided in an embodiment of the present disclosure Figure 1 ;

[0049] Figure 3 A schematic diagram of a structure of a repair sharing circuit provided in an embodiment of the present disclosure Figure 2 ;

[0050] Figure 4 A detailed structural diagram of a repair sharing circuit provided in an embodiment of the present disclosure;

[0051] Figure 5 A detailed structural diagram of a control subcircuit provided in an embodiment of the present disclosure;

[0052] Figure 6 A signal timing diagram provided for an embodiment of the present disclosure;

[0053] Figure 7 A flowchart of a repair sharing method provided by an embodiment of the present disclosure;

[0054] Figure 8 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0057] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0058] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0059] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0060] Post Package Repair (PPR)

[0061] Soft Post Package Repair (SPPR);

[0062] Hard Post Package Repair (HPPR);

[0063] Memory Built-In Self-Test (MBIST);

[0064] MBIST Post Package Repair (MPPR);

[0065] Dynamic Random Access Memory (DRAM);

[0066] D flip-flop (DFF);

[0067] Standard (SPEC);

[0068] Activation (ACT);

[0069] Row Address (RA);

[0070] Double Data Rate (DDR);

[0071] Mode Register (MR);

[0072] Bank (BK);

[0073] Bank Group (BG);

[0074] Most Significant Bit (MSB);

[0075] Write w / Auto Pre-charge (WRA);

[0076] WRA command with a burst length of 16 bits (Burst Length 16WRA, BL16WRA);

[0077] Data (DQ);

[0078] Row Address Select (RAS);

[0079] Column Address Select (CAS);

[0080] tRCD (RAS to CAS delay time).

[0081] Figure 1 A schematic diagram of the structure of a HPPR circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the HPPR circuit 10 includes four PPR sub-circuits: PPR Info 0, PPR Info 1, PPR Info 2 and PPR Info 3, the output end of PPR Info 0 is connected to an input end of PPR Info 1, the output end of PPR Info 1 is connected to an input end of PPR Info 2, and the output end of PPR Info 2 is connected to an input end of PPR Info 3. The specific composition of each PPR Info is as follows Figure 1 As shown in the dashed box on the left.

[0082] like Figure 1 As shown, each PPR Info includes a trigger DFF, a NOR gate NOR, and an AND gate AND. The input terminal D of the DFF receives a PPR_unused signal indicating whether the PPR resource is available, the clock terminal CK of the DFF receives a clock signal LatClk, the DFF can sample and latch the PPR_unused signal according to the clock signal LatClk, output a PPR_cur_ok_n signal at its inverting output terminal Qn, and send the PPR_cur_ok_n signal to the NOR gate NOR; the NOR gate NOR also receives a PPR_pre_ok signal, the output terminal of the NOR gate NOR is connected to the AND gate AND, and the NOR operation result of the PPR_pre_ok signal and the PPR_cur_ok_n signal is sent to the AND gate AND, the AND gate AND also receives a PPR_cmd signal and outputs a PPR_ok signal.

[0083] For PPR Info, the PPR_unused signal is used to indicate whether the PPR resources corresponding to the PPR Info are available, wherein the PPR resources are circuits for performing PPR operations, etc., and the PPR_unused signal can be provided or generated by a mode register; if the PPR_unused signal is logic 1 (high level), it means that the PPR resources corresponding to the PPR Info are available, and if the PPR_unused signal is logic 0 (low level), it means that the PPR resources corresponding to the PPR Info are unavailable; the clock signal LatLck can be generated according to the PPR_cmd signal, wherein when the PPR_cmd signal is 1, the HPPR circuit 10 enters a repaired working state, a pulse is generated in the clock signal LatClk, and the trigger DFF samples and latches the PPR_unused signal according to the rising edge of the clock signal LatClk. Since the PPR_cur_ok_n signal is the output signal of the inverting output terminal Qn of the trigger DFF, the level state of the PPR_cur_ok_n signal output after sampling is opposite to the level state of the PPR_unused signal.

[0084] The PPR_ok signal is used to indicate whether the corresponding PPR resources are used to perform the HPPR operation. If the PPR_ok signal is logic 1, it indicates that the corresponding PPR resources are used to perform the HPPR operation. If the PPR_ok signal is logic 0, it indicates that the corresponding PPR resources are not used to perform the HPPR operation. The PPR_pre_ok signal is the PPR_ok signal output by the previous PPR Info. For PPR Info 0, there is no previous PPR Info, and the PPR_pre_ok0 signal it receives is the GND signal (logic 0), that is, the ground connection; in PPR Info1 / 2 / 3, the PPR_pre_ok1 / 2 / 3 signal is the PPR_ok0 / 1 / 2 signal output by the previous PPR Info.

[0085] Thus, for the HPPR circuit 10, it is determined whether the PPR resources corresponding to each PPRInfo are available in order from PPR Info 0 to PPR Info 4. In short, for HPPR, four HPPR resources can be allocated to each half bank (the HPPR resources corresponding to PPR Info 0 are HPPR 0, the HPPR resources corresponding to PPR Info 1 are HPPR 1, the HPPR resources corresponding to PPR Info 2 are HPPR 2, and the HPPR resources corresponding to PPR Info 3 are HPPR 3). Figure 1When repairing, each HPPR resource has the following priority order: HPPR0>HPPR1>HPPR2>HPPR3, which means: first check whether HPPR0 is available? If so, use HPPR0 to repair; otherwise, check whether HPPR1 is available? If so, use HPPR1 to repair...

[0086] MPPR can be used after MBIST to repair faults found during the self-test phase. For HPPR and MPPR, the HPPR / MPPR resources and control can be completely separated to achieve these two functions. However, this will inevitably cause more circuit consumption and control troubles, resulting in an increase in chip area, which is not conducive to chip integration and has high costs.

[0087] Based on this, the embodiment of the present disclosure provides a repair sharing circuit for realizing that when resources are limited, the HPPR and the MPPR can share repair resources by controlling an enable signal, thereby facilitating the integration of the memory and saving costs.

[0088] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0089] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a repair sharing circuit provided by an embodiment of the present disclosure. Figure 2 As shown, the repair sharing circuit 20 includes: a mode selection circuit 21 and a repair control circuit 22, the repair control circuit 22 includes N control sub-circuits 23, M of the N control sub-circuits 23 are used as a shared circuit 24, each control sub-circuit 23 corresponds to a repair resource, N and M are both integers greater than 0, and M is less than N, wherein:

[0090] The mode selection circuit 21 is used to receive a preset clock signal and an enable signal, perform latch processing according to the preset clock signal and the enable signal, and generate a start signal;

[0091] The repair control circuit 22 is used to receive the start signal and N state indication signals, perform logic processing according to the start signal and the N state indication signals, and output N repair indication signals through the N control subcircuits 23, each state indication signal is used to indicate whether the repair resource corresponding to the corresponding control subcircuit 23 is available;

[0092] Wherein, when the start signal is in an enabled state and the repair indication signal output by the first control subcircuit in the shared circuit 24 is in an enabled state, a first repair operation is performed according to the repair resource corresponding to the first control subcircuit, and the first control subcircuit is any one of the M control subcircuits 23;

[0093] When the start signal is in a disabled state and the repair indication signal output by the second control subcircuit in the repair control circuit 22 is in an enabled state, a second repair operation is performed according to the repair resources corresponding to the second control subcircuit, and the second control subcircuit is any one of the N control subcircuits 23.

[0094] It should be noted that if Figure 2 As shown, the embodiment of the present disclosure provides a repair sharing circuit 20, based on which both the first repair operation and the second repair operation can be implemented. In this embodiment, the mode when the first repair operation is performed can be recorded as the first repair mode, and the mode when the second repair operation is performed can be recorded as the second repair mode. Taking the first repair operation as MPPR and the second repair operation as HPPR as an example, the present scheme is described in detail. The first repair mode is the MPPR mode, and the second repair mode is the HPPR mode, but it can also be the opposite, or other repair operations, which are not specifically limited. In this way, the subsequent repair resources (PPR resources) involved can all be HPPR resources.

[0095] Among them, regarding HPPR, the standard stipulates: Using HPPR, DDR5 can correct at least one row address for each BG. The HPPR resource designation (MR54, 55, 56, 57) will indicate the resource availability of the HPPR and can be read / checked before implementing the repair. It should be noted that the HPPR repair is permanent, and once the fuse is programmed, it cannot be switched back to the unblown state. The controller should prevent accidental entry into the HPPR mode to perform repairs (ie, during command / address training). Entering HPPR is enabled through the register, and the ACT command is used to transmit the BK address and row address of the row to be replaced in the DRAM. For non-binary density, ACT commands with invalid row addresses (both MSB and MSB-1 address bits are "high") are not allowed because it may consume PPR resources. After the tRCD time, the BL16WRA command is used to select a single DRAM through the DQ bit and transmit the repair address to the DRAM.

[0096] Regarding MPPR, the standard states: MBIST-PPR (MPPR) can be used after MBIST to repair faults found during the self-test phase. MPPR can be performed only after reading MR22 MBIST / MPPR completion, and MR22 MBIST / MPPR completion must be read after MPPR completion to determine if additional MPPR or MBIST is required. If it fails, it is retained after reading MR22 completion.

[0097] It should also be noted that, in this embodiment, M control sub-circuits 23 out of N control sub-circuits 23 form a shared circuit 24, and the remaining NM control sub-circuits 23 form a non-shared circuit 25. Figure 2 In the embodiment, in the order of numbering, it is taken as an example that the 1st control subcircuit 23 (control subcircuit 0) to the Mth control subcircuit 23 (control subcircuit M-1) form a shared circuit 24, and the M+1th control subcircuit 23 (control subcircuit M) to the Nth control subcircuit 23 (control subcircuit N-1) form a non-shared circuit 25; in other embodiments, it can also be other division methods, for example: the 1st control subcircuit 23 to the NMth control subcircuit 23 form a non-shared circuit 25, and the N-M+1th control subcircuit 23 to the Nth control subcircuit 23 form a shared circuit 24; or it can also be that M control subcircuits 23 are selected from the N control subcircuits 23 according to a certain rule or randomly to form a shared circuit 24, and the remaining NM control subcircuits 23 form a non-shared circuit 25, and there is no specific limitation on this.

[0098] like Figure 2 As shown, the mode selection circuit 21 controls whether to perform the first repair operation or the second repair operation according to the enable signal and the preset clock signal. If the enable signal is in the enabled state, it indicates entering the first repair mode and needs to perform the first repair operation. If the enable signal is in the disabled state, it indicates entering the second repair mode and needs to perform the second repair operation. The preset clock signal is used to control whether to sample the enable signal. Only when the state of the enable signal is sampled and latched, its control is meaningful.

[0099] The mode selection circuit 21 is a circuit with sampling and latching functions, so that the mode selection circuit 21 can sample and latch the state of the enable signal according to the preset clock signal, obtain the start signal and then transmit it to the repair control circuit 22 to perform the corresponding repair operation.

[0100] Each control subcircuit 23 receives a corresponding status indication signal, which is used to indicate whether the repair resource corresponding to the corresponding control subcircuit 23 is available; if the status indication signal is in an enabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 is available, so that the repair operation can be performed using the repair resource; if the status indication signal is in a disabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 is unavailable, so that the repair operation cannot be performed using the repair resource.

[0101] The output end of the mode selection circuit 21 is connected to each control subcircuit 23 in the non-shared circuit 25. That is, in the repair control circuit 22, the start signal is sent to the NM control subcircuits 23 in the non-shared circuit 25 respectively. If the enable signal is in the enabled state, the start signal obtained by sampling and latching is in the enabled state. At this time, the start signal "turns off" the NM control subcircuits 23 in the non-shared circuit 25, so that in the non-shared circuit 25, no matter whether the state indication signal is in the enabled state or the disabled state, the repair indication signal output by the control subcircuit 23 is in the disabled state, so that the repair operation will not be performed using these control subcircuits 23 in the non-shared circuit 25. At the same time, the M control subcircuits 23 in the shared circuit 24 do not receive the start signal. Among the M control subcircuits 23 in the shared circuit 24, one of the control subcircuits 23 (referred to as the first control subcircuit) will output a repair indication signal in the enabled state, indicating that the first repair operation is performed using the repair resource corresponding to the first control subcircuit.

[0102] If the enable signal is in a non-enabled state, the start signal obtained by sampling and latching is also in a non-enabled state. At this time, the start signal will not "turn off" the NM control sub-circuits 23 in the shared circuit 24; in this case, one of the N control sub-circuits 23 (referred to as the second control sub-circuit) will output a repair indication signal in an enabled state, indicating that the second repair operation will be performed using the repair resources corresponding to the second control sub-circuit.

[0103] That is, the start signal starts the first repair operation, and its function is to control the control subcircuit 23 that receives it not to start, so that the control subcircuit 23 that does not receive the start signal can be used to perform the first repair operation.

[0104] In this way, the embodiment of the present disclosure uses a preset clock signal to sample and latch the enable signal to generate a start signal, and then, according to whether the start signal is enabled and whether the repair resource corresponding to the control subcircuit 23 is available, when the start signal is enabled, a repair resource corresponding to a control subcircuit 23 in the shared circuit 24 is selected to perform the first repair operation, and when the start signal is not enabled, a repair resource corresponding to one of the N control subcircuits 23 is selected to perform the second repair operation. It can be seen that the M control subcircuits 23 in the shared circuit 24 can be applied to both the first repair operation and the second repair operation, that is, "shared", while the control subcircuit 23 in the non-shared circuit 25 is only used to perform the second repair operation, that is, "non-shared".

[0105] exist Figure 2 Based on Figure 3, which shows a schematic diagram of the composition structure of another repair sharing circuit provided by an embodiment of the present disclosure. Figure 3 As shown, in some embodiments, the i-th control subcircuit 23 is used to receive the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal; perform logic processing according to the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal to generate the i-th repair indication signal; wherein, i is an integer greater than 0 and less than or equal to N, and when i is greater than 0 and less than N, the output end of the i-th control subcircuit 23 is connected to the i+1-th control subcircuit 23; if the i-th control subcircuit 23 belongs to the shared circuit 24, the i-th first control signal is a preset signal, and if the i-th control subcircuit 23 belongs to the non-shared circuit 25, the i-th first control signal is a start signal; when i is equal to 1, the 1-th second control signal is a preset signal, and when i is greater than 1 and less than or equal to N, the i-th second control signal is the i-1-th repair indication signal;

[0106] Among them, when the i-th first control signal is in the enabled state and the control sub-circuit 23 belongs to the non-shared circuit 25, the i-th repair indication signal is in the disabled state; when the i-th first control signal is in the enabled state and the control sub-circuit 23 belongs to the shared circuit 24, or when the i-th first control signal is in the disabled state, if the i-th state indication signal is in the enabled state, the i-th second control signal is in the disabled state, and the repair command signal is in the enabled state, the i-th repair indication signal is in the enabled state.

[0107] It should be noted that if Figure 3 As shown, the N control subcircuits 23 are in a series relationship, and the output terminals of the control subcircuits 0 to N-2 are all connected to an input terminal of the next control subcircuit 23, so that the repair indication signal is sent to the next control subcircuit 23 as the second control signal of the next control subcircuit 23. In other words, the repair indication signal output by the previous control subcircuit 23 will have an impact on the next control subcircuit 23. The impact can be specifically: only when the i-1th repair indication signal is in a non-enabled state, it is necessary to judge the state of the i-th repair indication signal, and if the i-1th repair indication signal is in an enabled state, the repair operation is directly performed using the repair resource corresponding to the i-1th control subcircuit 23.

[0108] like Figure 3 As shown, each control subcircuit 23 may include at least four input terminals and one output terminal. The control subcircuit 23 performs logic processing according to the received signal to generate a corresponding repair indication signal.

[0109] Based on the series relationship between the N control subcircuits 23, for the i-th control subcircuit 23, the i-th second control signal it receives is the i-1th repair control signal output by the i-1th control subcircuit 23; for the first control subcircuit 23 ( Figure 3 In the control subcircuit 0), since there is no previous control subcircuit, the first second control signal received by the control subcircuit 0 is a preset signal with a fixed level state, and the state of the preset signal is opposite to the level state of the repair indication signal in the enabled state; for example: if the repair indication signal is in the enabled state at logic 1, the preset signal is fixed to logic 0; if the repair indication signal is in the enabled state at logic 0, the preset signal is fixed to logic 1. The second control signal is used to indicate whether the control subcircuit 23 determines the availability of the corresponding repair resource. Specifically, if the i-th repair indication signal is in an enabled state, it means that the repair operation is performed using the repair resource corresponding to the i-th control subcircuit 23, and there is no need to determine whether the repair resource corresponding to the subsequent control subcircuit 23 is available. In this case, the i+1-th to N-th control subcircuits 23 all output repair indication signals in a non-enabled state; or, if one or more of the i+1-th to N-th control subcircuits 23 output repair indication signals in an enabled state, a shielding mechanism can also be set to shield redundant repair indication signals to ensure that when the first repair operation is performed, according to the priority order of the 1st to M-th control subcircuits 23, and when the second repair operation is performed, according to the priority order of the 1st to N-th control subcircuits 23, the control subcircuit 23 that outputs the repair indication signal in the enabled state earliest is determined as the aforementioned first control subcircuit or second control subcircuit, and the repair operation is performed using the corresponding repair resources.

[0110] In the embodiment of the present disclosure, taking the repair indication signal as an enabled state when it is logic 1 as an example, the preset signal can be a ground signal GND (logic 0), and the input end of the control subcircuit 0 is grounded. Logic 1 can be recorded as a first level state, and logic 0 can be recorded as a second level state.

[0111] It should also be noted that the state indication signal is used to indicate the availability of the repair resource corresponding to the corresponding control subcircuit 23; the enable state of the state indication signal can be logic 1 or logic 0, and logic 1 is taken as an example here. When the state indication signal is in the enabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 is available, and when the state indication signal is in the disabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 is unavailable.

[0112] The first control signal indicates whether the corresponding control subcircuit 23 needs to perform a repair operation. The enable state of the first control signal can be logic 1 or logic 0, and logic 1 is taken as an example here. When the first control signal is in a non-enabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 needs to perform a repair operation (whether to perform it specifically needs to be determined in combination with other signals). When the first control signal is in an enabled state, it means that the repair resource corresponding to the corresponding control subcircuit 23 does not need to perform a repair operation. In the shared circuit 24, whether it is for the first repair operation or the second repair operation, the repair resource corresponding to each control subcircuit 23 needs to be used as a backup resource for performing the first repair operation. Therefore, the first control signal received by each control subcircuit 23 in the shared circuit 24 is always in a non-enabled state. Since in the embodiment of the present disclosure, taking the first control signal as an enabled state when logic 1 as an example, the first control signal received by the control subcircuit 23 in the shared circuit 24 can be a ground signal GND, so that the input end of the control subcircuit 0 to the control subcircuit M-1 is grounded. In the non-shared circuit 25, the first control signal received by each control sub-circuit 23 is the aforementioned start signal. According to the state of the start signal and in combination with the states of other signals, it is determined whether the repair resources corresponding to each control sub-circuit 23 in the non-shared circuit 25 are used to perform the repair operation; in this way, if the start signal received by the control sub-circuit 23 in the non-shared circuit 25 is in an enabled state, indicating that the repair resources corresponding to the control sub-circuit 23 are not used to perform the repair operation, then a repair indication signal in a disabled state is output; if the start signal received by the control sub-circuit 23 in the non-shared circuit 25 is in a disabled state, it indicates that the repair resources corresponding to the control sub-circuit 23 are used as backup resources for performing the repair operation, and it is necessary to output the repair indication signal in combination with other signals.

[0113] The repair command signal is used to indicate whether the repair shared circuit 20 is currently in a repair state. Only when the repair command signal is in an enabled state, it indicates that the repair shared circuit 20 is in a repair state, and only then will it be combined with other signals to perform the repair operation; otherwise, if the repair command signal is in a disabled state, the N repair indication signals are all in a disabled state.

[0114] In this way, when the start signal is in the enabled state, corresponding to the first repair mode of the first repair operation, the control subcircuits 23 in the non-shared circuit 25 are all turned off by the first control signal (start signal), and in the shared circuit 24, the first control signal (preset signal GND) is always in the disabled state. If the signal received by the i-th control subcircuit 23: the second control signal (i-1th repair indication signal) is in the disabled state (indicating that the repair resource corresponding to the i-1th control subcircuit 23 is not used to perform the repair operation), the state indication signal is in the enabled state (indicating that the repair resource corresponding to the i-th control subcircuit 23 is available), and the repair command signal is in the enabled state (indicating that the repair shared circuit 20 is in the repair working state), when these conditions are met, it means that the repair resource corresponding to the i-th control subcircuit 23 can be used to perform the repair operation, so that the i-th control subcircuit 23 outputs the i-th repair indication signal in the enabled state. When the start signal is in the disabled state, the same applies, which will not be repeated here.

[0115] The embodiment of the present disclosure utilizes the state indication signal, the first control signal, the second control signal and the repair command signal to jointly enable the control subcircuit 23 to output the repair indication signal to perform the repair operation. According to the state of the start signal, the first repair operation is performed using the repair resources corresponding to the shared circuit 24 or the second repair operation is performed using the repair resources corresponding to the repair control circuit 22, thereby realizing resource sharing of the first repair operation and the second repair operation.

[0116] like Figure 3 As shown, the repair sharing circuit 20 may further include:

[0117] The register circuit 26 is used to set N status indication signals and send the N status indication signals to the N control sub-circuits 23 respectively;

[0118] When the i-th state indication signal is in the enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit 23 is available, where i is an integer greater than 0 and less than or equal to N.

[0119] It should be noted that if Figure 3 As shown, the register circuit 26 can set a status indication signal indicating the availability of each repair resource. Here, the register circuit 26 can include MR54, 55, 56, and 57 in the DRAM. For example, Table 1 shows the corresponding information of the operand (OP[0]-OP[7]) of MR54 and the repair resource (HPPR Resource, HPPR Resource), and Table 2 shows the register definition of MR54.

[0120] Table 1

[0121]

[0122] Table 2

[0123]

[0124] In this way, the register circuit 26 can transform the data shown in Table 2 to obtain a corresponding status indication signal, thereby controlling the operation performed by the repair sharing circuit 20 .

[0125] It should also be noted that in order to ensure the reliability of the repair control circuit 22, in the first operating mode, the register circuit 26 can set only one of the M status indication signals corresponding to the shared circuit 24 to be in an enabled state, and in the second operating mode, the register circuit 26 can set only one of the N status indication signals to be in an enabled state, so that among the available alternative resources, only one repair resource corresponding to the control sub-circuit 23 is in an available state. In this way, it is avoided that multiple control sub-circuits 23 all output repair indication signals in an enabled state, causing errors.

[0126] Below, take N=4, M=1 as an example, see Figure 4 , which shows a detailed structural diagram of a repair sharing circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the N control subcircuits include a first subcircuit (PPR Info 0), a second subcircuit (PPR Info 1), a third subcircuit (PPR Info 2) and a fourth subcircuit (PPR Info 3), and the first subcircuit (PPR Info 0) is used as a shared circuit, and the second subcircuit (PPR Info 1), the third subcircuit (PPR Info 2) and the fourth subcircuit (PPR Info 3) are used as non-shared circuits; wherein:

[0127] The output end of the mode selection circuit 21 is respectively connected to the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3), and is used to send a start signal to the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3).

[0128] like Figure 4 As shown, the mode selection circuit 21 includes a latch LAT, wherein:

[0129] The first input terminal of the latch LAT is used to receive the enable signal mppr_n, the second input terminal of the latch LAT is used to receive the preset clock signal LatClk, the output terminal of the latch LAT is used to output the start signal mppr_on, and the output terminal of the latch LAT is respectively connected to each control sub-circuit in the non-shared circuit.

[0130] like Figure 4 As shown, the latch LAT also includes a reset terminal, which is used to receive a reset signal Reset_n, wherein:

[0131] The latch LAT is used for controlling the start signal mppr_on to be reset to a non-enabled state when the reset signal Reset_n is in an enabled state.

[0132] It should be noted that, taking the repair control circuit 22 including four control sub-circuits as an example, Figure 4 As shown, the first subcircuit (PPR Info 0) is a shared circuit, and the corresponding repair resource is PPR0. The first first control signal and the first second control signal received are both ground signals GND, the first state indication signal received is recorded as PPR_unused0, and the first state indication signal output is recorded as PPR_ok0. The second subcircuit (PPR Info 1), the third subcircuit (PPR Info 2) and the fourth subcircuit (PPR Info 3) are non-shared circuits, and the corresponding repair resources are PPR1, PPR2 and PPR3 respectively; the second first control signal received by the second subcircuit (PPR Info 1) is the start signal mppr_on, the second second control signal received is PPR_pre_ok1 (i.e., PPR_ok0), the second state indication signal received is recorded as PPR_unused1, and the second state indication signal output is recorded as PPR_ok1. The third subcircuit (PPR Info2) and the fourth subcircuit (PPR Info 3) are similar, and will not be repeated.

[0133] In this embodiment, four repair resources may be allocated to each half Bank in the memory, but other allocation methods may also be used, which are not specifically limited here.

[0134] like Figure 4 As shown, the second sub-circuit (PPR Info 1), the third sub-circuit (PPR Info 2) and the fourth sub-circuit (PPR Info 3) all receive the start signal mppr_on and are controlled thereby to determine whether to perform a repair operation according to the start signal mppr_on.

[0135] The mode selection circuit 21 may be implemented by a latch LAT, wherein the latch LAT includes a first input terminal, a second input terminal, a reset terminal, and an output terminal. The reset signal Reset_n is used to reset the start signal mppr_on output by the latch LAT. Exemplarily, the reset signal Reset_n can be a signal that is valid at a low level (logic 0). In this way, when the level state of Reset_n is logic 0, no matter what state the enable signal mppr_n and the preset clock signal LatClk are in, the start signal mppr_on will be reset to a non-enabled state (logic 0); when the level state of the reset signal Reset_n is logic 1 (high level), after the clock edge of the preset clock signal LatClk arrives, the latch LAT can sample and latch the enable signal mppr_n according to the preset clock signal LatClk to obtain the start signal mppr_on. Here, the enable signal mppr_n can be a signal that is valid at a low level, that is, when the enable signal mppr_n is logic 0, it indicates that it is in an enabled state. The high-level start signal mppr_on is obtained through sampling and latching by the latch LAT, indicating that the start signal mppr_on is in an enabled state.

[0136] The preset clock signal LatClk may be generated according to the repair command signal and the initial clock signal. Here, the initial clock signal may be a system clock or other signal, and the preset clock signal LatClk may be generated according to the repair command signal and the initial clock signal by performing an AND logic operation. For the preset clock signal LatClk, when the repair command signal PPR_cmd is in an enabled state, a short pulse is generated, which is used as a sampling clock for the latch LAT and the control subcircuit 23.

[0137] Furthermore, the latch LAT may be a latch composed of a NAND gate. Figure 4 As shown, the latch LAT includes a first NAND gate NA1 and a second NAND gate NA2, wherein:

[0138] The first input terminal of the first NAND gate NA1 is used as the first input terminal of the latch LAT to receive the enable signal mppr_n;

[0139] The second input terminal of the first NAND gate NA1 is connected to the output terminal of the second NAND gate NA2;

[0140] The output end of the first NAND gate NA1 is used as the output end of the latch LAT to output the start signal mppr_on, and the output end of the first NAND gate NA1 is connected to the first input end of the second NAND gate NA2;

[0141] The second input end of the second NAND gate NA2 serves as the second input end of the latch LAT, and is used to receive the preset clock signal LatClk;

[0142] The third input terminal of the second NAND gate NA2 serves as a reset terminal of the latch LAT, and is used to receive a reset signal Reset_n.

[0143] It should be noted that, taking the first repair operation as MPPR and the second repair operation as HPPR as an example, the enable signal mppr_n is in the enable state to indicate starting the MPPR, and the enable signal mppr_n is sampled and latched to obtain the start signal mppr_on to control the non-shared circuit to be turned off.

[0144] For each control subcircuit 23, see Figure 5 , which shows a detailed structural diagram of a control subcircuit provided by an embodiment of the present disclosure. Figure 5 As shown, the i-th control subcircuit 23 includes a sampling circuit 231, a first logic subcircuit 2321, a second logic subcircuit 2322 and a third logic subcircuit 2323, wherein:

[0145] The sampling circuit 231 is used to receive the i-th state indication signal PPR_unused i-1 and the preset clock signal LatClk, and perform sampling processing on the i-th state indication signal PPR_unused i-1 according to the preset clock signal LatClk to generate the i-th sampling indication signal PPR_cur_ok_n i-1; the state of the i-th sampling indication signal PPR_cur_ok_n i-1 is opposite to the state of the i-th state indication signal PPR_unused i-1;

[0146] The first logic sub-circuit 2321 is used to receive the i-th sampling indication signal PPR_cur_ok_n i-1 and the i-th first control signal (mppr_on or GND); perform logic processing according to the i-th sampling indication signal PPR_cur_ok_n i-1 and the i-th first control signal (mppr_on or GND) to generate the i-th first intermediate signal; when the i-th first control signal (mppr_on) is in an enabled state, the i-th first intermediate signal is in an enabled state, and when the i-th first control signal (mppr_on or GND) is in a disabled state, the state of the i-th first intermediate signal is the same as the state of the i-th sampling indication signal PPR_cur_ok_n i-1;

[0147] The second logic subcircuit 2322 is configured to receive the ith first intermediate signal and the ith second control signal (PPR_pre_ok i-1 or GND); perform logic processing according to the ith first intermediate signal and the ith second control signal (PPR_pre_ok i-1 or GND) to generate the ith second intermediate signal; when the ith first intermediate signal is in an enabled state, the ith second intermediate signal is in a disabled state, and when the ith first intermediate signal is in a disabled state, the state of the ith second intermediate signal is opposite to the state of the ith second control signal (PPR_pre_ok i-1 or GND);

[0148] The third logic sub-circuit 2323 is used to receive the i-th second intermediate signal and the repair command signal PPR_cmd; perform logic processing according to the i-th second intermediate signal and the repair command signal PPR_cmd, and generate the i-th repair indication signal PPR_ok i-1; wherein, when the i-th second intermediate signal and the repair command signal PPR_cmd are both in the enabled state, the i-th repair indication signal PPR_ok i-1 is in the enabled state, otherwise, the i-th repair indication signal PPR_ok i-1 is in the disabled state.

[0149] It should be noted that Figure 5 Take a control subcircuit 23 that is not the first and belongs to the non-shared circuit 25 as an example. If it is a control subcircuit 23 in the shared circuit 24, the first logic subcircuit 2321 does not receive the start signal mppr_on, but receives the preset signal GND; if it is the first control subcircuit 23, the second logic subcircuit 2322 does not receive the previous state indication signal (i.e., PPR_pre_ok i-1), but receives the preset signal GND.

[0150] like Figure 5 As shown, in the i-th control subcircuit, the sampling circuit 231 includes a trigger, wherein:

[0151] The input terminal D of the trigger 231 is used to receive the i-th state indication signal PPR_unused i-1;

[0152] The clock terminal CK of the trigger 231 is used to receive a preset clock signal LatClk;

[0153] The output terminal Qn of the flip-flop 231 is used to output the i-th sampling indication signal PPR_cur_ok_ni-1.

[0154] It should be noted that if Figure 5As shown, the sampling circuit 231 can be specifically implemented by a trigger (such as a D trigger DFF). Here, the sampling circuit 231 also includes a clock terminal CK, and the inverting output terminal Qn of the DFF outputs the i-th sampling indication signal PPR_cur_ok_n i-1. Therefore, the state of the i-th sampling indication signal PPR_cur_ok_n i-1 is opposite to the i-th state indication signal PPR_unused i-1.

[0155] like Figure 5 As shown, in the i-th control subcircuit 23, the first logic subcircuit 2321 includes an OR gate OR, the second logic subcircuit 2322 includes a NOR gate NOR, and the third logic subcircuit 2323 includes an AND gate AND, wherein:

[0156] The first input end of the OR gate OR is used to receive the i-th sampling indication signal PPR_cur_ok_n i-1; the second input end of the OR gate OR is used to receive the i-th first control signal (mppr_on / GND); the output end of the OR gate OR is connected to the second input end of the NOR gate NOR, and is used to output the i-th first intermediate signal;

[0157] The first input end of the NOR gate NOR is used to receive the i-th second control signal (PPR_pre_ok i-1 or GND); the second input end of the NOR gate NOR is used to receive the i-th first intermediate signal; the output end of the NOR gate NOR is connected to the second input end of the AND gate AND, and is used to output the i-th second intermediate signal;

[0158] The first input terminal of the AND gate AND is used to receive the repair command signal PPR_cmd; the second input terminal of the AND gate AND is used to receive the i-th second intermediate signal; and the output terminal of the AND gate AND is used to output the i-th repair indication signal PPR_ok i-1.

[0159] Combined with the above Figure 4 and Figure 5 On this basis, see Figure 6 , which shows a signal timing diagram provided by an embodiment of the present disclosure. Figure 6As shown, it is the signal timing corresponding to a certain control subcircuit 23 in the non-shared circuit 25. At time T1, the clock signal LatClk becomes a high level, the enable signal mppr_n is at a low level (enabled state), and the reset signal Rsset_n is at a high level, so that the latch LAT performs latching processing according to the enable signal mppr_n to obtain the start signal mppr_on (high level) in the enabled state; at this time, for the OR gate OR, since the start signal mppr_on of one of the input signals is a high level, no matter what state the other input signal is in, the first intermediate signal outputted by it is a high level; further, for the NOR gate NOR, since the first intermediate signal of one of its input signals is a high level, no matter what state the other input signal is in, the second intermediate signal outputted by it is always a low level; and further, for the AND gate AND, since the second intermediate signal of one of its input signals is a low level, no matter what state the other input signal is in, the repair indication signal PPR_ok outputted by it is always a low level. That is, for the control subcircuit 23 in the non-shared circuit 25, as long as the enable signal mppr_n is at a low level (enabled state), the state indication signal output by the control subcircuit 23 is in a disabled state, thereby ensuring that in the first repair mode, the non-shared circuit 25 is turned off and no repair operation is performed.

[0160] At time T2, the reset signal Reset_n resets the start signal mppr_on to a low level (disabled state).

[0161] At time T3, the clock signal LatClk becomes high, the enable signal mppr_n is at a high level (disabled state), and the reset signal Reset_n is high, so that the latch LAT performs latching processing according to the enable signal mppr_n, and obtains the start signal mppr_on (low level) in the non-enabled state; at the same time, the trigger DFF samples and latches the state indication signal PPR_unused at a high level (enabled state) according to the clock signal LatClk, and outputs the sampling indication signal PPR_cur_ok_n at a low level at its inverting output terminal. At this time, for the OR gate OR, since the start signal mppr_on of one of the input signals is low, its output signal is the same as the level state of the other input signal. Figure 6 In the example, if the sampling indication signal PPR_cur_ok_n is at a low level, the first intermediate signal is at a low level (if the sampling indication signal PPR_cur_ok_n is at a high level, the first intermediate signal is at a high level); further, for the NOR gate, since the first intermediate signal of one of its input signals is at a low level, its output signal is opposite to the level state of the other input signal. Figure 6In the embodiment, since the second control signal PPR_pre_ok is at a low level, the second intermediate signal is at a high level; furthermore, for the AND gate AND, the second intermediate signal is at a high level, and the repair command signal is also at a high level (enabled state), so that the output indication signal PPR_ok is at a high level.

[0162] Since the first control signal received by each control subcircuit 23 in the shared circuit 24 is logic 0, its timing is consistent with the timing of the control subcircuit 23 in the non-shared circuit 25 when the enable signal mppr_n is 1 (the start signal mppr_on is 0), which will not be repeated here. That is, when the first control signal (start signal mppr_on or preset signal GND) is at a low level (disabled state), for each control subcircuit 23 in the repair control circuit 22, if it is simultaneously satisfied that: the repair indication signal PPR_unused is in an enabled state (indicating that the repair resource corresponding to the control subcircuit 23 is available), the second control signal PPR_pre_ok is in a disabled state (indicating that the repair resource corresponding to the previous control subcircuit 23 does not perform a repair operation), and the repair command signal PPR_cmd is in an enabled state (indicating that the repair shared circuit 20 is in a repair working state), the control subcircuit 23 will output a repair indication signal in an enabled state, otherwise, as long as any one of the conditions is not satisfied, the repair subcircuit 23 will output a repair indication signal in a disabled state.

[0163] The simulation results show that the repair sharing circuit 20 can realize the sharing of repair resources between HPPR and MPPR.

[0164] In short, the embodiment of the present disclosure provides a circuit for realizing MPPR and HPPR resource sharing. In order to reduce chip size consumption, a simple implementation method is introduced. That is, MPPR and HPPR share some redundant resources and HPPR exclusively uses some resources. Figure 4 In the example, each half bank is allocated 4 hPPR resources. (The priority is: PPR0>PPR 1>PPR 2>PPR 3), where PPR0 is a shared resource that not only performs HPPR but also MPPR, while PPR1 / 2 / 3 are only used for HPPR. This solution introduces a simple but efficient design to achieve DDR5 MPPR and HPPR sharing PPR resources, which can achieve SPEC requirements under the limited circuit implementation based on the current HPPR design, thereby reducing design time and size cost.

[0165] In another embodiment of the present disclosure, see Figure 7 , which shows a flowchart of a repair and cancellation method provided by an embodiment of the present disclosure. Figure 7 As shown, the method may include:

[0166] S701: receiving a preset clock signal and an enable signal through a mode selection circuit, performing latch processing according to the preset clock signal and the enable signal, and generating a start signal.

[0167] S702: Receive a start signal and N status indication signals through a repair control circuit, perform logic processing based on the start signal and the N status indication signals, and output N repair indication signals through N control sub-circuits respectively, where each status indication signal is used to indicate whether a repair resource corresponding to its corresponding control sub-circuit is available.

[0168] Wherein, when the start signal is in an enabled state and the repair indication signal output by the first control subcircuit in the shared circuit is in an enabled state, the first repair operation is performed according to the repair resource corresponding to the first control subcircuit, and the first control subcircuit is any one of the M control subcircuits.

[0169] It should be noted that the repair sharing method provided in the embodiment of the present disclosure is applied to the repair sharing circuit 20 in the aforementioned embodiment. For details not disclosed in this embodiment, please refer to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0170] In another embodiment of the present disclosure, see Figure 8 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 8 As shown, the memory 80 at least includes the repair sharing circuit 20 in the aforementioned embodiment.

[0171] It should be noted that the memory 80 can be a semiconductor memory such as DRAM. For DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

[0172] Since the memory 80 includes the repair sharing circuit 20, the repair sharing function can be realized, and the chip area can be saved, which is beneficial to the integration of the memory and reduces the cost.

[0173] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0174] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0175] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0176] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0177] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0178] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0179] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A repair sharing circuit, characterized in that: It includes a mode selection circuit and a repair control circuit, wherein the repair control circuit includes N control subcircuits, M of the N control subcircuits are used as shared circuits, each of the control subcircuits corresponds to a repair resource, N and M are both integers greater than 0, and M is less than N, wherein: The mode selection circuit is used to receive a preset clock signal and an enable signal, perform latch processing according to the preset clock signal and the enable signal, and generate a start signal; The repair control circuit is used to receive the start signal and N status indication signals, perform logic processing according to the start signal and the N status indication signals, and output N repair indication signals through the N control subcircuits respectively, each of the status indication signals is used to indicate whether the repair resource corresponding to the corresponding control subcircuit is available; Among them, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits.

2. The repair sharing circuit according to claim 1, characterized in that: When the start signal is in a non-enabled state and the repair indication signal output by the second control sub-circuit in the repair control circuit is in an enabled state, a second repair operation is performed according to the repair resources corresponding to the second control sub-circuit, and the second control sub-circuit is any one of the N control sub-circuits.

3. The repair sharing circuit according to claim 2, characterized in that: The remaining (NM) control sub-circuits of the N control sub-circuits are non-shared circuits, and the mode selection circuit includes a latch, wherein: The first input end of the latch is used to receive the enable signal, the second input end of the latch is used to receive the preset clock signal, the output end of the latch is used to output the start signal, and the output end of the latch is respectively connected to each of the control sub-circuits in the non-shared circuit.

4. The repair sharing circuit according to claim 3, characterized in that: The latch further includes a reset terminal, which is used to receive a reset signal, wherein: The latch is used to control the start signal to be reset to a non-enabled state when the reset signal is in an enabled state.

5. The repair sharing circuit according to claim 4, characterized in that: The latch comprises a first NAND gate and a second NAND gate, wherein: The first input terminal of the first NAND gate is used as the first input terminal of the latch to receive the enable signal; The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate; The output end of the first NAND gate serves as the output end of the latch, and is used to output the start signal, and the output end of the first NAND gate is connected to the first input end of the second NAND gate; The second input end of the second NAND gate is used as the second input end of the latch to receive the preset clock signal; The third input terminal of the second NAND gate serves as a reset terminal of the latch, and is used to receive the reset signal.

6. The repair sharing circuit according to claim 3, characterized in that: The i-th control subcircuit is used to receive the i-th first control signal, the i-th second control signal, the i-th status indication signal and the repair command signal; Performing logical processing according to the i-th first control signal, the i-th second control signal, the i-th state indication signal and the repair command signal to generate the i-th repair indication signal; wherein, i is an integer greater than 0 and less than or equal to N, and when i is greater than 0 and less than N, the output end of the i-th control subcircuit is connected to the i+1-th control subcircuit; if the i-th control subcircuit belongs to the shared circuit, the i-th first control signal is a preset signal, and if the i-th control subcircuit belongs to the non-shared circuit, the i-th first control signal is the start signal; when i is equal to 1, the first second control signal is a preset signal, and when i is greater than 1 and less than or equal to N, the i-th second control signal is the i-1-th repair indication signal; Among them, when the i-th first control signal is in an enabled state and the i-th control sub-circuit belongs to the non-shared circuit, the i-th repair indication signal is in a disabled state; when the i-th first control signal is in an enabled state and the i-th control sub-circuit belongs to the shared circuit, or when the i-th first control signal is in a disabled state, if the i-th state indication signal is in an enabled state, the i-th second control signal is in a disabled state, and the repair command signal is in an enabled state, the i-th repair indication signal is in an enabled state.

7. The repair sharing circuit according to claim 6, characterized in that: The i-th control subcircuit comprises a sampling circuit, a first logic subcircuit, a second logic subcircuit and a third logic subcircuit, wherein: The sampling circuit is used to receive the i-th state indication signal and the preset clock signal, and perform sampling processing on the i-th state indication signal according to the preset clock signal to generate an i-th sampling indication signal; the state of the i-th sampling indication signal is opposite to the state of the i-th state indication signal; The first logic subcircuit is configured to receive the i-th sampling indication signal and the i-th first control signal; perform logic processing according to the i-th sampling indication signal and the i-th first control signal to generate an i-th first intermediate signal; when the i-th first control signal is in an enabled state, the i-th first intermediate signal is in an enabled state, and when the i-th first control signal is in a disabled state, the state of the i-th first intermediate signal is the same as the state of the i-th sampling indication signal; the second logic sub-circuit is configured to receive an i-th first intermediate signal and an i-th second control signal; perform logic processing according to the i-th first intermediate signal and the i-th second control signal to generate an i-th second intermediate signal; when the i-th first intermediate signal is in an enabled state, the i-th second intermediate signal is in a disabled state, and when the i-th first intermediate signal is in a disabled state, a state of the i-th second intermediate signal is opposite to a state of the i-th second control signal; The third logic sub-circuit is used to receive the i-th second intermediate signal and the repair command signal; perform logic processing according to the i-th second intermediate signal and the repair command signal to generate the i-th repair indication signal; wherein, when the i-th second intermediate signal and the repair command signal are both in an enabled state, the i-th repair indication signal is in an enabled state, otherwise, the i-th repair indication signal is in a disabled state.

8. The repair sharing circuit according to claim 7, characterized in that: In the i-th control subcircuit, the sampling circuit includes a trigger, wherein: The input end of the trigger is used to receive the i-th state indication signal; The clock terminal of the trigger is used to receive the preset clock signal; The output end of the trigger is used to output the i-th sampling indication signal.

9. The repair sharing circuit according to claim 7, characterized in that: In the i-th control subcircuit, the first logic subcircuit includes an OR gate, the second logic subcircuit includes a NOR gate, and the third logic subcircuit includes an AND gate, wherein: The first input end of the OR gate is connected to the output end of the sampling circuit, and is used to receive the i-th sampling indication signal; the second input end of the OR gate is used to receive the i-th first control signal; the output end of the OR gate is connected to the second input end of the NOR gate, and is used to output the i-th first intermediate signal; The first input end of the NOR gate is used to receive the i-th second control signal; the second input end of the NOR gate is used to receive the i-th first intermediate signal; the output end of the NOR gate is connected to the second input end of the AND gate, and is used to output the i-th second intermediate signal; The first input end of the AND gate is used to receive the repair command signal; the second input end of the AND gate is used to receive the i-th second intermediate signal; and the output end of the AND gate is used to output the i-th repair indication signal.

10. The repair sharing circuit according to claim 6, characterized in that: N=4, M=1, the N control subcircuits include a first subcircuit, a second subcircuit, a third subcircuit and a fourth subcircuit, and the first subcircuit serves as the shared circuit, and the second subcircuit, the third subcircuit and the fourth subcircuit serve as the non-shared circuit; wherein: The output end of the mode selection circuit is connected to the second sub-circuit, the third sub-circuit and the fourth sub-circuit respectively, and is used to send the start signal to the second sub-circuit, the third sub-circuit and the fourth sub-circuit.

11. The repair sharing circuit according to claim 1, characterized in that: The repair sharing circuit also includes: A register circuit, used for setting the N state indication signals, and sending the N state indication signals to the N control sub-circuits respectively; When the i-th state indication signal is in an enabled state, it indicates that the repair resource corresponding to the i-th control subcircuit is available, where i is an integer greater than 0 and less than or equal to N.

12. The repair sharing circuit according to claim 2, characterized in that: The first repair operation includes a test post-packaging repair (MPPR), and the second repair operation includes a hard post-packaging repair (HPPR).

13. The repair sharing circuit according to any one of claims 1 to 12, characterized in that: The preset clock signal is generated according to the repair command signal and the initial clock signal.

14. A repair sharing method, characterized in that: Applied to the repair shared circuit according to any one of claims 1 to 13, the method comprising: Receiving a preset clock signal and an enable signal through the mode selection circuit, performing latch processing according to the preset clock signal and the enable signal, and generating a start signal; The repair control circuit receives the start signal and N status indication signals, performs logic processing according to the start signal and the N status indication signals, and outputs N repair indication signals respectively through the N control subcircuits, each of the status indication signals being used to indicate whether the repair resource corresponding to the corresponding control subcircuit is available; Among them, when the start signal is in an enabled state and the repair indication signal output by the first control sub-circuit in the shared circuit is in an enabled state, a first repair operation is performed according to the repair resources corresponding to the first control sub-circuit, and the first control sub-circuit is any one of the M control sub-circuits.

15. A memory, characterized in that: Comprising the repair sharing circuit as claimed in any one of claims 1 to 13.

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