Channel anomaly detection method and system suitable for Chisel environment

Abstract

The invention relates to a channel anomaly detection method and system suitable for a Chisel environment. The method comprises the following steps: acquiring a target Chisel source code file, and performing tracking marking on a compiling behavior of the target Chisel source code file based on comprehensive abnormity existing after synthesis so as to obtain a channel mark Chisel source path related to the channel abnormity after tracking marking; and marking a Chisel source path for the generated channel, carrying out integrated path confirmation and marking on a compiling process of a communication abnormal signal so as to obtain a corresponding channel detection marking path after marking, carrying out abnormal signal source analysis and tracking based on the channel detection marking path so as to generate abnormal signal source marking information after analysis and tracking, and sending the abnormal signal source marking information to the communication terminal. And detecting and processing the abnormal signal source mark information by using a comprehensive tool. According to the invention, the channel abnormity in the bus protocol can be effectively detected, and the reliability of channel abnormity detection is improved.

Description

Technical Field

[0001] The present invention relates to a channel anomaly detection method and system, in particular to a channel anomaly detection method and system suitable for a Chisel environment. Background Art

[0002] Chisel (Constructed Hardware in Scala Embedded Language) is a Scala library for building high-level, synthesizable, modular hardware designs. It allows designers to define the behavior of the hardware at a high level and then convert it into low-level Verilog code or VHDL code through a series of conversion steps. This allows designers to focus on implementing the functionality of the hardware without having to worry about the underlying details. The Chisel environment has the following features: 1) High-level abstraction: The Chisel environment allows developers to use high-level Scala language features to describe hardware circuits, which makes the hardware design process more flexible and easier to maintain. Through high-level abstraction, designers can think and work at a higher level without paying too much attention to the underlying details.

[0003] 2) Reusability: The Chisel environment supports modular design, which means that the hardware circuit can be decomposed into multiple reusable modules, which not only improves the reusability of the code, but also enhances the scalability of the design, making it more efficient when building complex systems.

[0004] 3) Static type checking: The Chisel environment performs static type checking at compile time, which helps developers find potential errors at an early stage. Based on this feature, development efficiency and code quality can be significantly improved, and the workload of later debugging and modification can be reduced.

[0005] 4) Verilog code generation: The Chisel environment can convert high-level abstract hardware descriptions into corresponding Verilog codes, which facilitates subsequent synthesis and layout and routing. This feature makes the Chisel environment a bridge between high-level abstraction and actual hardware implementation.

[0006] Scala has many features that are suitable for describing circuits. For example, it is a static language, compiler-based, and suitable for conversion into Verilog code / VHDL code. Its operators are methods, currying, pure object-orientation, powerful pattern matching, convenient generic writing, trait mixins, functional programming and other features make it very convenient to develop DSL in Scala.

[0007] For circuits described in Scala, Chisel files can be converted into firrtl files through the firrtl compiler. This is a standard intermediate exchange format, which is a medium that allows various high-level languages ​​to be easily converted into Verilog code / VHDL code, but it is actually at the same level as Verilog code / VHDL code. Here, the Chisel environment chose to compromise and did not generate circuits directly, but used Verilog instead.

[0008] When converting Chisel files to Verilog code, some unsynthesizable syntax will not be used. Therefore, when writing Chisel files, you do not have to worry about not being able to generate circuits, which is a great convenience for hardware novices. For example, the reg in Verilog code does not necessarily refer to a register, which is often misunderstood by novices. However, the Reg in the Chisel environment is a register, and there is no ambiguity. Finally, by using the Scala language's pattern matching, trait mixin, class inheritance and other features, the circuit structure can be quickly changed.

[0009] From the above description, it can be seen that in the whole process of converting Chisel files into Verilog codes, if you are not familiar with these syntax differences and optimization processes, ambiguity and communication anomalies will often occur. This is especially true for various relatively complex bus protocols. How to effectively detect abnormal channels in bus protocols is a technical problem that urgently needs to be solved. Summary of the invention

[0010] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a channel anomaly detection method and system suitable for a Chisel environment, which can effectively detect channel anomalies in a bus protocol and improve the ability and reliability of channel anomaly detection.

[0011] According to the technical solution provided by the present invention, a channel anomaly detection method suitable for a Chisel environment is used to perform channel anomaly detection on a target Chisel source code file whose source code syntax check status is that the source code is normal but there is a comprehensive anomaly after synthesis, wherein the target Chisel source code file includes a bus protocol designed in the Chisel environment, and the comprehensive anomaly existing after synthesis at least includes a channel anomaly existing in the bus protocol; Channel anomaly detection includes: Acquire the target Chisel source code file, and based on the synthesis anomaly found after synthesis, trace and mark the compilation behavior of the target Chisel source code file, so as to obtain a channel mark Chisel source path related to the channel anomaly after tracing and marking; For the channel tag Chisel source path generated above, the compilation process of the communication abnormality signal is integrated with path confirmation and tagging to obtain a corresponding channel detection tag path after tagging, wherein the channel detection tag path includes the communication path included in the target bus protocol, and the target bus protocol is the bus protocol where the channel abnormality occurs; Based on the above-mentioned channel detection mark path, abnormal signal source analysis and tracking are performed to generate abnormal signal source mark information after analysis and tracking, wherein the abnormal signal source mark information includes a probe mark signal and a communication link corresponding to the probe mark signal; The above-mentioned abnormal signal source marking information is detected and processed using a comprehensive tool, wherein, when detecting and processing the abnormal signal source marking information, at least a channel comparison is performed between the probe marking signal and the marked original signal corresponding to the probe marking signal, and the abnormal state of the probe marking signal is determined based on the comparison result, and the abnormal state of the probe marking signal includes abnormal or non-abnormal.

[0012] When tracking and marking the compilation behavior of the target Chisel source code file based on the synthesis anomalies found after synthesis, it includes: Compile the target Chisel source code file to generate the target fir format file after compilation; Based on the synthesis anomaly found after the synthesis, the Chisel source path related to the synthesis anomaly is marked in the target fir format file to generate a channel marked Chisel source path after marking.

[0013] The generated channel marks the Chisel source path, and the compilation process of the communication abnormal signal is integrated to confirm and mark the path, including: Based on the channel anomaly in the comprehensive anomaly, determining the target bus protocol corresponding to the channel anomaly in the target Chisel source code file; In the target Chisel source code file, an integrated path corresponding to each channel tag Chisel source path and the target bus protocol is determined, and the determined integrated path is marked to generate a channel detection tag path after marking.

[0014] Based on the channel detection mark path, the abnormal signal source analysis and tracking includes: In the target Chisel source file, add a Chisel probe for each channel detection tag path; A probe driving signal is loaded to the Chisel probe, and the path output signal under the probe driving signal is captured. When the captured path output signal is inconsistent with the probe driving signal, the channel detection marking path is marked with an abnormal signal source to generate abnormal signal source marking information after the abnormal signal source is marked.

[0015] When the abnormal state of the probe marking signal is non-abnormal, the position of the Chisel probe is adjusted and the abnormal signal source marking information is regenerated; The regenerated abnormal signal source marker information is detected and processed by using a comprehensive tool to determine the abnormal state of the probe marker signal in the currently regenerated abnormal signal source marker information.

[0016] When using comprehensive tools to detect and process abnormal signal source marking information, it includes: Using a synthesis tool to convert the channel marker Chisel source path where the abnormal signal source marker information is located, so as to convert and generate the corresponding gate-level channel Chisel source path; In the gate-level channel Chisel source path generated by the conversion, the probe marking signal is compared with the marking original signal corresponding to the probe marking signal, wherein when the probe marking signal is consistent with the marking original signal, the abnormal state of the probe marking signal is non-abnormal, otherwise, the abnormal state of the probe marking signal is abnormal.

[0017] The synthesis tool includes a vivado tool, a synopsys tool or a Cadence tool; In the Chisel source path of the gate-level channel, the signal name of the probe-marked signal is different from the signal name of the original signal; When performing channel comparison between the probe marking signal and the marking original signal, the channel comparison method includes signal value and / or signal bit width.

[0018] When performing source code syntax detection on the target Chisel source code file, the source code syntax detection state also includes the source code normal function result consistency, wherein, When the source code syntax detection status is consistent with the normal function result of the source code, the target Chisel source code file is checked using the tool flow detection method. When the tool flow detection method is executed, the syntax usage anomalies in the target Chisel source code file are checked, where: The tool flow detection method comprises an sbt compiler checking step, a Treadle interpreter checking step and a waveform viewer checking step which are performed in sequence, wherein: When executing the sbt compiler check step, it is used to check the consistency of the library files, sbt compiler and / or compilation environment version used by the target Chisel source code file. When the sbt compiler check step passes, the Treadle interpreter check step is executed; When executing the Treadle interpreter check step, it is used to check the fir format file to the waveform file generated during the compilation process of the target Chisel source code file. After the Treadle interpreter check step is passed, the waveform viewer check is executed; Used for waveform viewer check when performing waveform viewer check.

[0019] When the synthesis anomaly exists after the synthesis of the target Chisel source code file, it at least includes that the synthesized logic circuit generated based on the target Chisel source code file is inconsistent with the logical function expected by the target Chisel source code file, and / or the waveform file obtained by simulating the synthesized logic circuit is inconsistent with the waveform file obtained by simulating the target Chisel source code file, wherein, When the channel abnormality is a signal setting abnormality, the channel abnormality includes a bit width abnormality and / or a connection abnormality.

[0020] A channel anomaly detection system suitable for Chisel environment includes a channel anomaly detection terminal, wherein for any target Chisel source code file whose source code syntax check status is that the source code is normal but the communication is abnormal, the channel anomaly detection terminal uses the above-mentioned channel anomaly detection to perform channel anomaly detection.

[0021] The advantages of the present invention are as follows: channel anomaly detection is performed on a target Chisel source code file whose source code syntax check status is normal but has synthesis anomalies after synthesis, and compilation behavior tracking marking, integrated path confirmation marking, abnormal signal source analysis and tracking, and synthesis tool detection processing are performed in sequence, so as to determine the channel anomaly in the bus protocol for detection, thereby improving the ability and reliability of channel anomaly detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The figure is a flow chart of an embodiment of channel anomaly detection of the present invention.

[0023] Figure 2 The present invention is a flowchart of an embodiment of performing anomaly detection based on source code syntax detection.

[0024] Figure 3 The present invention is a flow chart of an embodiment of processing Chisel source code files to generate bit stream files. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0026] In order to effectively detect channel anomalies in bus protocols and improve the ability and reliability of channel anomaly detection, the present invention provides a channel anomaly detection method suitable for a Chisel environment, specifically, for performing channel anomaly detection on a target Chisel source code file whose source code syntax check status is that the source code is normal but there is a comprehensive anomaly after synthesis, wherein the target Chisel source code file includes a bus protocol designed in the Chisel environment, and the comprehensive anomaly existing after synthesis at least includes a channel anomaly existing in the bus protocol; Channel anomaly detection includes: Step S1, obtaining the target Chisel source code file, and tracing and marking the compilation behavior of the target Chisel source code file based on the synthesis anomaly existing after synthesis, so as to obtain a channel marking Chisel source path related to the channel anomaly after tracing and marking; Step S2: for the channel mark Chisel source path generated above, the compilation process of the communication abnormality signal is integrated with the path confirmation and marking, so as to obtain the corresponding channel detection mark path after marking, wherein the channel detection mark path includes the communication path included in the target bus protocol, and the target bus protocol is the bus protocol where the channel abnormality occurs; Step S3: Based on the above-mentioned channel detection mark path, analyze and track the source of the abnormal signal to generate abnormal signal source mark information after analysis and tracking, wherein the abnormal signal source mark information includes a probe mark signal and a communication link corresponding to the probe mark signal; Step S4, using a comprehensive tool to detect and process the above-mentioned abnormal signal source marking information, wherein, when detecting and processing the abnormal signal source marking information, at least a channel comparison is performed between the probe marking signal and the marked original signal corresponding to the probe marking signal, and the abnormal state of the probe marking signal is determined according to the comparison result, and the abnormal state of the probe marking signal includes abnormal or non-abnormal.

[0027] It should be noted that the Chisel environment specifically refers to the Chisel language environment mentioned in the background technology. In the Chisel environment, the required Chisel source code files can be designed and generated, and the Chisel source code files can be converted into corresponding low-level Verilog codes or VHDL codes; specifically, the process of designing and generating Chisel source code files and converting them into Verilog codes or VHDL codes can be consistent with the prior art and will not be repeated here. The channel anomaly detection of the present invention specifically refers to checking and confirming that there are abnormal channels in the Chisel source code file. Therefore, the target Chisel source code file is the Chisel source code file to be subjected to channel anomaly detection. It should be noted that the abnormal channel may include at least one abnormal path for transmitting a signal, or at least one path for transmitting a signal has a signal setting abnormality.

[0028] The target Chisel source code file of the present invention specifically refers to a Chisel source code file whose source code syntax check status should be that the source code is normal, but there is a synthesis anomaly after synthesis, wherein the source code is normal specifically refers to the situation that there is no grammatical ambiguity or incorrect usage in the target Chisel source code file, that is, the target Chisel source code file does not have a grammatical anomaly. In one embodiment of the present invention, there is a synthesis anomaly after synthesis, which at least includes that the synthesized logic circuit generated based on the target Chisel source code file is inconsistent with the expected logic function of the target Chisel source code file, and / or the waveform file obtained by simulating the synthesized logic circuit is inconsistent with the waveform file obtained by simulating the target Chisel source code file, that is, when the logic circuit generated after synthesis is inconsistent with the expected logic function and / or the waveform file is inconsistent, it should be regarded as having a synthesis anomaly. It can be seen from this that the source code is normal but there is a synthesis anomaly after synthesis, which specifically refers to the state of the target Chisel source code file being that the source code is correct, but the function is incorrect, wherein the function is incorrect, specifically refers to the function of the current logic circuit being inconsistent with the expected circuit function.

[0029] In specific implementation, the logic circuit refers to the use of computer-aided logic synthesis tools to automatically convert the high-level description of the source code file into the corresponding logic gate circuit, that is, using the tool to convert a circuit with complete functions; the waveform file shows the high and low level changes, which is used to understand the timing logic of the signal. For a certain target Chisel source code file, the existing technology can be used to generate the corresponding logic circuit and waveform file, and the relationship between the logic circuit and the code logic and waveform file can be determined, that is, the way and means to judge whether there is a synthesis anomaly after synthesis can be consistent with the existing technology, such as through the data, handshake and other signals in the communication process (here the high and low levels of the signal can be displayed as 1, 0) to judge whether it is consistent with the expected result. If it is inconsistent with the expected result, it is an abnormality, otherwise, it is non-abnormal.

[0030] From the above description, it can be seen that for the target Chisel source code file, before performing channel anomaly detection, source code syntax checking and post-synthesis anomaly judgment should be performed. It should be noted that the main principle of generating synthesizable Verilog code from Chisel source code files is to call the dedicated chisel3 sacla library, and the entry point of the Scala program is the main function. Therefore, the program that generates Verilog code needs to instantiate the module to be compiled in the main function, and then run this main function. Instantiating the module to be compiled requires a special method call, which mainly uses the singleton object Driver in the library, which contains a method execute and accepts two parameters for calling.

[0031] Based on the above-mentioned principle description of generating synthesizable Verilog code from Chisel source code files, those skilled in the art can conclude that: if there are incorrect calls or incorrect parameter settings in the Chisel source code files, Verilog code cannot be generated in most cases. If Verilog code is generated, serious warnings will appear. However, if these warnings are ignored and the code functions are directly verified, the abnormal phenomenon of correct source code but incorrect functions will be obtained (this phenomenon may also occur in some other scenarios). Therefore, it is extremely important to perform source code syntax checking on Chisel source code files.

[0032] In one embodiment of the present invention, when performing source code syntax detection on a target Chisel source code file, the source code syntax detection state also includes a source code normal function result consistency, wherein, When the source code syntax detection status is consistent with the normal function result of the source code, the target Chisel source code file is checked using the tool flow detection method. When the tool flow detection method is executed, the syntax usage anomalies in the target Chisel source code file are checked, where: The tool flow detection method comprises an sbt compiler checking step, a Treadle interpreter checking step and a waveform viewer checking step which are performed in sequence, wherein: When executing the sbt compiler check step, it is used to check the consistency of the library files, sbt compiler and / or compilation environment version used by the target Chisel source code file. When the sbt compiler check step passes, the Treadle interpreter check step is executed; When executing the Treadle interpreter check step, it is used to check the fir format file to the waveform file generated during the compilation process of the target Chisel source code file. After the Treadle interpreter check step is passed, the waveform viewer check is executed; Used for waveform viewer check when performing waveform viewer check.

[0033] Specifically, when the source code syntax detection status is that the source code is normal and the functional results are consistent, the general tool flow detection method can be used for anomaly detection. Figure 2 An embodiment of the tool flow detection method is shown in FIG. 8 . As can be seen from the figure, the tool flow detection method mainly includes an sbt compiler check step, a Treadle interpreter check step, and a waveform viewer check step.

[0034] It should be noted that the consistency of functional results means that the source code function is consistent with the expected functional results. Specifically, for the source code of the communication function, a certain communication signal can be obtained (regardless of whether it is correct or not); for the source code of the calculation function, a certain calculation result can be given (regardless of whether it is correct or not). When performing source code syntax detection on the target Chisel source code file, the main purpose is to check whether the syntax of the target Chisel source code file and the version of the compilation tool are correct. If the target Chisel source code file has related errors during the compilation process, it can be detected through the tool flow detection method. It can be seen that the consistency of functional results generally refers to the consistency of the expected reply function (with the source code type), and does not strictly require complete result consistency.

[0035] The sbt compiler checks mainly for Figure 1The process from scala file to fir intermediate file shown in the figure is that Scala's sbt compiler generates Java class file *.class based on Chisel and Scala library, that is, bytecode file. Chisel driver executes this bytecode file to generate FIRRTL (Flexible Intermediate Representation for RTL, i.e., RTL variable intermediate representation) file *.fir. The sbt compiler check is mainly performed by compiler and other tools, and the main check is the version consistency of *.lib library file, sbt compiler and compilation environment. During the detection process, if there is inconsistency in the version of sbt compiler and / or compilation environment, log information can be output. Treadle interpreter detection mainly targets the process from *.fir intermediate file to *.vcd. With Chisel tester, it can be used to debug and test Chisel source code files, and the test results can be obtained based on the output assertion information. The Treadle interpreter can also generate a waveform file, namely Hello.vcd, which can be viewed with a waveform viewer, such as GTKWare or Modelsim. When viewed with a waveform viewer, it can be determined whether the final results are completely consistent, and the source of the channel error can be traced through the waveform.

[0036] Specifically, Treadle interpreter is a prior art. Treadle interpreter is a FIRRTL interpreter used for simulating circuits. Treadle interpreter and Chisel Tester can be used together for debugging and testing Chisel source code files. Specifically, when using Treadle interpreter for checking, there are multiple forms of checking. You can choose to directly output waveform results, or you can choose to only output log information. The specific selection can be based on needs, and will not be listed here one by one.

[0037] In specific implementation, the target Chisel source code file should also include a bus protocol, which can be designed and formed in the Chisel environment using existing commonly used technical means. The bus protocol in the target Chisel source code file can be one or more, which is specifically related to the logic circuit function formed based on the Chisel source code file. When a bus protocol exists in the target Chisel source code file, there will be synthesis anomalies after synthesis, which may include channel anomalies of the bus protocol, wherein, when the channel anomaly is a signal setting anomaly, the channel anomaly includes a bit width anomaly and / or a connection anomaly.

[0038] Figure 1A flow chart of an embodiment of the present invention for performing channel anomaly detection is shown in the figure. In the figure, when performing channel anomaly detection, it is necessary to first track and mark the compilation behavior of the target Chisel source code file, wherein the compilation behavior of the target Chisel source code file generally refers to the compilation behavior of compiling the target Chisel source code file into a fir format file. At this time, one or more channel mark Chisel source paths can be obtained. The following is a specific description of the method of obtaining the channel mark Chisel source path related to the channel anomaly after tracking and marking.

[0039] In one embodiment of the present invention, when generating a channel label Chisel source path, it includes: Compile the target Chisel source code file to obtain the target fir format file generated after compiling the target Chisel source code file; Based on the synthesis anomaly found after synthesis, the Chisel source path related to the synthesis anomaly is marked in the target fir format file to generate a channel marked Chisel source path after marking.

[0040] Specifically, the target Chisel source code file is generally a Scala format file, such as Figure 3 The Hello.scala in the file is a Chisel source code file. The target Chisel source code file can be compiled in a manner commonly used in the art to generate a target fir format file after compilation. The target fir format file is a fir format file. Figure 3 Hello.fir is the target fir format file. Figure 3 The Hello in the file is the file name. Figure 3 In the figure, the rectangular box refers to the compilation environment or software tools, such as scalac, Chisel JVM, Chisel Tester JVM, FIRRTL JVM and other JVMs (Java VirtualMachine). The cylindrical box refers to the library file, such as chisel3.lib and scala.lib, which are library files used during compilation. The flat box on the top and the wavy box on the bottom refer to the specific file name, which is named with Hello. + various suffixes indicating the file type. The arrows refer to various interactive relationships. Figure 3 The process of processing Chisel source code files to generate bit stream files is consistent with the existing technology. For details, please refer to Figure 3 As well as the above description, no further repetition is given here.

[0041] As can be seen from the above description, after synthesizing the target Chisel source code file, a logic circuit can be generated, and based on the logic circuit generated after synthesis, a synthesis anomaly can be found. Therefore, when performing channel anomaly detection, the situation of the synthesis anomaly can be determined in advance. Thereafter, based on the determined channel anomaly, the Chisel source path related to the synthesis anomaly can be marked in the target fir format file, so that the channel marking Chisel source path can be generated after marking. It should be noted that the process of marking and generating the channel marking Chisel source path, i.e., corresponding to Figure 2 The fir source path comparison in Figure 3 Backward tracing from the target Chisel source file to the target fir format file.

[0042] It should be noted that the code logic of the fir format file is completely consistent with the code logic of the target Chisel source code file. The fir format file includes a large number of intermediate variable declarations, and the corresponding intermediate variable declarations are annotated with the corresponding Chisel source paths. The Chisel source path is the Chisel module in the target Chisel source code file. Therefore, for the determined channel anomaly, the Chisel source path related to the channel anomaly can be determined from the intermediate variable declaration, and the channel-marked Chisel source path can be generated after tracking and marking; specifically, when tracking the channel anomaly, the source and operation process of the abnormal signal of the channel anomaly can be tracked, thereby issuing the Chisel source path related to the channel anomaly. Thereafter, the Chisel source path corresponding to the channel anomaly is marked in the existing commonly used method. The abnormality tracking and the marking method after tracking can be consistent with the existing technology, such as marking by annotation and the like. The marking method can be selected according to needs, and no examples are given here.

[0043] Depend on Figure 1 It can be seen that after generating the channel mark Chisel source path, it is necessary to perform integrated path confirmation and marking on the compilation process of the communication abnormality signal to obtain the corresponding channel detection mark path after marking. Specifically, the steps of generating the channel detection mark path are as follows: Figure 2 The integrated path confirmation step in corresponds to the integrated path confirmation step in. The following specifically describes the method and process of integrating the path confirmation and generating the channel detection mark path.

[0044] In one embodiment of the present invention, when generating a channel detection mark path, the process includes: Based on the channel anomaly in the comprehensive anomaly, determining the target bus protocol corresponding to the channel anomaly in the target Chisel source code file; In the target Chisel source code file, an integrated path corresponding to each channel tag Chisel source path and the target bus protocol is determined, and the determined integrated path is marked to generate a channel detection tag path after marking.

[0045] From the above description, it can be seen that there are one or more bus protocols in the target Chisel source code file, and the target bus protocol is a protocol in the target Chisel source code file, that is, the target protocol file is the bus protocol where the channel abnormality may occur. Since the comprehensive abnormality situation can be determined in advance, the corresponding bus protocol can be determined according to the determined comprehensive abnormality situation in a manner commonly used in the technical field, thereby determining the target bus protocol in the target Chisel source code file.

[0046] After determining the target protocol file and the channel-labeled Chisel source path, the integrated path corresponding to each channel-labeled Chisel source path and the target bus protocol can be determined. At this time, the path of the channel-labeled Chisel source path in the target bus protocol or the path of engineering integration can be determined. In specific implementation, when generating a channel detection label path, a feasible way is to mark all the paths of the channel-labeled Chisel source path in the target bus protocol or the paths of engineering integration. It should be noted that engineering integration generally refers to a relationship tree between similar files, which is used to determine the functional interconnection relationship between source codes so as to reflect the relationship of mutual influence between source codes. The situation of engineering integration is consistent with the existing one. Therefore, the technical means commonly used in this technical field can be used to achieve full marking of the paths of engineering integration.

[0047] It should be noted that after obtaining the channel detection mark path, an abnormal signal source analysis may be performed based on the channel detection mark path to generate abnormal signal source mark information; specifically, in one embodiment of the present invention, when generating the abnormal signal source mark information, it includes: In the target Chisel source file, add a Chisel probe for each channel detection tag path; A probe driving signal is loaded to the Chisel probe, and the path output signal under the probe driving signal is captured. When the captured path output signal is inconsistent with the probe driving signal, the channel detection marking path is marked with an abnormal signal source to generate abnormal signal source marking information after the abnormal signal source is marked.

[0048] Specifically, when the abnormal signal source marking information is generated by adding Chisel probes, that is, Figure 2In the target Chisel source code file, Chisel probes can be added in a manner commonly used in the art, wherein the process of adding Chisel probes is to insert the code for capturing signals, and use the added codes to capture and detect the operations of these signals; generally, after adding the Chisel probe, a drive signal different from the original drive signal needs to be loaded to the channel detection tag path through the Chisel probe, and the added drive signal is the probe drive signal, and thereafter, the output of the current probe drive signal is captured to obtain the path output signal.

[0049] In specific implementation, the path output signal is inconsistent with the probe drive signal, specifically, the path output signal is inconsistent with the expected output driven by the probe drive signal, and the path output signal can be captured by using existing commonly used methods, such as using the REG type and D flip-flop delay that can be detected by the synthesis tool to achieve the capture signal, so as to capture the path output signal. Specifically, commonly used synthesis tools include Synopsys' Design Compiler, Cadence's RTL Complier, Magma's RTL Blaster, etc. The type of synthesis tool can be selected according to needs.

[0050] It is understandable that the way of capturing path output signals using synthesis tools should be related to the synthesis tools and Chisel environment used. For example, in a waveform file, you can generally add a new REG to save the suspicious signal at a certain point in time to regenerate a new waveform file, and observe the path output signal and the probe drive signal in the generated waveform file; if the synthesis tool uses Vivado, you can add ILA's IP to the compiled Verilog (you need to know the corresponding signal relationship between the Chisel source code and the Verilog file) to achieve the observation of the path output signal and the probe drive signal; for example, the result data signal and the long handshake signal can be viewed with any tool that views the specific level.

[0051] It should be noted that the logic circuit synthesized by the synthesis tool is optimized and closer to the real logic circuit. By using these observable Chisel probes to mark the possible sources of abnormal signals and uniformly marking the corresponding channel marker Chisel source paths on each channel detection marker path, the process of abnormal signal generation and the communication link can be marked. It is understandable that the logic circuit synthesized by the synthesis tool is generally very close to the final logic circuit, but there will be slight differences, such as process differences with the real tape-out. Specifically, unified marking refers to recording the source of abnormal signals or using a tool to record them uniformly (with annotations or other recording methods), and then connecting these unified records into an erroneous communication link according to the results, thereby generating abnormal signal source marking information.

[0052] Depend on Figure 1 It can be seen that after obtaining the abnormal signal source marking information, the above abnormal signal source marking information can be detected and processed using a comprehensive tool. In one embodiment of the present invention, when the abnormal signal source marking information is detected and processed using a comprehensive tool, it includes: Using a synthesis tool to convert the channel marker Chisel source path where the abnormal signal source marker information is located, so as to convert and generate the corresponding gate-level channel Chisel source path; In the gate-level channel Chisel source path generated by the conversion, the probe marking signal is compared with the marking original signal corresponding to the probe marking signal, wherein when the probe marking signal is consistent with the marking original signal, the abnormal state of the probe marking signal is non-abnormal, otherwise, the abnormal state of the probe marking signal is abnormal.

[0053] Specifically, the synthesis tool can adopt the existing commonly used form, such as the synthesis tool can be a vivado tool, a synopsys tool or a Cadence tool. The synthesis tool can automatically convert the modules described at the behavioral level into gate-level models through the logic netlist, and the gate-level channel Chisel source path can be obtained. At this time, translation, logic optimization and gate-level mapping are realized, and the generated modules can correspond one by one to the basic elements of a certain process. Therefore, it can better reflect the final realized logic circuit than the target fir format file and verilog file.

[0054] After the conversion to form a gate-level channel Chisel source path, the probe marker signal can be renamed in the synthesis tool, that is, in the gate-level channel Chisel source path, the signal name of the probe marker signal is different from the signal name of the original marker signal; therefore, the probe marker signal can be better compared with the original marker signal corresponding to the probe marker signal, and the channel comparison method includes signal value and / or signal bit width. During the comparison, it can be observed in the results in the synthesis tool that when the probe marker signal is consistent with the original marker signal, the abnormal state of the probe marker signal is non-abnormal, otherwise, the abnormal state of the probe marker signal is abnormal; wherein, the probe marker signal is consistent with the original marker signal, specifically, the signal value and signal bit width are consistent.

[0055] In one embodiment of the present invention, when the abnormal state of the probe marking signal is non-abnormal, the position of the Chisel probe is adjusted, and the abnormal signal source marking information is regenerated; The regenerated abnormal signal source marker information is detected and processed by using a comprehensive tool to determine the abnormal state of the probe marker signal in the currently regenerated abnormal signal source marker information.

[0056] It can be understood that when the abnormal state of the probe marking signal is non-abnormal, it indicates that the current probe marking signal is not an abnormal signal, and it is necessary to adjust the position of the Chisel probe and regenerate the abnormal signal source marking information using the above-mentioned method. After that, the comprehensive tool is used for detection processing, such as Figure 2 As shown in the figure, it can be seen that in the specific implementation, there is a cycle of comprehensive tool detection and adding Chisel probe steps, and the condition for the end of the cycle is that the abnormal state of the probe marker signal is found to be abnormal, or the abnormal state of all probe marker signals can be non-abnormal after adjusting the Chisel probe.

[0057] The channel anomaly detection method of the present invention is described in detail below in conjunction with specific embodiments. Specifically; For the Chisel source code file with the axi bus protocol, the bit width of two signals changes during the synthesis process, and both the fir format file and the verilog code are normal. In addition, since the axi bus protocol can be used normally in other modules, the general tool flow detection method cannot detect the bit width change of the abnormal signal (the bit width change will be exchanged after passing through different modules, such as a5 bits and b12 bits in this module, and a12 bits and b7 bits in the next module). Among them, the axi bus protocol can be used normally in other modules, specifically referring to the function of normal use after integration and interconnection with the source code of other modules.

[0058] use Figure 2And when using the above detection method, after adding the Chisel probe signal, it is found that with the help of the synthesis tool, another signal processed across the clock domain is also similarly changed. The reason for the communication anomaly is finally detected to be inconsistent cross-clock processing requirements in the Chisel source code file. Specifically, another signal processed across the clock domain refers to a part of the signal from the axi bus in the Chisel source code file that needs to be processed across another clock domain. In addition, the channel anomaly detection method of the present invention can be found to be deliberately adding corresponding probe marker signals under the detection of tilelink bus protocol and wishbone protocol, and the validity of the probe marker signal can be determined.

[0059] From the above description, a channel anomaly detection system suitable for a Chisel environment can be obtained, specifically, comprising a channel anomaly detection terminal, wherein, for any pair of target Chisel source code files whose source code syntax check status is that the source code is normal but the communication is abnormal, the channel anomaly detection terminal uses the above-mentioned channel anomaly detection to perform channel anomaly detection.

[0060] Specifically, the channel anomaly detection terminal can be an existing commonly used computer device. The Chisel environment should be installed in the channel anomaly detection terminal, and the above method is used to detect channel anomalies. The method and process of channel anomaly detection can refer to the above description and will not be repeated here.

Claims

1. A channel anomaly detection method suitable for Chisel environment, characterized in that: Used to perform channel anomaly detection on a target Chisel source code file whose source code syntax check status is that the source code is normal but has a synthesis anomaly after synthesis, wherein the target Chisel source code file includes a bus protocol designed in a Chisel environment, and the synthesis anomaly after synthesis includes at least a channel anomaly existing in the bus protocol; Channel anomaly detection includes: Acquire the target Chisel source code file, and based on the synthesis anomaly found after synthesis, trace and mark the compilation behavior of the target Chisel source code file, so as to obtain a channel mark Chisel source path related to the channel anomaly after tracing and marking; For the channel tag Chisel source path generated above, the compilation process of the communication abnormality signal is integrated with path confirmation and tagging to obtain a corresponding channel detection tag path after tagging, wherein the channel detection tag path includes the communication path included in the target bus protocol, and the target bus protocol is the bus protocol where the channel abnormality occurs; Based on the above-mentioned channel detection mark path, abnormal signal source analysis and tracking are performed to generate abnormal signal source mark information after analysis and tracking, wherein the abnormal signal source mark information includes a probe mark signal and a communication link corresponding to the probe mark signal; The above-mentioned abnormal signal source marking information is detected and processed using a comprehensive tool, wherein, when detecting and processing the abnormal signal source marking information, at least a channel comparison is performed between the probe marking signal and the marked original signal corresponding to the probe marking signal, and the abnormal state of the probe marking signal is determined based on the comparison result, and the abnormal state of the probe marking signal includes abnormal or non-abnormal.

2. The channel anomaly detection method suitable for Chisel environment according to claim 1, characterized in that: When tracking and marking the compilation behavior of the target Chisel source code file based on the synthesis anomalies found after synthesis, it includes: Compile the target Chisel source code file to generate the target fir format file after compilation; Based on the synthesis anomaly found after the synthesis, the Chisel source path related to the synthesis anomaly is marked in the target fir format file to generate a channel marked Chisel source path after marking.

3. The channel anomaly detection method suitable for Chisel environment according to claim 1, characterized in that: The generated channel marks the Chisel source path, and the compilation process of the communication abnormal signal is integrated to confirm and mark the path, including: Based on the channel anomaly in the comprehensive anomaly, determining the target bus protocol corresponding to the channel anomaly in the target Chisel source code file; In the target Chisel source code file, an integrated path corresponding to each channel tag Chisel source path and the target bus protocol is determined, and the determined integrated path is marked to generate a channel detection tag path after marking.

4. The channel anomaly detection method suitable for Chisel environment according to claim 1, characterized in that: Based on the channel detection mark path, the abnormal signal source analysis and tracking includes: In the target Chisel source file, add a Chisel probe for each channel detection tag path; A probe driving signal is loaded to the Chisel probe, and the path output signal under the probe driving signal is captured. When the captured path output signal is inconsistent with the probe driving signal, the channel detection marking path is marked with an abnormal signal source to generate abnormal signal source marking information after the abnormal signal source is marked.

5. The channel anomaly detection method suitable for Chisel environment according to claim 4 is characterized in that: When the abnormal state of the probe marking signal is non-abnormal, the position of the Chisel probe is adjusted, and the abnormal signal source marking information is regenerated; The regenerated abnormal signal source marker information is detected and processed by using a comprehensive tool to determine the abnormal state of the probe marker signal in the currently regenerated abnormal signal source marker information.

6. The channel anomaly detection method suitable for Chisel environment according to any one of claims 1 to 5, characterized in that: When using comprehensive tools to detect and process abnormal signal source marking information, it includes: Using a synthesis tool to convert the channel marker Chisel source path where the abnormal signal source marker information is located, so as to convert and generate the corresponding gate-level channel Chisel source path; In the gate-level channel Chisel source path generated by the conversion, the probe marking signal is compared with the marking original signal corresponding to the probe marking signal, wherein when the probe marking signal is consistent with the marking original signal, the abnormal state of the probe marking signal is non-abnormal, otherwise, the abnormal state of the probe marking signal is abnormal.

7. The channel anomaly detection method suitable for Chisel environment according to claim 6, characterized in that: The synthesis tool includes a vivado tool, a synopsys tool or a Cadence tool; In the Chisel source path of the gate-level channel, the signal name of the probe-marked signal is different from the signal name of the original signal; When performing channel comparison between the probe marking signal and the marking original signal, the channel comparison method includes signal value and / or signal bit width.

8. The channel anomaly detection method suitable for Chisel environment according to any one of claims 1 to 5, characterized in that: When performing source code syntax detection on the target Chisel source code file, the source code syntax detection state also includes the source code normal function result consistency, wherein, When the source code syntax detection status is consistent with the normal function result of the source code, the target Chisel source code file is checked using the tool flow detection method. When the tool flow detection method is executed, the syntax usage anomalies in the target Chisel source code file are checked, where: The tool flow detection method includes an sbt compiler check step, a Treadle interpreter check step and a waveform viewer check performed in sequence, wherein: When executing the sbt compiler check step, it is used to check the consistency of the library files, sbt compiler and / or compilation environment version used by the target Chisel source code file. When the sbt compiler check step passes, the Treadle interpreter check step is executed; When executing the Treadle interpreter check step, it is used to check the fir format file to the waveform file generated during the compilation process of the target Chisel source code file. After the Treadle interpreter check step is passed, the waveform viewer check is executed; Used for waveform viewer check when performing waveform viewer check.

9. The channel anomaly detection method suitable for Chisel environment according to any one of claims 1 to 5, characterized in that: When the synthesis anomaly exists after the synthesis of the target Chisel source code file, it at least includes that the synthesized logic circuit generated based on the target Chisel source code file is inconsistent with the logical function expected by the target Chisel source code file, and / or the waveform file obtained by simulating the synthesized logic circuit is inconsistent with the waveform file obtained by simulating the target Chisel source code file, wherein, When the channel abnormality is a signal setting abnormality, the channel abnormality includes a bit width abnormality and / or a connection abnormality.

10. A channel anomaly detection system suitable for Chisel environment, characterized in that: It includes a channel anomaly detection terminal, wherein for any pair of target Chisel source code files whose source code syntax check status is that the source code is normal but the communication is abnormal, the channel anomaly detection terminal uses the channel anomaly detection described in any one of claims 1 to 9 to perform channel anomaly detection.

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