Display device

Abstract

A display device according to an embodiment includes: a substrate; and a transistor including an oxide semiconductor layer as an active layer and a gate electrode disposed on the oxide semiconductor layer to overlap the oxide semiconductor layer. The oxide semiconductor layer comprises a channel region, a source region arranged on the first side of the channel region and a drain region arranged on the second side of the channel region, and the source region comprises a first source region arranged adjacent to the channel region and a second source region arranged adjacent to the first source region; the drain region includes a first drain region disposed adjacent to the channel region and a second drain region disposed adjacent to the first drain region. Each of the first source region and the first drain region includes a first impurity ion, and each of the second source region and the second drain region includes a second impurity ion different from the first impurity ion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0096132 filed in the Korean Intellectual Property Office on July 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] The display device is a device that displays a picture, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and the like.

[0005] Such display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, electronic books, portable game consoles, and various terminals.

[0006] The display device may include a plurality of pixels arranged in row and column directions.

[0007] Various elements such as transistors and capacitors and various wirings capable of supplying signals to these elements may be located in each pixel.

[0008] Various elements such as transistors and capacitors are controlled by signals applied at respective times to display images, and the display device is controlled to emit light of a specific brightness to display images. Summary of the invention

[0009] The embodiment is directed to providing an oxide semiconductor layer including at least two regions having different carrier concentrations. The embodiment is directed to providing a stable threshold voltage value through the oxide semiconductor layer.

[0010] Embodiments are directed to improving the resolution of a display device by providing an oxide semiconductor layer having a short channel length.

[0011] A display device according to an embodiment may include: a substrate; and a transistor, the transistor including an oxide semiconductor layer as an active layer and a gate electrode disposed on the oxide semiconductor layer to overlap with the oxide semiconductor layer. The oxide semiconductor layer may include a channel region and a source region disposed on a first side of the channel region and a drain region disposed on a second side of the channel region. The source region may include a first source region disposed adjacent to the channel region and a second source region disposed adjacent to the first source region, and the drain region may include a first drain region disposed adjacent to the channel region and a second drain region disposed adjacent to the first drain region. Each of the first source region and the first drain region may include a first impurity ion, and each of the second source region and the second drain region may include a second impurity ion different from the first impurity ion.

[0012] The second source region and the second drain region may further include first impurity ions.

[0013] The atomic mass of the second impurity ions may be greater than the atomic mass of the first impurity ions.

[0014] The first impurity ions may be p-type impurity ions, and the second impurity ions may be n-type impurity ions.

[0015] The first impurity ions may include B ions, and the second impurity ions may include at least one of As ions, Sb ions, Si ions, Ge ions, and In ions.

[0016] The doping concentrations of the first source region and the first drain region are lower than the doping concentrations of the second source region and the second drain region.

[0017] The doping concentration of the first impurity ion may be 1×10 12 Ions / cm 2 Up to 1×10 13 Ions / cm 2 .

[0018] The doping concentration of the second impurity ion can be 1×10 12 Ions / cm 2 Up to 1×10 14 Ions / cm 2 .

[0019] Each of the first source region and the first drain region may include B ions.

[0020] Each of the second source region and the second drain region may include B ions as well as at least one of As ions, Sb ions, Si ions, Ge ions, and In ions.

[0021] A method for manufacturing a display device according to an embodiment may include the following steps: forming an oxide semiconductor layer on a substrate; forming a gate insulating layer on the oxide semiconductor layer; forming a gate electrode of an oxide transistor on the gate insulating layer; doping the oxide semiconductor layer with first impurity ions; and doping the oxide semiconductor layer with second impurity ions. The first impurity ions include p-type impurity ions, and the second impurity ions include impurity ions of a different type from the first impurity ions. The second impurity ions may include n-type impurity ions.

[0022] The method of manufacturing a display device may further include: before doping the second impurity ions in the oxide semiconductor layer, forming a mask covering a side surface of the gate electrode. The mask may be a photosensitive pattern.

[0023] The method of manufacturing a display device may further include removing the mask after doping the second impurity ions in the oxide semiconductor layer.

[0024] The first impurity ions may be B ions, and the second impurity ions may be at least one of As ions, Sb ions, Si ions, Ge ions, and In ions.

[0025] The method for manufacturing a display device may further include: before doping the oxide semiconductor layer with the first impurity ions and before doping the oxide semiconductor with the second impurity ions, forming a mask covering the side surface of the gate electrode. The method for manufacturing a display device may further include: before doping the oxide semiconductor layer with the first impurity ions, removing the mask.

[0026] The doping concentration of the first impurity ion may be 1×10 12 Ions / cm 2 Up to 1×10 13 Ions / cm 2 .

[0027] The doping concentration of the second impurity ion can be 1×10 12 Ions / cm 2 Up to 1×10 14 Ions / cm 2 .

[0028] According to an embodiment, an oxide semiconductor layer including at least two regions having different carrier concentrations may be provided.

[0029] A stable threshold voltage value can be provided by the oxide semiconductor layer.

[0030] The resolution of a display device can be improved by providing an oxide semiconductor layer having a short channel length. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic perspective view illustrating the display device according to the embodiment when a user is operating the display device.

[0032] Figure 2 is an exploded perspective view of a display device according to an embodiment.

[0033] Figure 3 is a circuit diagram of one pixel included in the display device according to the embodiment.

[0034] Figure 4 is a diagram illustrating a cross-sectional structure of a display device according to an embodiment.

[0035] Figure 5 is a diagram illustrating a cross-sectional structure of a second semiconductor layer according to an embodiment.

[0036] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a cross-sectional view of a process of manufacturing a second semiconductor layer according to an embodiment.

[0037] Fig.10 , Fig.11 , Fig.12 and Fig.13 is a cross-sectional view of a manufacturing process of a second semiconductor layer according to another embodiment.

[0038] Fig.14 is a graph showing threshold voltage values ​​of transistors including an oxide semiconductor according to an embodiment of the inventive concept and a comparative example. DETAILED DESCRIPTION

[0039] Hereinafter, various embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the inventive concept.

[0040] The inventive concept may be embodied in many different forms and is not limited to the embodiments set forth herein.

[0041] In order to clearly describe the present inventive concept, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

[0042] In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, the inventive concept is not necessarily limited to the shown contents.

[0043] In the drawings, the thickness is shown exaggerated to clearly show various layers and regions.

[0044] Also, in the drawings, the thicknesses of some layers and regions are exaggerated for convenience of explanation.

[0045] In addition, when a part such as a layer, film, region, or plate is referred to as being “on” or “on” another part, this includes not only the case where it is “directly on” the other part but also the case where the other part is in between.

[0046] In contrast, when a part is referred to as being “directly on” another part, it means that there are no other parts therebetween.

[0047] In addition, “above” or “on” a reference portion means being located above or below the reference portion, and does not necessarily mean being located “above” or “on” the reference portion in an opposite direction to gravity.

[0048] In addition, throughout the specification, when a certain component is referred to as “comprising”, unless otherwise specified, it means that it can further include other components without excluding the other components.

[0049] Furthermore, throughout the specification, when a “planar image” is mentioned, this means when the target portion is observed from above, and when a “cross-sectional image” is mentioned, this means when a cross section of the target portion cut vertically is observed from the side.

[0050] In the following, reference will be made to Figure 1 and Figure 2 A schematic structure of a display device is described.

[0051] Figure 1 is a schematic perspective view illustrating the display device according to the embodiment when a user is operating the display device, and Figure 2 is an exploded perspective view of a display device according to an embodiment.

[0052] refer to Figure 1 The display device 1000 according to the embodiment is a device that displays a video or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet PC, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra mobile PC (UMPC), as well as a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device.

[0053] In addition, the display device 1000 according to the embodiment can be used in wearable devices such as a smart watch, a watch phone, a glasses type display, and a head mounted display (HMD).

[0054] In addition, the display device 1000 according to the embodiment includes a central information display (CID) arranged on a dashboard of a vehicle, a center console or a dashboard of a vehicle and an interior mirror display (interior mirror display) replacing a side mirror of the vehicle or an entertainment device for the rear seats of a car, and can be used as a display placed on the backrest of a front seat.

[0055] For ease of explanation, Figure 1 The display device 1000 is shown when used as a smartphone.

[0056] The display device 1000 may display an image in the third direction DR3 on a display surface parallel to each of the first direction DR1 and the second direction DR2 .

[0057] The display surface on which an image is displayed may correspond to the front surface of the display device 1000 , and may correspond to the front surface of the cover window WU.

[0058] The images may include still images as well as dynamic images.

[0059] In this embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each member are defined based on the direction in which an image is displayed.

[0060] The front surface and the rear surface are opposite to each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3.

[0061] A distance between the front surface and the rear surface in the third direction DR3 may correspond to a thickness of the display panel in the third direction DR3.

[0062] The display device 1000 according to the embodiment may detect a user's input applied from the outside (refer to Figure 1 hand in the middle).

[0063] The user's input may include various types of external inputs, such as a part of the user's body, light, heat, or pressure.

[0064] In one embodiment, the user's input is shown as being applied by the user's hand in the foreground.

[0065] However, the inventive concept is not limited thereto.

[0066] User input can be provided in a variety of forms.

[0067] In addition, the display apparatus 1000 may detect a user's input applied to a side surface or a rear surface of the display apparatus 1000 according to the structure of the display apparatus 1000 .

[0068] refer to Figure 1 and Figure 2 , the display device 1000 may include a cover window WU, a housing HM, a display panel DP, and an optical element ES.

[0069] In one embodiment, the cover window WU and the housing HM may be combined to form the exterior of the display device 1000 .

[0070] The cover window WU may include an insulating panel.

[0071] For example, the cover window WU may be made of glass, plastic, or a combination thereof.

[0072] The front surface of the cover window WU may define the front surface of the display device 1000 .

[0073] The transmission area TA may be an optically transparent area.

[0074] For example, the transmission area TA may have a visible light transmittance of about 90% or more.

[0075] The blocking area BA may define the shape of the transmission area TA.

[0076] The blocking area BA may be disposed adjacent to the transmission area TA, and may surround the transmission area TA.

[0077] The blocking area BA may have relatively low light transmittance compared to the transmissive area TA.

[0078] The blocking area BA may include an opaque material that blocks light.

[0079] The barrier area BA may have a predetermined color.

[0080] The blocking area BA may be defined by a bezel layer provided separately from the transparent substrate defining the transmission area TA, or may be defined by an ink layer inserted into or colored in the transparent substrate.

[0081] The display panel DP may include a front surface including a display area DA and a non-display area PA.

[0082] The display area DA may be an area where pixels operate according to electrical signals to emit light.

[0083] The non-display area PA of the display panel DP may include a driving unit 50 .

[0084] In an embodiment, the display area DA may be a region including pixels and displaying an image, and may also be a region where a touch sensor is located above the pixels in the third direction DR3 to detect an external input.

[0085] The transmission area TA of the cover window WU may at least partially overlap the display area DA of the display panel DP.

[0086] For example, the transmission area TA may overlap the entire surface of the display area DA, or may overlap at least a portion of the display area DA.

[0087] Accordingly, the user may view an image through the transmissive area TA, or provide an external input based on the image.

[0088] However, the inventive concept is not limited thereto.

[0089] For example, within the display area DA, an area where an image is displayed and an area where an external input is sensed may be separated from each other.

[0090] The non-display area PA of the display panel DP may at least partially overlap the blocking area BA of the cover window WU.

[0091] The non-display area PA may be an area covered by the blocking area BA.

[0092] The non-display area PA is disposed adjacent to the display area DA, and may surround the display area DA.

[0093] An image is not displayed in the non-display area PA, and a driving circuit or a driving wiring for driving the display area DA may be disposed in the non-display area PA.

[0094] The non-display area PA may include a first peripheral area PA1 located outside the display area DA and a second peripheral area PA2 including the driving unit 50, the connection wiring, and the bending area.

[0095] exist Figure 2 In the embodiment of the present invention, the first peripheral area PA1 is located on three sides of the display area DA, and the second peripheral area PA2 is located on the other sides of the display area DA.

[0096] In one embodiment, the display panel DP may be assembled in a flat state in which the display area DA and the non-display area PA face the cover window WU.

[0097] However, the inventive concept is not limited thereto.

[0098] A portion of the non-display area PA of the display panel DP may be bent.

[0099] In this case, a portion of the non-display area PA faces the rear surface of the display device 1000, so that the blocking area BA visible on the front surface of the display device 1000 can be reduced. Figure 2 In the embodiment, the second peripheral area PA2 may be bent and located on the rear surface of the display area DA.

[0100] In addition, the display panel DP may include a component area EA including a first component area EA1 and a second component area EA2.

[0101] The first and second component areas EA1 and EA2 may be at least partially surrounded by the display area DA.

[0102] The first component area EA1 and the second component area EA2 are illustrated as being spaced apart from each other, but the configuration of the first component area EA1 and the second component area EA2 is not limited thereto and may be at least partially connected.

[0103] The first component area EA1 and the second component area EA2 may be areas under which components using infrared light, visible light, or sound are arranged.

[0104] In the display area DA, a plurality of light emitting diodes and a plurality of pixel circuit units (also referred to as pixel circuit parts) that generate and transmit a light emitting current (also referred to as a driving current) to each of the plurality of light emitting diodes are formed.

[0105] Here, one light emitting diode and one pixel circuit portion are referred to as a pixel PX.

[0106] In the display area DA, one pixel circuit unit and one light emitting diode are formed in a one-to-one arrangement.

[0107] The first component area EA1 may include a transmission portion through which light or / and sound may pass and a display portion including a plurality of pixels.

[0108] The transmissive portion is located between adjacent pixels and is composed of a layer through which light or / and sound can pass.

[0109] The transmissive portion may be located between adjacent pixels, and depending on the embodiment, a light-impermeable layer such as a light blocking member may overlap the first component area EA1.

[0110] The number of pixels per unit area (hereinafter, referred to as resolution) of pixels included in the display area DA (hereinafter, referred to as normal pixels) and pixels included in the first component area EA1 (hereinafter, referred to as first component pixels) may be the same.

[0111] The second component area EA2 includes an area made of a transparent layer to allow light to pass therethrough (hereinafter, referred to as a light-transmitting area). For example, a layer of a pixel defining layer and / or a light shielding member may include an opening in an area corresponding to a position corresponding to the second component area EA2 so as not to block light.

[0112] The number of pixels per unit area of ​​pixels included in the second component area EA2 (hereinafter, referred to as second component pixels) may be smaller than the number of pixels per unit area of ​​normal pixels included in the display area DA.

[0113] As a result, the resolution of the second component pixels may be lower than the resolution of the normal pixels.

[0114] The driving unit 50 may be installed in the second peripheral area PA2, and may be installed on the bending unit or located at one side or both sides of the bending unit.

[0115] The driving unit 50 may be provided in the form of a chip.

[0116] The driving unit 50 may be electrically connected to the display area DA to transmit an electrical signal to the display area DA.

[0117] For example, the driving unit 50 may provide a data signal to the pixels PX disposed in the display area DA.

[0118] Alternatively, the driving unit 50 may include a touch driving circuit and may be electrically connected to a touch sensor provided in the display area DA.

[0119] Meanwhile, the driving unit 50 may include various circuits other than the above-mentioned circuits, or may be designed to supply various electrical signals to the display area DA.

[0120] Meanwhile, the display device 1000 may have a pad portion located at an end of the second peripheral area PA2, and the display device 1000 may be electrically connected to a flexible printed circuit board (FPCB) including a driving chip through the pad portion.

[0121] Here, the driving chip included in the flexible printed circuit board may include various driving circuits for driving the display device 1000 or a connector for supplying power.

[0122] According to an embodiment, a rigid printed circuit board (PCB) may be used instead of a flexible printed circuit board.

[0123] The optical element ES may be disposed under the display panel DP.

[0124] The optical element ES may include a first optical element ES1 overlapping the first component area EA1 and a second optical element ES2 overlapping the second component area EA2.

[0125] The first optical element ES1 may be an electronic element using light or sound.

[0126] For example, the first optical element ES1 may be a sensor that receives and uses light, such as an infrared sensor, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, or a small lamp that outputs light. It may be a speaker that outputs sound, and the like.

[0127] In the case of an electronic component using light, light of various wavelength bands such as visible light, infrared light, and ultraviolet light can be used.

[0128] The second optical element ES2 may be at least one of a camera such as an infrared camera (IR camera), a dot projector, an infrared illuminator (IR illuminator), and a time-of-flight sensor (ToF sensor).

[0129] The housing HM may be coupled to the cover window WU.

[0130] A cover window WU may be provided on the front surface of the housing HM.

[0131] The housing HM may be coupled to the cover window WU to provide a predetermined receiving space.

[0132] The display panel DP and the optical element ES may be accommodated in a predetermined accommodation space provided between the housing HM and the cover window WU.

[0133] The housing HM may include a material having relatively high rigidity.

[0134] For example, the housing HM may include a plurality of frames and / or plates made of glass, plastic, or metal, or a combination thereof.

[0135] The housing HM can stably protect the components of the display device 1000 accommodated in the internal space from external impacts.

[0136] Hereinafter, one pixel PX located in the display area DA will be described.

[0137] Figure 3 is a circuit diagram of one pixel included in the display device according to the embodiment.

[0138] One pixel according to the embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to various wirings 127, 128, 151, 152, 153, 155, 171, 172, and 741, a holding capacitor Cst, a boosting capacitor C boost And light emitting diodes LED.

[0139] Here, the transistor and the capacitor except the light emitting diode LED constitute a pixel circuit unit.

[0140] Depending on the embodiment, the boost capacitor C may be omitted. boost .

[0141] Meanwhile, depending on the embodiment, an additional capacitor or an additional boosting capacitor may be formed.

[0142] A plurality of wirings 127 , 128 , 151 , 152 , 153 , 155 , 171 , 172 , and 741 are connected to one pixel PX.

[0143] The plurality of wirings include a first initialization voltage line 127 , a second initialization voltage line 128 , a first scan line 151 , a second scan line 152 , an initialization control line 153 , an emission control line 155 , a data line 171 , a driving voltage line 172 , and a common voltage line 741 .

[0144] The first scan line 151 is connected to a scan driver (not shown) to transmit a first scan signal GW to the second transistor T2 and the seventh transistor T7.

[0145] A voltage of a polarity opposite to that of a voltage applied to the first scan line 151 may be applied to the second scan line 152 simultaneously with a signal of the first scan line 151 .

[0146] For example, when a voltage of a negative polarity is applied to the first scan line 151 , a voltage of a positive polarity may be applied to the second scan line 152 .

[0147] The second scan line 152 transmits the second scan signal GC to the third transistor T3.

[0148] The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4.

[0149] The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6 .

[0150] The data line 171 is a wiring that transmits a data voltage DATA generated by a data driver (not shown), and accordingly, the size of a light emitting current delivered to the light emitting diode LED is changed so that the light emitting diode LED emits light according to the light emitting current.

[0151] The driving voltage line 172 applies a driving voltage ELVDD.

[0152] The first initialization voltage line 127 transmits a first initialization voltage VINT, and the second initialization voltage line 128 transmits a second initialization voltage VAINT.

[0153] The common voltage line 741 applies the common voltage ELVSS to the cathode of the light emitting diode LED.

[0154] In this embodiment, the voltage applied to the driving voltage line 172 , the first and second initialization voltage lines 127 and 128 , and the common voltage line 741 may be a constant voltage.

[0155] The driving transistor T1 (also referred to as a first transistor) is a p-type transistor, and has a silicon semiconductor (hereinafter, referred to as a polycrystalline semiconductor or a first semiconductor) as a semiconductor layer.

[0156] The transistor adjusts the amount of light emitting current output to the anode of the light emitting diode LED according to the level of the voltage of the gate electrode of the driving transistor T1 (ie, the voltage stored in the storage capacitor Cst).

[0157] Since the brightness of the light emitting diode LED is adjusted according to the size of the light emitting current output to the anode of the light emitting diode LED, the light emitting brightness of the light emitting diode LED can be adjusted according to the data voltage DATA applied to the pixel.

[0158] To this end, the first electrode of the driving transistor T1 receives the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5 .

[0159] In addition, the first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 to receive the data voltage DATA.

[0160] Meanwhile, the second electrode of the driving transistor T1 outputs a light emitting current through the light emitting diode LED, and is connected to the anode of the light emitting diode LED via the sixth transistor T6 (also referred to as an output control transistor).

[0161] In addition, the second electrode of the driving transistor T1 is connected to the third transistor T3 to transfer the data voltage DATA applied to the first electrode of the driving transistor T1 to the third transistor T3.

[0162] Meanwhile, the gate electrode of the driving transistor T1 is connected to one electrode (hereinafter, referred to as a second storage electrode) of the storage capacitor Cst.

[0163] The other electrode (hereinafter, referred to as a first storage electrode) of the storage capacitor Cst receives the driving voltage ELVDD.

[0164] Accordingly, the voltage of the gate electrode of the driving transistor T1 is changed according to the voltage stored in the storage capacitor Cst, and the light emitting current output from the driving transistor T1 is changed.

[0165] The storage capacitor Cst serves to keep the voltage of the gate electrode of the driving transistor T1 constant for one frame.

[0166] Meanwhile, the gate electrode of the driving transistor T1 may be connected to the third transistor T3 so that the data voltage DATA applied to the first electrode of the driving transistor T1 can be transmitted to the gate electrode of the driving transistor T1 through the third transistor T3 .

[0167] Meanwhile, the gate electrode of the driving transistor T1 may also be connected to the fourth transistor T4 to be initialized by receiving the first initialization voltage VINT.

[0168] The second transistor T2 is a p-type transistor, and has a silicon semiconductor as a semiconductor layer.

[0169] The second transistor T2 is a transistor that transmits the data voltage DATA to the first electrode of the driving transistor T1.

[0170] The gate electrode of the second transistor T2 is connected to the first scan line 151 and the boosting capacitor C boost An electrode (hereinafter, referred to as the lower boosting electrode).

[0171] Boost capacitor C boost The other electrode of is connected to the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0172] Meanwhile, a first electrode of the second transistor T2 is connected to the data line 171 , and a second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1 .

[0173] When the second transistor T2 is turned on in response to the negative voltage of the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1. The data voltage DATA is finally transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0174] The third transistor T3 is an n-type transistor, and has an oxide semiconductor (hereinafter, referred to as a second semiconductor) as a semiconductor layer.

[0175] The third transistor T3 electrically connects the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1 .

[0176] As a result, the data voltage DATA is compensated by the threshold voltage of the driving transistor T1 and is then stored in the storage capacitor Cst.

[0177] A gate electrode of the third transistor T3 is connected to the second scan line 152 , and a first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1 .

[0178] The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting capacitor Cst. boost The other electrode (hereinafter, referred to as the boosted voltage electrode) of the semiconductor device.

[0179] The third transistor T3 is turned on in response to a voltage of a positive polarity among the second scan signal GC transmitted through the second scan line 152 to electrically connect the gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1, and the voltage applied to the gate electrode of the driving transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst and stored in the storage capacitor Cst.

[0180] The voltage stored in the storage capacitor Cst is the voltage of the gate electrode of the driving transistor T1 when the driving transistor T1 is turned off, so that the threshold voltage Vth of the driving transistor T1 is stored in the compensation state (see Fig.14 ).

[0181] The fourth transistor T4 is an n-type transistor, and has an oxide semiconductor as a semiconductor layer.

[0182] The fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0183] A gate electrode of the fourth transistor T4 is connected to the initialization control line 153 , and a first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127 .

[0184] The second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting capacitor Cst. boost The rising voltage electrode.

[0185] The fourth transistor T4 is turned on in response to a voltage of a positive polarity among the initialization control signal GI transmitted through the initialization control line 153. The first initialization voltage VINT is applied to the gate electrode of the driving transistor T1, the second storage electrode of the storage capacitor Cst, and the boosting capacitor C boost The boosting electrode of the driving transistor T1 is initialized to initialize the gate electrode of the driving transistor T1, the second storage electrode of the storage capacitor Cst and the boosting capacitor C boost The rising voltage electrode.

[0186] The fifth transistor T5 and the sixth transistor T6 are p-type transistors and have a silicon semiconductor as a semiconductor layer.

[0187] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1 .

[0188] A gate electrode of the fifth transistor T5 is connected to the emission control line 155 , a first electrode of the fifth transistor T5 is connected to the driving voltage line 172 , and a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1 .

[0189] The sixth transistor T6 is used to transmit the light emitting current output from the driving transistor T1 to the light emitting diode LED.

[0190] A gate electrode of the sixth transistor T6 is connected to the emission control line 155 , a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1 , and a second electrode of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0191] The seventh transistor T7 is a p-type or n-type transistor and may have a silicon semiconductor or an oxide semiconductor as a semiconductor layer. Figure 3 In the embodiment of FIG. 5 , the seventh transistor T7 is a p-type transistor and includes a silicon semiconductor.

[0192] The seventh transistor T7 is used to initialize the anode of the light emitting diode LED.

[0193] A gate electrode of the seventh transistor T7 is connected to the first scan line 151 , a first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and a second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128 .

[0194] Here, the gate electrode of the seventh transistor T7 is connected to the first scan line 151 of the previous pixel PX instead of being connected to the same first scan line 151 as the gate electrode of the second transistor T2 belonging to the same pixel PX, but it can be connected to the same first scan line 151 as the gate electrode of the second transistor T2 of the previous pixel PX.

[0195] When a voltage of a negative polarity is applied to the first scan line 151, the seventh transistor T7 is turned on, and the second initialization voltage VAINT is applied to the anode of the light emitting diode LED to initialize it.

[0196] Meanwhile, the gate electrode of the seventh transistor T7 may be connected to a separate bypass control line through which the bypass signal GB is transmitted, and may be controlled by a wiring separate from the first scan line 151 .

[0197] In addition, depending on the embodiment, the second initialization voltage line 128 to which the second initialization voltage VAINT is applied may be the same as the first initialization voltage line 127 to which the first initialization voltage VINT is applied.

[0198] Although one pixel PX has been described as including seven transistors T1 to T7 and two capacitors (storage capacitor Cst and boosting capacitor Cst) boost ), but the present invention is not limited thereto. The boost capacitor C may be omitted. boost .

[0199] Furthermore, depending on the embodiment, an additional boosting capacitor may be formed between the gate electrode of the third transistor T3 and the gate electrode of the driving transistor T1 .

[0200] Furthermore, although the third transistor T3 and the fourth transistor T4 are formed of n-type transistors, only one of them may be formed of an n-type transistor, or the other transistor (eg, the seventh transistor T7) may be formed of an n-type transistor.

[0201] As described above, a pixel of a display device includes two semiconductors located on different layers, and the two semiconductors are respectively a polycrystalline semiconductor (also referred to as a first semiconductor) and an oxide semiconductor (also referred to as a second semiconductor).

[0202] Each of these semiconductors is included in a transistor, and hereinafter, a transistor including a polycrystalline semiconductor is referred to as a polycrystalline transistor and a transistor including an oxide semiconductor is referred to as an oxide transistor.

[0203] Therefore, one pixel may include a poly transistor and an oxide transistor, and the driving transistor T1 supplying a driving current to the light emitting diode LED is formed of the poly transistor.

[0204] All transistors except the driving transistor T1 are also referred to as switching transistors, and the switching transistors may be classified into polycrystalline switching transistors and oxide switching transistors.

[0205] In the following, reference will be made to Figure 4 and Figure 5 A display device according to the embodiment is described.

[0206] Figure 4 is a cross-sectional view of a display device according to an embodiment, and Figure 5 is a cross-sectional view of the second semiconductor layer.

[0207] The display device may include a lower panel layer and an upper panel layer, and the lower panel layer is a portion where a pixel circuit portion and a light emitting diode constituting a pixel are located, and may even include an encapsulation layer 400 covering them.

[0208] Here, the pixel circuit part includes a second organic layer 182 and a third organic layer 183. A light emitting diode is disposed on top of the third organic layer 183.

[0209] According to an embodiment, a structure located above the encapsulation layer 400 may correspond to an upper panel layer, and may include a color filter or a color conversion layer.

[0210] In addition, depending on the embodiment, the third organic layer 183 may not be included.

[0211] First, the metal layer BML is placed on the substrate 110 .

[0212] The substrate 110 may include a rigid material that does not bend, such as glass, or may include a flexible material that can bend, such as plastic or polyimide.

[0213] In the case of a flexible substrate, a double-layer structure of polyimide and a barrier layer formed of an inorganic insulating material thereon may have a dual structure.

[0214] The metal layer BML may be formed at a position overlapping a channel of the driving transistor in a plan view, and is also referred to as a lower shielding layer.

[0215] The metal layer BML may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0216] Here, the driving transistor may refer to a transistor that generates current transmitted to a light emitting diode.

[0217] A buffer layer 111 covering the substrate 110 and the metal layer BML is disposed.

[0218] The buffer layer 111 is used to block the impurity elements from penetrating into the first semiconductor layer ACT1, and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0219] The first semiconductor layer ACT1 including a silicon semiconductor (eg, a polycrystalline semiconductor (P—Si)) is located on the buffer layer 111 .

[0220] The first semiconductor layer ACT1 includes a polycrystalline transistor including a driving transistor (eg, Figure 4 A channel of a low temperature polysilicon transistor (LTPS) TFT) and a first region and a second region located on both sides of the channel.

[0221] Here, the polycrystalline transistor may include a plurality of polycrystalline switching transistors and a driving transistor.

[0222] In addition, the first and second regions disposed at both sides of the channel of the first semiconductor layer ACT1 may have improved conductivity through plasma treatment or doping, and can function as first and second electrodes of the transistor.

[0223] The first gate insulating layer 141 may be located on the first semiconductor layer ACT1 .

[0224] The first gate insulating layer 141 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0225] A first gate conductive layer including a gate electrode GE1 of the polycrystalline transistor may be located on the first gate insulating layer 141 .

[0226] In addition to the gate electrode GE1 of the poly transistor, a scan line or an emission control line may be formed in the first gate conductive layer.

[0227] Depending on the embodiment, the first gate conductive layer formed of different materials may include a 1-1 gate conductive layer and a 1-2 gate conductive layer.

[0228] After forming the first gate conductive layer, the exposed region of the first semiconductor layer ACT1 may be made conductive by performing a plasma treatment or a doping process.

[0229] In other words, a portion of the first semiconductor layer ACT1 covered by the first gate conductive layer has no conductivity, and a portion of the first semiconductor layer ACT1 not covered by the first gate conductive layer may have similar conductivity to that of the conductive material.

[0230] The second gate insulating layer 142 may be located on the first gate conductive layer and the first gate insulating layer 141 .

[0231] The second gate insulating layer 142 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0232] A second gate conductive layer including one electrode CE of the storage capacitor Cst may be positioned on the second gate insulating layer 142 .

[0233] One electrode CE of the storage capacitor Cst overlaps the gate electrode GE1 of the driving transistor to form the storage capacitor Cst.

[0234] According to an embodiment, the second gate conductive layer may further include a lower shielding layer BML-1 of the oxide transistor.

[0235] The lower shielding layer BML-1 of the oxide transistor may be located under the channel of the oxide transistor to shield it from light or electromagnetic interference provided to the channel from a lower side.

[0236] According to an embodiment, the second gate conductive layer may further include a scan line, a control line, or a voltage line.

[0237] The second gate conductive layer may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a plurality of layers.

[0238] A first interlayer insulating layer 161 may be located on the second gate conductive layer.

[0239] The first interlayer insulating layer 161 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y) or the like, and depending on the embodiment, the inorganic insulating material can be formed thickly.

[0240] A second semiconductor layer ACT2 (oxide semiconductor layer) including an oxide semiconductor may be located on the first interlayer insulating layer 161. The oxide semiconductor layer may serve as an active layer.

[0241] Oxide semiconductors are based on monometallic oxides such as indium oxide (In), tin oxide (Sn) or zinc oxide (Zn), binary metal oxides such as indium zinc oxide, tin zinc oxide, aluminum zinc oxide, zinc magnesium oxide, tin magnesium oxide, indium magnesium oxide or indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, tin aluminum zinc oxide, indium hafnium zinc oxide, indium lanthanum zinc oxide, indium oxide At least one of a ternary metal oxide of cerium zinc, indium praseodymium zinc oxide, indium neodymium zinc oxide, indium samarium zinc oxide, indium europium zinc oxide, indium gadolinium zinc oxide, indium terbium zinc oxide, indium dysprosium zinc oxide, indium holmium zinc oxide, indium erbium zinc oxide, indium thulium zinc oxide, indium ytterbium zinc oxide or indium lutetium zinc oxide and a quaternary metal oxide such as indium tin gallium zinc oxide, indium hafnium gallium zinc oxide, indium aluminum gallium zinc oxide, indium tin aluminum zinc oxide, indium tin hafnium zinc oxide or indium hafnium aluminum zinc oxide.

[0242] For example, the second semiconductor layer ACT2 may include indium gallium zinc oxide (IGZO) among indium gallium zinc-based oxides.

[0243] The second semiconductor layer ACT2 may include at least one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), and indium gallium oxide (IGO).

[0244] refer to Figure 5 , the second semiconductor layer ACT2 may include a 1-1 region A1-1, a 12 region A1-2, a 2-1 region A2-1, a 2-2 region A2-2, and a channel region AC overlapping a gate electrode GE3 of an oxide transistor to be described later.

[0245] The 1-1 region A1-1 and the 1-2 region A1-2 may be located on both sides of the channel region AC, respectively. The 2-1 region A2-1 may be disposed adjacent to the 1-1 region A1-1, and the 2-2 region A2-2 may be disposed adjacent to the 1-2 region A1-2. The 1-1 region A1-1 is disposed between the 2-1 region A2-1 and the channel region AC, and the 1-2 region A1-2 is disposed between the 2-2 region A2-2 and the channel region AC. Here, the 1-1 region A1-1 and the 2-1 region A2-1 may be source regions or drain regions, and may be referred to as first source / drain regions and second source / drain regions, respectively. Similarly, the 1-2 region A1-2 and the 2-2 region A2-2 may be drain regions or source regions, and may be referred to as first drain / source regions and second drain / source regions, respectively.

[0246] The length of the channel region AC may be 7 micrometers or less, for example, 3 micrometers or less.

[0247] The 1-1 region A1-1 and the 1-2 region A1-2 may be doped with first impurity ions.

[0248] The first impurity ions may be p-type impurity ions. For example, the first impurity ions may be boron (B) ions. The doping concentration of the first impurity ions may be 1×10 12 Up to 1×10 13 Ions / cm 2 .

[0249] The second impurity ions may be doped in the 2-1 region A2-1 and the 2-2 region A2-2. The second impurity ions may include impurity ions of a different type from the first impurity ions, and may be, for example, n-type impurity ions. For example, the second impurity ions may include at least one of arsenic (As) ions and antimony (Sb) ions.

[0250] Furthermore, according to another embodiment, the second impurity ions may include at least one of silicon (Si) ions, germanium (Ge) ions, and indium (In) ions. The doping concentration of the second impurity ions may be 1×10 12 Up to 1×10 14 Ions / cm 2 .

[0251] The 2-1 region A2-1 and the 2-2 region A2-2 according to the embodiment may further include first impurity ions. The first impurity ions may be p-type impurity ions, and for example, the first impurity ions may be boron (B) ions.

[0252] The process of doping the second impurity ions having a relatively large atomic mass may cause damage to the oxide semiconductor, and accordingly, the number of oxygen vacancies (Vo) included in the second semiconductor layer ACT2 increases.

[0253] Oxygen vacancies react with hydrogen to form carriers, and therefore, a highly doped oxide semiconductor (e.g., 2-1 region A2-1 and 2-2 region A2-2) may have higher conductivity than a lightly doped oxide semiconductor (e.g., 1-1 region A1-1 and 1-2 region A1-2). The process of doping the first impurity ions having a relatively small atomic mass also causes damage to the oxide semiconductor, and accordingly, the number of oxygen vacancies (Vo) may increase compared to the region not doped with impurities. Oxygen vacancies react with hydrogen to form carriers, so that the low-concentration conductive region (e.g., 1-1 region A1-1 and 1-2 region A1-2) may have a conductivity greater than that of the region not doped with impurities and less than that of the region doped with the second impurity ions. Since the first impurity ions have a smaller atomic mass than the second impurity ions, the damage to the oxide semiconductor doped with the first impurity ions may be less than the damage to the oxide semiconductor doped with the second impurity ions. Accordingly, the number of oxygen vacancies generated in the region doped with the first impurity ions may be relatively small. Accordingly, the 1-1 region A1-1 and the 1-2 region A1-2 may have lower carrier concentrations than the 2-1 region A2-1 and the 2-2 region A2-2.

[0254] The carrier concentration may decrease toward the 2-1 region A2-1, the 1-1 region A1-1, and the channel region AC, and the carrier concentration may decrease toward the 2-2 region A2-2, the 1-2 region A1-2, and the channel region AC. In the case of an oxide transistor including a second semiconductor layer ACT2 doped with different types of impurity ions, the threshold voltage value may remain substantially constant even if the length of the channel is reduced. The short channel effect (SCE) may be improved, and hot carriers may be reduced. Accordingly, the reliability of the transistor may be improved, and the display quality of the display device may be improved.

[0255] The third gate insulating layer 143 may be located on the second semiconductor layer ACT2 .

[0256] The third gate insulating layer 143 may be formed on the entire surface of the second semiconductor layer ACT2 and the first interlayer insulating layer 161 , and some portions of the third gate insulating layer 143 may be removed to form a contact hole.

[0257] The third gate insulating layer 143 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0258] A third gate conductive layer including a gate electrode GE3 of an oxide transistor may be located on the third gate insulating layer 143 .

[0259] The gate electrode GE3 of the oxide transistor may overlap with the channel of the oxide transistor.

[0260] The third gate conductive layer may further include a scan line or a control line.

[0261] The third gate conductive layer may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a plurality of layers.

[0262] The second interlayer insulating layer 162 may be located on the third gate conductive layer.

[0263] The second interlayer insulating layer 162 may have a single-layer or multi-layer structure.

[0264] According to an embodiment, the second interlayer insulating layer 162 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) of inorganic insulating materials, and may include organic materials.

[0265] A first data conductive layer including connection members C1 , C2 , C3 , C4 that may be connected to first and second regions of each of the poly transistor and the oxide transistor may be located over the second interlayer insulating layer 162 .

[0266] The first data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may consist of a single layer or a plurality of layers.

[0267] The first organic layer 181 may be located on the first data conductive layer.

[0268] The first organic layer 181 may be an organic insulating layer including an organic material, and the organic material may include at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0269] The second data conductive layer including the anode connection member ACM2 may be positioned on the first organic layer 181 .

[0270] The second data conductive layer may include a data line or a driving voltage line.

[0271] The second data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may consist of a single layer or a plurality of layers.

[0272] The anode connection member ACM2 is connected to the first data conductive layer through the opening OP3 located in the first organic layer 181 .

[0273] The second organic layer 182 and the third organic layer 183 are located over the second data conductive layer, and an anode connection opening OP4 is formed in the second organic layer 182 and the third organic layer 183 .

[0274] The anode connection member ACM2 is electrically connected to the anode Anode through the anode connection opening OP4.

[0275] The second organic layer 182 and the third organic layer 183 may be organic insulating layers, and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0276] Depending on the embodiment, the third organic layer 183 may be omitted.

[0277] The pixel defining layer 380 covering at least a portion of the anode Anode while having the opening OP exposing the anode Anode may be positioned on the anode Anode.

[0278] According to an embodiment, the pixel defining layer 380 may be a black pixel defining layer formed of a black organic material to prevent externally applied light from being reflected back to the outside, or may be formed of a transparent organic material.

[0279] The spacer 385 is located on the pixel defining layer 380 .

[0280] The spacer 385 may be formed of a transparent organic insulating material.

[0281] According to an embodiment, the spacer 385 may be formed of a positive type transparent organic material.

[0282] The spacer 385 may include two portions 385 - 1 and 385 - 2 having different heights, the high portion 385 - 1 may serve as a spacer, and the low portion 385 - 2 may improve adhesion between the spacer and the pixel defining layer 380 .

[0283] The functional layer FL and the cathode Cathode can be disposed on the anode Anode, the spacer 385 and the pixel defining layer 380 to cover the entire structure formed on the substrate 110 .

[0284] The light emitting layer EML is located between the functional layers FL, and the light emitting layer EML may be located only within the opening OP of the pixel defining layer 380 .

[0285] Hereinafter, the functional layer FL and the light emitting layer EML may be collectively referred to as an intermediate layer.

[0286] The functional layer FL may include at least one of an electron injection layer, an electron transport layer, a hole transport layer, and an auxiliary layer such as a hole injection layer, and the hole injection layer and the hole transport layer are disposed under the light emitting layer EML and the electron transport layer and the electron injection layer may be located on the light emitting layer EML.

[0287] The encapsulation layer 400 is located on the cathode.

[0288] The encapsulation layer 400 includes at least one inorganic layer and at least one organic layer, and may have a three-layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0289] The encapsulation layer 400 may protect the light emitting layer EML from moisture or oxygen that may be introduced from the outside.

[0290] Depending on the embodiment, the encapsulation layer 400 may include a structure in which an inorganic layer and an organic layer are sequentially stacked.

[0291] Sensing insulating layers 501 , 510 , and 511 and a plurality of sensing electrodes 540 and 541 are placed on the encapsulation layer 400 for touch sensing.

[0292] The touch may be sensed in a capacitive type using the two sensing electrodes 540 and 541 .

[0293] Specifically, a first sensing insulating layer 501 is formed on the encapsulation layer 400 , and a plurality of sensing electrodes 540 and 541 are formed on the first sensing insulating layer 501 .

[0294] The second sensing insulating layer 510 may be interposed between the plurality of sensing electrodes 540 and 541 , and the plurality of sensing electrodes 540 and 541 may be electrically connected through openings located in the second sensing insulating layer 510 .

[0295] Here, the sensing electrodes 540 and 541 include a metal or a metal alloy such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and they may include a single layer or a plurality of layers.

[0296] The third sensing insulating layer 511 is formed on the sensing electrode 540 .

[0297] exist Figure 4 In the present invention, no additional layer is disposed on top of the third sensing insulating layer 511, but a layer including a polarizer may be attached to the third sensing insulating layer 511 to reduce reflection of external light, or a color filter or a color conversion layer may be further formed on the third sensing insulating layer 511 to improve color quality.

[0298] The light blocking member may be located between the color filters or the color conversion layers.

[0299] In addition, depending on the embodiment, a layer having a material capable of absorbing some wavelengths of external light (hereinafter, referred to as a reflection adjusting material) may be further included.

[0300] Additionally, depending on the embodiment, the front surface of the display device may be flattened by covering it with an additional organic layer (also referred to as a planarization layer).

[0301] In the following, reference will be made to Figures 6 to 9 A manufacturing process of the second semiconductor layer according to the embodiment is described.

[0302] Figures 6 to 9 is a cross-sectional view of a process of manufacturing a second semiconductor layer according to an embodiment.

[0303] Description of the same components as those described above will be omitted.

[0304] First, refer to Figure 6 , a second semiconductor layer ACT2 including an oxide semiconductor, a third gate insulating layer 143, and a gate electrode GE3 of an oxide transistor are formed. Thereafter, a first doping process using first impurity ions is performed.

[0305] The doping process may be performed using the gate electrode GE3 as a self-aligned mask. Through the first doping process, the second semiconductor layer ACT2 including the channel region AC overlapping the gate electrode GE3 and the regions DP1 located at both sides of the channel region AC and doped with the first impurity ions is formed.

[0306] Because the gate electrode GE3 is used as a mask, the channel region AC is not doped with impurity ions, and both sides of the channel region AC may be doped with first impurity ions. The first impurity ions may be p-type impurity ions. For example, the first impurity ions may be B ions. The doping concentration of the first impurity ions may be 1×10 12 Up to 1×10 13 Ions / cm 2 .

[0307] like Figure 7 As shown in FIG. 1 , a photosensitive resin composition pattern PR is formed on the gate electrode GE3 of the oxide transistor. Then, as shown in FIG. Figure 8 As shown in , a second doping process using second impurity ions is performed. The second impurity ions may include impurity ions different from the first impurity ions, and may be, for example, n-type impurity ions. For example, the second impurity ions may include at least one of As ions and Sb ions. In addition, the second impurity ions according to another embodiment may include at least one of Si ions, Ge ions, and In ions. The doping concentration of the second impurity ions may be greater than or equal to the doping concentration of the first impurity ions, for example, may be 1×1012 Up to 1×10 14 Ions / cm 2 .

[0308] According to the doping process, second impurity ions may be doped into a portion of the second semiconductor layer ACT2 not covered by the photosensitive resin composition pattern PR. The second semiconductor layer ACT2 includes a channel region AC, a 1-1 region A1-1, a 1-2 region A1-2, a 2-1 region A2-1, and a 2-2 region A2-2.

[0309] The 1-1 region A1-1 and the 1-2 region A1-2 may be doped with the first impurity ions, and the 2-1 region A2-1 and the 2-2 region A2-2 may be doped with the first impurity ions and the second impurity ions.

[0310] Then, if Fig. 9 As shown in FIG. 1 , the photosensitive resin composition pattern PR is removed, and a second interlayer insulating layer 162 is formed on the gate electrode GE3. Hydrogen included in the second interlayer insulating layer 162 may diffuse into the second semiconductor layer ACT2 to form additional carriers.

[0311] The process of doping the second impurity ions having a relatively large atomic mass may cause relatively large damage to the oxide semiconductor, and accordingly, the number of oxygen vacancies (Vo) included in the second semiconductor layer ACT2 may increase.

[0312] Oxygen vacancies react with hydrogen to form carriers, and therefore, highly doped oxide semiconductors (e.g., 2-1 region A2-1 and 2-2 region A2-2) may have higher conductivity than lightly doped oxide semiconductors (e.g., 1-1 region A1-1 and 1-2 region A1-2). The process of doping the first impurity ions having a relatively small atomic mass may cause relatively small damage to the oxide semiconductor. In this case, oxygen vacancies (Vo) are generated, and the generated oxygen vacancies react with hydrogen to form carriers, thereby forming low-concentration conductive regions constituting 1-1 region A1-1 and 1-2 region A1-2. Since the first impurity ions have a smaller atomic mass than the second impurity ions, the damage to the oxide semiconductor in 1-1 region A1-1 and 1-2 region A1-2 may be relatively small. Accordingly, the number of oxygen vacancies generated by doping the first impurity ions may be less than the number of oxygen vacancies generated by doping the second impurity ions. Accordingly, the 1-1 region A1-1 and the 1-2 region A1-2 having a low carrier concentration are formed by the first impurity ions as compared to the second impurity ions.

[0313] In the case of an oxide transistor including a second semiconductor layer ACT2 doped with different types of impurity ions, the threshold voltage value can be kept substantially constant even if the length of the channel is reduced. The short channel effect (SCE) can be improved, and hot carriers can be reduced. Accordingly, the reliability of the transistor can be improved, and the display quality of the display device can be improved.

[0314] In the following, reference will be made to Figures 10 to 13 A manufacturing process of the second semiconductor layer according to the embodiment is described.

[0315] Figures 10 to 13 is a cross-sectional view of a manufacturing process of a second semiconductor layer according to another embodiment.

[0316] refer to Fig.10 , a photosensitive resin composition pattern PR is formed on the gate electrode GE3 of the oxide transistor.

[0317] Then, if Fig.11 As shown in , a doping process using second impurity ions is performed.

[0318] According to the doping process, the second semiconductor layer ACT2 (eg, region DP2 ) overlapping the gate electrode GE3 and / or the photosensitive resin composition pattern PR is not doped with the second impurity ions, and regions DP3 located at both sides of the region DP2 are doped with the second impurity ions.

[0319] The second impurity ions may include impurity ions of a different type from the first impurity ions, and may be, for example, n-type impurity ions. For example, the second impurity ions may include at least one of As ions and Sb ions. In addition, the second impurity ions according to another embodiment may include at least one of Si ions, Ge ions, and In ions. The doping concentration of the second impurity ions may be 1×10 12 Up to 1×10 14 Ions / cm 2 .

[0320] Afterwards, if Fig.12 As shown in , the photosensitive resin composition pattern PR is removed, and a doping process using the first impurity ions is performed. Through the doping process, the second semiconductor layer ACT2 has a channel region AC, a 1-1 region A1-1, a 1-2 region A1-2, a 2-1 region A2-1, and a 2-2 region A2-2. The first impurity ions are doped in the 1-1 region A1-1, the 1-2 region A1-2, the 2-1 region A2-1, and the 2-2 region A2-2, and the second impurity ions are doped in the 2-1 region A2-1 and the 2-2 region A2-2. The first impurity ions may be p-type impurity ions. For example, the first impurity ions may be B ions. The doping concentration of the first impurity ions may be 1×10 12 Up to 1×1013 Ions / cm 2 .

[0321] Afterwards, if Fig.13 As shown in FIG. 1 , a second interlayer insulating layer 162 is formed on the gate electrode GE3. Hydrogen included in the second interlayer insulating layer 162 may diffuse into the second semiconductor layer ACT2 to form additional carriers.

[0322] In the following, reference Fig.14 , comparative examples and embodiments of the inventive concept will be described. Fig.14 is a graph showing threshold voltage values ​​of transistors including an oxide semiconductor according to an embodiment of the inventive concept and a comparative example.

[0323] refer to Fig.14 , the comparative example is a transistor including an oxide semiconductor layer including only an n+ region and a channel region, and an embodiment of the inventive concept is a transistor including an oxide semiconductor layer including a 1-1 region, a 1-2 region, a 2-1 region, and a 2-1 region.

[0324] In the case of the comparative example, it was confirmed that the value of the threshold voltage Vth rapidly decreased as the length of the channel shortened.

[0325] On the other hand, in the case of the embodiment of the inventive concept, it is confirmed that even if the length of the channel is shortened, the value of the threshold voltage Vth is kept constant to some extent.

[0326] In the case of including an oxide semiconductor layer according to an embodiment of the inventive concept, since a threshold voltage of an oxide transistor is stabilized, a display device having improved reliability may be provided.

[0327] In addition, since the channel length of the oxide transistor can be shortened without deteriorating the characteristics of the oxide transistor, it is possible to provide a display device with improved resolution.

[0328] Although the embodiments of the inventive concept have been described in detail above, the scope of the inventive concept is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the inventive concept defined in the appended claims are also included in the scope of the inventive concept.

Claims

1. A display device, comprising: substrate; as well as A transistor including an oxide semiconductor layer as an active layer and a gate electrode provided on the oxide semiconductor layer so as to overlap with the oxide semiconductor layer, The oxide semiconductor layer includes a channel region, a source region disposed on a first side of the channel region, and a drain region disposed on a second side of the channel region. wherein the source region includes a first source region disposed adjacent to the channel region and a second source region disposed adjacent to the first source region, and the drain region includes a first drain region disposed adjacent to the channel region and a second drain region disposed adjacent to the first drain region, and Each of the first source region and the first drain region includes a first impurity ion, and each of the second source region and the second drain region includes a second impurity ion different from the first impurity ion.

2. The display device according to claim 1, wherein: The second source region and the second drain region further include the first impurity ions.

3. The display device according to claim 1, wherein: The atomic mass of the second impurity ions is greater than the atomic mass of the first impurity ions.

4. The display device according to claim 3, wherein: The first impurity ions are p-type impurity ions, and the second impurity ions are n-type impurity ions.

5. The display device according to claim 4, wherein: The first impurity ions include B ions, and the second impurity ions include at least one of As ions, Sb ions, Si ions, Ge ions, and In ions.

6. The display device according to any one of claims 1 to 5, wherein: The doping concentrations of the first source region and the first drain region are lower than the doping concentrations of the second source region and the second drain region.

7. The display device according to claim 6, wherein: The doping concentration of the first impurity ion is 1×10 12 Ions / cm 2 Up to 1×10 13 Ions / cm 2 .

8. The display device according to claim 6, wherein: The doping concentration of the second impurity ion is 1×10 12 Ions / cm 2 Up to 1×10 14 Ions / cm 2 .

9. The display device according to claim 1, wherein: Each of the first source region and the first drain region includes B ions.

10. The display device according to claim 1, wherein: Each of the second source region and the second drain region includes B ions and at least one of As ions, Sb ions, Si ions, Ge ions, and In ions.

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