A method, apparatus, medium, and product for automatically designing complex special-purpose instructions for hardware.

Abstract

This application discloses an automatic design method, device, medium, and product for complex special-purpose instructions (SPDIS) in hardware, relating to SPDIS hardware design, SPDIS instruction design, or instruction set extension. The method includes: analyzing the program to collect dynamic information; converting basic blocks in the program into a data dependency graph based on the compiler's intermediate representation and extracting seeds; using a genetic algorithm to obtain candidate programs that meet input / output constraints based on the seeds; using a specially designed cost model to score the candidate programs as a selection criterion; utilizing maximum weighted independent set analysis to overcome the overlap problem of candidate programs; and fusing the subgraphs corresponding to the SPDIS instructions to generate dedicated functional units, thus completing the automatic design of complex SPDIS instructions for hardware. This application can explore the similarities between basic blocks, discover common and frequently executed code segments in the program as SPDIS instructions; and the search can maximize the coverage of the target program, significantly accelerating the program.

Description

Technical Field

[0001] This application relates to special-purpose hardware design, special-purpose instruction design, or instruction set extension, and in particular to a method, apparatus, medium, and product for automatically designing complex special-purpose instructions for hardware. Background Technology

[0002] Recently, there has been a growing trend of integrating specialized instructions into general-purpose instruction set architectures (ISAs), leading to the rise of computing platforms such as Application-Specific Instruction Set Processors (ASIPs). This trend is driven by practical needs in various application areas, including image processing and advanced cryptographic standards. Representative instruction set extensions include Intel's SSE, GPU (Graphics Processing Unit) Tensor Cores, Intel's AMX, and Qualcomm's HVX. Intel's SSE is used for stream processing applications, GPU Tensor Cores for deep learning, and both Intel's AMX and Qualcomm's HVX are used for deep learning. However, specialized instructions require a deep understanding of the application's algorithms, data structures, and performance bottlenecks, involving a significant amount of manual work.

[0003] Currently, the exploration and design of dedicated instructions (DIPs) using intermediate representation (IR) for automation is becoming a trend. However, several challenges need to be addressed to extract valuable DIPs and verify their performance, power consumption, and area. First, DIPs can be extracted from any part of the application, requiring a search of the entire code to identify candidate instructions and select the best one. Furthermore, given the similarity of instruction sequences, this process involves graph isomorphism judgment, an NP-hard (Nondeterministic polynomial) problem. These factors collectively result in a large and complex search space. Second, DIPs should maximize performance benefits while minimizing overhead. DIPs can benefit from reduced address fetch and decode overhead, reduced register accesses, and operational parallelism. The more operations in a DIP, the greater these benefits are likely to be. However, given the limited hardware area, it is necessary to limit the number and size (number of operations) of DIPs.

[0004] Current research has not fully addressed these challenges. Some methods use heuristics to extract candidate instructions to avoid extensive searches. However, these methods excessively reduce the search space, neglecting certain design considerations. The number of inputs and outputs for each specialized instruction should be limited. On one hand, inputs and outputs should meet specific design requirements, such as scalar instructions with finite operands; on the other hand, reducing inputs and outputs reduces data movement (between general-purpose registers and special-purpose registers / buffers) and swizzling instructions, which would otherwise diminish the performance gains from specialized instructions. Related work has not considered the limitations on the number of inputs and outputs. Other methods can extract candidates with precise input and output counts, but they fail to leverage the similarity between exploring basic blocks during the search process, only fusing them after obtaining specialized instructions. This only reduces hardware area overhead and does not contribute to the search process itself. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this application provides a method, apparatus, medium, and product for automatically designing complex special-purpose instructions for hardware.

[0006] To achieve the above objectives, this application provides the following solution:

[0007] In a first aspect, this application provides a method for automatically designing complex special-purpose instructions for hardware, including:

[0008] The analysis program collects dynamic information, including the number of times the basic blocks are executed.

[0009] The program is converted into an intermediate representation by the compiler, and based on the intermediate representation, the basic blocks in the program are converted into a data dependency graph;

[0010] The data dependency graph is divided into subgraphs using prohibition instructions; the subgraphs contain only arithmetic instructions; the prohibition instructions include memory access instructions and branch instructions.

[0011] Candidates are obtained based on the subgraph using a seed growth method; the seed growth method is a genetic algorithm that incorporates a seed multi-component simultaneous growth algorithm.

[0012] Obtain the arithmetic instructions corresponding to the candidate options, evaluate the arithmetic instructions corresponding to the candidate options using a cost model, and use the candidate option with the highest evaluation score as the dedicated instruction;

[0013] By integrating the sub-graphs corresponding to the dedicated instructions, dedicated functional units are generated, thus completing the automatic design of complex dedicated instructions for hardware.

[0014] Optionally, candidate options are obtained based on the subgraph using a seed growth method, specifically including:

[0015] Extract a seed from the subgraph; the seed may be one or more;

[0016] The seed is subjected to a genetic algorithm for growth, and during the process of invoking the genetic algorithm, a multi-component simultaneous growth algorithm for the seed is invoked to explore the code similarity between basic blocks, thereby obtaining a growth subgraph that repeatedly appears in the code and satisfies predefined conditions; the genetic algorithm includes selection, mutation, and crossover operations;

[0017] Define a seed component; the defined seed component is an instance of the seed that exists in the same or different basic blocks.

[0018] The growth subgraph that connects the nodes to the seed component is used as the candidate.

[0019] Optionally, extracting a seed from the subgraph specifically includes:

[0020] Extract recurring instruction pairs from the subgraph as seeds;

[0021] The greedy strategy is used to iteratively extract the instruction pair with the longest total delay in the subgraph as the seed.

[0022] Optionally, a greedy strategy is used to iteratively extract the instruction pair with the longest total latency in the subgraph as a seed, specifically including:

[0023] Traverse all nodes in the subgraph, identify and extract the node pair with the longest total delay, and remove the node pair with the longest total delay from the subgraph. Repeat this process until all nodes in the subgraph have been traversed. Then, use the instructions corresponding to all nodes with the longest total delay extracted from the subgraph as the seed.

[0024] Optionally, the method for automatically designing complex special-purpose instructions for the hardware further includes:

[0025] After obtaining candidate options from all seeds using the seed growth method, a conflict graph is constructed for all candidate options. The evaluation score is used as the weight, and the independent set with the largest weight sum is extracted from the conflict graph. The candidate options in the independent set are taken as the region of interest. The independent set refers to a group of nodes in the subgraph where there is no edge between any two nodes. The conflict refers to a subgraph corresponding to two candidate options containing the same node.

[0026] The node corresponding to the region of interest will be deleted from the subgraph, and the step of extracting the seed from the subgraph will be returned until no more seeds can be extracted.

[0027] The regions of interest are merged to enable the reuse of dedicated functional units.

[0028] Optionally, the method for automatically designing complex special-purpose instructions for the hardware is based on a framework for automatically extracting and verifying instructions; the framework takes the intermediate representation of the compiler as input.

[0029] Optionally, the resulting candidate options do not overlap; overlapping candidate options refer to the subgraphs corresponding to different candidate options sharing one or more nodes.

[0030] In a second aspect, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the complex special-purpose instruction automatic design method for the hardware provided above.

[0031] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the complex special-purpose instruction automatic design method for the hardware provided above.

[0032] Fourthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the complex special-purpose instruction automatic design method for the hardware provided above.

[0033] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0034] This application provides an automated design method, device, medium, and product for complex special-purpose instructions (SPDIS) in hardware. It can identify frequently executed code segments from programs as candidates for SPDIS and overcome the overlap problem of candidate options through maximum weighted independent set analysis. By employing a cost model to compare and select the best instruction (i.e., SPDIS) from these candidates, maximum performance can be pursued under predefined input and output constraints. Through seed growth, the similarity between basic blocks can be explored, and iterative search methods are used to address the problem of over-reducing the search space and neglecting design points, thereby uncovering SPDIS with potential benefits as much as possible. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a flowchart illustrating an automatic design method for complex special-purpose instructions based on CCExplorer in one embodiment of this application.

[0037] Figure 2 A flowchart illustrating an automatic design method for complex special-purpose instructions in hardware, provided as an embodiment of this application;

[0038] Figure 3 A data dependency graph provided for another embodiment of this application;

[0039] Figure 4 This is a schematic diagram of a seed multi-component simultaneous growth algorithm provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram of three candidate options, 0, 1, and 2, provided in an embodiment of this application;

[0041] Figure 6 A conflict diagram of three candidate options and a schematic diagram of the selected maximum weighted independent set provided for another embodiment of this application;

[0042] Figure 7 A schematic diagram of candidate instructions provided for another embodiment of this application;

[0043] Figure 8 A schematic diagram illustrating an implementation method for an automated design method of complex special-purpose instructions for hardware provided in another embodiment of this application;

[0044] Figure 9 This is a schematic diagram of region-of-interest fusion provided in another embodiment of this application;

[0045] Figure 10 A schematic diagram of a non-convex subgraph provided for another embodiment of this application;

[0046] Figure 11 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] To better present the concepts of this application, let's first introduce some basic terms:

[0050] (1) Candidate Options. Candidate options are subgraphs derived from basic blocks; in this application, they contain only arithmetic operations. For example, in Figure 7 In this context, all subgraphs 0-3 and repeating subgraphs are potential candidates. Based on a cost model, their potential benefits as dedicated instructions are evaluated. Figure 7 Part (A) is a subgraph of basic block 0. Figure 7 (B) is a subgraph of basic block 1. Figure 7 (C) is a repeating subgraph.

[0051] (2) Region of Interest. The region of interest is used to implement special instructions. It is the most promising candidate selected from all extracted candidates.

[0052] (3) Candidate Components. Subgraphs corresponding to candidates may appear repeatedly in the application; each subgraph instance is called a candidate component. For example, in Figure 7 There are five add-getelementptr instruction pairs, so add-getelementptr is a candidate with five candidate components. The candidate components can be distributed in the same or different basic blocks.

[0053] (4) Seed and Seed Components. A seed is a repeating subgraph containing only two connected nodes. For example, Figure 7 In the panel shown in section (C), only the first three subgraphs can be seeds. Seed components are similar to candidate components, representing different seed instances.

[0054] To implement the automated design method for complex custom instructions for hardware provided in the embodiments of this application, CCExplorer (Complex Custom Instruction Explorer) can be designed. CCExplorer is a framework for automatically extracting and verifying custom instructions. Figure 1 The entire framework's workflow is demonstrated. CCExplorer takes the LLVM (Low Level Virtual Machine) intermediate representation (IR) as input. CCExplorer first analyzes the program, collecting dynamic information such as the execution count of basic blocks, and converts these basic blocks into data dependency graphs based on the compiler's intermediate representation. Then, it uses prohibited instructions to partition these data dependency graphs into subgraphs, ensuring that these subgraphs contain only arithmetic instructions, effectively reducing the search space. CCExplorer uses a seed-growing method to quickly and automatically select non-overlapping candidate options and choose the best one as the dedicated instruction. Overlap refers to different candidate options sharing one or more nodes in their corresponding subgraphs, such as... Figure 5Candidates 0 and 1 both contain nodes A and B. The quality (or benefit) of the specialized instructions is evaluated using a cost model. The entire search process is iterative to avoid missing design points and achieve high coverage of arithmetic operations. Then, all selected specialized instructions are fused in post-processing (the fusion process uses methods from existing work to fuse different new instructions) to generate specialized functional units, minimizing the area cost of hardware implementation. Finally, verification is performed using an IR that can directly execute the compiler and a simulator that can run arbitrary custom instructions.

[0055] Based on this, this application can quickly and automatically explore and verify complex special-purpose instructions in the early stages of design, automatically identify common and frequently executed operations in the application as special-purpose instructions, and ensure that special-purpose instructions comply with predefined input and output quantity limits.

[0056] In one exemplary embodiment, such as Figure 2 As shown, a method for automatically designing complex special-purpose instructions for hardware is provided. This method is executed by a computer device, specifically by a terminal or server alone, or by both a terminal and a server. In this embodiment, the method is described using a server as an example, and includes the following steps 200 to 205. Wherein:

[0057] Step 200: Analyze the program and collect dynamic information. Dynamic information includes the number of times the basic blocks are executed.

[0058] Step 201: Convert the program into an intermediate representation of the compiler, and based on the intermediate representation, convert the basic blocks in the program into a data dependency graph.

[0059] Step 202: Use prohibition instructions to divide the data dependency graph into subgraphs. The subgraphs contain only arithmetic instructions.

[0060] Step 203: Candidates are obtained based on the subgraph using the seed growth method. The seed growth method is a genetic algorithm that embeds a seed multi-component simultaneous growth algorithm.

[0061] Step 204: Obtain the arithmetic instructions corresponding to the candidate options, evaluate the arithmetic instructions corresponding to the candidate options using a cost model, and use the candidate option with the highest evaluation score as the dedicated instruction.

[0062] Step 205: Merge the sub-graphs corresponding to the special instructions to generate special functional units and complete the automatic design of complex special instructions for the hardware.

[0063] By implementing steps 200 to 205 above, common and frequently executed code snippets can be identified from the program as candidates for dedicated instructions, overcoming the problem of overlapping candidates, solving the problem of excessive reduction of the search space leading to the neglect of design points, and exploring the similarity between basic blocks.

[0064] In another exemplary embodiment of this application, the implementation process of step 203 described above can be described as follows:

[0065] Extract the seed from the subgraph.

[0066] The seed is subjected to a genetic algorithm for growth, and during the process of invoking the genetic algorithm, a multi-component simultaneous growth algorithm for the seed is invoked to explore the code similarity between basic blocks, thereby obtaining a growth subgraph that repeatedly appears in the code and satisfies predefined conditions; the genetic algorithm includes selection, mutation, and crossover operations;

[0067] Define a seed component; the defined seed component is an instance of the seed that exists in the same or different basic blocks.

[0068] The growth subgraph that connects the nodes to the seed component is used as the candidate.

[0069] In another exemplary embodiment of this application, to avoid over-pruning the search space (or searching for as many design points as possible), an algorithm is needed that can include design points from fine-grained to coarse-grained. For example, fine-grained design points could be new instructions formed by fusing two instructions, while coarse-grained design points could be new instructions generated by fusing the entire basic block, or some design point in between. Enumerating all design points would ensure no design point is missed, but this would result in an excessively large search space, making it impossible to complete the search within a reasonable timeframe. Therefore, the algorithm also needs to be able to complete the search quickly. Since basic blocks are composed of instructions, two instructions with data dependencies can be used as a starting point, continuously adding new instructions to form larger candidate blocks (subgraphs containing more instructions). This process can be implemented using a seed growth method. However, larger candidate blocks do not necessarily mean greater performance gains. Therefore, these candidate blocks need to be scored to obtain instructions that can generate more benefits. This scoring is implemented using a cost model.

[0070] Based on the above description, in this embodiment, the seed growth method uses a genetic algorithm to grow the seed into a larger subgraph that satisfies predefined input-output constraints. A cost model is integrated into the genetic algorithm to evaluate and filter these subgraphs. The genetic algorithm uses the seed multi-component simultaneous growth algorithm proposed in this application to solve the graph similarity checking problem.

[0071] Since this embodiment only focuses on arithmetic instructions, in step 202 above, the data dependency graph of the basic blocks is divided into subgraphs using prohibition instructions. Then, seeds are extracted from these subgraphs using two methods.

[0072] The first approach is to extract recurring instruction pairs from the subgraph as seeds. As the seeds grow into a larger graph, all seed components should grow simultaneously, and the similarity of these graphs needs to be checked. These instruction pairs may overlap; select the instruction pairs that appear earlier in the program sequence and discard the others. It's worth noting that not all basic blocks contain recurring instruction pairs, so the second approach is used when these basic blocks are hotspots and specific instructions need to be extracted.

[0073] The second method uses a greedy strategy to iteratively extract the instruction pair with the longest total latency in the subgraph, which can be summarized as follows:

[0074] (1) Identify and extract the node pair with the longest total delay.

[0075] (2) Remove these nodes from the subgraph.

[0076] (3) If there are still unvisited nodes, repeat step (1); otherwise, complete the extraction.

[0077] In another exemplary embodiment of this application, a seed growth method is described using a genetic algorithm. The first step is to encode a data dependency graph, which should be able to represent the seed growth process. Figure 3 Part (A) shows a subgraph containing eight nodes, coded as 00001100, where the black solid line represents the seed node. Figure 3 Part (B) shows the subgraph (red and black nodes) grown from the seed, which will be encoded as 00111100. In the subgraph, the order of the nodes corresponds to the order in which the instructions appear in the intermediate representation. Based on this, the implementation process of the seed growth method is as follows:

[0078] 1) Seed growth. Figure 3 Part (B) to Figure 3 Part (E) describes various cases where red nodes are attempted to be integrated to construct a new subgraph during seed growth. For simplicity, the example only considers the case of growing a single seed component. Assume the design objective is to find a subgraph with at most eight inputs and only one output.

[0079] Figure 3 Part (B) and Figure 3 Part (C) shows two valid subgraphs. After adding the red node to the seed, both subgraphs have five inputs and one output, all nodes are connected, acyclic, and convex. Convex means that there is no path between any two nodes outside the subgraph. Conversely, Figure 3The subgraph in part (D) is invalid because the newly added node is not connected to the seed, while Figure 3 The subgraph in part (E) has nine inputs. Figure 3 Sections (A) to (E) are data dependency graphs, each containing eight nodes. Solid black circles represent nodes of the seed component, red circles represent nodes of the seed growth, and dashed black circles represent nodes not considered. Black arrows indicate the direction of data dependencies; input and output nodes are omitted.

[0080] 2) Implementation. The genetic algorithm is initialized using the seed's encoding, ensuring that the randomly generated encoding during the algorithm's execution contains the seed. The genetic algorithm includes selection, mutation, and crossover operations; before execution, we search for the optimal parameters for these operations. A cost model is used to score subgraphs and determine if they meet predefined conditions. The genetic algorithm executes once for each seed and outputs the best subgraph with the highest score as a candidate.

[0081] 3) Challenges. The seed growth method needs to consider the similarity of the graph, which poses the following challenges to the implementation of genetic algorithms:

[0082] First, the different lengths of basic blocks inevitably lead to variations in the encoding length.

[0083] Secondly, seed components appear in different base blocks, thus having different contexts. When a new node is added to a seed component, the instruction corresponding to that node may not exist in the base block to which other seed components belong, or it may exist but its location is unknown, which makes seed growth difficult.

[0084] Furthermore, it is necessary to check whether these subgraphs remain isomorphic during seed growth. However, graph isomorphism is NP-hard. To address this, this application proposes a simultaneous multi-component seed growth algorithm.

[0085] Figure 4 This paper demonstrates the implementation flow of a seed multi-component simultaneous growth algorithm, embedded within a genetic algorithm. The various components of the seed should grow simultaneously in different basic blocks. To achieve this, a candidate component is selected for growth, and then it is checked whether other components can grow into the same subgraph. If the basic block containing the seed component is small, the subgraph grown from the seed will also be small. In this case, this application utilizes the SelectCandidateComponent function to select components defined as seed... x The seed component, which belongs to the basic block bb containing the most instructions. x (correspond Figure 4 (Line 3). The GenerateNewCode function generates code based on the seed. x Generate new encoding (corresponding) Figure 4 (line 6), encoding length and bb x The same applies. Then, the Decode function extracts the newly added nodes and constructs the subgraph g. x (correspond Figure 4 (Line 7). The encoding generated by the genetic algorithm does not guarantee the subgraph g. x Nodes and seeds x The connection is established, so the CheckConnectivity function is used to determine g. x If the graph is not connected, the multi-component simultaneous growth algorithm will terminate and return immediately (corresponding to...). Figure 4 (Lines 8 and 9). Corresponding to Figure 4 Lines 10 through 16 iterate through the other seed components and use the Grow function for each seed component. i Construct graph g i (correspond Figure 4 (Line 12). If there is a lack of a connected, acyclic, and convex subgraph g, then... i The Grow function will return null if the required instructions for the corresponding node are not provided. The Grow function ensures that the subgraph g... i subgraph g x The existence and connectivity of instructions in the subgraph g. In other words, the subgraph g i subgraph g x If the number and type of instructions are the same, but the instructions may have different orders and dependencies, this is a relaxed way to check graph similarity. If subgraph g i If it is not empty, then the subgraph g i subgraph g x If they are considered similar, then subgraph g i Add to the subgraph g x In the set R of similar repeating subgraphs (corresponding to) Figure 4 Line 14). Finally, the CostModel function is called to score the candidate R using the cost model (corresponding to...). Figure 4 (Line 18). This application does not strictly guarantee graph isomorphism, because this application can assume that if two subgraphs are identical in the number and type of operations, they can share hardware area using a multiplexer.

[0086] During the execution of the genetic algorithm, when calling the seed multi-component simultaneous growth algorithm... x The structure itself won't change, but the encoding will be different. The genetic algorithm will generate many encodings based on the seed, and each encoding will invoke a seed multi-component simultaneous growth algorithm to check how many seed components can grow into a subgraph g. x and the effective subgraph g iAdd elements to set R. R represents a candidate set, where each subgraph is a candidate component. The number of elements in R can be less than or equal to the number of elements in the seed seeds. The genetic algorithm compares and maintains R with the highest score as the output.

[0087] Based on the above description, it is easier to count and control the number of inputs and outputs of candidate options as instructions are continuously added; that is, the count is performed every time a new candidate option is generated. The counting of input and output counts is integrated into the cost model to filter candidates that meet specific input and output count requirements and to score and compare candidates that meet the conditions. Furthermore, finding recurring candidate options in the program involves graph isomorphism judgment, which is an NP-hard problem, but this problem can also be solved using a growth process. In implementation, we first select recurring instruction pairs in the program as the starting point, then add identical instructions to these instruction pairs, and determine whether the newly generated subgraphs are similar. The similarity judgment algorithm is a seed multi-component simultaneous growth algorithm.

[0088] In another exemplary embodiment of this application, the cost model adopted above is designed to achieve optimal performance under predefined input and output constraints, and can be summarized as formula (1).

[0089] score=∏constraint i ×merit (1)

[0090] In the public domain, "score" represents the evaluation score, and "constraint" represents the performance factor. i Let represent the i-th constraint term, and 'merit' represent the benefit term. This embodiment employs four constraints: convexity, input-output constraints (io_num), acyclicity, and connectivity. If the inputs and outputs of the subgraph exceed the limits, the input-output constraints will be 0. Convexity ensures that the subgraph can become a dedicated instruction. For example... Figure 10 As shown, non-convex means that there exists a path (3->2->0) between two nodes (3 and 0) outside the subgraph. In this case, node 2 needs both the output of the candidate (consisting of nodes 0, 1, and 3) and the input of the subgraph, so the candidate cannot be used as a new instruction. Merit only applies to ∏constraint. i It takes effect when the value is equal to 1.

[0091]

[0092] Formula (2) shows the method for calculating the benefit item merit, where, To measure the potential performance improvement of the i-th candidate component, io_score is the number of times the basic block containing the i-th component is executed. i It is used to evaluate the Euclidean distance between the input and output formats of the i-th component and a predefined threshold.

[0093]

[0094] Formula (3) Calculation α is an empirical parameter. Calculate the total latency for sequential execution and execution of all instructions along the critical path in the i-th component, respectively.

[0095]

[0096] Formulas (4) to (6) together constitute io_score i The calculation method. and represent the number of inputs and outputs for the i-th candidate component, respectively. It is a predefined maximum threshold. i The coordinates corresponding to the number of inputs and outputs. With threshold coordinates The Euclidean distance between them, where l is the Euclidean distance from the threshold coordinates to the origin (0,0). io_score i It's a value between 0 and 1, indicating that the closer it is to the predefined threshold for the number of inputs and outputs, the better. It's worth noting that `io_score`... i `io_num` can be preset to 1, allowing the cost model to ignore the influence of the number of inputs and outputs in the subgraph. `pow` and `sqrt` represent exponentiation and square root operations, respectively.

[0097] In another exemplary embodiment of this application, when the seed growth method is applied to each seed separately, the influence of other seeds during seed growth is not taken into account, which may lead to overlap between candidates. For example... Figure 5 As shown, candidate 0 and candidate 1 share two nodes, A and B. These overlapping nodes cannot be accelerated by multiple dedicated instructions, so it is necessary to select the optimal one. Based on this, maximum weighted independent set analysis and iterative search are performed to eliminate the overlap between candidates. Wherein:

[0098] (1) Maximum Weighted Independent Set Analysis. Two candidate options with overlapping nodes are considered to be in conflict, thus constructing a conflict graph. For example... Figure 6As shown, candidate 0 and candidate 1 conflict, therefore there is an edge between their corresponding nodes. Selecting one or more non-conflicting optimal candidates can be viewed as solving the maximum weighted independent set problem, which is used to identify the independent set with the maximum total score. A weighted independent set is a set of nodes in a graph, each node has a weight, and there are no edges between them. In this embodiment, nodes 0 and 1, and nodes 1 and 2 are two independent sets. Using the scores generated by the cost model as weights, a maximum weighted independent set analysis method based on the Bron-Kerbosch algorithm is implemented to find the independent set with the maximum total score. For example, Figure 6 There are two independent sets. The independent set containing candidates 1 and 2 has a total score of 9, which is higher than the independent set containing candidates 0 and 2, so it will be selected.

[0099] (2) Iterative search. Some candidate options may still have the potential to accelerate the search even after resolving candidate conflicts, for example... Figure 5 The remaining three nodes of candidate 0 (excluding nodes A and B). In this case, an iterative method can be used. Each iteration starts from seed extraction and ends with the maximum weighted independent set analysis, after which the nodes contained in the extracted region of interest are removed from the subgraph. If it is still possible to extract the seed from the remaining nodes, a new iteration is started.

[0100] In another exemplary embodiment of this application, after extracting the region of interest (ROI), the method proposed by Novia is used to merge the ROIs to achieve reuse of dedicated functional units, thereby reducing the overhead of hardware implementation area. When extracting candidates, the method provided in this application considers the similarity of graphs to maintain candidate components with the same type and number of nodes, but this merging process can merge dissimilar graphs. Figure 9 As shown, Region of Interest 1 and Region of Interest 2 are two instructions, but in hardware implementation, they can share the hardware implementation corresponding to division and subtraction operations.

[0101] In another exemplary embodiment of this application, the results were verified using a simulator. Compared to not introducing dedicated instructions, CCExplorer achieved an average performance improvement of 1.36 times and a power consumption reduction of 17.12% on some common algorithms. On some deep neural network operators, it achieved an average performance improvement of 1.50 times and a power consumption reduction of 30.36%. Table 1 shows these benchmark programs.

[0102] Table 1 Benchmark Test Procedure Table

[0103] Some common algorithms Neural network operators Breadth-first search Average pooling layer Fast Fourier Transform Reshape operator Dense matrix multiplication Fully connected layer Sparse matrix-vector multiplication Residual calculation Molecular dynamics (K-nearest neighbor algorithm) depthwise convolution Molecular Dynamics (Grid Algorithm) Pointwise convolution 2D template calculation Convolutional layer 3D template calculation

[0104] like Figure 8As shown, CCExplorer takes the intermediate representation from the LLVM compiler as input and finds specialized instructions that satisfy the requirements for the number of repetitions and the number of inputs and outputs. For example... Figure 8 It includes dedicated instructions with 6 inputs / 1 output and dedicated instructions with 12 inputs / 3 outputs.

[0105] In summary, this application has the following advantages over the prior art:

[0106] 1. This application establishes CCExplorer, which can automatically explore specialized instructions and evaluate their performance, power consumption, and area end-to-end.

[0107] 2. This application proposes a seed growth method, which has the ability to consider code similarity across basic blocks during the candidate selection process, and can discover common and frequently executed code segments in the program as dedicated instructions. This method can extract code segments that appear repeatedly in the code with a specified number of inputs and outputs.

[0108] 3. This application proposes an iterative search strategy to fully explore possible special instructions based on solving the problem of overlapping candidate special instructions.

[0109] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 11 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores complex special-purpose instruction automatic data for the hardware. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a complex special-purpose instruction automatic design method for hardware.

[0110] Those skilled in the art will understand that Figure 11The structures shown are merely block diagrams of some structures related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0111] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0112] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0113] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0114] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0115] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchain. The processors involved in the embodiments provided in this application may be, but are not limited to, general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for automatically designing complex special-purpose instructions for hardware, characterized in that, The method for automatically designing complex special-purpose instructions for the hardware includes: The analysis program collects dynamic information, including the number of times the basic blocks are executed. The program is converted into an intermediate representation by the compiler, and based on the intermediate representation, the basic blocks in the program are converted into a data dependency graph; The data dependency graph is divided into subgraphs using prohibition instructions; the subgraphs contain only arithmetic instructions; the prohibition instructions include memory access instructions and branch instructions. Candidates are obtained based on the subgraph using a seed growth method; the seed growth method is a genetic algorithm that incorporates a seed multi-component simultaneous growth algorithm. Obtain the arithmetic instructions corresponding to the candidate options, evaluate the arithmetic instructions corresponding to the candidate options using a cost model, and use the candidate option with the highest evaluation score as the dedicated instruction; By integrating the sub-graphs corresponding to the dedicated instructions, dedicated functional units are generated, thus completing the automatic design of complex dedicated instructions for hardware.

2. The method for automatically designing complex special-purpose instructions for hardware according to claim 1, characterized in that, Candidates are obtained based on the subgraph using a seed growth method, specifically including: Extract a seed from the subgraph; the seed may be one or more; The seed is subjected to a genetic algorithm for growth, and during the process of invoking the genetic algorithm, a multi-component simultaneous growth algorithm for the seed is invoked to explore the code similarity between basic blocks, thereby obtaining a growth subgraph that repeatedly appears in the code and satisfies predefined conditions; the genetic algorithm includes selection, mutation, and crossover operations; Define a seed component; the defined seed component is an instance of the seed that exists in the same or different basic blocks. The growth subgraph that connects the nodes to the seed component is used as the candidate.

3. The method for automatically designing complex special-purpose instructions for hardware according to claim 2, characterized in that, Extracting the seed from the subgraph specifically includes: Extract recurring instruction pairs from the subgraph as seeds; The greedy strategy is used to iteratively extract the instruction pair with the longest total delay in the subgraph as the seed.

4. The method for automatically designing complex special-purpose instructions for hardware according to claim 3, characterized in that, The greedy strategy iteratively extracts the instruction pair with the longest total latency in the subgraph as the seed, specifically including... Traverse all nodes in the subgraph, identify and extract the node pair with the longest total delay, and remove the node pair with the longest total delay from the subgraph. Repeat this process until all nodes in the subgraph have been traversed. Then, use the instructions corresponding to all nodes with the longest total delay extracted from the subgraph as the seed.

5. The method for automatically designing complex special-purpose instructions for hardware according to claim 2, characterized in that, The method for automatically designing complex special-purpose instructions for the hardware also includes: After obtaining candidate options from all seeds using the seed growth method, a conflict graph is constructed for all candidate options. The evaluation score is used as the weight, and the independent set with the largest sum of weights is extracted from the conflict graph. The candidate options in the independent set are taken as the region of interest. The independent set refers to a group of nodes in the subgraph where there is no edge between any two nodes. The conflict refers to the subgraphs corresponding to two candidate options containing the same node. The node corresponding to the region of interest will be deleted from the subgraph, and the step of extracting the seed from the subgraph will be returned until no more seeds can be extracted. The regions of interest are merged to enable the reuse of dedicated functional units.

6. The method for automatically designing complex special-purpose instructions for hardware according to claim 1, characterized in that, The method for automatically designing complex special-purpose instructions for the hardware is based on a framework for automatically extracting and verifying instructions; the framework takes the intermediate representation of the compiler as input.

7. The method for automatically designing complex special-purpose instructions for hardware according to claim 1, characterized in that, The obtained candidate options do not overlap; overlapping candidate options refer to the subgraphs corresponding to different candidate options sharing one or more nodes.

8. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement a method for automatically designing complex special-purpose instructions for the hardware according to any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the method for automatically designing complex special-purpose instructions for the hardware as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the method for automatically designing complex special-purpose instructions for the hardware as described in any one of claims 1-7.

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