Heuristics and apparatus for multiple issue processor instruction reordering

Abstract

The application discloses a heuristic method suitable for instruction rearrangement of a multi-transmitter processor, comprising the following steps: in a data preparation stage, obtaining runtime parameters of each instruction according to instruction set information and functional unit information, obtaining a data dependency graph according to data dependency relationships between instructions, processing the data dependency graph to obtain transmission priorities of the instructions, and then in a simulation running stage, ensuring that the instruction transmission process meets constraint conditions of a parallel transmission instruction number, an available functional unit number and a pipeline function limit. The application also provides a device suitable for instruction rearrangement of the multi-transmitter processor. The application solves the problem of instruction parallel optimization caused by the performance decline of an application program due to the migration of assembly codes between different generations of a domestic Shenwei many-core processor, improves the program transplantation efficiency, and solves the adaptability problem of an application assembly program library to a dual-transmission pipeline microstructure compared with the prior art.

Description

Technical Field

[0001] This invention relates to the field of hardware and software collaboration technology for multi-issue processors, specifically to a heuristic method and apparatus for instruction reordering in multi-issue processors. Background Technology

[0002] On the existing domestic Shenwei many-core processor platform, writing program code at the assembly instruction level is a common optimization method to achieve higher program performance. However, when migrating existing assembly language programs to the new generation Shenwei processor, due to changes in the instruction set and microarchitecture, the original assembly instruction sequence cannot be well adapted to the new instruction set and microarchitecture, resulting in decreased program performance and failing to fully utilize the computing power of the new generation Shenwei processor. For example, to increase the clock frequency, a new model of Shenwei processor changed a specific instruction that originally only required one clock cycle to complete on the old model to complete three clock cycles. Therefore, after porting the assembly program code written for the old model to the new model, all instructions that depend on that specific instruction need to be issued at least two clock cycles apart, which may cause pipeline congestion and degrade application performance. To solve the problem of assembly program performance degradation caused by changes in the microarchitecture of multi-issue processors, instruction reordering based on the processor microarchitecture is an effective optimization method. Its basic principle is as follows: Figure 1 As shown.

[0003] Instruction reordering is an optimization of assembly instructions to reduce program execution time. In high-level language programs, instruction reordering is handled by the compiler backend. However, in assembly language program development for the Shenwei processor platform, due to the lack of suitable compiler optimization tools, instruction reordering must be manually performed by analyzing instruction dependencies and manually reordering instructions, significantly reducing the efficiency of program porting and optimization. Furthermore, existing instruction reordering algorithms in high-level language compilers are difficult to apply to the Shenwei processor. On the one hand, these compilers cannot grasp the accurate microarchitecture information of the Shenwei processor; on the other hand, existing instruction reordering algorithms such as list scheduling are not suitable for the dual-pipeline architecture of the Shenwei processor's slave core. Taking the Shenwei 26010 processor as an example, its slave core's two pipelines execute instructions of different function types. In addition to scalar integer operations, pipeline 0 handles floating-point and vector operations, while pipeline 1 handles memory access and register communication. Existing instruction reordering methods do not systematically consider computational resources and the multi-issue pipeline microarchitecture.

[0004] Therefore, it is necessary to design efficient and high-quality assembly instruction reordering methods to improve the porting and optimization efficiency of assemblers on multi-issue processor platforms such as Shenwei many-core processors and improve program performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a heuristic method and apparatus for instruction reordering in multi-issue processors, so as to optimize assembly instruction ordering and improve instruction-level parallelism while ensuring the correctness of the algorithm.

[0006] To address the aforementioned technical problems, this invention provides an apparatus for instruction reordering in multi-issue processors, comprising: an input module, an assembly instruction reordering device, and an output module connected sequentially; the input module includes a code block input module to be ordered and a microarchitecture / instruction set information input module; the assembly instruction reordering device includes a microarchitecture / instruction set information processing module, a data dependency graph acquisition and reordering priority calculation module, a functional unit operation simulation module, and a register renaming logic module; the output of the microarchitecture / instruction set information input module is connected to the input of the microarchitecture / instruction set information processing module, the output of the code block input module to be ordered is connected to the input of the data dependency graph acquisition and processing module, and the output of the microarchitecture / instruction set information processing module is connected to the data dependency graph... The inputs of the acquisition and processing module and the scheduling priority acquisition and processing module are connected. The output of the data dependency graph acquisition and processing module is connected to the inputs of the scheduling priority acquisition and processing module and the breadth-first search module, respectively. The output of the scheduling priority acquisition and processing module is connected to the input of the breadth-first search module. The output of the breadth-first search module is connected to the input of the functional unit scoreboard. The output of the functional unit scoreboard is connected to the input of the structural hazard judgment module. The output of the structural hazard judgment module is connected to the input of the read-before-write / write-before-write data dependency judgment module. The input of the read-before-write / write-before-write data dependency judgment module is connected to the input of the register renaming application module. The output of the register renaming application module is connected to the input of the output module.

[0007] The present invention also provides a heuristic method for instruction reordering suitable for multiple issue processors using the aforementioned apparatus for instruction reordering suitable for multiple issue processors, comprising the following steps:

[0008] S1, Data Preparation Stage

[0009] The input module and the microstructure / instruction set information processing module obtain the runtime parameters of each instruction based on the instruction set information and functional unit information, including instruction format, instruction cycle, relevant data of the functional unit used, execution timing relevant data, and relevant data of available registers; based on the instruction information after matching the instruction set and functional unit, they are matched to the instruction sequence to be processed, and a data dependency graph is obtained from the data dependency relationship between instructions.

[0010] S2: Dependency Graph Processing Stage

[0011] The data dependency graph acquisition and reordering priority calculation module abstracts the instruction reordering problem into a graph processing problem: it abstracts the data dependency relationship between instructions into edges between nodes in the graph, the earliest clock cycle that each instruction can be emitted into is abstracted into the longest path length between the node representing the instruction and the starting node in the graph, and the execution time of the instruction sequence into the longest path length from the starting node to the ending node in the graph; it obtains the farthest distance of each instruction from the starting instruction based on the dependency graph as the earliest clock cycle that the instruction can be emitted into, and calculates the emission priority of each instruction based on this path;

[0012] S3: Simulation Run Phase

[0013] The functional unit operation simulation module simulates the actual program execution process based on the processor's core microarchitecture, ensuring that the instruction issuance process meets the constraints of the number of parallel issued instructions, the number of available functional units, and pipeline function limitations. As the clock cycle progresses, starting from the highest priority node in the node set, it determines the currently issueable instructions that meet the data dependencies, checks whether there are functional unit structural hazards among the issueable instructions, adds instructions that meet the issuance conditions to the scheduled queue, delays the issuance time of instructions that do not meet the issuance conditions, updates the current instruction dependency data, and enters the next clock cycle. This process is repeated until all instructions are added to the scheduled queue. The determination of structural hazards is achieved by using a scoreboard with the maximum number of instruction cycles to record the current occupancy status of each functional unit at each stage, and the scoreboard is cyclically overwritten.

[0014] As an improvement to the heuristic method of instruction reordering applicable to multi-issue processors in this invention:

[0015] The specific process of the data preparation phase is as follows:

[0016] S11: Obtain processor slave core microstructure information through the microstructure / instruction set information input module;

[0017] S12: Obtain processor slave core instruction set information through the microstructure / instruction set information input module;

[0018] S13: In the microarchitecture / instruction set information processing module, the processor's core microarchitecture information and processor's core instruction set information are matched to the input assembly code segment instructions, and the destination register, source register, address offset, and the minimum number of clock cycles required from emission to data availability for each instruction are obtained or calculated.

[0019] S14: Based on the correspondence between source registers and destination registers between instructions, determine the three types of data dependencies between instructions: write-before-read, read-before-write, and write-before-write, and calculate the minimum number of clock cycles required for the transmission of instructions with dependencies, ins_interval.

[0020] S15: The data dependency graph acquisition and processing module uses nodes to represent assembly instructions and directed edges to represent the write-before-read dependency relationship between instructions to obtain a data dependency graph. The weight of the directed edge C from node A to node B is W, which means that there is a write-before-read data dependency between the instruction represented by node B and the instruction represented by node A. The instruction can only be issued at least W clock cycles after the instruction represented by node A is issued.

[0021] As a further improvement to the heuristic method of the present invention for instruction reordering in multi-issue processors:

[0022] The specific process of the dependency graph processing stage is as follows:

[0023] S21: Based on the data dependency graph, the scheduling priority acquisition and processing module determines the earliest clock cycle that each instruction can be emitted after the initial instruction is emitted. In the data dependency graph, this is the longest path from the starting point of the data dependency graph to the instruction node. The device uses breadth-first search on the data dependency graph from the starting node. For the currently searched node i, if all its predecessor nodes with direct edges have been searched and the interval between them and the current clock cycle is greater than or equal to the length of the corresponding edge, then the path length from the currently searched starting node to node i is the earliest clock cycle that instruction i represented by node i can be emitted after the initial instruction is emitted. Otherwise, it indicates that there is a predecessor instruction with data dependency on instruction i that has not yet been emitted or the emission interval does not meet the constraint, and instruction i does not meet the emission condition. Record the longest path corresponding to each searched node. If there are two longest paths with the same length, record them both. When determining the longest path, let the length of the longest path corresponding to the predecessor vertex j directly connected to node i be L. j The corresponding connecting edge length is W. ij Then the longest path length L corresponding to node i is i =max{L j +W ij After all nodes have been searched, the longest path of each node is recorded in all the records. The length of the longest path is used as the first priority during scheduling, and the longer the path, the higher the priority of the instruction.

[0024] S22: The scheduling priority acquisition and processing module determines whether each instruction can be issued on both pipelines, as well as its execution status and the number of available functional units, based on the processor's core functional unit information. This is recorded as the second priority. Instructions that can only be executed on one pipeline have a higher priority than instructions that can be executed on both pipelines. Instructions with fewer available functional units have a higher priority than instructions that may have more functional units. For functional units whose execution behavior cannot be determined before program execution, or instructions whose functional units cannot be determined before program execution, all possible situations and their occurrence conditions are listed when inputting information. When calculating the number of available units for an instruction and various timing characteristics, the worst-case scenario is used.

[0025] S23: The scheduling priority acquisition and processing module determines the number of subsequent vertices that have a direct dependency relationship with each node based on the data dependency graph, which is recorded as the third priority. Instructions that have a direct dependency relationship with more subsequent nodes have a higher priority.

[0026] S24: The breadth-first search module integrates the scheduling priority information, groups the nodes according to the critical path length from the starting point to the node and arranges them in ascending order. Within each group, the nodes in the node set are sorted according to the priority relationship of first priority > second priority > third priority to obtain the instruction sorting after preliminary rearrangement. Each group represents the set of instructions that can be issued in the clock cycle corresponding to the critical path length when hardware resource limitations and write-before-read and write-before-write data dependencies are not considered.

[0027] As a further improvement to the heuristic method of the present invention for instruction reordering in multi-issue processors:

[0028] The specific process of the simulation operation phase is as follows:

[0029] S31: Starting from the starting node in the rearranged node set obtained in step S24, let the current clock cycle be C, determine the set of unscheduled nodes with critical path length L≤C between the starting node, that is, the set of identifiable instructions that satisfy the write-then-read data dependency in the current clock cycle, and retain the scheduling priority order.

[0030] S32: The functional unit scoreboard sets up a running status record table for each of the two pipelines according to the processor's core pipeline issue execution logic, recording the current execution status of all issued instructions and the occupancy status of each functional unit in the two pipelines. The structural hazard judgment module starts from the node with the highest priority in the node set, and judges whether there is a structural hazard in the instruction issued by the current node according to the processor instruction issue logic. If there is no structural hazard, proceed to step S33; otherwise, repeat step S32.

[0031] S33: The read-before-write / write-before-write data dependency judgment module determines whether the instruction issued by the current node has a read-before-write or write-before-write data dependency. If it does not exist or the dependency condition is met, the current node is added to the scheduled queue, the corresponding pipeline's running status record table is updated according to the processor's issue logic, and the process proceeds to step S34. Otherwise, the process returns to step S32. Thus, the instructions in the scheduled queue do not have data hazards or structural hazards during the issue execution process.

[0032] S34: Determine whether the number of scheduled nodes in the current clock cycle has reached the upper limit of the number of instructions that can be issued. If it has, proceed to step S36. Otherwise, determine whether all instructions that can be issued in the current clock cycle have been evaluated. If there are still unevaluated instructions, return to step S32. If all the instructions that can be issued have been evaluated, continue to determine whether there are any instructions that are delayed due to data hazards and control hazards and are paused because they do not meet the data dependency of read-before-write or write-before-write. If there are no such instructions, proceed to step S36. Otherwise, proceed to step S35.

[0033] S35: The register renaming application module combines the register renaming operation with the instruction rearrangement operation to determine whether there is a free available register. If not, proceed to step S36. Otherwise, rename the destination register of the instruction represented by the current node and perform the same renaming operation on subsequent registers with the same name. Add the replaced register to the list of available registers and return to step S32 to determine whether the renamed instruction meets the launch conditions.

[0034] S36: Determine whether all nodes have been scheduled. If not, return to step S31. After all nodes have been scheduled, the output module outputs the rearranged assembly code segment.

[0035] As a further improvement to the heuristic method of the present invention for instruction reordering in multi-issue processors:

[0036] In the pipeline's operational status record table design, the maximum latency from instruction issuance to execution completion is set to T. T scoreboards are used to record the current usage of processor core functional units, including the occupancy and quantity of each functional unit at each stage in the current clock cycle, and the occupancy and quantity of each functional unit at each stage in the next T clock cycles. When determining whether the current instruction has a structural hazard, it is assumed that the instruction is issued in the current clock cycle. Based on the processor pipeline instruction issuance logic, the instruction issuance and subsequent execution are simulated to determine which pipeline the instruction will be executed on. It is also determined whether the number of available functional units in the corresponding pipeline is exceeded. If it is exceeded, the current instruction cannot be issued in that clock cycle. If the issuance conditions are met, the functional unit usage of the instruction is updated to the scoreboard.

[0037] When reordering instructions based on two pipelines with different functions, consider the following three cases:

[0038] (1). If the two instructions selected based on priority can be executed on both pipelines, then there is no need to consider the pipeline difference when issuing instructions. If it is determined that there is a structural hazard in the instruction issuance execution, first consider swapping the order of the two instructions, changing the pipeline in which they are located, and re-judging. If the issuance conditions are still not met, then select the instruction with higher priority from the sequence of instructions to be issued that can meet the issuance conditions.

[0039] (2) If one of the two launchable instructions selected based on priority can only be executed on one pipeline, then the order of the two instructions needs to be adjusted according to the pipeline launch rules to ensure that the instructions are executed on the corresponding pipeline and that the two instructions can be launched in parallel.

[0040] (3) If the two launchable instructions selected based on priority can only be executed on one of the pipelines, it is necessary to first determine whether the two instructions are on the same pipeline. If so, there is a structural hazard and the launch conditions are not met, so the launch instruction needs to be reselected. Otherwise, the order of the two instructions is adjusted according to the pipeline launch rules to ensure that the instructions are executed on the corresponding pipeline and that the two instructions can be launched in parallel.

[0041] As a further improvement to the heuristic method of the present invention for instruction reordering in multi-issue processors:

[0042] The launch priorities of each instruction are as follows: instructions on the critical path of program execution have higher priority than other instructions; instructions that can only be executed on one pipeline have higher priority than instructions that can be executed on two pipelines; instructions with fewer available functional units have higher priority than instructions that may have more functional units; and instructions that depend on more subsequent instructions have higher priority than instructions with lower dependencies.

[0043] As a further improvement to the heuristic method of the present invention for instruction reordering in multi-issue processors:

[0044] The clock cycle count ins_interval is as follows: Starting from the start instruction, it is sequentially determined whether the source register of the subsequent instruction j of instruction i matches the destination register of instruction i. If they match, there is a write-then-read data dependency between instruction j and instruction i, and the clock cycle count of the minimum time interval between the two instruction issuances is ins_interval_(i,j) = ins_dataAvail_i - ins_dataReady_i; Starting from the start instruction, it is sequentially determined whether the destination register of the subsequent instruction j of instruction i matches the destination register of instruction i. If they match, there is a write-then-write data dependency between instruction j and instruction i, and the clock cycle count of the minimum time interval between the two instruction issuances is ins_interval_(i,j) = 1; Starting from the start instruction, it is sequentially determined whether the destination register of the subsequent instruction j of instruction i matches the source register of instruction i. If they match, there is a read-then-write data dependency between instruction j and instruction i, and the clock cycle count of the minimum time interval between the two instruction issuances is ins_interval_(i,j) = 1.

[0045] When determining the write-before-read and write-before-write data dependencies between instructions i and j, if instruction z modifies the destination register value of instruction i, then subsequent instructions of instruction z will not have a direct write-before-read or write-before-write data dependency with instruction i, and the determination will not continue. When determining the read-before-write data dependency between instructions i and j, if instruction z modifies the source register value of instruction i that has a read-before-write data dependency, then subsequent instructions of instruction z will not have a direct read-before-write data dependency with instruction i, and the determination will not continue.

[0046] The beneficial effects of this invention are mainly reflected in:

[0047] To address the instruction parallelism optimization problem caused by the performance degradation of applications when migrating assembly code between different generations of the domestic Shenwei many-core processor, a heuristic method for assembly instruction rearrangement adapted to multi-issue processor microarchitectures is proposed. This method utilizes data dependency graph processing, breadth-first search, and register renaming to maximize code instruction parallelism in an efficient and flexible manner. On the one hand, it avoids manual assembly optimization, improving program porting efficiency; on the other hand, compared to existing algorithms, it overcomes the challenge of adapting assembler libraries to dual-issue pipelined microarchitectures. Attached Figure Description

[0048] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0049] Figure 1 A schematic diagram illustrating the basic principle of instruction rearrangement for processor microarchitecture;

[0050] Figure 2This is a schematic diagram of the apparatus for the heuristic method of instruction reordering applicable to multi-issue processors of the present invention;

[0051] Figure 3 This is a schematic diagram of the data preparation stage of the heuristic method for instruction reordering applicable to multi-issue processors according to the present invention.

[0052] Figure 4 This is a schematic diagram of the dependency graph processing stage of the heuristic method for instruction reordering applicable to multi-issue processors according to the present invention.

[0053] Figure 5 This is a schematic diagram of data dependency graphs and paths;

[0054] Figure 6 This is a schematic diagram illustrating the simulation process of the heuristic method for instruction reordering applicable to multi-issue processors of the present invention.

[0055] Figure 7 A schematic diagram illustrating the changes in instruction dependency caused by modifications to the microstructure. Detailed Implementation

[0056] The present invention will be further described below with reference to specific embodiments, but the scope of protection of the present invention is not limited thereto:

[0057] Example 1: An apparatus suitable for a heuristic method of instruction reordering in multi-issue processors, such as... Figure 2As shown, the input module 200, the assembly instruction reordering device 100, and the output module 300 are connected in sequence. The input module 200 includes a code block input module 210 to be sorted and a microstructure / instruction set information input module 220. The assembly instruction reordering device 100 includes a microstructure / instruction set information processing module 110. The output of the microstructure / instruction set information input module 220 is connected to the input of the microstructure / instruction set information processing module 110. The output of the code block input module 210 to be sorted is connected to the input of the data dependency graph acquisition and processing module 121. The output of the microstructure / instruction set information processing module 110 is connected to the input of the data dependency graph acquisition and processing module 121 and the scheduling priority acquisition and processing module 122, respectively. The output of block 121 is connected to the inputs of the scheduling priority acquisition and processing module 122 and the breadth-first search module 123, respectively. The output of the scheduling priority acquisition and processing module 122 is connected to the input of the breadth-first search module 123. The output of the breadth-first search module 123 is connected to the input of the functional unit scoreboard 131. The output of the functional unit scoreboard 131 is connected to the input of the structural hazard judgment module 132. The output of the structural hazard judgment module 132 is connected to the input of the read-before-write / write-before-write data dependency judgment module 141. The input of the read-before-write / write-before-write data dependency judgment module 141 is connected to the input of the register renaming application module 142. The output of the register renaming application module 142 is connected to the input of the output module 300. Specifically:

[0058] The input module 200 includes a code block input module 210 for reordering and a microstructure / instruction set information input module 220, while the output module 300 is responsible for outputting the reordered assembly code segment according to the instruction specification. The assembly instruction reordering device 100 includes a microstructure / instruction set information processing module 110, a data dependency graph acquisition and reordering priority calculation module 120, a functional unit operation simulation module 130, and a register renaming logic module 140. The microarchitecture / instruction set information processing module 110 acquires the processor microarchitecture and instruction set information input from the input module 200 and performs necessary processing. The microarchitecture / instruction set information processing module 110 sends the processor functional unit information to the data dependency graph acquisition and processing module 121 and the scheduling priority acquisition and processing module 122, respectively. The data dependency graph acquisition and processing module 121, combined with the information from the code block input module 210, obtains the data dependency graph corresponding to the code segment and sends the data dependency graph to the scheduling priority acquisition and processing module 122 and the breadth-first search module 123, respectively. The scheduling priority acquisition and processing module 122 obtains the instruction launch priority relationship based on the data dependency graph and the processor functional unit information and sends the priority relationship to the breadth-first search module 123. The breadth-first search module 123, according to the designed search logic and the acquired instruction launch priority order, processes the data dependency graph corresponding to the code segment. The search is sorted according to the nodes in the dependency graph; the functional unit operation simulation module 130 includes a functional unit scoreboard 131 and a structural hazard judgment module 132, which are responsible for recording the current processor functional unit occupancy status and judging whether there is a structural hazard in the current instruction issuance, respectively. The breadth-first search module 123 obtains the search sorting results and, after passing through the functional unit operation simulation module 130, obtains the instruction sorting sequence without structural hazards, which is then used as the input of the register renaming logic module 140; the register renaming logic module 140 includes a read-before-write / write-before-write data dependency judgment module 141 and a register renaming application module 142, which are responsible for judging whether there is a false data hazard in the current instruction issuance and renaming the necessary instructions, respectively. After passing through the register renaming logic module 140, an instruction sequence that integrates instruction reordering and register renaming is obtained, and finally, the reordered code segment is output through the output module 300.

[0059] The method for performing multi-issue processor instruction reordering using a heuristic approach based on multi-issue processor instruction reordering mainly includes three main stages:

[0060] S1, Data Preparation Stage

[0061] Input module 200 and microarchitecture / instruction set information processing module 110 obtain runtime parameters for each instruction based on instruction set information and functional unit information, including instruction format, instruction cycle, relevant data of the functional unit used, execution timing data, and relevant data of available registers. Based on the instruction information after matching the instruction set and functional unit, they are matched to the instruction sequence to be processed, and the minimum pause time required between instructions is obtained from the data dependencies between instructions, i.e., the data dependency graph.

[0062] like Figure 3 As shown, it includes the following steps:

[0063] S11: Obtain the microarchitecture information of the slave core of the domestic Shenwei many-core processor through the microarchitecture / instruction set information input module 220, including the upper limit of the number of instructions that can be issued in parallel, the types of instructions that can be executed by each pipeline, the type of functional unit of each pipeline, the number of cycles that can be advanced before the source operands are available, the operation delay, the issue delay, and the number and delay of available units in each execution stage, and obtain the list of available free registers of the slave core of the domestic Shenwei many-core processor;

[0064] S12: Obtain instruction set information of the domestic Shenwei many-core processor through the microstructure / instruction set information input module 220, including instruction type, instruction format, whether to read or store instructions, and the functional unit to be used;

[0065] The microstructure information of the slave core of the domestic Shenwei many-core processor and the instruction set information of the slave core need to be obtained in steps S11 and S12, as shown in Table 1.

[0066] Table 1: Microstructure information and instruction set information of the slave cores in the Shenwei many-core processor

[0067]

[0068] The maximum number of clock cycles between instruction i being issued and the source operand being ready to complete in ins_dataReady i This equals the number of cycles that the functional unit used by instruction i can advance the instruction issuance before the source operand becomes available. The minimum number of clock cycles required from instruction i until data becomes available in ins_dataAvail i Equal to the operation delay of the functional unit used by instruction i

[0069] S13: In the microarchitecture / instruction set information processing module 110, the domestic Shenwei many-core processor is matched from the core microarchitecture information and instruction set information to the input assembly code segment instructions. In addition to the basic information mentioned in S11 and S12, the destination register, source register, address offset, and the minimum number of clock cycles required from emission to data availability for each instruction are obtained or calculated.

[0070] S14: Based on the correspondence between source registers and destination registers between instructions, determine the three types of data dependencies between instructions: write-before-read, read-before-write, and write-before-write, and calculate the minimum number of clock cycles required for the transmission of instructions with dependencies, ins_interval.

[0071] Starting from the initial instruction, sequentially check whether the source register of instruction j, which follows instruction i, matches the destination register of instruction i. If they match, then there is a write-then-read data dependency between instruction j and instruction i. The minimum time interval between the two instruction issuances is measured in clock cycles: ins_interval. i,j =ins_dataAvail i -ins_dataReady i Starting from the initial instruction, sequentially check if the destination register of instruction j, which follows instruction i, matches the destination register of instruction i. If they match, then there is a write-first-write data dependency between instruction j and instruction i. The minimum time interval between the two instruction issuances is measured in clock cycles, ins_interval. i,j =1; Starting from the initial instruction, sequentially check whether the destination register of instruction j, the subsequent instruction of instruction i, matches the source register of instruction i. If they match, then there is a read-then-write data dependency between instruction j and instruction i. The minimum time interval between the two instruction issuances is the number of clock cycles ins_interval. i,j =1.

[0072] When determining the write-before-read and write-before-write data dependencies between instructions i and j, if instruction z modifies the destination register value of instruction i, then subsequent instructions of instruction z will not have a direct write-before-read or write-before-write data dependency with instruction i, and the determination will not continue. When determining the read-before-write data dependency between instructions i and j, if instruction z modifies the source register value of instruction i that has a read-before-write data dependency, then subsequent instructions of instruction z will not have a direct read-before-write data dependency with instruction i, and the determination will not continue.

[0073] S15: The data dependency graph acquisition and processing module 121 uses nodes to represent assembly instructions and directed edges to represent the write-before-read dependency relationship between instructions to obtain a data dependency graph. The weight of the directed edge C from node A to node B is W, which means that there is a write-before-read data dependency between the instruction represented by node B and the instruction represented by node A. The instruction can only be issued at least W clock cycles after the instruction represented by node A is issued.

[0074] S2: Dependency graph processing stage:

[0075] The data dependency graph acquisition and reordering priority calculation module 120 abstracts the instruction reordering problem into a graph processing problem: it abstracts the data dependencies between instructions as edges between nodes in the graph; it abstracts the earliest clock cycle that each instruction can be emitted as the longest path length between the node representing the instruction and the starting node in the graph; and it abstracts the execution time of the instruction sequence as the longest path length from the starting node to the ending node in the graph. The scheduling priority acquisition and processing module obtains the farthest distance of each instruction from the starting instruction based on the dependency graph, i.e., the earliest clock cycle that the instruction can be emitted, and calculates the emission priority of each instruction based on this path. Instructions on the critical path of program execution have higher priority than other instructions; instructions that can only be executed on one pipeline have higher priority than instructions that can be executed on two pipelines; instructions with fewer available functional units have higher priority than instructions that may have more functional units; and instructions that have dependencies on more subsequent instructions have higher priority than instructions with lower dependencies. The process is as follows: Figure 4 As shown, the details are as follows:

[0076] S21: Based on the data dependency graph, such as Figure 5 As shown, the scheduling priority acquisition and processing module 122 determines the earliest clock cycle that each instruction can be emitted after the initial instruction is emitted, i.e., the critical path that determines the execution time from the initial instruction to the current instruction. In the data dependency graph, this is the longest path from the starting point of the data dependency graph to the instruction node. The breadth-first search module 123 performs a breadth-first search on the data dependency graph from the starting node. For the currently searched node i, if all its predecessor nodes with direct edges have been searched and the interval between them and the current clock cycle is greater than or equal to the length of the corresponding edge, then the path length from the currently searched starting node to node i is the earliest clock cycle that instruction i represented by node i can be emitted after the initial instruction is emitted. Otherwise, it indicates that there is a predecessor instruction with data dependency on instruction i that has not yet been emitted or the emission interval does not meet the constraint, and instruction i does not meet the emission condition. The longest path corresponding to each searched node is recorded. If there are two longest paths with the same length, both are recorded. When determining the longest path, let the length of the longest path corresponding to the predecessor vertex j directly connected to node i be L. j The corresponding connecting edge length is W. ijThen the longest path length L corresponding to node i is i =max{L j +W ij After all nodes have been searched, the length of the longest path (a node is on a path, but not necessarily the end point of the path) of each node in all the recorded paths is recorded as the first priority during scheduling, where instructions with longer paths have higher priority;

[0077] S22: The scheduling priority acquisition and processing module 122, based on the core functional unit information of the domestically produced Shenwei many-core processor, determines whether each instruction can be issued on both pipelines, its execution status after issuance, and the number of available functional units, which is recorded as the second priority. Instructions that can only be executed on one pipeline have a higher priority than instructions that can be executed on both pipelines. Instructions with fewer available functional units have a higher priority than instructions that may have more functional units. For functional units whose execution behavior cannot be determined before program execution, or instructions whose functional units cannot be determined before program execution, all possible situations and their occurrence conditions are listed when relevant information is input. When calculating the number of available units and timing characteristics of instructions, the worst-case scenario is used.

[0078] S23: The scheduling priority acquisition and processing module 122 determines the number of subsequent vertices that have a direct dependency relationship with each node based on the data dependency graph, that is, the number of different nodes pointed to by the edge issued by the instruction node in the data dependency graph, which is recorded as the third priority. Instructions that have a direct dependency relationship with more subsequent nodes have a higher priority.

[0079] S24: The breadth-first search module 123 integrates the scheduling priority information, groups the nodes according to the critical path length from the starting point to the node and arranges them in ascending order. Within each group, the nodes in the node set are sorted according to the priority relationship of first priority > second priority > third priority to obtain the instruction order after preliminary rearrangement. Each group represents the set of instructions that can be issued in the clock cycle corresponding to the critical path length when hardware resource limitations and write-before-read and write-before-write data dependencies are not considered.

[0080] S3: Simulation Run Phase

[0081] The functional unit operation simulation module 130 simulates the actual operation of the program based on the core microarchitecture of the domestic Shenwei many-core processor, ensuring that the instruction issuance process meets constraints such as the number of parallel issuance instructions and the number of available functional units. As the clock cycle progresses, starting from the highest priority node in the node set, it determines which instructions can be issued that meet the data dependencies, checks whether there are functional unit structural hazards, adds instructions that meet the issuance conditions to the scheduled queue, delays the issuance time of instructions that do not meet the issuance conditions, updates the current instruction dependency data, and enters the next clock cycle. This process is repeated until all instructions are added to the scheduled queue. The determination of structural hazards is achieved by using a scoreboard with the maximum number of instruction cycles to record the current occupancy status of each functional unit at each stage. To save storage space, the scoreboard is cyclically overwritten. The process is as follows: Figure 6 As shown, the details are as follows:

[0082] S31: Starting from the starting node in the rearranged node set obtained in step S24, let the current clock cycle be C, determine the set of unscheduled nodes with critical path length L≤C between the starting node, that is, the set of identifiable instructions that satisfy the write-then-read data dependency in the current clock cycle, and retain the scheduling priority order.

[0083] S32: Functional unit scoreboard 131 sets up a running status record table for each of the two pipelines according to the execution logic of the domestic Shenwei many-core processor from the core pipeline. It records the current execution status of all issued instructions and the occupancy status of each functional unit of the two pipelines. The structural hazard judgment module 132 starts from the node with the highest priority in the node set and judges whether there is a structural hazard in the instruction issued by the current node according to the processor instruction issuance logic. If there is no structural hazard, proceed to step S33; otherwise, repeat step S32.

[0084] In the pipeline's operational status log design, the maximum instruction cycle, i.e., the maximum latency from instruction issuance to completion, is set to T. T scoreboards are used to record the current usage of the core functional units of the domestic Shenwei many-core processor, including the occupancy and quantity of each functional unit at each stage in the current clock cycle, and the occupancy and quantity of each functional unit at each stage in the next T clock cycles. To determine if a structural hazard exists for the current instruction, assuming the instruction is issued in the current clock cycle, the processor's pipeline instruction issuance logic is used to simulate the instruction issuance and subsequent execution. This determines which pipeline the instruction will execute on and whether the number of available functional units in the corresponding pipeline is exceeded. If it is exceeded, the current instruction cannot be issued in that clock cycle; otherwise, the issuance conditions are met, and no structural hazard occurs during the execution of the current instruction.

[0085] When performing structural hazard assessment and instruction sequence adjustment based on two pipelines with different functions, consider the following three scenarios:

[0086] (1). If the two instructions selected based on priority can be executed on both pipelines, then there is no need to consider the pipeline difference when issuing instructions. If it is determined that there is a structural hazard in the instruction issuance execution, first consider swapping the order of the two instructions, changing the pipeline in which they are located, and re-judging. If the issuance conditions are still not met, then select the instruction with higher priority from the sequence of instructions to be issued that can meet the issuance conditions.

[0087] (2) If one of the two launchable instructions selected based on priority can only be executed on one pipeline, then the order of the two instructions needs to be adjusted according to the pipeline launch rules to ensure that the instructions are executed on the corresponding pipeline and that the two instructions can be launched in parallel.

[0088] (3) If the two launchable instructions selected based on priority can only be executed on one of the pipelines, it is necessary to first determine whether the two instructions are on the same pipeline. If so, there is a structural hazard and the launch conditions are not met, so the launch instruction needs to be reselected. Otherwise, the order of the two instructions is adjusted according to the pipeline launch rules to ensure that the instructions are executed on the corresponding pipeline and that the two instructions can be launched in parallel.

[0089] S33: Read-before-write / Write-before-write data dependency judgment module 141 judges whether there is a read-before-write or write-before-write data dependency for the instruction issued by the current node. If there is no dependency or the dependency condition is met, the current node is added to the scheduled queue, the corresponding pipeline running status record table is updated according to the processor's issue logic, and the process proceeds to step S34. Otherwise, the process returns to step S32. Thus, the instructions in the scheduled queue obtained at this point do not have any data hazards or structural hazards during the issue execution process.

[0090] S34: Determine whether the number of scheduled nodes in the current clock cycle has reached the upper limit of the number of instructions that can be issued. If it has, proceed to step S36. Otherwise, determine whether all instructions that can be issued in the current clock cycle have been evaluated. If there are still unevaluated instructions, return to step S32. If all the instructions that can be issued have been evaluated, continue to determine whether there are any instructions that are delayed due to data hazards and control hazards and are paused because they do not meet the data dependency of read-before-write or write-before-write. If there are no such instructions, proceed to step S36. Otherwise, proceed to step S35.

[0091] S35: The register renaming application module 142 combines the register renaming operation with the instruction reordering operation to determine whether there is a free available register. If not, proceed to step S36. Otherwise, the register renaming logic module 140 renames the destination register of the instruction represented by the current node and performs the same renaming operation on subsequent registers with the same name. The replaced register is added to the list of available registers, and the process returns to step S32 to determine whether the renamed instruction meets the issue conditions.

[0092] When renaming registers, in order to ensure the normal functioning of the code segment, all subsequent registers with the same name as the register being replaced are replaced. This avoids complex judgment operations and allows the replaced registers to be added to the list of available registers for subsequent register renaming operations, thus avoiding register resource shortages.

[0093] S36: Determine whether all nodes have been scheduled. If not, return to step S31. After all nodes have been scheduled, the output module 300 is responsible for outputting the rearranged assembly code segment according to the instruction specification.

[0094] experiment:

[0095] To verify the beneficial effects of this invention, the embodiments were applied to the MD5 hash algorithm. The gem5 simulator was used as the experimental platform for the heuristic method and device of instruction reordering. Two different pipeline architectures were simulated during the upgrade of domestic many-core processors, where the instruction cycle of a specific instruction was changed from one cycle to three cycles to increase the clock frequency. The modification of the pipeline architecture caused changes in the correlation between instructions, such as... Figure 7 As shown, instructions that could originally be issued in two consecutive clock cycles must be delayed by two clock cycles due to data dependencies, increasing the number of clock cycles required for code execution and offsetting the performance improvement brought about by the increase in clock frequency. When this situation occurs in a certain proportion of all instructions executed, it will cause a performance degradation compared to the processor before the upgrade.

[0096] The experimental results are shown in Table 2. The microarchitecture and instruction set of CPU-SW5 are the same as those of the domestic many-core processor Shenwei 26010. CPU-SW7, compared to CPU-SW5, changes the clock cycle count for specific instructions, thereby altering the number of clock cycles required to pause when dependencies between instructions conflict. Assembly code 0 is the initial MD5 algorithm assembly code obtained by adapting and optimizing it according to the microarchitecture and instruction set information of CPU-SW5. Assembly code 0 contains 592 instructions, of which 64 are specific instructions. Assembly code 1 is the MD5 algorithm assembly code obtained by optimizing the instruction order based on the microarchitecture of CPU-SW7 using the method of this invention.

[0097] Table 2: Performance test results of multi-issue processors before and after instruction reordering

[0098] Test program CPU-SW5+ Code 0 CPU-SW7+ Code 0 CPU-SW7+ Code 1 Number of instructions 592 592 592 Execution clock cycles 331 442 345 Average number of instructions executed per clock cycle 1.79 1.34 1.72 Number of data adventures 67 179 95 Number of structural hazards 2 2 2 Number of idle cycles for no-command launch 1 111 1

[0099] Assembly code 0 achieved an average performance of 1.79 instructions per clock cycle on CPU-SW5. However, when running on CPU-SW7, the performance dropped to an average of only 1.34 instructions per clock cycle. After optimizing assembly code 0 using the instruction reordering method proposed in this invention, assembly code 1 was obtained. By filling in pipeline idle cycles caused by instruction dependencies, assembly code 1 achieved an average of 1.72 instructions per clock cycle on CPU-SW7. This verifies that this invention addresses the instruction-level parallelism optimization problem caused by the performance degradation of assemblers when migrating between domestic Shenwei many-core processors. It proposes a heuristic method and apparatus adapted to multi-issue processor microarchitectures for assembly instruction reordering, maximizing code-instruction parallelism in an efficient and flexible manner while ensuring correctness.

[0100] As can be seen from the above embodiments, the present invention, based on the core microstructure information and instruction set information of the domestically produced Shenwei many-core processor, rearranges the instructions of the input assembly code segment and renames the registers, thereby improving the instruction parallelism of code execution and shortening the overall execution time of the code.

[0101] Finally, it should be noted that the above examples are merely some specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments and many variations are possible. All variations that can be directly derived or conceived by those skilled in the art from the disclosure of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An apparatus suitable for instruction reordering in multi-issue processors, characterized in that... include: The input module, assembly instruction reordering device, and output module are connected sequentially. The input module includes a code block input module to be ordered and a microstructure / instruction set information input module. The assembly instruction reordering device includes a microstructure / instruction set information processing module, a data dependency graph acquisition and reordering priority calculation module, a functional unit operation simulation module, and a register renaming logic module. The output of the microstructure / instruction set information input module is connected to the input of the microstructure / instruction set information processing module. The output of the code block input module to be ordered is connected to the input of the data dependency graph acquisition and processing module. The output of the microstructure / instruction set information processing module is connected to both the data dependency graph acquisition and processing module and the scheduling priority acquisition and processing module. The inputs of the modules are connected. The output of the data dependency graph acquisition and processing module is connected to the inputs of the scheduling priority acquisition and processing module and the breadth-first search module, respectively. The output of the scheduling priority acquisition and processing module is connected to the input of the breadth-first search module. The output of the breadth-first search module is connected to the input of the functional unit scoreboard. The output of the functional unit scoreboard is connected to the input of the structural hazard judgment module. The output of the structural hazard judgment module is connected to the input of the read-before-write / write-before-write data dependency judgment module. The input of the read-before-write / write-before-write data dependency judgment module is connected to the input of the register renaming application module. The output of the register renaming application module is connected to the input of the output module. The data preparation stage is as follows: the input module and the microstructure / instruction set information processing module obtain the runtime parameters of each instruction based on the instruction set information and functional unit information, including instruction format, instruction cycle, relevant data of the functional unit used, execution timing relevant data, and relevant data of available registers; based on the instruction information after matching the instruction set and functional unit, they are matched to the instruction sequence to be processed, and a data dependency graph is obtained from the data dependency relationship between instructions; The specific process of the data preparation phase is as follows: The processor slave core microstructure information is obtained through the microstructure / instruction set information input module; The processor slave core instruction set information is obtained through the microstructure / instruction set information input module; In the microarchitecture / instruction set information processing module, the kernel microarchitecture information and the processor kernel instruction set information are matched to the input assembly code segment instructions, and the destination register, source register, address offset, and the minimum number of clock cycles required from emission to data availability for each instruction are obtained or calculated. Based on the correspondence between source and destination registers between instructions, determine the three types of data dependencies between instructions: write-before-read, read-before-write, and write-before-write, and calculate the minimum number of clock cycles required for the transmission of instructions with dependencies, ins_interval. The data dependency graph acquisition and processing module uses nodes to represent assembly instructions and directed edges to represent the write-before-read dependency relationship between instructions to obtain a data dependency graph. The weight of the directed edge C from node A to node B is W, which means that there is a write-before-read data dependency between the instruction represented by node B and the instruction represented by node A. The instruction can only be issued at least W clock cycles after the instruction represented by node A is issued.

2. A heuristic method for instruction reordering applicable to multiple issue processors using the apparatus for instruction reordering applicable to multiple issue processors as described in claim 1, characterized in that... Includes the following steps: S1, Data Preparation Stage; S2: Dependency Graph Processing Stage The data dependency graph acquisition and reordering priority calculation module abstracts the instruction reordering problem into a graph processing problem: it abstracts the data dependency relationship between instructions into edges between nodes in the graph, the earliest clock cycle that each instruction can be emitted into is abstracted into the longest path length between the node representing the instruction and the starting node in the graph, and the execution time of the instruction sequence into the longest path length from the starting node to the ending node in the graph; it obtains the farthest distance of each instruction from the starting instruction based on the dependency graph as the earliest clock cycle that the instruction can be emitted into, and calculates the emission priority of each instruction based on this path; S3: Simulation Run Phase The functional unit operation simulation module simulates the actual program execution process based on the processor's core microarchitecture, ensuring that the instruction issuance process meets the constraints of the number of parallel instruction issuances, the number of available functional units, and pipeline function limitations. As the clock cycle progresses, starting from the highest priority node in the node set, it determines which instructions can be issued that meet the data dependencies. It then determines whether there are any functional unit structural hazards among the issued instructions. Instructions that meet the issuance conditions are added to the scheduled queue, while the issuance time of instructions that do not meet the issuance conditions is delayed. The current instruction dependency data is updated, and the process is repeated until all instructions are added to the scheduled queue. The determination of structural hazards is achieved by using a scoreboard with the maximum number of instruction cycles to record the current occupancy status of each functional unit at each stage. The scoreboard is cyclically overwritten.

3. The heuristic method for instruction reordering in multi-issue processors according to claim 2, characterized in that: The specific process of the dependency graph processing stage is as follows: S21: Based on the data dependency graph, the scheduling priority acquisition and processing module determines the earliest clock cycle that each instruction can be emitted after the initial instruction is emitted. In the data dependency graph, this is the longest path from the starting point of the data dependency graph to the instruction node. The device uses a breadth-first search on the data dependency graph from the starting node. For the currently searched node i, if all its predecessor nodes with direct edges have been searched and the interval between them and the current clock cycle is greater than or equal to the length of the corresponding edge, then the path length from the currently searched starting node to node i is the earliest clock cycle that instruction i represented by node i can be emitted after the initial instruction is emitted. Otherwise, it indicates that there is a predecessor instruction with data dependency on instruction i that has not yet been emitted or the emission interval does not meet the constraint, and instruction i does not meet the emission condition. Record the longest path corresponding to each searched node. If there are two longest paths with the same length, record them both. When determining the longest path, let the length of the longest path corresponding to the predecessor vertex j directly connected to node i be 1. The corresponding connecting edge length is Then the longest path length corresponding to node i After all nodes have been searched, the paths of all records are recorded. The length of the longest path containing each node is used as the first priority during scheduling, with instructions on longer paths having higher priority. S22: The scheduling priority acquisition and processing module determines whether each instruction can be issued on both pipelines, as well as its execution status and the number of available functional units, based on the processor's core functional unit information. This is recorded as the second priority. Instructions that can only be executed on one pipeline have a higher priority than instructions that can be executed on both pipelines. Instructions with fewer available functional units have a higher priority than instructions that may have more functional units. For functional units whose execution behavior cannot be determined before program execution, or instructions whose functional units cannot be determined before program execution, all possible situations and their occurrence conditions are listed when inputting information. When calculating the number of available units for an instruction and various timing characteristics, the worst-case scenario is used. S23: The scheduling priority acquisition and processing module determines the number of subsequent vertices that have a direct dependency relationship with each node based on the data dependency graph, which is recorded as the third priority. Instructions that have a direct dependency relationship with more subsequent nodes have a higher priority. S24: The breadth-first search module integrates the scheduling priority information, groups the nodes according to the critical path length from the starting point to the node and arranges them in ascending order. Within each group, the nodes in the node set are sorted according to the priority relationship of first priority > second priority > third priority to obtain the instruction sorting after preliminary rearrangement. Each group represents the set of instructions that can be issued in the clock cycle corresponding to the critical path length when hardware resource limitations and write-before-read and write-before-write data dependencies are not considered.

4. The heuristic method for instruction reordering in multi-issue processors according to claim 3, characterized in that: The specific process of the simulation operation phase is as follows: S31: Starting from the starting node in the rearranged node set obtained in step S24, let the current clock cycle be C, determine the set of unscheduled nodes with critical path length L≤C between the starting node, that is, the set of identifiable instructions that satisfy the write-then-read data dependency in the current clock cycle, and retain the scheduling priority order. S32: The functional unit scoreboard sets up a running status record table for each of the two pipelines according to the processor's core pipeline issue execution logic, recording the current execution status of all issued instructions and the occupancy status of each functional unit in the two pipelines. The structural hazard judgment module starts from the node with the highest priority in the node set, and judges whether there is a structural hazard in the instruction issued by the current node according to the processor instruction issue logic. If there is no structural hazard, proceed to step S33; otherwise, repeat step S32. S33: The read-before-write / write-before-write data dependency judgment module determines whether the instruction issued by the current node has a read-before-write or write-before-write data dependency. If it does not exist or the dependency condition is met, the current node is added to the scheduled queue, the corresponding pipeline's running status record table is updated according to the processor's issue logic, and the process proceeds to step S34. Otherwise, the process returns to step S32. Thus, the instructions in the scheduled queue do not have data hazards or structural hazards during the issue execution process. S34: Determine whether the number of scheduled nodes in the current clock cycle has reached the upper limit of the number of instructions that can be issued. If it has, proceed to step S36. Otherwise, determine whether all instructions that can be issued in the current clock cycle have been evaluated. If there are still unevaluated instructions, return to step S32. If all the instructions that can be issued have been evaluated, continue to determine whether there are any instructions that are delayed due to data hazards and control hazards and are paused because they do not meet the data dependency of read-before-write or write-before-write. If there are no such instructions, proceed to step S36. Otherwise, proceed to step S35. S35: The register renaming application module combines the register renaming operation with the instruction rearrangement operation to determine whether there is a free available register. If not, proceed to step S36. Otherwise, rename the destination register of the instruction represented by the current node and perform the same renaming operation on subsequent registers with the same name. Add the replaced register to the list of available registers and return to step S32 to determine whether the renamed instruction meets the launch conditions. S36: Determine whether all nodes have been scheduled. If not, return to step S31. After all nodes have been scheduled, the output module outputs the rearranged assembly code segment.

5. The heuristic method for instruction reordering in multi-issue processors according to claim 4, characterized in that: In the pipeline's operational status record table design, the maximum latency from instruction issuance to execution completion is set to T. T scoreboards are used to record the current usage of processor core functional units, including the occupancy and quantity of each functional unit at each stage in the current clock cycle, and the occupancy and quantity of each functional unit at each stage in the next T clock cycles. When determining whether the current instruction has a structural hazard, it is assumed that the instruction is issued in the current clock cycle. Based on the processor pipeline instruction issuance logic, the instruction issuance and subsequent execution are simulated to determine which pipeline the instruction will be executed on. It is also determined whether the number of available functional units in the corresponding pipeline is exceeded. If it is exceeded, the current instruction cannot be issued in that clock cycle. If the issuance conditions are met, the functional unit usage of the instruction is updated to the scoreboard. When reordering instructions based on two pipelines with different functions, consider the following three cases: (1). If the two instructions selected based on priority can be executed on both pipelines, then there is no need to consider the pipeline difference when issuing instructions. If it is determined that there is a structural hazard in the instruction issuance execution, first consider swapping the order of the two instructions, changing the pipeline they are in, and re-judging. If the issuance conditions are still not met, then select the instruction with higher priority from the sequence of instructions to be issued that can meet the issuance conditions. (2). If one of the two launchable instructions selected based on priority can only be executed on one pipeline, then the order of the two instructions needs to be adjusted according to the pipeline launch rules to ensure that the instructions are executed on the corresponding pipeline and that the two instructions can be launched in parallel. (3). If the two launchable instructions selected based on priority can only be executed on one of the pipelines, it is necessary to first determine whether the two instructions are on the same pipeline. If so, there is a structural hazard and the launch conditions are not met, so the launch instruction needs to be reselected. Otherwise, the order of the two instructions is adjusted according to the pipeline launch rules to ensure that the instructions are executed on the corresponding pipeline and that the two instructions can be launched in parallel.

6. The heuristic method for instruction reordering in multi-issue processors according to claim 5, characterized in that: The launch priorities of each instruction are as follows: instructions on the critical path of program execution have higher priority than other instructions; instructions that can only be executed on one pipeline have higher priority than instructions that can be executed on two pipelines; instructions with fewer available functional units have higher priority than instructions that may have more functional units; and instructions that depend on more subsequent instructions have higher priority than instructions with lower dependencies.

7. The heuristic method for instruction reordering in multi-issue processors according to claim 6, characterized in that: The clock cycle count ins_interval is specifically defined as follows: starting from the initial instruction, sequentially checking whether the source register of instruction j, a subsequent instruction of instruction i, matches the destination register of instruction i. If they match, then there is a write-then-read data dependency between instruction j and instruction i, and the clock cycle count is the minimum time interval between the two instruction issuances. Starting from the initial instruction, sequentially check if the destination register of instruction j, which follows instruction i, matches the destination register of instruction i. If they match, then there is a write-first-write data dependency between instruction j and instruction i. The minimum time interval between the two instruction issuances is the number of clock cycles. Starting from the initial instruction, sequentially check whether the destination register of instruction j, which follows instruction i, matches the source register of instruction i. If they match, then there is a read-then-write data dependency between instruction j and instruction i. The minimum time interval between the two instruction issuances is the number of clock cycles. ; When determining the write-before-read and write-before-write data dependencies between instructions i and j, if instruction z modifies the destination register value of instruction i, then subsequent instructions of instruction z will not have a direct write-before-read or write-before-write data dependency with instruction i, and the determination will not continue. When determining the read-before-write data dependency between instructions i and j, if instruction z modifies the source register value of instruction i that has a read-before-write data dependency, then subsequent instructions of instruction z will not have a direct read-before-write data dependency with instruction i, and the determination will not continue.

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