A data processing method based on FlexE layer cross-connect

Abstract

The application discloses a data processing method based on FlexE layer cross connection, comprising the following steps: constructing cross connection between two FlexE board cards in a network node; wherein each FlexE board card comprises a line side FlexE group and a system side FlexE group; each FlexE group comprises a plurality of PHY interfaces of the same type; each PHY interface comprises a plurality of lanes and supports a plurality of FlexE channels; the data structure of the line side FlexE group and the system side FlexE group in each FlexE board card is defined, and data processing from the line side to the system side and from the system side to the line side is performed; the method improves the reliability and real-time performance of data cross connection transmission between the local FlexE board card and the opposite FlexE board card through efficient processing of data transmission from the line side to the system side and vice versa in a single FlexE board card, and realizes performance optimization and stability enhancement of a slice packet network.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of 5G network transmission, and more particularly to a data processing method based on FlexE layer cross connection. BACKGROUND

[0002] In the field of high-speed data transmission today, with the rapid development of communication technology, higher requirements are put forward for the delay and bandwidth of data transmission. As a key technology defined by the Optical Internetworking Forum (OIF) standard, Flexible Ethernet (FlexE) plays an important role in 5G SPN (Slicing Packet Network).

[0003] FlexE technology not only supports flexible connection scheduling of Ethernet packet, but also has SPN channel switching capability, supports FlexE layer data cross connection (referring to the exchange and connection of data directly between FlexE channels at the physical level, without the need for higher layer processing), and ensures the hard pipe isolation and bandwidth guarantee of the service.

[0004] In the existing FlexE channel data cross connection processing, it usually relies on a dedicated network processor (NP) to realize. This processing method needs to go through multiple processing links, including the interconnection of FlexE module and NP through Interlaken bus interface, data slice reassembly (SAR) processing, data transmission of Interlaken interface, etc. These links not only increase the complexity of processing, but also cause high latency.

[0005] Specifically, the existing scheme involves the interconnection of multiple processing modules and interfaces, and each link may introduce additional processing delay. And the SAR module performs data slice reassembly between the FlexE module and the NP, which increases the overall latency due to the additional overhead generated in this process.

[0006] Due to the excessive processing links, the one-layer data cross processing delay is high, usually about 8us, which cannot meet the requirement of ITU-T standard that the access device single node delay is less than 3us, and it is difficult to meet the current network communication demand for low latency and high bandwidth data transmission.

[0007] Therefore, how to design a data processing method based on FlexE layer cross connection to reduce the multi-link data processing steps and ensure low delay, high reliability and scalability of data transmission is a problem that needs to be solved by those skilled in the art. SUMMARY

[0008] Therefore, the application provides a data processing method based on FlexE layer cross connection, which reduces the multi-link data conversion and processing steps by performing cross connection of FlexE layer data, thereby significantly reducing the single node layer data exchange delay, supporting flexible bandwidth configuration and efficient data verification mechanism, ensuring low delay, high reliability and scalable data transmission, and being particularly suitable for 5G transmission and other extremely high performance requirement application scenarios.

[0009] In order to achieve the above purpose, the application adopts the following technical solutions:

[0010] The embodiment provides a data processing method based on FlexE layer cross connection, comprising the following steps:

[0011] S1, cross connection between two FlexE board cards in a network node is constructed; wherein each FlexE board card comprises a line side FlexE Group and a system side FlexE Group; each FlexE Group comprises a plurality of PHY interfaces of the same type; each PHY interface comprises a plurality of lanes and supports a plurality of FlexE Channels;

[0012] S2, the data structure of the line side FlexE Group and the system side FlexE Group in each FlexE board card is defined, and data processing from the line side to the system side and from the system side to the line side is performed;

[0013] The data processing from the line side to the system side comprises:

[0014] S211, the data of each FlexE Channel in the line side FlexE Group of the local FlexE board card is framed, verified and scrambled, and stored in a layer data FIFO buffer;

[0015] S212, forwarded to the system side FlexE Group of the local FlexE board card, and sent to the corresponding FlexE Channel of the line side FlexE Group of the opposite FlexE board card;

[0016] The data processing from the system side to the line side comprises:

[0017] S221, receiving the data of each FlexE Channel in the system side FlexE Group of the opposite FlexE board card and performing frame stripping, descrambling and verification processing, and storing in a layer data FIFO buffer;

[0018] S222, forwarded to the line side FlexE Group of the local FlexE board card.

[0019] Further, the S1 comprises:

[0020] The FlexE Channel for cross-connection between two FlexE board cards is determined, and the same bandwidth is configured for the FlexE Channel for cross-connection.

[0021] Further, in the S2, when the type of the PHY interface is a 100G PHY interface, the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board card is defined, comprising:

[0022] The data structure of the line-side FlexE Group is defined:

[0023] Each 100G PHY interface comprises four Lanes, and the data of each Lane is processed in a 66-bit block unit; each FlexE Channel transmits and receives a data structure composed of a 4*66-bit data block, a 5-bit Channel id, and a 1-bit Sync for each 100G PHY interface; the data structure is a total of 270 bits;

[0024] The data structure of the system-side FlexE Group is defined:

[0025] The 270-bit data of each 100G PHY interface is divided into five Lanes for transmission, each Lane transmits a 54-bit data frame, and a sixth Lane is used as a control frame;

[0026] The data structure of each data frame comprises 54-bit data, 1-bit SPR, 1-bit Skip, 1-bit Sync, and 7-bit BIP check bits; the data structure of the control frame comprises a 5-bit Channel id, a 10-bit valid transmission and reception frame counter CNT, a 40-bit Spare, a 1-bit Skip, a 1-bit Sync, and a 7-bit BIP check bit.

[0027] Further, when the type of the PHY interface is a 50G PHY interface, the data structure of the line-side FlexE Group and the system-side FlexE Group is defined, comprising:

[0028] The data structure of the line-side FlexE Group is defined:

[0029] Each 50G PHY interface includes 2 Lanes, and the data of each Lane is processed in units of 66-bit blocks; each FlexE Channel transmits and receives a data structure composed of 2*66-bit data blocks, 132-bit Skip, 5-bit Channel id, and 1-bit Sync for each 100G PHY interface; the data structure totals 270 bits;

[0030] The data structure for defining the system-side FlexE Group is the same as the definition under the 100G PHY interface.

[0031] Further, when the type of the PHY interface is K*100G PHY interface, where K is a positive integer and K≥2; the data structure for defining the line-side FlexE Group and the system-side FlexE Group includes:

[0032] Combination processing of the definition under the K 100G PHY interfaces.

[0033] Further, the valid frame counter CNT is incremented by 1 when a valid frame without Skip is transmitted or received.

[0034] Further, in the S2, the maximum FIFO data cache amount that can be supported by one layer of data FIFO buffer is 32*N*M*270 bits;

[0035] where the depth of one layer of data FIFO buffer is 32, and each FlexE Channel caches 32 270-bit data in one layer of data FIFO buffer for each 100G PHY interface; one layer of data FIFO buffer supports a maximum of N 100G PHY interfaces, where N is a positive integer and N≤4; and each 100G PHY interface supports a maximum of M FlexE channels, where M is a positive integer and M≤20.

[0036] Further, in the S2, the scrambling processing and descrambling processing generate a pseudo-random sequence using a linear feedback shift register LFSR;

[0037] The state of the linear feedback shift register LFSR is determined by the polynomial 1+x 39 +x 58 ; where x represents a one-time shift operation.

[0038] Further, in the S2, the check processing includes:

[0039] BIP check is performed, and data frames with abnormal check results in the data are ignored;

[0040] The Sync set check is performed, and the data frame with abnormal check result in the data is ignored;

[0041] The Skip set check is performed, and the data frame with abnormal check result in the data is ignored.

[0042] Further, the BIP check comprises:

[0043] The data after the descrambling processing is divided into 7 subsets, wherein each subset contains 8-bit data;

[0044] The parity check bit of all data bits in each subset is calculated, and a check result is generated.

[0045] The calculation of the parity check bit of all data bits in each subset comprises: if the sum of the values of all data bits in the subset is even, the corresponding check bit is set to 0; if the sum of the values of all data bits in the subset is odd, the corresponding check bit is set to 1.

[0046] According to the technical solution, compared with the prior art, the present application has the following advantages

[0047] Beneficial effects:

[0048] 1. By performing cross connection of FlexE layer 1 data, using layer 1 data FIFO buffer to cache and forward data, multiple fragmentation and reassembly and Interlaken channel conversion steps are avoided, and the single node layer 1 data exchange delay can be reduced to within 2 microseconds, not only meeting the 3-microsecond requirement of ITU-T for access equipment, but also providing better performance, which is particularly critical for application scenarios requiring low-delay communication.

[0049] 2. In the process of defining the data structure of the line side FlexE Group and the system side FlexE Group in each FlexE board, the layer 1 data FIFO buffer can support up to 20 FlexE channel data caches under each 100G PHY interface, and also supports multiple PHY interfaces of the same type (such as 100G PHY, 50G PHY, and 200G PHY). This allows the network to dynamically adjust the number of FlexE channels and their bandwidth allocation according to actual needs to adapt to different traffic patterns.

[0050] 3. The line side to system side and system side to line side data processing, provides an efficient data check mechanism, including BIP (bit check) check, Sync synchronization flag check and Skip skip flag check on the descrambled data. In addition, a linear feedback shift register (LFSR) is used to generate a pseudo-random sequence for data scrambling and descrambling. Together, they ensure the integrity and reliability of the data during transmission, effectively reduce the error rate, and enhance the overall security level of the system. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only a part of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0052] Figure 1 A flow chart of the data processing method based on FlexE layer cross connection provided by the embodiment of the present application is provided.

[0053] Figure 2 A data processing process diagram from the line side to the system side provided by the embodiment of the present application is provided.

[0054] Figure 3 A data processing process diagram from the system side to the line side provided by the embodiment of the present application is provided.

[0055] Figure 4 A connection structure diagram between end to end based on FlexE layer cross connection provided by the embodiment of the present application is provided.

[0056] Figure 5 A comparison diagram of FlexE layer cross connection and conventional FlexE cross connection provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0058] As shown in Figure 1 The present embodiment provides a data processing method based on FlexE layer cross connection, including the following steps:

[0059] S1, cross-connection between two FlexE board cards in a network node is constructed; wherein each FlexE board card includes a line-side FlexE Group and a system-side FlexE Group; each FlexE Group includes a plurality of PHY interfaces of the same type; each PHY interface includes a plurality of Lanes and supports a plurality of FlexE Channels;

[0060] S2, data structures of the line-side FlexE Group and the system-side FlexE Group in each FlexE board card are defined, and data processing from the line side to the system side and from the system side to the line side is performed;

[0061] As shown in Figure 2 , the data processing from the line side to the system side includes:

[0062] S211, data of each FlexE Channel in the line-side FlexE Group of the local FlexE board card is subjected to framing, checking and scrambling processing, and is stored in a layer of data FIFO buffer;

[0063] S212, forwarded to the system-side FlexE Group of the local FlexE board card, and sent to the corresponding FlexE Channel of the line-side FlexE Group of the opposite FlexE board card;

[0064] As shown in Figure 3 , the data processing from the system side to the line side includes:

[0065] S221, receiving data of each FlexE Channel in the system-side FlexE Group of the opposite FlexE board card and performing de-framing, de-scrambling and checking processing, and storing in a layer of data FIFO buffer;

[0066] S222, forwarded to the line-side FlexE Group of the local FlexE board card.

[0067] The method realizes efficient data transmission and flexible network resource configuration in a slice packet network (SPN). By constructing cross-connection between two FlexE board cards in a network node and performing scrambling, de-scrambling and checking processing on data, the technical solution enhances the security and integrity of data transmission, and also improves the flexibility and bandwidth utilization of the network. Specifically, the scrambling processing increases the anti-interference ability of data transmission, and the de-scrambling and checking ensure the correctness of data in the transmission process. Combined with the network slicing function of SPN, resources can be dynamically allocated according to different business needs, thereby supporting diversified application scenarios and quality of service requirements in the 5G era.

[0068] The following further details each of the above steps and related technical features:

[0069] In a specific FlexE architecture, the Slice Transport Layer (STL) serves as the foundation layer, directly interacting with the IEEE 802.3 physical layer, forming FlexE Groups by combining multiple physical lanes, and creating logical FlexE Channels to carry different types of data traffic. The Slice Channel Layer (SCL) is responsible for mapping upper-layer traffic to these FlexE Channels and managing and coordinating bandwidth allocation to ensure that each channel receives sufficient resources to meet service level requirements. In the Slice Packet Layer (SPL), higher-level protocol stacks such as MPLS-TP, SR-TP, and SR-BE tunnels are processed, customer service data packets are encapsulated, and efficient transmission is achieved through the corresponding FlexE Channels.

[0070] “FlexE Layer 1 Cross Connect” refers to the process of implementing data exchange and routing selection between different physical interfaces within network devices, especially within routers or switches. This process mainly occurs in the STL (Slice Transport Layer) and SCL (Slice Channel Layer) layers in the FlexE architecture, which are closer to the physical layer and data link layer of the network, responsible for handling low-level transmission details of data frames.

[0071] As shown in Figure 4 , data enters the FlexE Group from the FlexE Client of PE1; within the FlexE Group, data is mapped to the corresponding FlexE Channel; the FlexE Channel is cross-connected through the FlexE L1XC module and then reaches the P3 or P4 node; at the P3 or P4 node, data is again cross-connected through the FlexE L1XC module and finally reaches the FlexE Group of PE2; finally, data exits the FlexE Group of PE2 and returns to the packet switch through the FlexE Client.

[0072] PE1 and PE2 are packet switches, representing two edge routers or core routers in the network; FlexE Client is the FlexE client, responsible for encapsulating packet data into FlexE format and decapsulating at the other end; P3 and P4 are intermediate nodes, which are routers, switches or other network devices; FlexE L1XC (FlexE Layer 1 Cross Connect) is a cross-connection module used to implement cross-connection between FlexE board cards within network elements.

[0073] In the embodiment S1, cross-connection between two FlexE board cards in a network node is constructed; including: determining FlexE Channels between the two FlexE board cards for cross-connection, and configuring the same bandwidth for the FlexE Channels for cross-connection.

[0074] Specifically, FlexE Groups of the FlexE board card at the local end and FlexE Groups of the FlexE board card at the opposite end are selected to select FlexE Channels for cross-connection, and each selected FlexE Channel is assigned a unique Channel ID and recorded. Then, the bandwidth of each FlexE Channel is determined according to the service requirement, and the same bandwidth is configured on the line side and the system side. Finally, the bandwidth configuration of each FlexE Channel is checked using a network monitoring tool or a command line interface to ensure that the bandwidth of all FlexE Channels is consistent and meets the expectation.

[0075] As shown in Figure 5 For a conventional FlexE cross-connection, FlexE channel data needs to be fragmented and reassembled first, and then converted into Interlaken channel data, and then transmitted to a network processor (NP) through an Interlaken bus for further processing. It involves many conversion steps and links, so it is difficult to meet the requirement that the single-node delay is less than 3 microseconds.

[0076] The FlexE one-layer cross-connection in the embodiment completes the fragmentation, reassembly and switching of data by defining a special cross-connection module, and directly processes data through the bus between the backplanes of the FlexE board cards, reducing the number of intermediate links, so that the single-node cross-connection processing delay can be reduced to 2 microseconds.

[0077] In the embodiment S2, the working clock of the line side FlexE Group and the system side FlexE Group is 402MHz, and when the type of the PHY interface is a 100G PHY interface, the data structure of the line side FlexE Group and the system side FlexE Group is defined, including:

[0078] The data structure of the line side FlexE Group is defined as follows:

[0079] Each 100G PHY interface includes 4 lanes, and the data of each lane is processed in 66-bit block units; each FlexE Channel transmits and receives a data structure composed of 4*66-bit data blocks, 5-bit Channel id and 1-bit Sync for each 100G PHY interface; the data structure is a total of 270 bits;

[0080] Channel id is a channel identifier, used to identify the unique ID of the FlexE Channel; Sync is a synchronization flag bit, used to indicate the synchronization state between Lanes;

[0081] The data structure of the system-side FlexE Group is defined as follows:

[0082] The 270-bit data of each 100G PHY interface is divided into 5 Lanes (Lane0, Lane1, Lane2, Lane3, and Lane4) for transmission, each Lane transmits a 54-bit data frame, and the 6th Lane (Lane5) is used as a control frame;

[0083] The data structure of each data frame includes 54-bit data, 1-bit SPR, 1-bit Skip, 1-bit Sync, and 7-bit BIP check bits; the data structure of the control frame includes 5-bit Channel id, 10-bit valid transceiver frame counter CNT, 40-bit Spare, 1-bit Skip, 1-bit Sync, and 7-bit BIP check bits.

[0084] SPR (Spare) is a spare bit, used for padding; Skip is a skip flag bit, used to indicate whether the frame needs to be ignored; Sync is a synchronization flag bit, used to indicate the synchronization state between Lanes; BIP check bits are bit-by-bit check bits, used for data integrity check.

[0085] When the PHY interface is 100G, by defining the data structure of the line-side and system-side FlexE Group, each 100G PHY interface includes 4 Lanes, and the data is processed in 66-bit block units, and the total data structure of each FlexE Channel is 270 bits. The system-side divides the 270-bit data into 5 Lanes for transmission, and uses the 6th Lane as a control frame. This significantly reduces the data transmission delay, while the BIP check bits ensure data integrity, the Sync flag bit ensures Lane synchronization, and the Skip flag bit allows skipping of invalid frames, thereby improving the reliability, flexibility, and consistency of the system, and meeting and exceeding the single-node delay requirements specified by ITU-T.

[0086] Further, when the type of the PHY interface is a 50G PHY interface, the data structure of the line-side and system-side FlexE Group is defined as follows:

[0087] The data structure of the line-side FlexE Group is defined as follows:

[0088] Each 50G PHY interface includes 2 lanes, and the data of each lane is processed in 66-bit block units; each FlexE channel transmits and receives a data structure composed of 2*66-bit data blocks, 132-bit skips, 5-bit channel ids, and 1-bit syncs for each 100G PHY interface; the data structure totals 270 bits;

[0089] Wherein, the 132-bit skip is the processing of the data of two lanes into a skip, and the data structure of the line-side FlexE group is the same as that of the 100G PHY.

[0090] The data structure of the system-side FlexE group is defined in the same way as the definition of the 100G PHY interface.

[0091] Further, when the type of the PHY interface is K*100G PHY interface, where K is a positive integer and K≥2; the data structure of the line-side FlexE group and the system-side FlexE group is defined, including:

[0092] The combination processing of the definition of the K 100G PHY interfaces.

[0093] Specifically, when the type of the PHY interface is 200G PHY interface (i.e., K=2), in defining the data structure of the line-side FlexE group and the system-side FlexE group, each 200G PHY interface contains 2 100G instances (instances), and the processing of each 100G instance is the same as that of a single 100G PHY.

[0094] In this way, the 200G PHY and the 100G PHY adopt a unified processing method to ensure an efficient, reliable and consistent data transmission scheme, while meeting the requirement of low latency. Similarly, it can meet the data transmission under the K*100G PHY interface.

[0095] Further, the above valid frame counter CNT is incremented by 1 when a valid frame without a skip is sent or received.

[0096] The valid frame counter CNT is a 10-bit counter used to record the number of valid frames sent or received in the control frame. By monitoring the number of valid frames, data transmission can be monitored and managed to ensure data integrity and reliability.

[0097] Specifically, at the sending end, the CNT counter of the sending end is incremented by 1 each time a valid frame without the Skip bit is sent. The sending end includes the current CNT value in the data structure of the control frame and sends it together with the data frame. At the receiving end, the CNT counter of the receiving end is incremented by 1 for each valid frame without the Skip bit. The receiving end compares the updated CNT value with the CNT value sent by the sending end to ensure the consistency and integrity of the data transmission.

[0098] For example, the sequence of data frames sent by the sending end is as follows: frame 1: valid frame, Skip bit = 1; frame 2: valid frame, Skip bit = 0; frame 3: invalid frame, Skip bit = 1; frame 4: valid frame, Skip bit = 0.

[0099] When frame 1 is sent, CNT = 1; when frame 2 is sent, CNT = 2; when frame 3 is sent, Skip bit = 1, CNT is not incremented, CNT = 2; when frame 4 is sent, CNT = 3.

[0100] When frame 1 is received, the verification is correct, CNT = 1; when frame 2 is received, the verification is correct, CNT = 2; when frame 3 is received, Skip bit = 1, the frame is ignored, CNT = 2; when frame 4 is received, the verification is correct, CNT = 3.

[0101] In this way, the valid transceiving frame counter CNT can accurately record and monitor the number of valid data frames, ensuring the reliability and consistency of the data transmission.

[0102] In this embodiment, the maximum FIFO data cache amount that can be supported by the one-layer data FIFO buffer is 32*N*M*270 bits;

[0103] Among them, the depth of the one-layer data FIFO buffer is 32, and each FlexE Channel caches 32 270-bit data in the one-layer data FIFO buffer for each 100G PHY interface; the one-layer data FIFO buffer supports a maximum of N 100G PHY interfaces, where N is a positive integer and N≤4; and each 100G PHY interface supports a maximum of M FlexE channels, where M is a positive integer and M≤20.

[0104] By defining the maximum cache amount and configuration of the one-layer data FIFO buffer, not only high-capacity data buffering capability is provided, but also low latency, high reliability and flexibility are ensured. The system can efficiently process multiple high-speed PHY interfaces and multiple FlexE channels to adapt to the needs of high-performance network applications.

[0105] Further, the scrambling and descrambling processes use a linear feedback shift register (LFSR) to generate a pseudo-random sequence.

[0106] The state of the linear feedback shift register LFSR is determined by the polynomial 1+x 39 +x 58 ; where x represents a shift operation. For example, in the LFSR, x39represents a right shift of the value in the register by 39 bits, and x58represents a right shift by 58 bits. These shift operations determine the feedback function of the LFSR, which in turn affects the generated pseudo-random sequence.

[0107] Specifically, the scrambling and descrambling process includes the following steps:

[0108] Scrambling process: initialize a linear feedback shift register (LFSR) with a length of 39+58=97 bits, and the state of the LFSR is determined by the polynomial. A pseudo-random sequence is generated using the LFSR as a scrambling sequence. The scrambling sequence is XORed with the original data to obtain the scrambled data.

[0109] Descrambling process: the receiving end receives the scrambled data. Another pseudo-random sequence is generated using the same LFSR polynomial. The received scrambled data is XORed with the descrambling sequence to recover the original data.

[0110] The key to scrambling and descrambling is to use the same LFSR polynomial and initial state. As long as the sending end and the receiving end follow the same rules, the correct descrambling effect can be guaranteed.

[0111] The verification process in this embodiment includes: performing BIP verification, ignoring data frames with abnormal verification results in the data; performing Sync set verification, ignoring data frames with abnormal verification results in the data; performing Skip set verification, ignoring data frames with abnormal verification results in the data.

[0112] Specifically, the BIP verification of the descrambled data in S221 includes: dividing the descrambled data into 7 subsets; each subset contains 8 bits of data; specifically: the 1st subset: data bit(7:0); the 2nd subset: data bit(15:8); the 3rd subset: data bit(23:16); the 4th subset: data bit(31:24); the 5th subset: data bit(39:32); the 6th subset: data bit(47:40); the 7th subset: data bit(56:48);

[0113] Calculate the parity bit of all data bits in each subset and generate the verification result; calculate the parity bit of all data bits in each subset, including:

[0114] If the sum of the values of all data bits in the subset is even, the corresponding check bit is set to 0; if the sum of the values of all data bits in the subset is odd, the corresponding check bit is set to 1.

[0115] Seven check bits are generated, corresponding to the above seven subsets, specifically: Bit(57) - the check result of the data bits(7:0) corresponding to the first subset; Bit(58) - the check result of the data bits(15:8) corresponding to the second subset; Bit(59) - the check result of the data bits(23:16) corresponding to the third subset; Bit(60) - the check result of the data bits(31:24) corresponding to the fourth subset; Bit(61) - the check result of the data bits(39:32) corresponding to the fifth subset; Bit(62) - the check result of the data bits(47:40) corresponding to the sixth subset; Bit(63) - the check result of the data bits(56:48) corresponding to the seventh subset;

[0116] The 57-bit data and 7-bit check bits are combined into a 64-bit data block for transmission, and the receiving end verifies the integrity of the data by recalculating and comparing the received check bits; if any check bit does not match the expected value, it is considered that the data has an error, and the current data frame is ignored.

[0117] Further, the Sync setting check is performed, and the data frame with abnormal check result in the data is ignored;

[0118] Specifically, it is checked whether the Sync flag bit in the data frame is correctly set. If the Sync flag bit is not set (i.e. 0), the current data frame is ignored. The purpose is to ensure the synchronization state between lanes. Only when all lanes are synchronized, the receiving end considers the data to be valid.

[0119] Further, the Skip setting check is performed, and the data frame with abnormal check result in the data is ignored, and the checked data is stored in a layer of data FIFO buffer.

[0120] Specifically, it is checked whether the Skip flag bit in the data frame is set. If the Skip flag bit is set (i.e. 1), the current data frame is ignored. If the Skip flag bit is not set (i.e. 0), the checked data is stored in a layer of data FIFO buffer. The purpose is to skip invalid or unnecessary data frames, and to ensure that only valid data frames are processed.

[0121] In this step, through BIP check, Sync set check and Skip set check, the high integrity, synchronization and validity of the data are ensured. BIP check detects and ignores data frames with bit errors, Sync set check ensures the synchronization state between Lanes, and Skip set check skips invalid data frames. These check steps collectively improve the reliability of the system, reduce the data processing delay, and ensure that only valid data is stored to the FIFO buffer, thereby improving the efficiency and stability of the overall data transmission.

[0122] The embodiment provides a data processing method based on FlexE layer cross connection, mainly including constructing cross connection between two FlexE board cards in a network node, and defining data structures of FlexE Groups on a line side and a system side, realizing data scrambling processing and forwarding from the line side to the system side, and data descrambling, checking and storing from the system side to the line side. The method enhances the security and integrity of data transmission through scrambling, descrambling, BIP check, Sync set and Skip set check, and supports efficient cache management by configuring a layer of data FIFO buffer.

[0123] This method is applicable to the same type of PHY interface (such as 100G, 50G, 200G, etc.), and through defining corresponding data structures and processing procedures, low delay, high reliability and flexibility are ensured, and it is suitable for efficient data transmission and flexible resource configuration in SPN network.

[0124] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the system disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0125] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing method based on FlexE layer 1 cross-connect, characterized in that, The method comprises the following steps: S1, constructing cross-connection between two FlexE board cards in a network node; wherein each FlexE board card comprises a line-side FlexE Group and a system-side FlexE Group; each FlexE Group comprises a plurality of PHY interfaces of the same type; each PHY interface comprises a plurality of Lanes and supports a plurality of FlexE Channels; S2, defining the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board card, and performing data processing from the line side to the system side and from the system side to the line side; wherein the data processing from the line side to the system side comprises: S211, performing framing, checking and scrambling processing on the data of each FlexE Channel in the line-side FlexE Group of the local FlexE board card, and storing the data into a one-layer data FIFO buffer; S212, forwarding to the system-side FlexE Group of the local FlexE board card and sending to the corresponding FlexE Channel of the line-side FlexE Group of the opposite FlexE board card; the data processing from the system side to the line side comprises: S221, receiving the data of each FlexE Channel in the system-side FlexE Group of the opposite FlexE board card and performing deframing, descrambling and checking processing, and storing the data into a one-layer data FIFO buffer; S222, forwarding to the line-side FlexE Group of the local FlexE board card; when the type of the PHY interface is a 100G PHY interface, the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board card is defined, comprising: the data structure of the line-side FlexE Group is defined: each 100G PHY interface comprises four Lanes, and the data of each Lane is processed in units of 66-bit blocks; each FlexE Channel transmits and receives the data structure composed of 4*66-bit data blocks, 5-bit Channel id and 1-bit Sync for each 100G PHY interface; the data structure is a total of 270 bits; the data structure of the system-side FlexE Group is defined: the 270-bit data of each 100G PHY interface is divided into five Lanes for transmission, each Lane transmits a 54-bit data frame, and the sixth Lane is used as a control frame; wherein the data structure of each data frame comprises 54-bit data, 1-bit SPR, 1-bit Skip, 1-bit Sync and 7-bit BIP check bits; the data structure of the control frame comprises 5-bit Channel id, 10-bit valid transmission and reception frame counter CNT, 40-bit Spare, 1-bit Skip, 1-bit Sync and 7-bit BIP check bits.

2. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, the S1 comprises: Determine the FlexE Channel for cross-connection between two FlexE boards, and configure the same bandwidth for the FlexE Channel for cross-connection.

3. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, When the type of the PHY interface is a 50G PHY interface, define the data structure of the line-side FlexE Group and the system-side FlexE Group, including: Define the data structure of the line-side FlexE Group: Each 50G PHY interface includes 2 lanes, and the data of each lane is processed in 66-bit block units; each FlexE Channel transmits and receives the data structure of 2*66-bit data blocks, 132-bit Skip, 5-bit Channel id, and 1-bit Sync for each 100G PHY interface; the data structure totals 270 bits; the data structure of the system-side FlexE Group is defined in the same way as under the 100G PHY interface.

4. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, When the type of the PHY interface is a K*100G PHY interface, where K is a positive integer and K≥2; define the data structure of the line-side FlexE Group and the system-side FlexE Group, including: Combination processing of the definition mode under K 100G PHY interfaces.

5. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, The valid frame counter CNT is incremented by 1 when a valid frame without Skip is transmitted or received.

6. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, In the S2, the maximum FIFO data cache amount that can be supported by a one-layer data FIFO buffer is 32*N*M*270 bits; Wherein, the depth of the one-layer data FIFO buffer is 32, and each FlexE Channel caches 32 270-bit data in the one-layer data FIFO buffer for each 100G PHY interface; the one-layer data FIFO buffer supports a maximum of N 100G PHY interfaces, where N is a positive integer and N≤4; and each 100G PHY interface supports a maximum of M FlexE channels, where M is a positive integer and M≤20.

7. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, In the S2, the scrambling processing and descrambling processing generate a pseudo-random sequence using a linear feedback shift register (LFSR); The state of the linear feedback shift register LFSR is determined by the polynomial 1 + x 39 + x 58 ; wherein, denotes a shift operation by one.

8. The data processing method based on the FlexE layer cross-connection according to claim 1, characterized in that, In the S2, the check processing includes: Perform BIP check and ignore data frames with abnormal check results in the data; Perform Sync setting check and ignore data frames with abnormal check results in the data; Perform Skip setting check and ignore data frames with abnormal check results in the data.

9. The data processing method based on the FlexE layer cross-connection according to claim 8, characterized in that, The BIP check includes: Divide the data after descrambling into 7 subsets; each subset contains 8 bits of data; Calculate the parity bits of all data bits in each subset and generate a check result; The calculation of the parity bits of all data bits in each subset includes: if the sum of the values of all data bits in the subset is even, the corresponding parity bit is set to 0; if the sum of the values of all data bits in the subset is odd, the corresponding parity bit is set to 1.

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