Bus performance test method and device, storage medium and electronic equipment

Abstract

The invention provides a bus performance test method and device, a storage medium and electronic equipment, and relates to the field of chip design. In the method, the electronic device obtains a chip design code, and the chip design code designs a bus to be tested and a sending end and a receiving end which can communicate through the bus to be tested; loading the chip design code to a simulation environment, and obtaining the current used bandwidth and the bandwidth upper limit of the bus to be tested through the simulation environment; and if the used bandwidth is smaller than the bandwidth upper limit, improving the data sending rate of the sending end to obtain test information after the to-be-tested bus reaches the bandwidth upper limit. Thus, the running effect of the chip is simulated in the simulation environment, and when the designed bandwidth upper limit cannot be reached, the sending rate of the sending end is automatically improved to promote the to-be-tested bus to reach the bandwidth upper limit; therefore, manual intervention can be reduced, the verification period is shortened, and the production efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip design, and more specifically, to a bus performance testing method, device, storage medium and electronic device. Background Art

[0002] In the complex process of chip design, bus performance verification is a crucial link. This link not only needs to verify whether the bus design can achieve the established bandwidth target and ensure that it has sufficient data transmission capacity to meet the efficient operation requirements of the system. More importantly, it is also necessary to conduct in-depth research on whether its performance can remain stable in extreme scenarios, that is, when the bus load reaches the maximum bandwidth.

[0003] In practice, it is found that the current traditional bus verification method still relies on manual intervention, which includes constantly adjusting and writing new test cases based on test feedback. This process may lead to a long feedback and optimization cycle, thus affecting the overall efficiency of verification. Summary of the invention

[0004] In order to overcome at least one of the deficiencies in the prior art, the present application provides a bus performance testing method, device, storage medium and electronic device, specifically including:

[0005] In a first aspect, the present application provides a bus performance testing method, the method comprising:

[0006] Obtaining a chip design code, wherein the chip design code designs a bus to be tested and a transmitting end and a receiving end capable of communicating through the bus to be tested;

[0007] Loading the chip design code into a simulation environment, and obtaining the current used bandwidth and bandwidth upper limit of the bus to be tested through the simulation environment;

[0008] If the used bandwidth is less than the bandwidth upper limit, the data sending rate of the sending end is increased to obtain the test information of the bus to be tested after reaching the bandwidth upper limit.

[0009] In conjunction with the optional implementation manner of the first aspect, the transmitting end includes a working core that sends data to the receiving end and a standby core that does not send data to the receiving end, and increasing the data transmission rate of the transmitting end includes:

[0010] Increasing the data transmission rate of the working core; and / or

[0011] A target core is selected from the spare cores, and the target core is configured as a working core that sends data to the receiving end.

[0012] In conjunction with an optional implementation manner of the first aspect, the working core includes a configuration register for controlling a data transmission rate, and the step of increasing the data transmission rate of the working core includes:

[0013] According to the bandwidth upper limit, a target sending rate required by the working core is obtained;

[0014] Mapping the target sending rate to a target configuration parameter of the configuration register through a parameter mapping relationship;

[0015] The configuration register is configured using the target configuration parameter to increase the data transmission rate of the working core.

[0016] In conjunction with the optional implementation manner of the first aspect, before mapping the target sending rate to the target configuration parameter of the configuration register through the parameter mapping relationship, the method further includes:

[0017] Mapping a preset test sending rate to a test configuration parameter through a theoretical mapping relationship, wherein the test sending rate is less than a sending rate required by the bandwidth upper limit;

[0018] Obtaining the measured sending rate of the working core after the configuration register is configured with the test configuration parameters;

[0019] Obtaining a correction coefficient of the theoretical mapping relationship according to the measured sending rate and the test sending rate;

[0020] The theoretical mapping relationship is corrected by the correction coefficient to obtain the parameter mapping relationship.

[0021] In conjunction with the optional implementation manner of the first aspect, the working core includes a configuration register for controlling a data transmission rate, and the step of increasing the data transmission rate of the working core includes:

[0022] Obtaining the current remaining bandwidth of the bus to be tested;

[0023] Determining a target configuration parameter of the configuration register according to the current remaining bandwidth, wherein a data transmission rate increased by the target configuration parameter is positively correlated with the remaining bandwidth;

[0024] If the bus under test does not reach the upper bandwidth limit after the configuration register is configured with the target configuration parameters, the process returns to the step of obtaining the current remaining bandwidth of the bus under test until the bus under test reaches the upper bandwidth limit.

[0025] In conjunction with the optional implementation manner of the first aspect, obtaining the current bandwidth upper limit of the bus to be tested through the simulation environment includes:

[0026] Capturing data packets transmitted on the bus to be tested;

[0027] Parsing the state information of the bus to be tested from the data packet;

[0028] The current bandwidth upper limit of the bus to be tested is determined according to the current state information.

[0029] In conjunction with an optional implementation manner of the first aspect, the transmitting end includes a working core that sends data to the receiving end, the working core includes a status register of the bus to be tested, and obtaining a current bandwidth upper limit of the bus to be tested through the simulation environment includes:

[0030] Reading the status information in the status register;

[0031] The current bandwidth upper limit of the bus to be tested is determined according to the state information.

[0032] In combination with the optional implementation manner of the first aspect, the obtaining, through the simulation environment, the current used bandwidth of the bus to be tested includes:

[0033] Counting the amount of data transmitted by the bus under test within a preset time period;

[0034] The currently used bandwidth of the bus to be tested is obtained according to the amount of data transmitted within the preset time period.

[0035] In a second aspect, the present application further provides a bus performance testing device, the device comprising:

[0036] A code simulation module, used for obtaining a chip design code, wherein the chip design code designs a bus to be tested and a transmitting end and a receiving end capable of communicating through the bus to be tested;

[0037] The code simulation module is further used to load the chip design code into a simulation environment, and obtain the current used bandwidth and bandwidth upper limit of the bus to be tested through the simulation environment;

[0038] The bus test module is used to increase the data transmission rate of the transmitting end if the used bandwidth is less than the bandwidth upper limit, so as to obtain the test information of the bus to be tested after reaching the bandwidth upper limit.

[0039] In conjunction with the optional implementation manner of the second aspect, the transmitting end includes a working core that sends data to the receiving end and a standby core that does not send data to the receiving end, and the bus test module is further specifically used to:

[0040] Increasing the data transmission rate of the working core; and / or

[0041] A target core is selected from the spare cores, and the target core is configured as a working core that sends data to the receiving end.

[0042] In conjunction with the optional implementation manner of the second aspect, the working core includes a configuration register for controlling a data transmission rate, and the bus test module is further specifically used for:

[0043] According to the bandwidth upper limit, a target sending rate required by the working core is obtained;

[0044] Mapping the target sending rate to a target configuration parameter of the configuration register through a parameter mapping relationship;

[0045] The configuration register is configured using the target configuration parameter to increase the data transmission rate of the working core.

[0046] In conjunction with the optional implementation manner of the second aspect, before mapping the target sending rate to the target configuration parameter of the configuration register through the parameter mapping relationship, the bus test module is further specifically used to:

[0047] Mapping a preset test sending rate to a test configuration parameter through a theoretical mapping relationship, wherein the test sending rate is less than a sending rate required by the bandwidth upper limit;

[0048] Obtaining the measured sending rate of the working core after the configuration register is configured with the test configuration parameters;

[0049] Obtaining a correction coefficient of the theoretical mapping relationship according to the measured sending rate and the test sending rate;

[0050] The theoretical mapping relationship is corrected by the correction coefficient to obtain the parameter mapping relationship.

[0051] In conjunction with the optional implementation manner of the second aspect, the working core includes a configuration register for controlling a data transmission rate, and the bus test module is further specifically used for:

[0052] Obtaining the current remaining bandwidth of the bus to be tested;

[0053] Determining a target configuration parameter of the configuration register according to the current remaining bandwidth, wherein a data transmission rate increased by the target configuration parameter is positively correlated with the remaining bandwidth;

[0054] If the bus under test does not reach the upper bandwidth limit after the configuration register is configured with the target configuration parameters, the process returns to the step of obtaining the current remaining bandwidth of the bus under test until the bus under test reaches the upper bandwidth limit.

[0055] In conjunction with the optional implementation manner of the second aspect, the code simulation module is further specifically used for:

[0056] Capturing data packets transmitted on the bus to be tested;

[0057] Parsing the state information of the bus to be tested from the data packet;

[0058] The current bandwidth upper limit of the bus to be tested is determined according to the current state information.

[0059] In conjunction with the optional implementation manner of the second aspect, the transmitting end includes a working core that sends data to the receiving end, the working core includes a status register of the bus to be tested, and the code simulation module is further specifically used for:

[0060] Reading the status information in the status register;

[0061] The current bandwidth upper limit of the bus to be tested is determined according to the state information.

[0062] In conjunction with the optional implementation manner of the second aspect, the code simulation module is further specifically used for:

[0063] Counting the amount of data transmitted by the bus under test within a preset time period;

[0064] The currently used bandwidth of the bus to be tested is obtained according to the amount of data transmitted within the preset time period.

[0065] In a third aspect, the present application also provides a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the bus performance testing method is implemented.

[0066] In a fourth aspect, the present application further provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the bus performance testing method is implemented.

[0067] Compared with the prior art, this application has the following beneficial effects:

[0068] The present application provides a bus performance test method, device, storage medium and electronic device. In the method, the electronic device obtains a chip design code, wherein the chip design code designs the bus to be tested and the transmitter and receiver that can communicate through the bus to be tested; the chip design code is loaded into a simulation environment, and the current used bandwidth and bandwidth upper limit of the bus to be tested are obtained through the simulation environment; if the used bandwidth is less than the bandwidth upper limit, the data transmission rate of the transmitter is increased to obtain the test information of the bus to be tested after reaching the bandwidth upper limit. In this way, the operation effect of the chip is simulated in the simulation environment, and when the designed bandwidth upper limit cannot be reached, the transmission rate of the transmitter is automatically increased to prompt the bus to be tested to reach the bandwidth upper limit; thereby reducing manual intervention, shortening the verification cycle, and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0070] Figure 1 A flowchart of a bus performance testing method provided in an embodiment of the present application;

[0071] Figure 2 A schematic diagram of the function of the AMBA bus provided in the embodiment of the present application;

[0072] Figure 3 A schematic diagram of the structure of a bus performance test device provided in an embodiment of the present application;

[0073] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0075] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0076] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0077] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the invented product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0078] In addition, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0079] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0080] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0081] Based on the above statement, as introduced in the background technology, the current traditional bus verification method still relies on manual intervention. This includes constantly adjusting and writing new test cases based on test feedback. This process may lead to a long feedback and optimization cycle, which in turn affects the overall efficiency of verification.

[0082] For example, take the AMBA (Advanced Microcontroller Bus Architecture) bus as an example. In the chip design process, if you want to verify whether the AMBA bus can achieve a designed bandwidth of 2GB / s. Engineers first need to manually write and execute a series of complex test scripts to simulate different data transmission scenarios. However, in the actual test process, it is found that the gap between ideal and reality, that is, the expected high-speed bandwidth is difficult to achieve in actual testing. This is not only because there may be omissions in the writing of the script, but also because the prediction of the bus behavior is not accurate enough, or the coverage of the test scenario is not comprehensive enough. At this time, engineers need to redesign more sophisticated and rigorous test cases and simulate and verify the bus design again. This iterative process of repeatedly adjusting and optimizing test cases consumes a lot of time, thereby reducing the speed and efficiency of the entire verification process.

[0083] Based on the discovery of the above technical problems, the inventors have proposed the following technical solutions to solve or improve the above problems through creative work. It should be noted that the defects in the solutions in the above prior art are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of the present application for the above problems below should all be the contributions made by the inventors to the present application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0084] In view of this, the present embodiment provides a bus performance testing method. In the method, the electronic device obtains a chip design code, wherein the chip design code designs the bus to be tested and the transmitter and receiver that can communicate through the bus to be tested; the chip design code is loaded into the simulation environment, and the current used bandwidth and bandwidth upper limit of the bus to be tested are obtained through the simulation environment; if the used bandwidth is less than the bandwidth upper limit, the data transmission rate of the transmitter is increased to obtain the test information of the bus to be tested after reaching the bandwidth upper limit. In this way, the operation effect of the chip is simulated in the simulation environment, and when the designed bandwidth upper limit cannot be reached, the transmission rate of the transmitter is automatically increased to prompt the bus to be tested to reach the bandwidth upper limit; thereby reducing manual intervention, shortening the verification cycle, and improving production efficiency.

[0085] It should be noted that the electronic device implementing the method may be, but is not limited to, a mobile terminal, a tablet computer, a laptop computer, a desktop host, and a server, etc. When it is a server, the server may be a single server or a server group. The server group may be centralized or distributed (for example, the server may be a distributed system). In some embodiments, the server may be local or remote relative to the user terminal. In some embodiments, the server may be implemented on a cloud platform; as an example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud (Community Cloud), a distributed cloud, an inter-cloud (Inter-Cloud), a multi-cloud (Multi-Cloud), etc., or any combination thereof. In some embodiments, the server may be implemented on an electronic device having one or more components.

[0086] To make the solution provided by this embodiment clearer, the following uses a server as an electronic device to implement the method, and combines Figure 1 Each step of the method is described in detail. However, it should be understood that the operations of the flowchart may not be implemented in order, and steps without logical contextual relationships may be reversed in order or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart, or remove one or more operations from the flowchart under the guidance of the content of this application. Figure 1 As shown, the method includes:

[0087] S1, obtain chip design code.

[0088] In this embodiment, the chip design code includes the function code and optimization code of the chip itself, wherein the function code is used to realize the chip function of the chip itself, for example, the bus to be tested and the transmitter and receiver that can communicate through the bus to be tested are realized through the function code; while the test of the bus to be tested requires the help of the optimization code. For example, the optimization code is used to optimize the transmitter of the bus to be tested when it is detected that the bandwidth on the bus to be tested does not reach the designed bandwidth upper limit, so that the optimized chip can fully utilize the performance upper limit of the bus to be tested.

[0089] In addition, the bus to be tested may be not only the AMBA bus mentioned above, but also an OCP (Open Core Protocol) bus, a PCI Express (Peripheral Component Interconnect Express) bus, a NoC (Network-on-Chip) bus, etc. Continuing with the AMBA bus as an example, Figure 2As shown, the cores, memories, peripherals, caches, etc. in the multi-core processor are directly or indirectly connected to each other through the AMBA bus. Therefore, in this embodiment, the transmitting end of the bus to be tested may include multiple cores, which may be pre-designed IP cores and / or self-developed cores. The core that sends data to the receiving end is called a working core, and the core that does not send data to the receiving end is called a standby core. The receiving end may include the remaining cores, memories, peripherals, caches, and other devices.

[0090] Based on the above implementation of the chip design code, continue to see Figure 1 , the method provided in this embodiment also includes:

[0091] S2, loading the chip design code into the simulation environment, and obtaining the current used bandwidth and bandwidth upper limit of the bus to be tested through the simulation environment.

[0092] It should be noted that in the field of chip design, simulation is an important measure to verify the correctness of the design. The chip design code, which is usually written in a hardware description language (such as Verilog or VHDL), can be run in the simulation environment provided by the simulation tool to verify its function. These codes can be parsed in the simulation environment to generate a behavioral model of the logic circuit, and then perform timing or functional simulation. In addition, the simulation environment will create a test platform to drive the chip design through given input signals and timing conditions to observe whether the output results meet expectations. In this way, designers can find and fix potential design errors before actually manufacturing the chip, ensure the correctness of the chip function and the achievement of performance indicators, thereby reducing development costs and cycles.

[0093] Research has found that the bandwidth upper limit of the bus under test does not always remain the same, but changes with the current working stage of the bus. In this regard, taking the AMBA bus as an example, the AMBA bus includes the initial stage, stable working stage, low power mode, burst transmission stage, etc. The characteristics of each stage are as follows:

[0094] Initial stage: When the system starts, the AMBA bus may be in the initial stage. At this time, the upper limit of the bus bandwidth may be low because the system is configuring and initializing each IP core, and data transmission on the bus is not the top priority.

[0095] Stable working stage: Once the system enters a stable working state, the bandwidth limit of the AMBA bus will increase to meet the needs of high-performance data transmission. For example, when the processor core needs to frequently read instructions and data from the memory, the bandwidth of the AHB system bus will reach a higher level.

[0096] Low power mode: In the system's low power mode, the bandwidth limit of the AMBA bus may be limited to save energy. For example, when the system detects that the processor core is idle, the bandwidth of the APB peripheral bus may be reduced because the communication requirements of the peripheral devices are not high at this time.

[0097] Burst transfer phase: When performing a burst transfer, such as high-speed transmission of a large amount of data through the AXI bus, the bus bandwidth limit will be temporarily increased to support this high-throughput data transmission mode.

[0098] When changes occur between the above stages, the AMBA bus will transmit relevant configuration information, so the state information of the AMBA can be parsed from it. Based on this discovery, this embodiment provides the following optional implementation of step S2:

[0099] S2-1A, capture the data packets transmitted on the bus under test.

[0100] S2-2A, parse the data packet to obtain the status information of the bus to be tested.

[0101] S2-3A, determining the current bandwidth upper limit of the bus to be tested according to the current status information.

[0102] In this way, since the chip will send relevant configuration information on the bus at the beginning of each working stage, by continuously capturing data packets on the bus, when the bus status information is parsed from the captured configuration information, it can be determined which working stage the bus under test has entered.

[0103] In addition, the study also found that the working core that sends data to the receiving end is provided with a status register that records the bus status. Therefore, this embodiment also provides another implementation of step S2:

[0104] S2-1B, read the status information in the status register.

[0105] S2-2B, determining the current bandwidth upper limit of the bus to be tested according to the status information.

[0106] Thus, since the status register contains the status information of the bus to be tested, the working phase of the current bus to be tested can be determined by reading the status information in the status register in the working core, and then the bandwidth upper limit in the working state can be determined.

[0107] As for the currently used bandwidth of the bus under test, the server in this embodiment can count the amount of data transmitted by the bus under test within a preset time period; and obtain the currently used bandwidth of the bus under test according to the amount of data transmitted within the preset time period.

[0108] Exemplarily, the server captures data packets within 10 μs on the bus and performs statistics to obtain the amount of data within 10 μs. The amount of data is divided by 10 μs to obtain the current used bandwidth of the bus to be tested.

[0109] Based on the above embodiment, the used bandwidth and the upper bandwidth limit of the bus to be tested are introduced. Figure 1 , the method further comprises:

[0110] S3, if the used bandwidth is less than the bandwidth upper limit, the data transmission rate of the transmitting end is increased to obtain the test information of the bus to be tested after reaching the bandwidth upper limit.

[0111] For the test information of the bus to be tested, we continue to take the AMBA bus as an example. After reaching the bandwidth upper limit of the AMBA bus, the data packets of the AMBA bus communication can be collected and parsed in real time to monitor the frequency, timing and resource usage of the bus operation. On this basis, the functions of the AMBA bus transactions are captured, and the correctness and performance indicators of the transactions are confirmed through efficient analysis algorithms. In addition, the performance analysis algorithm, including consistency check, anomaly detection and performance benchmark comparison, can be used to comprehensively evaluate the throughput, delay and resource occupancy of the bus to be tested. In this way, the test information of the AMBA bus after reaching the bandwidth upper limit can be obtained.

[0112] In this embodiment, it is considered that the sending end includes a working core that sends data to the receiving end and a standby core that does not send data to the receiving end. Therefore, this embodiment provides multiple ways to increase the data sending rate of the sending end. That is, the optional implementation of step S3 may include:

[0113] S3-1A, increase the data transmission rate of the working core; and / or

[0114] S3-1B, selects a target core from the spare cores and configures the target core as a working core that sends data to the receiving end.

[0115] When selecting the target core, the high-priority spare core is selected as the new working core; and the priority of the spare core is determined by the working scenario of the simulation test. For example, in the video playback scenario, the spare core involved in video encoding and decoding has a higher priority. In the user interaction application scenario, the spare core responsible for processing input and output has a higher priority.

[0116] It can be understood that when it is detected that the used bandwidth is less than the bandwidth limit, the server can increase the data sending amount of the current working core; or select more cores to participate in data sending; or, while increasing the data sending amount of the current working core, also select more cores to participate in data sending.

[0117] It was found in practice that since the bus in the physical chip is not tested and verified in this embodiment, but the designed chip code is verified in a simulation environment, there may be a certain deviation between the simulation results of the chip and the performance of the actual physical chip. It is precisely because of these differences in performance that there may be a deviation between the expected data transmission rate of the working core and the actual measured data transmission rate. For example, according to the design expectations, under the existing configuration parameters, the data transmission rate of the working core should reach 16Gbps, but the actual measurement result is only 15Gbps. In addition, if there are defects in the chip code design, it will also cause a discrepancy between the design expectations and the actual performance.

[0118] For the above S3-1A, this embodiment can gradually increase the data transmission rate of the working chip to approach the bandwidth upper limit of the bus to be tested. In this regard, this embodiment provides the following optional implementation methods:

[0119] The server obtains the current remaining bandwidth of the bus to be tested; determines the target configuration parameter of the configuration register according to the current remaining bandwidth, wherein the data transmission rate increased by the target configuration parameter is positively correlated with the remaining bandwidth; if the bus to be tested does not reach the bandwidth upper limit after the configuration register is configured with the target configuration parameter, then returns to the step of obtaining the current remaining bandwidth of the bus to be tested until the bus to be tested reaches the bandwidth upper limit.

[0120] Exemplarily, the registers related to setting transmission data include a control register, a configuration register, and a terminal register, and the functions of each register are as follows:

[0121] Control register: used to start or stop data transmission, affecting the transmission speed and shortening the total time of pausing data transmission during the transmission process.

[0122] Configuration register: The clock frequency and data bit width can be configured through the configuration register. Among them, the clock frequency determines the working mode of the core. If it works in high-speed or low-speed mode, the core processes data faster in high-speed mode, and more data packets are processed and sent to the bus per unit time. The data bit width affects the bit width of each data transmission, for example, 8, 16, 32, 64, 128 bits, etc.

[0123] Interrupt register: If the IP transmission is affected by the interrupt, the next data transmission can only be continued after the interrupt is responded to. In this case, the interrupt priority can be changed so that the interrupt related to the bus to be tested is processed first.

[0124] In this example, the clock frequency and bit width are adjusted by configuring registers to jointly determine the data transmission rate of the working core. The relationship is as follows:

[0125] Data transmission rate (bps) = clock frequency (Hz) × bit width of transmitted data (bits)

[0126] Assuming the clock frequency is 200 MHz and the bit width of each data transmission is 64 bits, the data transmission rate is 12.8 Gbps (gigabits per second).

[0127] Therefore, assuming that the current bit width is 16, when the server detects that the remaining bandwidth is small, the bit width is configured to 32. Conversely, when the remaining bandwidth is large, the bit width is configured to 64. Then, continue to check whether the bandwidth upper limit of the bus to be tested is reached. If it is not reached, continue to increase the bit width. If the bit width is increased to the maximum and the bandwidth upper limit is not reached, further increase the clock frequency. And so on, until the bandwidth upper limit of the bus to be tested is reached.

[0128] Compared with the above implementation, multiple adjustments are required to reach the bandwidth upper limit of the bus to be tested. This embodiment also provides another implementation of step S3-1A:

[0129] The server obtains the target transmission rate required by the working core according to the bandwidth upper limit; maps the target transmission rate to the target configuration parameter of the configuration register through the parameter mapping relationship; and configures the configuration register using the target configuration parameter to increase the data transmission rate of the working core. In this way, the data transmission rate of the working core can be quickly made to reach the bandwidth upper limit of the bus to be tested through calculation without repeated configuration.

[0130] Among them, the parameter mapping relationship is the relationship between the above-mentioned clock frequency, bit width, and data transmission rate. However, it was found in practice that when verifying the designed chip code in a simulation environment, there may be a certain deviation between the simulation results of the chip and the performance of the actual physical chip. For example, according to the designed configuration specification, the clock frequency is configured to 200MHz, but in the simulation environment, it is limited by factors such as the context switching consumption of the simulation program and the performance of the simulation platform processor, which will eventually cause the actual frequency to be not 200MHz. In this regard, this embodiment provides the following implementation method to obtain the above-mentioned parameter mapping relationship:

[0131] The server maps the preset test sending rate to the test configuration parameters through a theoretical mapping relationship, wherein the test sending rate is less than the sending rate required by the bandwidth upper limit. In this regard, it should be understood that the test sending rate here is less than the sending rate required by the bandwidth upper limit in order to avoid the test sending rate being too large, that is, much larger than the bandwidth upper limit of the bus to be tested, which will cause the bus to be tested to be abnormal after being configured through the corresponding test configuration parameters. In addition, the theoretical mapping relationship is the above-mentioned data sending rate (bps) = clock frequency (Hz) × bit width (bits) of the transmitted data.

[0132] Then, the server obtains the measured sending rate of the working core after the configuration register is configured with the test configuration parameters; and obtains the correction coefficient of the theoretical mapping relationship according to the measured sending rate and the test sending rate.

[0133] Finally, the server corrects the theoretical mapping relationship through the correction coefficient to obtain the parameter mapping relationship.

[0134] It should be noted that after a large number of experiments, it was found that due to the different design methods of different simulation platforms, the correction coefficient is the difference between the measured sending rate and the test sending rate in some simulation platforms, that is, no matter what clock frequency, the difference between the two is close to the difference. In other simulation platforms, the correction coefficient is the ratio between the measured sending rate and the test sending rate, that is, no matter what clock frequency, the two satisfy a certain proportional relationship. For example, the measured sending rate is 0.8 times the theoretical test sending rate.

[0135] Based on the same inventive concept as the bus performance test method provided in this embodiment, this embodiment also provides a bus performance test device, which includes at least one software function module that can be stored in a memory or fixed in an electronic device in the form of software. The processor 22 in the electronic device is used to execute the executable module stored in the memory. For example, the software function module and computer program included in the bus performance test device. Please refer to Figure 3 , functionally speaking, the device may include:

[0136] A code simulation module 11 is used to obtain a chip design code, wherein the chip design code designs a bus to be tested and a transmitter and a receiver capable of communicating through the bus to be tested;

[0137] The code simulation module 11 is also used to load the chip design code into the simulation environment, and obtain the current used bandwidth and bandwidth upper limit of the bus to be tested through the simulation environment;

[0138] The bus test module 12 is used to increase the data transmission rate of the transmitting end if the used bandwidth is less than the bandwidth upper limit, so as to obtain the test information of the bus to be tested after reaching the bandwidth upper limit.

[0139] In this embodiment, the code simulation module 11 is used to implement Figure 1 The bus test module 12 is used to implement step S1 and S2 in step 1, and therefore, the detailed description of each module can refer to the specific implementation of the corresponding step. In addition, it should be noted that, since the bus performance test method has the same inventive concept, the bus performance test device can also implement other steps or sub-steps of the method through the above modules or other modules.

[0140] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0141] It should also be understood that if the above implementation is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0142] Therefore, this embodiment further provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by the processor, the bus performance test method provided in this embodiment is implemented. Among them, the storage medium can be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc., which can store program codes.

[0143] This embodiment provides an electronic device for implementing a bus performance test method. Figure 4 As shown, the electronic device may include a processor 22 and a memory 21. In addition, the memory 21 stores a computer program, and the processor implements the bus performance test method provided in this embodiment by reading and executing the computer program corresponding to the above implementation in the memory 21.

[0144] Continue to see Figure 4 The electronic device may further include a communication unit 23. The memory 21, the processor 22 and the communication unit 23 are electrically connected to each other directly or indirectly through a system bus 24 to achieve data transmission or interaction.

[0145] The memory 21 may be an information recording device based on any electronic, magnetic, optical or other physical principle, used to record execution instructions, data, etc. In some embodiments, the memory 21 may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0146] In some embodiments, the volatile memory may be a random access memory (RAM); in some embodiments, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a disk drive, a solid-state drive, any type of storage disk (such as a CD, a DVD, etc.), or a similar storage medium, or a combination thereof, etc.

[0147] The communication unit 23 is used to send and receive data through a network. In some embodiments, the network may include a wired network, a wireless network, a fiber optic network, a telecommunication network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth network, a ZigBee network, or a near field communication (NFC) network, or any combination thereof. In some embodiments, the network may include one or more network access points. For example, the network may include a wired or wireless network access point, such as a base station and / or a network switching node, through which one or more components of the service request processing system may be connected to the network to exchange data and / or information.

[0148] The processor 22 may be an integrated circuit chip having a signal processing capability, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor may include a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0149] Understandably, Figure 4 The structure shown is for illustration only. The electronic device may also have Figure 4 More or fewer components than shown, or with Figure 4 Different configurations shown. Figure 4 The components shown may be implemented in hardware, software or a combination thereof.

[0150] It should be understood that the apparatus and method disclosed in the above-mentioned embodiments can also be implemented in other ways. The apparatus embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0151] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A bus performance testing method, characterized in that: The method comprises: Obtaining a chip design code, wherein the chip design code designs a bus to be tested and a transmitting end and a receiving end capable of communicating through the bus to be tested; Loading the chip design code into a simulation environment, and obtaining the current used bandwidth and bandwidth upper limit of the bus to be tested through the simulation environment; If the used bandwidth is less than the bandwidth upper limit, the data sending rate of the sending end is increased to obtain the test information of the bus to be tested after reaching the bandwidth upper limit.

2. The bus performance testing method according to claim 1, characterized in that: The transmitting end includes a working core that sends data to the receiving end and a standby core that does not send data to the receiving end, and the step of increasing the data transmission rate of the transmitting end includes: Increasing the data transmission rate of the working core; and / or A target core is selected from the spare cores, and the target core is configured as a working core that sends data to the receiving end.

3. The bus performance testing method according to claim 2, characterized in that: The working core includes a configuration register for controlling a data transmission rate, and the step of increasing the data transmission rate of the working core includes: According to the bandwidth upper limit, a target sending rate required by the working core is obtained; Mapping the target sending rate to a target configuration parameter of the configuration register through a parameter mapping relationship; The configuration register is configured using the target configuration parameter to increase the data transmission rate of the working core.

4. The bus performance testing method according to claim 3, characterized in that: Before mapping the target transmission rate to the target configuration parameter of the configuration register through the parameter mapping relationship, the method further includes: Mapping a preset test sending rate to a test configuration parameter through a theoretical mapping relationship, wherein the test sending rate is less than a sending rate required by the bandwidth upper limit; Obtaining the measured sending rate of the working core after the configuration register is configured with the test configuration parameters; Obtaining a correction coefficient of the theoretical mapping relationship according to the measured sending rate and the test sending rate; The theoretical mapping relationship is corrected by the correction coefficient to obtain the parameter mapping relationship.

5. The bus performance testing method according to claim 2, characterized in that: The working core includes a configuration register for controlling a data transmission rate, and the step of increasing the data transmission rate of the working core includes: Obtaining the current remaining bandwidth of the bus to be tested; Determining a target configuration parameter of the configuration register according to the current remaining bandwidth, wherein a data transmission rate increased by the target configuration parameter is positively correlated with the remaining bandwidth; If the bus under test does not reach the upper bandwidth limit after the configuration register is configured with the target configuration parameters, the process returns to the step of obtaining the current remaining bandwidth of the bus under test until the bus under test reaches the upper bandwidth limit.

6. The bus performance testing method according to claim 1, characterized in that: The obtaining the current bandwidth upper limit of the bus to be tested through the simulation environment includes: Capturing data packets transmitted on the bus to be tested; Parsing the state information of the bus to be tested from the data packet; The current bandwidth upper limit of the bus to be tested is determined according to the current state information.

7. The bus performance testing method according to claim 1, characterized in that: The transmitting end includes a working core for sending data to the receiving end, the working core includes a status register of the bus to be tested, and obtaining the current bandwidth upper limit of the bus to be tested through the simulation environment includes: Reading the status information in the status register; The current bandwidth upper limit of the bus to be tested is determined according to the state information.

8. The bus performance testing method according to claim 1, characterized in that: The obtaining the currently used bandwidth of the bus to be tested through the simulation environment includes: Counting the amount of data transmitted by the bus under test within a preset time period; The currently used bandwidth of the bus to be tested is obtained according to the amount of data transmitted within the preset time period.

9. A bus performance testing device, characterized in that: The device comprises: A code simulation module, used for obtaining a chip design code, wherein the chip design code designs a bus to be tested and a transmitting end and a receiving end capable of communicating through the bus to be tested; The code simulation module is further used to load the chip design code into a simulation environment, and obtain the current used bandwidth and bandwidth upper limit of the bus to be tested through the simulation environment; The bus test module is used to increase the data transmission rate of the transmitting end if the used bandwidth is less than the bandwidth upper limit, so as to obtain the test information of the bus to be tested after reaching the bandwidth upper limit.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the bus performance testing method according to any one of claims 1 to 8 is implemented.

11. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, the bus performance testing method according to any one of claims 1 to 8 is implemented.

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