Refresh control circuit and memory

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a refresh control circuit and a memory, and the refresh control circuit comprises a counting identification circuit which is configured to generate and output a counting identification signal at an effective level based on a full-array refresh identification signal and a refresh activation signal when a same-array refresh identification signal is effective; the counting processing circuit is configured to receive the counting identification signal and count based on the counting identification signal to generate a counting result; and the first control circuit is configured to receive the counting result, generate and output an initial supplementary refresh indication signal of an effective level when the counting result is within a first preset range, and indicate the memory to execute supplementary refresh operation when the supplementary refresh indication signal is effective, so as to provide a Row Hammer protection control strategy during frequent switching of refresh modes. And therefore, vulnerabilities of Row Hammer protection of the memory can be prevented.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a refresh control circuit and a memory. Background Art

[0002] The fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) is a high-bandwidth memory. DDR5 usually contains two refresh modes and two types of refresh commands. The two refresh modes include: normal refresh mode and fine-grained refresh mode (compared with the normal refresh mode, the fine-grained refresh mode has fewer activated word lines in each tRFC, for example, one tRFC in the normal refresh mode performs 4 ACTIVEs, while one tRFC in the fine-grained refresh mode performs 2 ACTIVEs); the two types of refresh commands include: full array refresh command REFab and same array refresh command REFsb (full array refresh command REFab is used to refresh all arrays of the memory, and same array refresh command REFsb is used to refresh the target array of the memory). The full array refresh command REFab can usually be executed in both refresh modes, while the same array refresh command REFsb can only be executed in the fine-grained refresh mode. If the same array refresh command is issued in the normal refresh mode, the current same array refresh command will be blocked because the same array refresh command cannot be executed.

[0003] With the popularization of the Dynamic Random Access Memory (DRAM) industry, people are no longer just satisfied with the demand for high density and low cost, and process size reduction has become a DRAM development trend. However, as the process size continues to shrink, frequent access to a row will make the bit flipping of the adjacent rows of the row more serious; therefore, RowHammer protection becomes more and more important, and it is necessary to regularly refresh the two adjacent rows of the attacked row. Since the development of DRAM, there have been multiple refresh modes. Row Hammer protection is embedded in these refresh operations, and frequent switching of refresh modes will cause loopholes in Row Hammer protection. Summary of the invention

[0004] The embodiments of the present disclosure provide a refresh control circuit and a memory to provide a Row Hammer protection control strategy when the refresh mode is frequently switched, thereby preventing loopholes in the Row Hammer protection of the memory.

[0005] An embodiment of the present disclosure provides a refresh control circuit, comprising: a counting identification circuit, configured to receive a refresh activation signal, a full array refresh identification signal and a same array refresh identification signal, and when the full array refresh identification signal or the same array refresh identification signal is valid, generate and output a counting identification signal based on each refresh activation signal; wherein the full array refresh identification signal indicates that the memory to which it belongs currently performs a refresh operation based on the full array refresh command; the same array refresh identification signal indicates that the memory to which it belongs currently performs a refresh operation on the last storage array in each storage array group based on the same array refresh command; and the memory to which it belongs generates at least one refresh activation signal based on each full array refresh command or the same array refresh command, and performs a refresh operation based on each refresh activation signal; a counting processing circuit, configured to receive the counting identification signal, and count based on the counting identification signal to generate a counting result; a first control circuit, configured to receive the counting result, and when the counting result is within a first preset range, generate and output a supplementary refresh indication signal at a valid level; wherein when the supplementary refresh indication signal is valid, it indicates that the memory to which it belongs performs a supplementary refresh operation based on the full array refresh command or the same array refresh command.

[0006] The Row Hammer protection strategy of the memory is raised to the overall level of the memory, so that the Row Hammer protection strategy of the memory is no longer limited to a specific refresh mode. At this time, no matter how frequently the refresh mode changes, the refresh control circuit performs a supplementary refresh based on the counting result of the first preset value, that is, the Row Hammer protection is performed when the refresh operation of the memory is executed to the first preset value, thereby preventing loopholes in the Row Hammer protection of the memory.

[0007] Optionally, the first control circuit is also used to receive a precharge delay signal, which is a delay signal of the precharge signal, each of the refresh activation signals corresponds to one precharge signal, and the corresponding memory performs a precharge operation on the corresponding word line based on the precharge signal; the first control circuit includes: a first processing unit, configured to receive a counting result, and generate and output an initial supplementary refresh indication signal based on the counting result, wherein the generated initial supplementary refresh indication signal is at a valid level only when the counting result is within a first preset range; a first D flip-flop, whose input end is used to receive the initial supplementary refresh indication signal, the clock end is used to receive the precharge delay signal, and the output end is used to output the supplementary refresh indication signal; the first D flip-flop is configured to sample the initial supplementary refresh indication signal based on each precharge delay signal to output and latch the supplementary refresh indication signal.

[0008] Optionally, the counting identification circuit includes: a first NAND logic circuit, wherein the first input end is used to receive the same array refresh identification signal, and the second input end is used to receive the refresh activation signal; a second NAND logic circuit, wherein the first input end is used to receive the full array refresh identification signal, and the second input end is used to receive the refresh activation signal; a second NOR logic circuit, wherein the first input end is connected to the output end of the first NAND logic circuit, the second input end is connected to the output end of the second NAND logic circuit, and the output end is used to output the counting identification signal.

[0009] Optionally, the refresh control circuit also includes: a second control circuit, configured to receive a counting result, and when the counting result is a preset value, generate a counting reset signal, the counting reset signal is used to reset the counting result generated by the counting processing circuit, and the preset value is greater than any value within the first preset range.

[0010] Optionally, the second control circuit includes: a second processing unit, which receives the counting result and generates a trigger signal when the counting result is a preset value; a second D flip-flop, whose input end is used to receive the trigger signal, the clock end is used to receive the pre-charge delay signal, and the output end is connected to the first input end of the second AND logic circuit and the input end of the second delay circuit; the output end of the second delay circuit is connected to the input end of the second inverter, the output end of the second inverter is connected to the second input end of the second AND logic circuit, and the output end of the second AND logic circuit is used to output a counting reset signal.

[0011] Optionally, the counting processing circuit includes: K cascaded third D flip-flops, the clock end of the rear third D flip-flop is connected to the inverting output end of the previous third D flip-flop, and the clock end of the first-stage third D flip-flop is used to receive a counting identification signal; the inverting output end of each third D flip-flop is connected to the input end, and the output data of the output end of each third D flip-flop constitutes the counting result.

[0012] Optionally, when the first preset range is [2, 3], the first processing unit includes: a first OR-NOT logic circuit, including K-2 input terminals, and the K-2 input terminals are connected one-to-one with the output terminals of the third D flip-flop of the next K-2 levels; a third AND logic circuit, the first input terminal is connected to the output terminal of the third D flip-flop of the second level, the second input terminal is connected to the output terminal of the first OR-NOT logic circuit, and the output terminal is used to output an initial supplementary refresh indication signal, and K is greater than or equal to 2.

[0013] Optionally, the second processing unit includes: a fourth AND logic circuit, a first input terminal connected to the output terminal of the third-stage third D flip-flop, a second input terminal connected to the output terminal of the fourth-stage third D flip-flop, and an output terminal used to output a trigger signal, K is greater than 4.

[0014] Optionally, the first control circuit also includes: a fifth AND logic circuit, a first input terminal connected to the output terminal of the first D trigger, a second input terminal for receiving a self-refresh identification signal, and an output terminal for outputting an adjusted supplementary refresh indication signal; wherein the self-refresh identification signal indicates whether the memory to which it belongs is in a self-refresh mode; and when the memory to which it belongs is currently in a self-refresh mode, the adjusted supplementary refresh indication signal is at an invalid level.

[0015] Optionally, the counting identification circuit includes: a first NAND logic circuit, wherein the first input terminal is used to receive the same array refresh identification signal, and the second input terminal is used to receive the refresh activation signal; a second NAND logic circuit, wherein the first input terminal is used to receive the full array refresh identification signal, and the second input terminal is used to receive the refresh activation signal; a second NOR logic circuit, wherein the first input terminal is connected to the output terminal of the first NAND logic circuit, the second input terminal is connected to the output terminal of the second NAND logic circuit, and the output terminal is used to output the counting identification signal; a sixth AND logic circuit, wherein the first input terminal is connected to the output terminal of the second NOR logic circuit, the second input terminal is used to receive the self-refresh identification signal, and the output terminal is used to output the counting identification signal.

[0016] Optionally, the refresh control circuit further includes: a signal generating circuit, configured to generate an identical array refresh identification signal.

[0017] Optionally, the signal generating circuit includes: N latches, N is the number of storage arrays in each storage array group in the corresponding memory, and the N latches are arranged in a one-to-one correspondence with the N storage arrays in each storage array group, the set end of each latch is used to receive the same array refresh command corresponding to the corresponding storage array, and the output end of each latch is used to output the corresponding array refresh identification signal; a first AND logic circuit, including N input ends, and the N input ends are connected to the output ends of the N latches in a one-to-one correspondence, and the output end is used to output the same array refresh identification signal; a first delay circuit, the input end is used to receive the same array refresh identification signal, and the output end is connected to the input end of the first inverter; a third OR-NOT logic circuit, the first input end is connected to the output end of the first inverter, the second input end is used to receive the refresh window signal, the output end is used to output the reset control signal, and the reset end of each latch is coupled to the output end of the third OR-NOT logic circuit.

[0018] Optionally, the latch includes: a fourth OR-NOT logic circuit, a first input end serving as a set end of the latch for receiving the same array refresh command corresponding to the corresponding storage array, a second input end connected to the output end of the fifth OR-NOT logic circuit, and an output end connected to the first input end of the fifth OR-NOT logic circuit; the second input end of the fifth OR-NOT logic circuit serving as a reset end of the latch for receiving a reset control signal, and the output end serving as an output end of the latch for outputting a corresponding array refresh identification signal.

[0019] Optionally, the signal generating circuit also includes: a sixth OR-NOT logic circuit, a first input terminal for receiving a full array refresh command, and a second input terminal for receiving a self-refresh command; a third AND-NOT logic circuit, a first input terminal connected to the output terminal of the sixth OR-NOT logic circuit, a second input terminal connected to the output terminal of the third inverter, the input terminal of the third inverter is used to receive a reset control signal, and the output terminal is connected to the reset terminal of each latch.

[0020] Another embodiment of the present disclosure further provides a memory, including the refresh control circuit provided by the above embodiment, to provide a Row Hammer protection control strategy when the refresh mode is frequently switched, thereby preventing loopholes in the Row Hammer protection of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the principle of generating a refresh activation signal in different refresh modes for a memory provided by an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of the structure of a refresh control circuit provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the structure of another refresh control circuit provided by an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of the principle of a refresh control circuit performing stable Row Hammer protection when a refresh mode of a memory is switched according to an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the principle of a refresh control circuit performing stable Row Hammer protection when a refresh mode of another memory provided by an embodiment of the present disclosure is switched;

[0027] Figure 6 A structural schematic diagram of a refresh control circuit for accurately generating a supplementary refresh indication signal provided by an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the structure of a first control circuit for accurately generating a supplementary refresh indication signal provided by an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram of the structure of a counting identification circuit provided in one embodiment of the present disclosure;

[0030] Fig. 9 A schematic diagram of the structure of a signal generating circuit provided by an embodiment of the present disclosure;

[0031] Fig.10 A schematic diagram of the structure of a latch provided in one embodiment of the present disclosure;

[0032] Fig.11 A schematic diagram of the working principle of a signal generating circuit provided in one embodiment of the present disclosure;

[0033] Fig.12 A schematic structural diagram of a refresh control circuit including a second control circuit provided in an embodiment of the present disclosure;

[0034] Fig.13 A schematic diagram of the structure of a second control circuit provided in one embodiment of the present disclosure;

[0035] Fig.14 A schematic diagram of the structure of a counting processing circuit provided in one embodiment of the present disclosure;

[0036] Fig.15 A schematic diagram of the structure of a first processing unit provided in one embodiment of the present disclosure;

[0037] Fig.16 A schematic diagram of the structure of a second processing unit provided in one embodiment of the present disclosure;

[0038] Fig.17 A schematic structural diagram of a refresh control circuit also used for self-refresh shielding provided in an embodiment of the present disclosure;

[0039] Fig.18 A schematic structural diagram of a first control circuit also used for self-refresh shielding provided in an embodiment of the present disclosure;

[0040] Fig.19 A schematic diagram of the structure of a counting identification circuit also used for self-refresh shielding provided in an embodiment of the present disclosure;

[0041] Fig. 20 A schematic diagram of a self-refresh shielding principle provided by an embodiment of the present disclosure;

[0042] Fig.21 A schematic diagram of another principle of self-refresh shielding provided by an embodiment of the present disclosure;

[0043] Fig. 22 A schematic diagram of the structure of a signal generating circuit also used for self-refresh shielding provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] As can be seen from the background technology, DRAM has developed into various refresh modes. Row Hammer protection is embedded in these refresh operations. However, frequent switching of refresh modes will cause loopholes in Row Hammer protection.

[0045] An embodiment of the present disclosure provides a refresh control circuit to provide a Row Hammer protection control strategy when the refresh mode is frequently switched, thereby preventing loopholes in the Row Hammer protection of the memory.

[0046] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0047] Figure 1 A schematic diagram showing the principle of generating a refresh activation signal in different refresh modes in the memory provided in this embodiment, Figure 2 A schematic diagram of the structure of the refresh control circuit provided in this embodiment, Figure 3 A schematic diagram of the structure of another refresh control circuit provided in this embodiment, Figure 4 A schematic diagram of the principle of a refresh control circuit for stable Row Hammer protection when a refresh mode of a memory is switched provided in this embodiment. Figure 5 A schematic diagram of the principle of a refresh control circuit for stable Row Hammer protection when the refresh mode of another memory provided in this embodiment is switched, Figure 6 A schematic diagram of the structure of a refresh control circuit for accurately generating a supplementary refresh indication signal provided by this embodiment, Figure 7 A schematic diagram of the structure of a first control circuit for accurately generating a supplementary refresh indication signal provided in this embodiment, Figure 8 A schematic diagram of the structure of the counting identification circuit provided in this embodiment, Fig. 9 A schematic diagram of the structure of a signal generating circuit provided in this embodiment, Fig.10 A schematic diagram of the structure of a latch provided in this embodiment, Fig.11 A schematic diagram of the working principle of the signal generating circuit provided in this embodiment, Fig.12A schematic diagram of the structure of a refresh control circuit including a second control circuit provided in this embodiment, Fig.13 A schematic diagram of the structure of the second control circuit provided in this embodiment, Fig.14 A schematic diagram of the structure of the counting processing circuit provided in this embodiment, Fig.15 A schematic diagram of the structure of the first processing unit provided in this embodiment, Fig.16 A schematic diagram of the structure of the second processing unit provided in this embodiment, Fig.17 A schematic diagram of the structure of a refresh control circuit also used for self-refresh shielding provided in this embodiment, Fig.18 A schematic diagram of the structure of a first control circuit also used for self-refresh shielding provided in this embodiment, Fig.19 The schematic diagram of the structure of the counting identification circuit also used for self-refresh shielding provided in this embodiment is as follows: Fig. 20 A schematic diagram of the principle of the self-refresh shield provided in this embodiment, Fig.21 Schematic diagram of another self-refresh shielding principle provided in this embodiment Fig. 22 This is a schematic diagram of a structure of a signal generating circuit for self-refresh shielding provided in an embodiment of the present disclosure. The refresh control circuit provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0048] For different memory refresh modes, refer to Figure 1 If the memory is in normal refresh mode and refreshes based on the full array refresh command REFab, during the validity period of each full array refresh command REFab, the memory opens 4 refresh windows in sequence, that is, 4 refresh activation signals, and each refresh window is used to refresh the target addresses of all storage arrays; if the memory is in fine-grained refresh mode and refreshes based on the full array refresh command REFab, during the validity period of each full array refresh command REFab, the memory opens 2 refresh windows in sequence, that is, 2 refresh activation signals, and each refresh window is used to refresh the target addresses of all storage arrays; if the memory is in fine-grained refresh mode and refreshes based on the same array refresh command REFsb, during the validity period of each same array refresh command REFsb, the memory opens 2 refresh windows in sequence, that is, 2 refresh activation signals, and each refresh window is used to refresh the target address of the target storage array.

[0049] It should be noted that the above examples of the number of refresh windows opened in different refresh modes of the memory are only used to help those skilled in the art understand the implementation of the present solution, and do not constitute a limitation on the present embodiment.

[0050] refer to Figure 2 The refresh control circuit 100 provided in the present disclosure includes: a counting identification circuit 101, a counting processing circuit 102 and a first control circuit 110.

[0051] The counting identification circuit 101 is configured to receive the refresh activation signal, the full array refresh identification signal REFab_CNT and the same array refresh identification signal REFsb_CNT, and generate and output a counting identification signal RH_CNT_CLK based on each refresh activation signal when the full array refresh identification signal REFab_CNT or the same array refresh identification signal REFsb_CNT is valid.

[0052] For the full array refresh identification signal REFab_CNT, the full array refresh identification signal REFab_CNT indicates that the memory to which it belongs is currently performing a refresh operation based on the full array refresh command CMD_REFab; for the same array refresh identification signal REFsb_CNT, the same array refresh identification signal REFsb_CNT indicates that the memory to which it belongs is currently performing a refresh operation on the last storage array in each storage array group based on the same array refresh command CMD_REFsb; the memory to which it belongs generates at least one refresh activation signal based on each full array refresh command CMD_REFab or the same array refresh command CMD_REFsb, and performs a refresh operation based on each refresh activation signal.

[0053] For the counting identification signal RH_CNT_CLK, this embodiment takes the valid level of the counting identification signal RH_CNT_CLK, the full array refresh identification signal REFab_CNT and the same array refresh identification signal REFsb_CNT as "1", and the invalid level as "0" as an example for illustration, so as to facilitate those skilled in the art to understand the refresh control circuit provided by the present disclosure, and does not constitute a limitation on this embodiment; in other embodiments, the valid level of the counting identification signal, the full array refresh identification signal and the same array refresh identification signal can be set to "0", and the invalid level can be set to "1".

[0054] It should be noted that in the subsequent figures of this embodiment, the same array refresh identification signal REFsb_CNT received by the counting identification circuit 101 is provided based on the signal generating circuit 103. This is because the generation circuit of the same array refresh identification signal REFsb_CNT is given later in the embodiment of this disclosure.

[0055] Specifically, refer to Figure 4 and Figure 5 For the counting identification circuit 101, when the full array refresh identification signal REFab_CNT is valid, the counting identification circuit 101 generates and outputs a counting identification signal RH_CNT_CLK based on each refresh activation signal, or when the same array refresh identification signal REFsb_CNT is valid, the counting identification circuit 101 generates and outputs a counting identification signal RH_CNT_CLK based on each refresh activation signal.

[0056] Continue to refer Figure 2 The refresh control circuit 100 further includes: a counting processing circuit 102 configured to receive a counting identification signal RH_CNT_CLK and perform counting based on the counting identification RH_CNT_CLK to generate a counting result.

[0057] Specifically, refer to Figure 4 and Figure 5 The counting processing circuit 102 counts based on the counting identification signal RH_CNT_CLK. Every time the counting processing circuit 102 receives a counting identification signal RH_CNT_CLK, the counting result generated by the counting processing circuit 102 is accumulated and added by 1.

[0058] Continue to refer Figure 2 The refresh control circuit 100 also includes: a first control circuit 100, which is configured to receive a counting result, and when the counting result is in a first preset range, generate and output a supplementary refresh indication signal CNT1 at a valid level, and when the supplementary refresh indication signal CNT1 is valid, it indicates that the memory to which it belongs performs a supplementary refresh operation based on the full array refresh command REFab_CNT or the same array refresh command REFsb_CNT, and the supplementary refresh operation is a row hammer refresh or a redundant row address refresh of the memory.

[0059] refer to Figure 4 and Figure 5 It should be noted that, in this embodiment, the first control circuit 110 is specifically described with the first preset range of the counting result being [2, 3] (i.e., when the counting result is greater than or equal to "2" and less than or equal to "3"), so as to facilitate those skilled in the art to understand the refresh control circuit provided by the present disclosure, and does not constitute a limitation on this embodiment. In addition, this embodiment is described by taking the effective level of the supplementary refresh indication signal CNT1 as "1" and the invalid level as "0" as an example, which does not constitute a limitation on this embodiment; in other embodiments, the effective level of the supplementary refresh indication signal CNT1 can be set to "0", and the invalid level can be set to "1".

[0060] For the activation process in the refresh operation, the high level of WIN_ACT_Bank1 indicates that bank1 is currently in the activation window, the high level of WIN_ACT_Bank2 indicates that bank2 is currently in the activation window, the high level of WIN_ACT_Bank3 indicates that bank3 is currently in the activation window, and the high level of WIN_ACT_Bank4 indicates that bank4 is currently in the activation window. Based on the foregoing, when the memory is refreshed based on the full array refresh command CMD_REFab, the full array refresh identification signal REFab_CNT is valid, and the memory opens the activation windows of Bank1 to Bank4 based on each refresh activation signal; when the memory is refreshed based on the same array refresh command CMD_REFab, the memory opens the activation windows of the target storage blocks in Bank1 to Bank4 based on each refresh activation signal.

[0061] refer to Figure 4 When the memory frequently switches between normal refresh mode → fine-grained refresh mode and refresh based on the same array refresh command CMD_REFsb → fine-grained refresh mode and refresh based on the full array refresh command CMD_REFab → normal refresh mode, the supplementary refresh indication signal CNT1 covers the activation windows of the specific storage array twice after the normal refresh mode.

[0062] refer to Figure 5 When the memory frequently switches between fine-grained refresh mode and refresh based on the full array refresh command CMD_REFab → fine-grained refresh mode and refresh based on the same array refresh command CMD_REFsb → fine-grained refresh mode and refresh based on the full array refresh command CMD_REFab → normal refresh mode, the supplementary refresh indication signal CNT1 covers the activation window of the specific storage array in the fine-grained refresh mode and refresh based on the same array refresh command CMD_REFsb.

[0063] When the supplementary refresh indication signal CNT1 is valid, it indicates that the memory to which it belongs performs supplementary refresh based on the full array refresh command CMD_REFab or the same array refresh command CMD_REFsb. The supplementary refresh is the Row Hammer protection process of the memory. For the refresh control circuit 100 provided in this embodiment, the Row Hammer protection strategy of the memory is raised to the overall height of the memory, so that the Row Hammer protection strategy of the memory is no longer limited to a specific refresh mode. At this time, no matter how frequently the refresh mode changes, the refresh control circuit 100 performs supplementary refresh based on the counting result of the first preset value, that is, the Row Hammer protection is performed when the refresh operation of the memory is executed to the first preset value, thereby preventing loopholes in the Row Hammer protection of the memory.

[0064] For the refresh operation of the memory, the memory opens the word line corresponding to the address to be refreshed based on the refresh activation signal, that is, the activation process in the refresh operation. After activating the corresponding word line, the memory cell connected to the word line is charged / discharged to realize the refresh process in the refresh operation. Among them, the memory receives the refresh activation signal, which can be considered that the activation process in the refresh operation starts, and the memory completes the charge / discharge of the memory cell connected to the word line, which can be considered that the refresh process in the refresh operation ends.

[0065] In some embodiments, reference Figure 6 The first control circuit 110 is also used to receive a precharge delay signal REFPRE_DLY, which is a delay signal of the precharge signal. Each refresh activation signal corresponds to a precharge signal. The memory performs a precharge operation on the corresponding word line based on the precharge signal, that is, the charging / discharging of the storage cells connected to the word line as mentioned above.

[0066] refer to Figure 7 The first control circuit 110 includes: a first processing unit 500, which is configured to receive a counting result, and generate and output an initial supplementary refresh indication signal based on the counting result, wherein the generated initial supplementary refresh indication signal CNT0 is at a valid level only when the counting result is in a first preset range; a first D flip-flop 501, wherein the input terminal D is used to receive the initial supplementary refresh indication signal CNT0, the clock terminal CK is used to receive the precharge delay signal REFPRE_DLY, and the output terminal is used to output a supplementary refresh indication signal CNT1, wherein the precharge delay signal REFPRE_DLY is a delay signal of the precharge signal, so that the precharge operation of the current corresponding word line is completed; the memory performs a precharge operation on the corresponding word line based on the precharge signal, and each refresh activation signal corresponds to a precharge signal; the first D flip-flop 501 is configured to sample the initial supplementary refresh indication signal CNT0 based on each precharge delay signal REFPRE_DLY, so as to output and latch the supplementary refresh indication signal CNT1.

[0067] Continue to refer Figure 4 and Figure 5For the supplementary refresh indication signal CNT1, the supplementary refresh indication signal CNT1 needs to cover the next one or more complete row hammer refresh operation processes (based on the specific number of row hammer refresh operations performed by each supplementary refresh indication signal CNT1, which can be set through the parameters in the mode register), so it is necessary to delay the initial supplementary refresh indication signal CNT0 to the completion time of the current refresh operation. Specifically, by sampling CNT0 with the precharge delay signal REFPRE_DLY, the supplementary refresh indication signal CNT1 is delayed to the moment aligned with the precharge delay signal REFPRE_DLY; this delay time can be recorded as t2, t2 is the delay between the count identification signal RH_CNT_CLK and the precharge delay signal REFPRE_DLY.

[0068] It should be noted that in the specific application process, t1 is the delay between the refresh activation signal and the pre-charge delay signal REFPRE_DLY. t1 can represent the execution time of the current refresh operation. Since the pulse of the counting identification signal has a certain delay relative to the pulse of the refresh activation signal, t2 is slightly smaller than t1.

[0069] The principle of generating the supplementary refresh indication signal CNT1 is that when the counting result received by the first control circuit 110 is "2" or "3" which meets the first preset range, the first control circuit 110 generates and outputs the supplementary refresh indication signal CNT1 at a valid level; the process of generating the supplementary refresh indication signal CNT1 includes: the first control circuit 110 generates and outputs the initial refresh indication signal CNT0 at a valid level within the time when the counting result is "2" or "3", and then the first control circuit 110 delays the initial supplementary refresh indication signal CNT0 to generate the supplementary refresh indication signal CNT1, and the purpose of the delay is to ensure that the supplementary refresh indication signal covers the next corresponding two (i.e., the 2nd+1st and 3rd+1st) refresh windows opened by the refresh activation signals.

[0070] For the counting identification circuit, in some embodiments, reference Figure 8 , the counting identification circuit 101 includes: a first NAND logic circuit 201, a first input end for receiving the same array refresh identification signal REFsb_CNT, and a second input end for receiving the refresh activation signal; a second NAND logic circuit 209, a first input end for receiving the full array refresh identification signal REFab_CNT, and a second input end for receiving the refresh activation signal; a second NOR logic circuit 202, a first input end connected to the output end of the first NAND logic circuit 201, a second output end connected to the output end of the second NAND logic circuit 209, and an output end for outputting the counting identification signal RH_CNT_CLK.

[0071] The counting identification circuit 101 implements the arithmetic logic of the counting identification signal RH_CNT_CLK generated by the counting identification circuit 101 based on a logic circuit composed of the first NAND logic circuit 201 , the second NAND logic circuit 209 and the second NOR logic circuit 202 .

[0072] In some embodiments, Figure 3 and Figure 6 As shown, the refresh control circuit 100 further includes: a signal generating circuit for generating a same array refresh identification signal REFsb_CNT.

[0073] In one example, refer to Fig. 9 The signal generating circuit 103 includes: N latches 301, N is the number of storage arrays in each storage array group in the memory, and the N latches 301 are set in one-to-one correspondence with the N storage arrays in each storage array group, and the set end of each latch 301 is used to receive the same array refresh command CMD_REFsb corresponding to the corresponding storage array, and the output end of each latch 301 is used to output the corresponding array refresh identification signal WIN_SB_REF. The first AND logic circuit 302 includes N input ends, and the N input ends are connected to the output ends of the N latches 301 in one-to-one correspondence, and the output end is used to output the same array refresh identification signal REFsb_CNT. The first delay circuit 303 has an input end for receiving the same array refresh identification signal REFsb_CNT, and an output end connected to the input end of the first inverter 304; the third OR logic circuit 305 has a first input end connected to the output end of the first inverter 304, a second input end for receiving the refresh window signal WIN_REF, and an output end for outputting the reset control signal REFsb_CNT_PULL, and the reset end of each latch is coupled to the output end of the first inverter. The refresh window signal WIN_REF is the refresh window opened by the memory based on the same array refresh command CMD_REFsb. When the refresh window exists, the refresh window signal WIN_REF is a valid level "1", and when the refresh window does not exist, the refresh window signal WIN_REF is an invalid level "0".

[0074] In one example, each memory includes M storage array groups (Bank Group), each storage array group (Bank Group) includes N storage arrays (Bank), that is, each memory includes M*N storage arrays. In addition, Fig. 9 The example is illustrated by taking the example that each storage array group includes 4 storage arrays (storage array A, storage array B, storage array C and storage array D) to help those skilled in the art understand the technical solution of the present disclosure, and does not constitute a limitation of this embodiment.

[0075] The set end of latch S1 is used to receive the same array refresh command CMD_REFsb corresponding to storage array A <1> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF0. The set terminal of latch S2 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array B. <2> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF1. The set terminal of latch S3 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array C. <3> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF2. The set terminal of latch S4 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array D. <4> The reset end is used to receive the reset control signal REFsb_CNT_PULL, and the output end is used to output the array refresh identification signal WIN_SB_REF3.

[0076] For each latch 301, in one example, the latch 301 is implemented based on an SR latch, specifically, refer to Fig.10 The latch 301 includes: a fourth OR logic circuit 320, a first input end serving as a set end of the latch 301, for receiving the same array refresh command CMD_REFsb corresponding to the corresponding storage array, a second input end connected to the output end of the fifth OR logic circuit 330, and an output end connected to the first input end of the fifth OR logic circuit 330; a second input end of the fifth OR logic circuit 330 serving as a reset end of the latch 301, for receiving a reset control signal REFsb_CNT_PULL, and an output end serving as an output end of the latch 301, for outputting a corresponding array refresh identification signal WIN_SB_REF.

[0077] It should be noted that Fig.10 The signal flow of latch S1 is illustrated as an example, and those skilled in the art may replace it with the signal flow of latch S2, latch S3 or latch S4 accordingly.

[0078] It should also be noted that in other embodiments, the latch can also be implemented based on the RS latch. Those skilled in the art can Fig.10 The connection mode of the latch 301 is modified in the example, and if the effect is not different from that of the present embodiment, it should all fall within the protection scope of the present disclosure.

[0079] refer to Fig.11, the latch 301 sets the output terminal based on the same array refresh command CMD_REFsb to generate the corresponding array refresh identification signal WIN_SB_REF. A single same array refresh command CMD_REFsb is used to refresh the same storage array of all storage array groups. Four corresponding same array refresh commands CMD_REFsb are required to complete four refreshes of the same storage array group. When the last storage array is refreshed, the same array refresh identification signal REFsb_CNT output by the first AND logic circuit 302 is set to "1", and the refresh window signal WIN_REF is "1" at this time. The reset control signal REFsb_CNT_PULL output by the third OR logic circuit 305 is "1". When the refresh window signal WIN_REF jumps to "0", at this time, the reset control signal REFsb_CNT_PULL output by the third NOR logic circuit 305 is set to "0", and the reset control signal REFsb_CNT_PULL feedback controls the latch 301 to make the corresponding array refresh identification signal WIN_SB_REF set to "0", and the same array refresh identification signal REFsb_CNT output by the first NAND logic circuit 302 is set to "0", and the same array refresh identification signal REFsb_CNT set to "0" is delayed by the first delay circuit 303 for t3, and then the reset control signal REFsb_CNT_PULL is set to "1", that is, when the memory refreshes the last storage array of a storage array group, the signal generating circuit 103 generates a valid pulse of the same array refresh identification signal REFsb_CNT. Among them, the delay t3 of the first delay circuit 303 can be set to any value.

[0080] In some embodiments, reference Fig.12 The refresh control circuit 100 also includes: a second control circuit 120, which is configured to receive a counting result and generate a counting reset signal when the counting result is a preset value, wherein the counting reset signal is used to reset the counting result generated by the counting processing circuit 102, and the preset value is greater than any value within the first preset range.

[0081] It should be noted that, in this embodiment, the second control circuit 120 is specifically described with the preset value of the counting result being "12" to facilitate those skilled in the art to understand the refresh control circuit provided by the present disclosure, and does not constitute a limitation on this embodiment.

[0082] When the counting result received by the second control circuit 120 is "12", that is, the counting result is the preset value, the second control circuit 120 generates a counting reset signal, referring to Figure 4 and Figure 5 , the count reset signal is transmitted to the count processing circuit 102 to reset the count result.

[0083] refer to Fig.13 The second control circuit 120 is also used to receive the pre-charge delay signal REFPRE_DLY. The second control circuit 120 includes: a second processing unit 600, which is configured to receive the counting result and generate a trigger signal RE when the counting result is a preset value; a second D flip-flop 601, whose input end is used to receive the trigger signal RE, whose output end is connected to the first input end of the second AND logic circuit 602 and the output end of the second delay circuit 603, and whose clock end is used to receive the pre-charge delay signal REFPRE_DLY; whose output end is connected to the input end of the second inverter 604, whose output end is connected to the second input end of the second AND logic circuit 602; whose output end is used to output a counting reset signal.

[0084] For the counting processing circuit 102, in some embodiments, reference Fig.14 The counting processing circuit 102 includes: K cascaded third D flip-flops 401, the clock terminal CK of the rear third D flip-flop 401 is connected to the inverting output terminal Q- of the previous third D flip-flop 401, and the clock terminal CK of the first stage third D flip-flop 401 is used to receive the counting identification signal RH_CNT_CLK; the inverting output terminal Q- of the first third D flip-flop 401 is connected to the output terminal D, and the output data of the output terminal of each third D flip-flop 401 constitutes the counting result.

[0085] It should be noted that Fig.14 The example of the counting processing circuit 102 composed of five-stage cascaded third D flip-flops 401 does not constitute a limitation on the counting processing circuit 102. In specific applications, the specific value of K can be set based on specific application scenarios.

[0086] for Fig.14 In the circuit shown in the figure, the data output by the second D flip-flop in the first stage is Q <0> The data output by the second D flip-flop of the second stage is Q <1> , the data output by the second D flip-flop of the third stage is Q <2> , the data output by the second D flip-flop of the fourth stage is Q <3> , the data output by the second D flip-flop of the fifth stage is Q <4> The data output by the first-stage second D flip-flop to the fifth-stage second D flip-flop constitute the counting result Q<4:0>.

[0087] When the count identification signal RH_CNT_CLK is valid, the data output by the second D flip-flop of the first stage is Q <0> The inverting output terminal Q- is set to "1", and a falling edge is generated. The third D flip-flop 401 is configured as a rising edge drive, so the subsequent second D flip-flop does not work. When there is a count identification signal RH_CNT_CLK valid, the data output by the first-stage second D flip-flop is Q <0> The inverting output terminal Q- is set to "0", and a rising edge is generated. The second D flip-flop of the second stage is set to "1" based on this rising edge, and so on, thereby counting based on the cascaded third D flip-flop 401.

[0088] Among them, the data output by the second D flip-flop of the first stage is Q <0> When it is "1", the output result is 1; the data output by the second D flip-flop of the second stage is Q <1> When it is "1", the output result is 2; the data output by the second D flip-flop of the third stage is Q <2> When it is "1", the output result is 4; the data output by the second D flip-flop of the fourth stage is Q <3> When it is "1", the output result is 8; the data output by the second D flip-flop of the fifth stage is Q <4> When it is "1", the output result is 16; the counting result is the sum of all the output results. At this time, the counting processing circuit 102 can count from 0 to 32.

[0089] Based on the foregoing, the first processing unit 500 is used to sample the counting result of the first preset range, and the first preset range is "2" or "3". At this time, the first processing unit 500 can be configured as a logic circuit composed of a NOR gate and an AND gate. Fig.15 , the first processing unit 500 includes: a first OR logic circuit 901, including K-2 input terminals, and the K-2 input terminals are connected to the output terminals of the third D flip-flop 401 of the next K-2 stages in a one-to-one correspondence; a third AND logic circuit 902, the first input terminal of which is connected to the output terminal of the third D flip-flop 401 of the second stage, the second input terminal of which is connected to the output terminal of the first OR logic circuit 901, and the output terminal is used to output the initial supplementary refresh indication signal CNT0, K is greater than or equal to 2. If and only if Q <2> ~Q <k-1>The output is "0" and Q <1> When the output of is "1", the initial supplementary refresh indication signal CNT0 output by the first processing unit 500 is at an effective level. <0> It can be output as "1" or "0", thereby outputting a valid initial supplementary refresh indication signal CNT0 based on the counting results 2 and 3.

[0090] It should be noted that in actual applications, if K=2, then K-1<2, and the highest bit count value of the counting result is Q <1> In this case, the first processing unit 500 does not need to be provided with the first OR logic circuit 901.

[0091] Based on the foregoing, the second processing unit 600 is used to sample the counting result of the preset value, and the preset value is "12". At this time, the second processing unit 600 can be configured as a logic circuit composed of a NOR gate and an AND gate. Fig.16 The second processing unit 600 includes: a fourth AND logic circuit 903, a first input terminal connected to the output terminal of the third-stage third D flip-flop 401, a second input terminal connected to the output terminal of the fourth-stage third D flip-flop 401, and an output terminal for outputting a trigger signal RE. <3> and Q <4> When the output of is "1", the trigger signal RE output by the second processing unit 500 is at a valid level, thereby achieving output of a valid trigger signal RE based on the counting result 12.

[0092] refer to Fig.13 and Fig.14 , the count reset signal is used to reset each third D flip-flop 401 so that the count result is reset to "0", that is, the count processing circuit 102 counts a preset value for one cycle, and in this cycle, the count result is a first preset range to execute the Row Hammer protection of the memory, thereby preventing loopholes in the Row Hammer protection of the memory.

[0093] Since the memory does not need to perform Row Hammer protection during the self-refresh process, in some embodiments, reference Fig.17 and Fig.18 The first control circuit 110 is also used to perform self-refresh shielding, that is, the memory does not generate a supplementary refresh indication signal CNT1 during the self-refresh process.

[0094] Specifically, the first control circuit 110 also includes: a fifth AND logic circuit 502, a first input terminal connected to the output terminal of the first D flip-flop 501, a second input terminal for receiving a self-refresh identification signal SREF, and an output terminal for outputting an adjusted supplementary refresh indication signal CNT1; wherein, the self-refresh identification signal SREF indicates whether the memory to which it belongs is in a self-refresh mode, and when the memory to which it belongs is currently in a self-refresh mode, the self-refresh identification signal SREF is an invalid signal, and the adjusted supplementary refresh indication signal is at an invalid level, thereby achieving that the memory does not perform RowHammer protection within a counting cycle in which a self-refresh mode exists.

[0095] For the self-refresh identification signal SREF, this embodiment is specifically described by taking the effective level of the self-refresh identification signal SREF as "1" and the invalid level as "0" as an example, which does not constitute a limitation of this embodiment; in other embodiments, the effective level of the self-refresh identification signal SREF can be set to "0" and the invalid level can be set to "1".

[0096] In some embodiments, in order to avoid the self-refresh mode affecting the counting of the counting processing circuit 102, in some embodiments, reference Fig.17 and Fig.19 The counting identification circuit 101 is also configured to generate and output a counting identification signal RH_CNT_CLK at an invalid level when the self-refresh identification signal SREF is invalid, wherein the self-refresh identification signal SREF indicates whether the memory to which it belongs is in the self-refresh mode, and when the memory is currently in the self-refresh mode, the self-refresh identification signal SREF is an invalid signal.

[0097] Specifically, refer to Fig.19 , the counting identification circuit 101 includes: a first NAND logic circuit 201, a first input end for receiving the same array refresh identification signal REFsb_CNT, and a second input end for receiving the refresh activation signal; a second NAND logic circuit 209, a first input end for receiving the full array refresh identification signal REFab_CNT, and a second input end for receiving the refresh activation signal; a second NOR logic circuit 202, a first input end connected to the output end of the first NAND logic circuit 201, a second input end connected to the output end of the second NAND logic circuit 209, and a sixth AND logic circuit 203, a first input end connected to the output end of the second NOR logic circuit 202, a second input end for receiving the self-refresh identification signal SREF, and an output end for outputting the counting identification signal RH_CNT_CLK. In one case, the reference Fig. 20 , the refresh activation signal in the self-refresh mode is prevented from being counted through the sixth AND logic circuit 203, and then the initial supplementary refresh identification signal CNT0 in the self-refresh mode is shielded through the fifth AND logic circuit 502, thereby avoiding the influence of the refresh activation signal in the self-refresh mode on the Row Hammer protection strategy. In another case, refer to Fig.21 The sixth AND logic circuit 203 is used to avoid counting the refresh activation signal in the self-refresh mode, thereby avoiding the influence of the refresh activation signal in the self-refresh mode on the counting.

[0098] In addition, the same array refresh identification signal REFsb_CNT must be generated when the memory refreshes the last memory array of a memory array group. In order to prevent the refresh mode change from interfering with the generation of the same array refresh identification signal REFsb_CNT, in some embodiments, the reference Fig. 22 , the signal generating circuit 103 further includes: a sixth NOR logic circuit 306, a first input end for receiving the full array refresh command CMD_REFab, and a second input end for receiving the self-refresh command CMD_SREF; a third NAND logic circuit 307, a first input end connected to the output end of the sixth NOR logic circuit 306, a second input end for receiving the reset control signal REFsb_CNT_PULL, and an output end connected to the reset end of each latch 301. That is, if the memory changes in the refresh mode during the refresh process based on the same array refresh command CMD_REFsb, the signal generating circuit 103 directly resets the latch 301 based on the self-refresh command CMD_SREF and the full array refresh command CMD_REFab, thereby not generating the same array refresh identification signal REFsb_CNT, so as to ensure the generation logic of the same array refresh identification signal REFsb_CNT.

[0099] For the refresh control circuit provided in this embodiment, the Row Hammer protection strategy of the memory is raised to the overall level of the memory, so that the Row Hammer protection strategy of the memory is no longer limited to a specific refresh mode. At this time, no matter how frequently the refresh mode changes, the refresh control circuit performs a supplementary refresh based on the counting result of the first preset value, that is, when the refresh operation of the memory is executed to the first preset value, the Row Hammer protection is executed, thereby preventing loopholes in the Row Hammer protection of the memory.

[0100] It should be noted that the features disclosed in the refresh control circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain a new refresh control circuit embodiment.

[0101] Another embodiment of the present disclosure provides a memory, including the refresh control circuit provided by the above embodiment, to provide a Row Hammer protection control strategy when the refresh mode is frequently switched, thereby preventing loopholes in the Row Hammer protection of the memory.

[0102] Specifically, the Row Hammer protection strategy of the memory is raised to the overall level of the memory, so that the Row Hammer protection strategy of the memory is no longer limited to a specific refresh mode. At this time, no matter how frequently the refresh mode changes, the refresh control circuit performs a supplementary refresh based on the counting result of the first preset value, that is, the Row Hammer protection is performed when the refresh operation of the memory is executed to the first preset value, thereby preventing loopholes in the Row Hammer protection of the memory.

[0103] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0104] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A refresh control circuit, characterized in that: include: A counting identification circuit is configured to receive a refresh activation signal, a full array refresh identification signal and a same array refresh identification signal, and generate and output a counting identification signal based on each refresh activation signal when the full array refresh identification signal or the same array refresh identification signal is valid; Wherein, the full array refresh identification signal indicates that the memory to which it belongs currently performs a refresh operation based on the full array refresh command; the same array refresh identification signal indicates that the memory to which it belongs currently performs a refresh operation on the last storage array in each storage array group based on the same array refresh command; and the memory to which it belongs generates at least one refresh activation signal based on each full array refresh command or the same array refresh command, and performs a refresh operation based on each refresh activation signal; A counting processing circuit is configured to receive the counting identification signal and perform counting based on the counting identification signal to generate a counting result; The first control circuit is configured to receive the counting result, and when the counting result is within a first preset range, generate and output a supplementary refresh indication signal at a valid level; wherein, when the supplementary refresh indication signal is valid, it instructs the corresponding memory to perform a supplementary refresh operation based on the full array refresh command or the same array refresh command.

2. The refresh control circuit according to claim 1, characterized in that: The first control circuit is further used to receive a precharge delay signal, where the precharge delay signal is a delayed signal of the precharge signal, each refresh activation signal corresponds to one precharge signal, and the memory performs a precharge operation on the corresponding word line based on the precharge signal; The first control circuit comprises: a first processing unit configured to receive the counting result, and generate and output an initial supplementary refresh indication signal based on the counting result, wherein the generated initial supplementary refresh indication signal is at a valid level only when the counting result is within the first preset range; A first D flip-flop, whose input terminal is used to receive the initial supplementary refresh indication signal, whose clock terminal is used to receive the precharge delay signal, and whose output terminal is used to output the supplementary refresh indication signal; The first D flip-flop is configured to sample the initial supplementary refresh indication signal based on each of the precharge delay signals to output and latch the supplementary refresh indication signal.

3. The refresh control circuit according to claim 1, characterized in that: The counting identification circuit comprises: A first NAND logic circuit, wherein the first input terminal is used to receive the same array refresh identification signal, and the second input terminal is used to receive the refresh activation signal; A second NAND logic circuit, wherein the first input terminal is used to receive the full array refresh identification signal, and the second input terminal is used to receive the refresh activation signal; The second NOR logic circuit has a first input end connected to the output end of the first NAND logic circuit, a second input end connected to the output end of the second NAND logic circuit, and an output end used to output the counting identification signal.

4. The refresh control circuit according to claim 2, characterized in that: Also includes: The second control circuit is configured to receive the counting result and generate a counting reset signal when the counting result is a preset value, wherein the counting reset signal is used to reset the counting result generated by the counting processing circuit, and the preset value is greater than any value within the first preset range.

5. The refresh control circuit according to claim 4, characterized in that: The second control circuit comprises: A second processing unit receives the counting result and generates a trigger signal when the counting result is the preset value; A second D flip-flop, whose input end is used to receive the trigger signal, whose clock end is used to receive the precharge delay signal, and whose output end is connected to the first input end of the second AND logic circuit and the input end of the second delay circuit; The output end of the second delay circuit is connected to the input end of the second inverter, the output end of the second inverter is connected to the second input end of the second AND logic circuit, and the output end of the second AND logic circuit is used to output the counting reset signal.

6. The refresh control circuit according to claim 5, characterized in that: The counting processing circuit comprises: K cascaded third D flip-flops, the clock end of the third D flip-flop of the latter stage is connected to the inverting output end of the third D flip-flop of the former stage, and the clock end of the third D flip-flop of the first stage is used to receive the counting identification signal; An inverting output terminal of each of the third D flip-flops is connected to an input terminal, and output data of an output terminal of each of the third D flip-flops constitutes the counting result.

7. The refresh control circuit according to claim 6, characterized in that: When the first preset range is [2, 3], the first processing unit includes: The first NOR logic circuit includes K-2 input terminals, and the K-2 input terminals are connected to the output terminals of the third D flip-flops of the subsequent K-2 stages in a one-to-one correspondence; The third AND logic circuit has a first input connected to the output of the second-stage third D flip-flop, a second input connected to the output of the first OR-NOT logic circuit, and an output for outputting the initial supplementary refresh indication signal, K being greater than or equal to 2.

8. The refresh control circuit according to claim 6, characterized in that: The second processing unit comprises: The fourth AND logic circuit has a first input terminal connected to the output terminal of the third-stage third D flip-flop, a second input terminal connected to the output terminal of the fourth-stage third D flip-flop, and an output terminal used to output the trigger signal, and K is greater than or equal to 4.

9. The refresh control circuit according to claim 2, characterized in that: The first control circuit further includes: A fifth AND logic circuit, wherein the first input terminal is connected to the output terminal of the first D flip-flop, the second input terminal is used to receive the self-refresh identification signal, and the output terminal is used to output the adjusted supplementary refresh indication signal; The self-refresh identification signal indicates whether the memory is in the self-refresh mode; and when the memory is currently in the self-refresh mode, the adjusted supplementary refresh indication signal is in an invalid level.

10. The refresh control circuit according to claim 9, characterized in that: The counting identification circuit comprises: A first NAND logic circuit, wherein the first input terminal is used to receive the same array refresh identification signal, and the second input terminal is used to receive the refresh activation signal; A second NAND logic circuit, wherein the first input terminal is used to receive the full array refresh identification signal, and the second input terminal is used to receive the refresh activation signal; A second NOR logic circuit, wherein a first input end is connected to the output end of the first NAND logic circuit, a second input end is connected to the output end of the second NAND logic circuit, and an output end is used to output the counting identification signal; A sixth AND logic circuit has a first input terminal connected to the output terminal of the second OR logic circuit, a second input terminal for receiving the self-refresh identification signal, and an output terminal for outputting the counting identification signal.

11. The refresh control circuit according to any one of claims 1 to 10, characterized in that: Also includes: The signal generating circuit is used to generate the same array refresh identification signal.

12. The refresh control circuit according to claim 11, characterized in that: The signal generating circuit comprises: N latches, N being the number of storage arrays in each storage array group in the memory, and the N latches being arranged in one-to-one correspondence with the N storage arrays in each storage array group, the set end of each latch being used to receive the same array refresh command corresponding to the corresponding storage array, and the output end of each latch being used to output a corresponding array refresh identification signal; A first AND logic circuit includes N input terminals, and the N input terminals are connected to the output terminals of the N latches in a one-to-one correspondence, and the output terminal is used to output the same array refresh identification signal; A first delay circuit, whose input end is used to receive the same array refresh identification signal, and whose output end is connected to the input end of the first inverter; A third OR-NOT logic circuit has a first input terminal connected to the output terminal of the first inverter, a second input terminal for receiving a refresh window signal, an output terminal for outputting a reset control signal, and a reset terminal of each latch coupled to the output terminal of the third OR-NOT logic circuit.

13. The refresh control circuit according to claim 12, characterized in that: The latch comprises: A fourth OR-NOT logic circuit, wherein the first input terminal is used as the set terminal of the latch, and is used to receive the same array refresh command corresponding to the corresponding storage array, the second input terminal is connected to the output terminal of the fifth OR-NOT logic circuit, and the output terminal is connected to the first input terminal of the fifth OR-NOT logic circuit; The second input terminal of the fifth OR-NOT logic circuit serves as the reset terminal of the latch for receiving the reset control signal, and the output terminal serves as the output terminal of the latch for outputting the corresponding array refresh identification signal.

14. The refresh control circuit according to claim 12, characterized in that: The signal generating circuit further includes: A sixth OR-NOT logic circuit, wherein the first input terminal is used to receive the full array refresh command, and the second input terminal is used to receive a self-refresh command; The third NAND logic circuit has a first input terminal connected to the output terminal of the sixth OR-NON logic circuit, a second input terminal connected to the output terminal of the third inverter, the input terminal of the third inverter is used to receive the reset control signal, and the output terminal is connected to the reset terminal of each of the latches.

15. A memory, characterized in that: The refresh control circuit comprises the refresh control circuit according to any one of claims 1 to 14.

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