Training method, electronic device and medium for reading logic gate enable signal

Abstract

The present application relates to the field of memory technology and provides a training method, electronic device and medium for reading logic gate enable signals. In the face of edge judgment error problems, the training method compares the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, and according to the comparison result, selects the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal to calculate the first delay value, or selects the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal to calculate the second delay value. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a training method, electronic device and medium for reading logic gate enable signals. Background Art

[0002] The fifth generation of double data rate (DDR5) memory and low power double data rate (LPDDR5) memory, as well as memory types that use similar storage technology specifications, need to train the read logic gate enable signal in data reading. For example, after the physical layer of the interface circuit connected to the dynamic random access memory (DRAM) using the LPDDR5 standard issues a read command, it may reach the DRAM through various paths, such as cache, other hardware, etc. After receiving the read command, the DRAM feeds back the data pulse (Data, DQ) signal and the data selection pulse (Data Strobe, DQS) signal. After these two signals reach the physical layer of the interface circuit, the interface circuit opens the read logic gate (read gate) to activate the receiver and receives the complete data. The data is sent in burst mode. In order to ensure that the complete data sent in burst mode is received, the physical layer of the interface circuit needs to use the data selection pulse signal to train the read logic gate enable signal to match the transition from low level to high level of the data selection pulse signal. In the prior art, due to the influence of various possible path delays, the time for the data pulse signal and the data selection pulse signal to arrive at the physical layer after a read command is issued from the physical layer is difficult to predict. In addition, due to the influence of electrical characteristics, the waveform of the data selection pulse signal sent in a burst manner may not be ideal, which may result in errors in edge judgment when training the read logic gate enable signal, thereby possibly leading to poor training results, data reading deviations, data loss and other problems.

[0003] To this end, the present application provides a training method, electronic device and medium for reading logic gate enable signals. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay, electrical characteristics, chip manufacturing process deviation and chip operating conditions can be effectively overcome. Summary of the invention

[0004] In a first aspect, the present application provides a training method for a read logic gate enable signal. The training method comprises: receiving a first data selection pulse signal sequence for data reading of a first memory, wherein the first data selection pulse signal sequence comprises a plurality of differential signal pairs in sequence, and the sampling of each differential signal pair in the plurality of differential signal pairs is based on the rising edge of a first phase signal and a falling edge of a second phase signal included in the differential signal pair; when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to a preset threshold, based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, calculating a first delay value, and then, using the first Delay value is used to train the read logic gate enable signal to be trained; when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determine whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold, if so, calculate the second delay value based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then use the second delay value to train the read logic gate enable signal to be trained.

[0005] Through the first aspect of the present application, the improved training method can effectively and accurately locate the delay value of the read logic gate enable signal, and can effectively overcome the effects of path delay, electrical characteristics, chip manufacturing process deviation and chip operating conditions.

[0006] In a possible implementation of the first aspect of the present application, the training method also includes: when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determining whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is higher than or equal to the preset threshold; if not, determining whether the duty cycle of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal in the first data selection pulse signal sequence relative to the second data selection pulse signal is higher than or equal to the preset threshold; if yes, calculating a third delay value based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal and the rising edge of the read logic gate enable signal to be trained; and then using the third delay value to train the read logic gate enable signal to be trained.

[0007] In a possible implementation manner of the first aspect of the present application, the second data selection pulse signal is sent immediately after the first data selection pulse signal in the first data selection pulse signal sequence.

[0008] In a possible implementation manner of the first aspect of the present application, the third data selection pulse signal is sent immediately after the second data selection pulse signal in the first data selection pulse signal sequence.

[0009] In a possible implementation of the first aspect of the present application, calculating the first delay value includes: starting from the initial position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, thereby determining the first delay value.

[0010] In a possible implementation manner of the first aspect of the present application, calculating the first delay value further includes: subtracting a compensation value corresponding to the pre-emphasis jump signal sent by the first memory from the determined first delay value.

[0011] In a possible implementation of the first aspect of the present application, calculating the second delay value includes: starting from the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping half of the clock cycle associated with the first data selection pulse signal sequence as the second position of the rising edge of the read logic gate enable signal to be trained, and then, starting from the second position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal, thereby determining the second delay value.

[0012] In a possible implementation manner of the first aspect of the present application, calculating the second delay value further includes: subtracting a compensation value corresponding to the pre-emphasis jump signal sent by the first memory from the determined second delay value.

[0013] In a possible implementation manner of the first aspect of the present application, when the pre-emphasis jump signal sent by the first memory is one, the compensation value corresponding to the pre-emphasis jump signal sent by the first memory is one quarter of the clock cycle.

[0014] In a possible implementation of the first aspect of the present application, calculating the third delay value includes: starting from the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping two thirds of the clock cycle associated with the first data selection pulse signal sequence as the third position of the rising edge of the read logic gate enable signal to be trained, and then, starting from the third position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal, thereby determining the third delay value.

[0015] In a possible implementation of the first aspect of the present application, the first data selection pulse signal sequence is issued by the first memory in response to a data read command, the data read command is issued by the physical layer of the interface circuit connected to the first memory, and the training method is executed by the physical layer of the interface circuit.

[0016] In a possible implementation manner of the first aspect of the present application, the first data selection pulse signal sequence is sent in a burst manner.

[0017] In a possible implementation manner of the first aspect of the present application, each of the plurality of differential signal pairs includes a pair of two square wave pulse signals, or a pair of two sine wave pulse signals.

[0018] In a possible implementation manner of the first aspect of the present application, the preset threshold is 50%, 48%, 45% or 40%.

[0019] In a possible implementation of the first aspect of the present application, the first memory is a dynamic random access memory that complies with the fifth generation double data rate storage technology specification or the low power fifth generation double data rate storage technology specification.

[0020] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0021] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0022] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A flowchart of a training method for reading a logic gate enable signal provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a first memory and an interface circuit provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0028] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0029] Figure 1 A flowchart of a training method for reading a logic gate enable signal provided by an embodiment of the present application is shown below. Figure 1 As shown, the training method includes the following steps.

[0030] Step S101: Receive a first data selection pulse signal sequence for data reading of a first memory, wherein the first data selection pulse signal sequence includes a plurality of differential signal pairs in sequence, and sampling of each differential signal pair in the plurality of differential signal pairs is based on a rising edge of a first phase signal and a falling edge of a second phase signal included in the differential signal pair.

[0031] Step S103: When the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to a preset threshold, a first delay value is calculated based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then the first delay value is used to train the read logic gate enable signal to be trained.

[0032] Step S105: When the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determine whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold; if so, calculate the second delay value based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained; and then, use the second delay value to train the read logic gate enable signal to be trained.

[0033] Figure 1The training method for reading logic gate enable signal shown can be applied to application fields such as data center, artificial intelligence, cloud computing, automobile driving, industrial control, etc. In these application fields, fifth-generation double data rate (Double Data Rate 5, DDR5) memory and low power fifth-generation double data rate (Low Power Double Data Rate 5, LPDDR5) memory are used, and there are memory types using similar storage technology specifications. Therefore, it is necessary to train the read logic gate enable signal in data reading. For example, the physical layer of the interface circuit connected to the dynamic random access memory (dynamic RAM, DRAM) using the LPDDR5 standard may reach the DRAM through various paths such as cache and other hardware after issuing a read command. After receiving the read command, the DRAM feeds back a data pulse (Data, DQ) signal and a data selection pulse (Data Strobe, DQS) signal. After these two signals reach the physical layer of the interface circuit, the interface circuit opens the read logic gate (read gate) to activate the receiver, receives the complete data, and the data is sent in a burst mode. In order to ensure that the complete data sent in burst mode is received, the physical layer of the interface circuit needs to use the data selection pulse signal to train the read logic gate enable signal, so as to match the jump from low level to high level of the data selection pulse signal. Because of the influence of various possible path delays, the time when the data pulse signal and the data selection pulse signal arrive at the physical layer after the read command is issued from the physical layer is difficult to predict, and the waveform of the data selection pulse signal sent in burst mode may also be unsatisfactory due to the influence of electrical characteristics. For this reason, it is necessary to ensure that the edge can be accurately and reliably judged when training the read logic gate enable signal, so as to ensure good training effect and avoid data reading deviation and data loss. Here, because the data selection pulse signal is generally sent in a burst mode, taking the common square wave pulse as an example, there is a moment from a low level, such as corresponding to 0, to a high level, such as corresponding to 1, so the read logic gate enable signal should be able to sample the jump from 0 to 1 better after training. Taking the square wave pulse as an example, the duty cycle of the square wave pulse is 50% under ideal conditions, that is, half a cycle is 0 and the other half cycle is 1. Affected by electrical characteristics, such as the influence of components such as capacitors on the signal transmission path, the duty cycle of the pulse signal may deviate from the ideal situation, which may cause waveform deformation, waveform distortion, and waveform distortion. In addition, the data selection pulse signal generally adopts a differential signal method, that is, the data selection pulse signal is actually divided into a pair of differential signal pairs of T-phase signal and C-phase signal. Therefore, there may be a clock offset between the T-phase signal and the C-phase signal of the same differential signal pair. In this case, the impact caused by the clock offset also needs to be considered. Figure 1 Further details are given.

[0034] refer to Figure 1 , in step S101, a first data selection pulse signal sequence for data reading of a first memory is received, wherein the first data selection pulse signal sequence includes a plurality of differential signal pairs in sequence, and the sampling of each differential signal pair in the plurality of differential signal pairs is based on the rising edge of the first phase signal and the falling edge of the second phase signal included in the differential signal pair. Here, the first data selection pulse signal sequence means a plurality of data selection pulse signals in sequence, which are sent one by one by the first memory in sequence order and then received by the physical layer of the interface circuit connected to the first memory. The data selection pulse signals in the first data selection pulse signal sequence are transmitted in the form of differential signals, therefore, the first data selection pulse signal sequence includes a plurality of differential signal pairs in sequence, which correspond one to one with the data selection pulse signals in the first data selection pulse signal sequence, that is, each data selection pulse signal in the first data selection pulse signal sequence corresponds to a differential signal pair. Each differential signal pair means a differential signal pair consisting of a T phase signal and a C phase signal, and here, each differential signal pair consists of a first phase signal and a second phase signal. The sampling of each differential signal pair is based on the rising edge of the first phase signal and the falling edge of the second phase signal included in the differential signal pair. As mentioned above, after the read command is issued from the physical layer, the time when the data pulse signal and the data selection pulse signal arrive at the physical layer is difficult to predict, and affected by the electrical characteristics, the waveform of the data selection pulse signal sent in a burst mode may not be ideal. Therefore, the duty cycle of the first phase signal and the second phase signal of each differential signal pair may be unsatisfactory, that is, there is a certain deviation from the ideal 50% duty cycle. This brings challenges to determining the rising edge of the first phase signal and the falling edge of the second phase signal, that is, determining the edge. In addition, there may be a clock offset between the first phase signal and the second phase signal, for example, due to the influence of the transmission path.

[0035] Continue to refer Figure 1In step S103, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold, a first delay value is calculated based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then the first delay value is used to train the read logic gate enable signal to be trained. In step S105, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, it is determined whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal in the first data selection pulse signal sequence relative to the first data selection pulse signal is higher than or equal to the preset threshold, if yes, a second delay value is calculated based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then the second delay value is used to train the read logic gate enable signal to be trained. Here, through step S103 and step S105, based on the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence, by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with the preset threshold, the subsequent steps of step S103 are selectively executed to calculate the first delay value so as to use the first delay value to train the read logic gate enable signal to be trained, or the subsequent steps of step S105 are executed to calculate the second delay value so as to use the second delay value to train the read logic gate enable signal to be trained. Here, the basis for judgment is whether the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is higher than or equal to the preset threshold, or is lower than the preset threshold. When the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is higher than or equal to the preset threshold, this means that the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal meets the design requirements. In this way, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal can be used to calculate the trained delay value, and then it can be combined with other requirements of the first memory, such as the redundant pre-emphasis (PRE) jump signal issued by DRAM to subtract the corresponding compensation value. The actual delay value finally obtained can be used to determine the compensated position of the read logic gate enable signal.

[0036] Continue to refer Figure 1, considering the influence of electrical characteristics, the signal in the first data selection pulse signal sequence may have waveform distortion, waveform distortion, etc., which may lead to a poor duty cycle of the signal. Therefore, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is lower than the preset threshold, this means that the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal does not meet the design requirements. Therefore, if the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal continues to be used as the judgment basis, it may lead to a large error in the delay value calculated and trained, and finally lead to a large deviation between the compensated position of the read logic gate enable signal and the edge position. Moreover, as the performance of the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal becomes worse, for example, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is lower than the preset threshold and the gap is larger, this may lead to a larger deviation between the compensated position of the read logic gate enable signal and the actual signal edge position, thereby resulting in poor training effect, and further causing data reading errors and data loss.

[0037] Continue to refer Figure 1, by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with the preset threshold, and then selectively executing different delay value calculation and training subsequent steps according to the comparison result, it is realized that when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal performs poorly, it is considered whether to use the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal. Further, in the case where the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal performs poorly, if it is determined that the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is higher than or equal to the preset threshold, it means that the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal meets the design requirements, then, the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is used as a reference, and corresponding adjustments are made to the compensation algorithm, so as to calculate the second delay value and use the second delay value to train the read logic gate enable signal to be trained, so that the compensation value of the read logic gate enable signal determined in this way is The compensated position overcomes the adverse effect caused by the poor performance of the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, and by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with the preset threshold, according to the comparison result, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is selected to calculate the first delay value, or the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is selected to calculate the second delay value, which means that the calculation of the delay value only needs to be performed once, that is, only one gate delay signal needs to be generated, which can be achieved by any suitable gate delay circuit. Therefore, in the implementation of the algorithm and circuit, only one delay value calculation and only one gate delay signal generation can realize the accurate and reliable positioning of the position of the trained read logic gate enable signal, that is, the compensated position of the read logic gate enable signal. In addition, it should be noted that the calculation of the second delay value is based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained. The second delay value calculated and trained in this way can be combined with other requirements of the first memory, such as the redundant pre-emphasis (PRE) jump signal issued by the DRAM to subtract the corresponding compensation value, and the actual delay value finally obtained can be used to determine the compensated position of the read logic gate enable signal. Therefore, the calculation of the second delay value is not based on the falling edge of the second phase signal of the differential signal pair corresponding to the first data selection pulse signal, nor is it based on the falling edge of the second phase signal of the differential signal pair corresponding to the second data selection pulse signal.In other words, the calculation of the second delay value is based only on the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal, for example, by adjusting the delay of the rising edge of the read logic gate enable signal to be trained through a compensation algorithm, so that when the rising edge of the read logic gate enable signal to be trained can sample the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal, for example, when sampling the level jump from 0 to 1, the delay value trained at this time can be used as the edge of the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. In this way, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0038] Continue to refer Figure 1 , affected by the process voltage temperature (PVT), such as the deviation of the chip manufacturing process such as the difference in process corners, and the chip working conditions such as the chip supply voltage (Voltage) and the chip operating temperature (Temperature), which may cause the driving capability, performance and gate delay of the logic gate device to deviate, which affects the differential signal pairs transmitted along different signal transmission paths. Therefore, the first phase signal and the second phase signal of each differential signal pair may be affected by the chip manufacturing process deviation and the chip working conditions, and there is a clock offset, which means that if the edge of the first phase signal and the edge of the second phase signal of the same differential signal pair are used to calculate the delay value, the influence of routing and offset needs to be considered. Figure 1 The training method for reading the logic gate enable signal shown in the figure compares the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, and according to the comparison result, selects to calculate the first delay value based on the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, or selects to calculate the second delay value based on the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. In this way, Figure 1The training method for reading the logic gate enable signal shown in the figure only selects the edge of the first phase signal as the reference, and the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the first phase signal of the differential signal pair corresponding to the second data selection pulse signal use the same routing and pass through the same signal transmission path, and are therefore affected by the same logic gate device, which can effectively overcome the above-mentioned effects such as clock offset caused by chip manufacturing process deviations and chip working condition deviations. In this way, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the effects of path delay, electrical characteristics, chip manufacturing process deviations and chip working conditions can be effectively overcome.

[0039] refer to Figure 1 , Figure 1 The training method for reading the logic gate enable signal shown in the figure compares the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, and according to the comparison result, selects to calculate the first delay value based on the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, or selects to calculate the second delay value based on the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. Here, Figure 1 The training method for the read logic gate enable signal shown is based on the rising edge of the read logic gate enable signal to be trained as the sampling signal. To this end, during the training process, the rising edge of the read logic gate enable signal to be trained is adjusted by a compensation algorithm. When the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the corresponding data selection pulse signal (the first data selection pulse signal or the second data selection pulse signal), this is used as a basis to determine the compensated position of the read logic gate enable signal. It should be understood that Figure 1 The training method for the read logic gate enable signal shown can also be understood to include a case where the falling edge of the read logic gate enable signal to be trained is used as a sampling signal, that is, during the training process, the falling edge of the read logic gate enable signal to be trained is adjusted by a compensation algorithm, and when the falling edge of the read logic gate enable signal to be trained samples the falling edge of the second phase signal of the differential signal pair corresponding to the corresponding data selection pulse signal, this is used as a basis to determine the compensated position of the read logic gate enable signal. Therefore, Figure 1The training method for reading logic gate enable signals shown in the figure is based on the rising edge of the first phase signal and the falling edge of the second phase signal included in the differential signal pair. The rising edge of the read logic gate enable signal to be trained is used as the sampling signal, and the rising edge of the read logic gate enable signal to be trained is used to sample the rising edge of the first phase signal; on the contrary, the falling edge of the read logic gate enable signal to be trained is used as the sampling signal, and the falling edge of the read logic gate enable signal to be trained is used to sample the falling edge of the second phase signal. In this way, because the edge of the first phase signal is selected as the reference (the first data selection pulse signal or the second data selection pulse signal), or the edge of the second phase signal is selected as the reference (the first data selection pulse signal or the second data selection pulse signal), the same routing is used, and the same signal transmission path is passed, so it is also affected by the same logic gate device, which can effectively overcome the above-mentioned influences such as clock offset caused by chip manufacturing process deviation and chip working condition deviation. In this way, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay, electrical characteristics, chip manufacturing process deviation and chip working conditions can be effectively overcome.

[0040] In conclusion, Figure 1 The training method for reading the logic gate enable signal shown in the figure compares the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold value. According to the comparison result, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is selected to calculate the first delay value, or the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is selected to calculate the second delay value. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0041] Figure 2 A schematic diagram of a first memory and an interface circuit provided in an embodiment of the present application. Figure 2As shown, the first memory 201 is connected to the interface circuit 203. A first data selection pulse signal sequence is issued by the first memory 201 in response to a data read command, and the data read command is issued by the physical layer of the interface circuit 203 connected to the first memory 201, and the training method is executed by the physical layer of the interface circuit 203. The training method includes: receiving a first data selection pulse signal sequence for data reading of the first memory 201, wherein the first data selection pulse signal sequence includes a plurality of differential signal pairs in sequence, and the sampling of each differential signal pair in the plurality of differential signal pairs is based on the rising edge of the first phase signal and the falling edge of the second phase signal included in the differential signal pair; when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to a preset threshold, based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, a first delay value is calculated, and then, the first delay value is calculated using the first delay value. A first delay value is used to train the read logic gate enable signal to be trained; when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, it is determined whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold, and if so, a second delay value is calculated based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then the second delay value is used to train the read logic gate enable signal to be trained.

[0042] Figure 2 The first memory and interface circuit shown in the figure, the training method executed by them, by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold value, according to the comparison result, selects to calculate the first delay value based on the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, or selects to calculate the second delay value based on the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0043] refer to Figure 1 and Figure 2In a possible implementation, the training method further includes: when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determining whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is higher than or equal to the preset threshold; if not, determining whether the duty cycle of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal relative to the second data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold; if yes, calculating a third delay value based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal and the rising edge of the read logic gate enable signal to be trained; and then, using the third delay value to train the read logic gate enable signal to be trained. Considering the influence of electrical characteristics, the signal in the first data selection pulse signal sequence may have waveform distortion, waveform aberration, etc., which may lead to poor duty cycle of the signal. Therefore, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is lower than the preset threshold, this means that the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal does not meet the design requirements. Therefore, if the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal continues to be used as the judgment basis, it may lead to a large error in the delay value calculated and trained, and finally lead to a large deviation between the compensated position of the read logic gate enable signal and the edge position. Moreover, as the performance of the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal becomes worse, for example, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is lower than the preset threshold and the gap is larger, this may lead to a larger deviation between the compensated position of the read logic gate enable signal and the actual signal edge position, thereby leading to poor training effect, and then causing data reading errors and data loss. To this end, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal performs poorly, consider whether to use the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal. Further, when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal performs poorly, if the judgment is no, that is, it is judged that the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is lower than the preset threshold, then this means that the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal also does not meet the design requirements.In this way, continue to judge whether the duty cycle of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal relative to the second data selection pulse signal is higher than or equal to the preset threshold value. If it is judged to be yes, then when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal are both poor, use the edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal as a reference, and make corresponding adjustments in the compensation algorithm, so as to calculate the third delay value and use the third delay value to train the read logic gate enable signal to be trained, so as to determine the compensated position of the read logic gate enable signal. In this way, the influence of poor signal duty cycle is effectively overcome. It should be understood that, when the duty cycle of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal does not meet the design requirements, the subsequent fourth data selection pulse signal and the fifth data selection pulse signal are selected in order until the duty cycle of the first phase signal of the differential signal pair corresponding to the selected data selection pulse signal meets the design requirements (that is, higher than or equal to the preset threshold value). In this way, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay, electrical characteristics, chip manufacturing process deviation and chip working conditions can be effectively overcome. In addition, it should be understood that no matter which edge of the first phase signal of the differential signal pair corresponding to the data selection pulse signal is selected as the reference, it means that the calculation of the delay value only needs to be performed once, that is, only one gate delay signal needs to be generated, which can be achieved by any suitable gate delay circuit. Therefore, in the implementation of the algorithm and the circuit, only one delay value calculation and only one gate delay signal generation can achieve accurate and reliable positioning of the position of the trained read logic gate enable signal, that is, the compensated position of the read logic gate enable signal.

[0044] In a possible implementation, the second data selection pulse signal is sent immediately after the first data selection pulse signal in the first data selection pulse signal sequence. Thus, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay, electrical characteristics, chip manufacturing process deviation and chip working conditions can be effectively overcome.

[0045] In some embodiments, the third data selection pulse signal is sent immediately after the second data selection pulse signal in the first data selection pulse signal sequence. Thus, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay, electrical characteristics, chip manufacturing process deviation and chip working conditions can be effectively overcome.

[0046] In a possible implementation, calculating the first delay value includes: starting from the initial position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, thereby determining the first delay value. The first phase signal and the second phase signal of each differential signal pair may be affected by the chip manufacturing process deviation and the chip working conditions, and there is a clock offset, which means that if the edge of the first phase signal and the edge of the second phase signal of the same differential signal pair are used to calculate the delay value, the influence of routing and offset needs to be considered. Figure 1 The training method for reading the logic gate enable signal shown in the figure compares the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, and according to the comparison result, selects to calculate the first delay value based on the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, or selects to calculate the second delay value based on the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. In this way, Figure 1 The training method for reading the logic gate enable signal shown in the figure only selects the edge of the first phase signal as the reference, and the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the first phase signal of the differential signal pair corresponding to the second data selection pulse signal use the same routing and pass through the same signal transmission path, and are therefore affected by the same logic gate device, which can effectively overcome the above-mentioned effects such as clock offset caused by chip manufacturing process deviations and chip working condition deviations. In this way, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the effects of path delay, electrical characteristics, chip manufacturing process deviations and chip working conditions can be effectively overcome.

[0047] In some embodiments, calculating the first delay value further includes: subtracting a compensation value corresponding to a pre-emphasis jump signal issued by the first memory from the determined first delay value. In this way, the trained delay value is calculated, and then the corresponding compensation value can be subtracted in combination with other requirements of the first memory, such as an excess pre-emphasis (PRE) jump signal issued by a DRAM, and the actual delay value finally obtained can be used to determine the compensated position of the read logic gate enable signal. This is conducive to adapting various signal algorithms and memory designs.

[0048] In some embodiments, calculating the second delay value includes: starting from the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping half of the clock cycle associated with the first data selection pulse signal sequence as the second position of the rising edge of the read logic gate enable signal to be trained, and then, starting from the second position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal, thereby determining the second delay value. In the case where the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal performs poorly, if it is determined that the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is higher than or equal to the preset threshold, which means that the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal meets the design requirements, then the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is used as a reference, and corresponding adjustments are made to the compensation algorithm to calculate the second delay value and use the second delay value to train the read logic gate enable signal to be trained. The compensated position of the read logic gate enable signal determined in this way overcomes the adverse effects caused by the poor duty cycle performance of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal. This means that the calculation of the delay value only needs to be performed once, that is, only one gate delay signal needs to be generated, which can be achieved by any suitable gate delay circuit. Therefore, in the implementation of the algorithm and the circuit, the position of the trained read logic gate enable signal, that is, the compensated position of the read logic gate enable signal, is accurately and reliably located by only calculating the delay value once and generating the gate delay signal once. The calculation of the second delay value is based only on the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. For example, the delay of the rising edge of the read logic gate enable signal to be trained is adjusted by the compensation algorithm, so that when the rising edge of the read logic gate enable signal to be trained can be sampled to the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal, for example, when the level jump from 0 to 1 is sampled, the delay value trained at this time can be used as the edge of the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. In this way, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0049] In some embodiments, calculating the second delay value further includes: subtracting a compensation value corresponding to a pre-emphasis jump signal issued by the first memory from the determined second delay value. The calculation of the second delay value is based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained. The second delay value calculated and trained in this way can be combined with other requirements of the first memory, such as the redundant pre-emphasis (PRE) jump signal issued by the DRAM to subtract the corresponding compensation value, and the actual delay value finally obtained can be used to determine the compensated position of the read logic gate enable signal. This is conducive to adapting various signal algorithms and memory designs.

[0050] In some embodiments, when the pre-emphasis jump signal sent by the first memory is one, the compensation value corresponding to the pre-emphasis jump signal sent by the first memory is one quarter of the clock cycle. This is conducive to adapting various signal algorithms and memory designs.

[0051] In one possible implementation, calculating the third delay value includes: starting from the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping two thirds of the clock cycle associated with the first data selection pulse signal sequence as the third position of the rising edge of the read logic gate enable signal to be trained, and then, starting from the third position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal, thereby determining the third delay value. In the case where the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal are both poor, the edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal is used as a reference, and corresponding adjustments are made to the compensation algorithm, so as to calculate the third delay value and use the third delay value to train the read logic gate enable signal to be trained, thereby determining the compensated position of the read logic gate enable signal. In this way, the influence of the poor signal duty cycle is effectively overcome.

[0052] In a possible implementation, the first data selection pulse signal sequence is issued by the first memory in response to a data read command, the data read command is issued by the physical layer of the interface circuit connected to the first memory, and the training method is executed by the physical layer of the interface circuit. In this way, by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with the preset threshold, according to the comparison result, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is selected to calculate the first delay value, or the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is selected to calculate the second delay value. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0053] In a possible implementation, the first data selection pulse signal sequence is sent in a burst mode. Thus, by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, according to the comparison result, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is selected to calculate the first delay value, or the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is selected to calculate the second delay value. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0054] In a possible implementation, each of the plurality of differential signal pairs includes two paired square wave pulse signals, or two paired sine wave pulse signals. Thus, by comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, according to the comparison result, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is selected to calculate the first delay value, or the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is selected to calculate the second delay value. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0055] In a possible implementation, the preset threshold is 50%, 48%, 45% or 40%. In this way, by flexibly setting the preset threshold, flexible adaptation can be achieved in combination with the needs of the application environment. By comparing the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with the preset threshold, according to the comparison result, the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal is selected to calculate the first delay value, or the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is selected to calculate the second delay value. Through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0056] In a possible implementation, the first memory is a dynamic random access memory that complies with the fifth generation double data rate storage technology specification or the low power fifth generation double data rate storage technology specification. Thus, through the improved training method, the delay value of the read logic gate enable signal can be effectively and accurately located, and the influence of path delay and electrical characteristics can be effectively overcome.

[0057] refer to Figure 1 and Figure 2 , Figure 1 The training method for reading the logic gate enable signal shown in the figure compares the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal with a preset threshold, and according to the comparison result, selects to calculate the first delay value based on the edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, or selects to calculate the second delay value based on the edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal. Here, Figure 1 The training method for the read logic gate enable signal shown is based on the rising edge of the read logic gate enable signal to be trained as the sampling signal. To this end, during the training process, the rising edge of the read logic gate enable signal to be trained is adjusted by a compensation algorithm. When the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the corresponding data selection pulse signal (the first data selection pulse signal or the second data selection pulse signal), this is used as a basis to determine the compensated position of the read logic gate enable signal. It should be understood that Figure 1The training method for reading logic gate enable signal shown can also be understood to include the case where the falling edge of the read logic gate enable signal to be trained is used as the sampling signal, that is, in the training process, the falling edge of the read logic gate enable signal to be trained is adjusted by a compensation algorithm, and when the falling edge of the read logic gate enable signal to be trained samples the falling edge of the second phase signal of the differential signal pair corresponding to the corresponding data selection pulse signal, this is used as a basis to determine the compensated position of the read logic gate enable signal. To this end, the sampling of each differential signal pair in the plurality of differential signal pairs is based on the rising edge of the first phase signal and the falling edge of the second phase signal included in the differential signal pair. The following embodiments and implementation methods are based on the falling edge of the read logic gate enable signal to be trained as the sampling signal, and the falling edge of the read logic gate enable signal to be trained is used to sample the falling edge of the second phase signal. Therefore, it has similar technical effects to the above embodiments and implementation methods, and will not be repeated here.

[0058] In a possible implementation, a training method for a read logic gate enable signal includes: receiving a first data selection pulse signal sequence for data reading of a first memory, wherein the first data selection pulse signal sequence includes a plurality of differential signal pairs in sequence, and sampling of each differential signal pair in the plurality of differential signal pairs is based on a rising edge of a first phase signal and a falling edge of a second phase signal included in the differential signal pair; when a duty cycle of a first phase signal of a differential signal pair corresponding to a first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to a preset threshold, calculating a first delay time based on a difference between a falling edge of a second phase signal of the differential signal pair corresponding to the first data selection pulse signal and a falling edge of a read logic gate enable signal to be trained. Delay value, and then, use the first delay value to train the read logic gate enable signal to be trained; when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determine whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold, if so, calculate the second delay value based on the difference between the falling edge of the second phase signal of the differential signal pair corresponding to the second data selection pulse signal and the falling edge of the read logic gate enable signal to be trained, and then, use the second delay value to train the read logic gate enable signal to be trained.

[0059] In a possible embodiment, the training method also includes: when the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determining whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is higher than or equal to the preset threshold; if not, determining whether the duty cycle of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal in the first data selection pulse signal sequence relative to the second data selection pulse signal is higher than or equal to the preset threshold; if yes, calculating a third delay value based on the difference between the falling edge of the second phase signal of the differential signal pair corresponding to the third data selection pulse signal and the falling edge of the read logic gate enable signal to be trained; and then using the third delay value to train the read logic gate enable signal to be trained.

[0060] In one possible implementation, calculating the first delay value includes: starting from the initial position of the falling edge of the read logic gate enable signal to be trained, increasing the delay of the falling edge of the read logic gate enable signal to be trained until the falling edge of the read logic gate enable signal to be trained samples the falling edge of the second phase signal of the differential signal pair corresponding to the first data selection pulse signal, thereby determining the first delay value.

[0061] In one possible implementation, calculating the second delay value includes: starting from the falling edge of the second phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping half of the clock cycle associated with the first data selection pulse signal sequence as the second position of the falling edge of the read logic gate enable signal to be trained, and then, starting from the second position of the falling edge of the read logic gate enable signal to be trained, increasing the delay of the falling edge of the read logic gate enable signal to be trained until the falling edge of the read logic gate enable signal to be trained samples the falling edge of the second phase signal of the differential signal pair corresponding to the second data selection pulse signal, thereby determining the second delay value.

[0062] In one possible implementation, calculating the third delay value includes: starting from the falling edge of the second phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping two thirds of the clock cycle associated with the first data selection pulse signal sequence as the third position of the falling edge of the read logic gate enable signal to be trained, and then, starting from the third position of the falling edge of the read logic gate enable signal to be trained, increasing the delay of the falling edge of the read logic gate enable signal to be trained until the falling edge of the read logic gate enable signal to be trained samples the falling edge of the second phase signal of the differential signal pair corresponding to the third data selection pulse signal, thereby determining the third delay value.

[0063] It should be understood that, in a possible implementation, the sampling of each differential signal pair in the plurality of differential signal pairs is based on the rising edge of the first phase signal and the falling edge of the second phase signal included in the differential signal pair, respectively, based on the rising edge of the read logic gate enable signal to be trained as the sampling signal to adjust the rising edge of the read logic gate enable signal to be trained through the compensation algorithm, and based on the falling edge of the read logic gate enable signal to be trained as the sampling signal to adjust the falling edge of the read logic gate enable signal to be trained through the compensation algorithm, so that two compensation results can be obtained, that is, two gate delay signals can be generated. When the communication environment is relatively bad, for example, when the waveform distortion is serious, the compensation result can be obtained by combining the two compensation results, that is, the two gate delay signals, which helps to overcome the influence of routing and clock offset.

[0064] Figure 3 3 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0065] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0066] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0067] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0068] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0069] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0070] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0071] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0072] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0073] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A training method for reading a logic gate enable signal, characterized in that: The training method comprises: Receiving a first data selection pulse signal sequence for reading data from a first memory, wherein the first data selection pulse signal sequence includes a plurality of differential signal pairs in sequence, and sampling of each differential signal pair in the plurality of differential signal pairs is based on a rising edge of a first phase signal and a falling edge of a second phase signal included in the differential signal pair; When the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to a preset threshold, a first delay value is calculated based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then the first delay value is used to train the read logic gate enable signal to be trained; When the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determine whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal relative to the first data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold. If so, calculate the second delay value based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal and the rising edge of the read logic gate enable signal to be trained, and then use the second delay value to train the read logic gate enable signal to be trained.

2. The training method according to claim 1, characterized in that: The training method further comprises: When the duty cycle of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal in the first data selection pulse signal sequence is lower than the preset threshold, determine whether the duty cycle of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal is higher than or equal to the preset threshold; if not, determine whether the duty cycle of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal relative to the second data selection pulse signal in the first data selection pulse signal sequence is higher than or equal to the preset threshold; if yes, calculate the third delay value based on the difference between the rising edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal and the rising edge of the read logic gate enable signal to be trained; and then, use the third delay value to train the read logic gate enable signal to be trained.

3. The training method according to claim 1, characterized in that: The second data selection pulse signal is sent immediately after the first data selection pulse signal in the first data selection pulse signal sequence.

4. The training method according to claim 2, characterized in that: The third data selection pulse signal is sent immediately after the second data selection pulse signal in the first data selection pulse signal sequence.

5. The training method according to claim 1, characterized in that: Calculating the first delay value includes: starting from the initial position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, thereby determining the first delay value.

6. The training method according to claim 5, characterized in that: Calculating the first delay value further includes: subtracting a compensation value corresponding to the pre-emphasis jump signal sent by the first memory from the determined first delay value.

7. The training method according to claim 5, characterized in that: Calculating the second delay value includes: starting from the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping half of the clock cycle associated with the first data selection pulse signal sequence as the second position of the rising edge of the read logic gate enable signal to be trained, and then, starting from the second position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the second data selection pulse signal, thereby determining the second delay value.

8. The training method according to claim 7, characterized in that: Calculating the second delay value further includes: subtracting a compensation value corresponding to the pre-emphasis jump signal sent by the first memory from the determined second delay value.

9. The training method according to claim 8, characterized in that: When the pre-emphasis jump signal sent by the first memory is one, the compensation value corresponding to the pre-emphasis jump signal sent by the first memory is one quarter of the clock cycle.

10. The training method according to claim 2, characterized in that: Calculating the third delay value includes: starting from the rising edge of the first phase signal of the differential signal pair corresponding to the first data selection pulse signal, skipping two and three of the clock cycle associated with the first data selection pulse signal sequence as the third position of the rising edge of the read logic gate enable signal to be trained, and then, starting from the third position of the rising edge of the read logic gate enable signal to be trained, increasing the delay of the rising edge of the read logic gate enable signal to be trained until the rising edge of the read logic gate enable signal to be trained samples the rising edge of the first phase signal of the differential signal pair corresponding to the third data selection pulse signal, thereby determining the third delay value.

11. The training method according to claim 1, characterized in that: The first data selection pulse signal sequence is issued by the first memory in response to a data read command, the data read command is issued by a physical layer of an interface circuit connected to the first memory, and the training method is executed by the physical layer of the interface circuit.

12. The training method according to claim 1, characterized in that: The first data selection pulse signal sequence is sent in a burst mode.

13. The training method according to claim 1, characterized in that: Each of the plurality of differential signal pairs includes a pair of two square wave pulse signals, or a pair of two sine wave pulse signals.

14. The training method according to claim 1, characterized in that: The preset threshold is 50%, 48%, 45% or 40%.

15. The training method according to claim 1, characterized in that: The first memory is a dynamic random access memory that complies with the fifth generation double data rate storage technology specification or the low power fifth generation double data rate storage technology specification.

16. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 15.

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