Circuit and method for adjusting duty ratio of phase-locked loop clock signal, phase-locked loop and chip

Abstract

The invention belongs to the technical field of phase-locked loops, and discloses a duty ratio adjusting circuit and method for a phase-locked loop clock signal, a phase-locked loop and a chip, the duty ratio adjusting circuit is arranged between a voltage-controlled oscillator and a frequency divider, and the duty ratio adjusting circuit is used for detecting the pulse width of high and low levels in the clock signal output by the voltage-controlled oscillator; the duty ratio of the clock signal output by the voltage-controlled oscillator is adjusted through the detected pulse width of the high level and the low level, adjustment is stopped until the duty ratio of the output clock signal is 50%, and the adjusted clock signal is obtained; and finally, taking the adjusted clock signal as an output clock signal of the phase-locked loop. Therefore, an additional duty ratio adjusting circuit is introduced, and the duty ratio of the clock signal is adjusted based on the pulse widths of 0 and 1 of the high-speed clock, so that 50% of the duty ratio of the output clock can be effectively kept, and the problem that the duty ratio of the output clock deviates from 50% in the prior art is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of phase-locked loops, and in particular relates to a duty cycle adjustment circuit, method, phase-locked loop and chip for a phase-locked loop clock signal. Background Art

[0002] PFD (Phase and Frequency Detector) is a necessary module for PLL (Phase-Locked Loop). Its function is to identify the frequency and phase difference between the reference clock and feedback clock of PLL, and then transmit this difference to CP (Charge Pump). CP generates current according to this difference and outputs it to LPF (Low-Pass Filter), while LPF generates voltage to adjust the frequency of VCO (Voltage-Controlled Oscillator). Finally, divider divides the clock frequency generated by VCO to obtain feedback clock, thereby locking the output frequency.

[0003] Among them, the output clock comes from the output signal of the VCO, and the high-speed PLL will generate a high-speed output clock. Ideally, the duty cycle of the output clock is 50%, that is, the time when the signal is 1 (high level) and the time when the signal is 0 (low level) are equal. This clock is beneficial to the subsequent digital system, and can ensure that the setup time and hold time of this clock are the same, thereby leaving more margin for the system; however, in non-ideal conditions, the output clock duty cycle is not 50%, that is, the time when the output clock is 1 and the time when it is 0 are not equal, which is not good for the subsequent system, that is, the time when the clock is 1 and the time when it is 0 are not equal, which will affect the balance of the setup and hold time of the subsequent system.

[0004] In practical applications, the traditional solution is to achieve a duty cycle of 50% as much as possible through design, which can add more margin to the subsequent system; however, it has the following shortcomings: in the phase-locked loop, as long as the transistor has leakage, it is impossible to fundamentally solve the problem of the duty cycle not being 50%, and if affected by the process voltage and temperature, the deviation of the duty cycle during actual operation will be greater; therefore, the traditional technology cannot output a clock signal with a duty cycle of 50%, which will affect the balance of the establishment and hold time of the subsequent system; therefore, based on the aforementioned shortcomings, how to provide a duty cycle adjustment circuit that can adjust the duty cycle of the output clock signal to 50% has become a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the present invention is to provide a duty cycle adjustment circuit, method, phase-locked loop and chip for a phase-locked loop clock signal, so as to solve the problem that the prior art cannot adjust the duty cycle of the clock signal output by the phase-locked loop to 50%, thereby affecting the establishment of the subsequent digital system clock.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, a duty cycle adjustment circuit for a phase-locked loop clock signal is provided, wherein the duty cycle adjustment circuit is connected in series between a voltage-controlled oscillator and a frequency divider in the phase-locked loop, and the duty cycle adjustment circuit comprises: A pulse width detection unit, wherein the input end of the pulse width detection unit is electrically connected to the output end of the voltage-controlled oscillator, and is used to receive the clock signal output by the voltage-controlled oscillator at a preset time interval, and determine a first pulse width of a high-level signal and a second pulse width of a low-level signal in the received clock signal; A duty cycle adjustment unit is electrically connected to the pulse width detection unit, and is used to adjust the duty cycle of the clock signal according to the first pulse width and the second pulse width, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as an output clock signal.

[0007] Based on the above disclosed content, the present invention provides a duty cycle adjustment circuit between the voltage-controlled oscillator and the frequency divider in the phase-locked loop, wherein the circuit is used to detect the pulse widths of the high and low levels in the clock signal output by the voltage-controlled oscillator in real time, and then adjust the duty cycle of the clock signal output by the voltage-controlled oscillator according to the detected pulse widths of the high and low levels, until the duty cycle of the output clock signal is 50%, then stop adjusting to obtain the adjusted clock signal; finally, the adjusted clock signal can be used as the output clock signal of the phase-locked loop; thus, the present invention introduces an additional duty cycle adjustment circuit, and adjusts the duty cycle of the clock signal based on the pulse widths of 0 and 1 of the high-speed clock, so that the output clock can be effectively kept at a duty cycle of 50%, thereby solving the problem of the duty cycle of the output clock deviating from 50% in the traditional technology, thereby bringing better margin to the subsequent digital system; based on this, the present invention is very suitable for large-scale application and promotion.

[0008] In one possible design, the pulse width detection unit includes: a first time-to-digital converter and a second time-to-digital converter; a first time-to-digital converter, electrically connected to the output end of the voltage-controlled oscillator, for receiving a clock signal output by the voltage-controlled oscillator at a preset time interval, and detecting a first pulse width of a high-level signal in the received clock signal; a second time-to-digital converter, electrically connected to the output end of the voltage-controlled oscillator, for receiving a clock signal output by the voltage-controlled oscillator at a preset time interval, and detecting a second pulse width of a low-level signal in the received clock signal; The first time data converter and the second time digital converter are both electrically connected to the duty cycle adjustment unit, and are used to send the detected first pulse width and second pulse width to the duty cycle adjustment unit.

[0009] In one possible design, the duty cycle adjustment unit includes: a comparator and a duty cycle adjuster; a comparator, electrically connected to the pulse width detection unit, configured to compare the first pulse width and the second pulse width output by the pulse width detection unit, obtain a comparison result, and generate a duty cycle adjustment signal according to the comparison result; A duty cycle regulator, wherein the duty cycle regulator is electrically connected to the comparator, and is used to adjust the duty cycle of the clock signal according to the duty cycle adjustment signal, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as the output clock signal.

[0010] In one possible design, the duty cycle regulator includes: a buffer; Among them, the buffer is electrically connected to the comparator, and is used to adjust its own charging current and discharging current according to the duty cycle adjustment signal, so as to adjust the duty cycle of the clock signal by adjusting the charging current and the discharging current, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal.

[0011] In one possible design, the duty cycle adjustment signal includes a first adjustment signal or a second adjustment signal; Wherein, the comparator is used to generate a first adjustment signal when the first pulse width is smaller than the second pulse width, or to generate a second adjustment signal when the first pulse width is larger than the second pulse width; a buffer, configured to maintain the magnitude of the charging current and reduce the discharging current after receiving the first adjustment signal, so as to adjust the duty cycle of the clock signal to 50% by reducing the discharging current, thereby obtaining an adjusted clock signal; The buffer is also used to maintain the size of the discharge current and reduce the charging current after receiving the second adjustment signal, so as to adjust the duty cycle of the clock signal to 50% by reducing the charging current to obtain an adjusted clock signal.

[0012] In a possible design, the duty cycle adjustment unit is further used to use the clock signal received by the pulse width detection unit as the output clock signal when the first pulse width is equal to the second pulse width.

[0013] In a second aspect, a method for adjusting the duty cycle of a phase-locked loop clock signal is provided, the method being implemented based on the first aspect or the duty cycle adjustment circuit of the phase-locked loop clock signal of any possible design in the first aspect, wherein the method comprises: receiving a clock signal output by a voltage-controlled oscillator at a preset time interval; Determine a first pulse width of a high level signal and a second pulse width of a low level signal in the received clock signal; According to the first pulse width and the second pulse width, the duty cycle of the clock signal is adjusted until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as an output clock signal.

[0014] In one possible design, the duty cycle adjustment circuit includes a buffer; According to the first pulse width and the second pulse width, the duty cycle of the clock signal is adjusted until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, including: comparing the first pulse width and the second pulse width to obtain a comparison result; generating a duty cycle adjustment signal according to the comparison result; Based on the duty cycle adjustment signal, the charging current and the discharging current of the buffer are adjusted to adjust the duty cycle of the clock signal by adjusting the charging current and the discharging current, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining the adjusted clock signal.

[0015] In a third aspect, a phase-locked loop is provided, comprising a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider, and a duty cycle adjustment circuit of the phase-locked loop clock signal of the first aspect or any possible design of the first aspect.

[0016] In a fourth aspect, a chip is provided, wherein the chip includes the phase-locked loop described in the third aspect.

[0017] Beneficial effects: (1) The present invention introduces an additional duty cycle adjustment circuit and adjusts the duty cycle of the clock signal based on the pulse widths of the high-speed clock of 0 and 1. In this way, the duty cycle of the output clock can be effectively maintained at 50%, thereby solving the problem of the duty cycle of the output clock deviating from 50% in the traditional technology. As a result, better margin can be brought to the subsequent digital system. Based on this, the present invention is very suitable for large-scale application and promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of a duty cycle adjustment circuit for a phase-locked loop clock signal provided by an embodiment of the present invention; Figure 2 A schematic diagram of adjusting the duty cycle when the duty cycle of the clock signal output by the voltage-controlled oscillator is 50% provided in an embodiment of the present invention; Figure 3A schematic diagram of adjusting the duty cycle when the duty cycle of the clock signal output by the voltage-controlled oscillator is less than 50% provided in an embodiment of the present invention; Figure 4 A schematic flow chart of the steps of a method for adjusting the duty cycle of a clock signal of a phase-locked loop provided in an embodiment of the present invention; Figure 5 A circuit structure diagram of a phase-locked loop provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0020] It should be understood that although the terms first, second, etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another unit. For example, a first unit can be referred to as a second unit, and similarly, a second unit can be referred to as a first unit without departing from the scope of the exemplary embodiments of the present invention.

[0021] It should be understood that the term "and / or" that may appear in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" that may appear in this article describes another type of association object relationship, indicating that two relationships may exist. For example, A / and B can represent two situations: A exists alone, and A and B exist alone. In addition, the character " / " that may appear in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0022] Example: See also Figure 1As shown, the duty cycle adjustment circuit of the phase-locked loop clock signal provided in this embodiment is connected in series between the voltage-controlled oscillator and the frequency divider in the phase-locked loop. It detects the pulse widths of the signals of 0 and 1 in the high-speed clock output by the voltage-controlled oscillator, and on this basis, adjusts the duty cycle of the clock signal based on the size of the pulse widths of the two. In this way, the circuit can effectively maintain the duty cycle of the phase-locked loop output clock at 50%, thereby solving the problem of the duty cycle of the output clock deviating from 50% in the traditional technology, thereby bringing better margin for the subsequent digital system. Among them, the following discloses one specific circuit structure of the aforementioned duty cycle adjustment circuit.

[0023] In a specific application, the duty cycle adjustment circuit of the phase-locked loop clock signal may include, but is not limited to: a pulse width detection unit and a duty cycle adjustment unit; wherein the input end of the pulse width detection unit is electrically connected to the output end of the voltage-controlled oscillator, and is used to receive the clock signal output by the voltage-controlled oscillator at a preset time interval (i.e. Figure 1 ), and determines the first pulse width of the high level signal and the second pulse width of the low level signal in the received clock signal; in this way, the pulse width detection unit detects the duration of the high level and the low level in the clock signal output by the voltage-controlled oscillator in real time (i.e. the aforementioned first pulse width and the second pulse width), and then sends the duration of the two to the duty cycle adjustment unit, and the duty cycle adjustment unit adjusts the duty cycle of the aforementioned clock signal based on this; of course, the aforementioned preset time interval can be specifically set according to actual use, and is not limited to the aforementioned example.

[0024] Specifically, the duty cycle adjustment unit is electrically connected to the pulse width detection unit, and is used to adjust the duty cycle of the clock signal according to the first pulse width and the second pulse width, until the duty cycle of the clock signal is adjusted to 50%, an adjusted clock signal is obtained, and the adjusted clock signal is used as the output clock signal; in this embodiment, the duty cycle adjustment principle is: by comparing the time periods of the high and low levels in the clock signal output by the voltage-controlled oscillator, the duty cycle of the original clock signal is adjusted, that is, if the time period of the low level is longer than the time period of the high level, the time period of the high level is increased, conversely, if the time period of the low level is shorter than the time period of the high level, then the time period of the low level is increased until the time periods of the two are the same, and then the adjustment can be stopped; at this time, the duty cycle of the adjusted clock signal is 50%; in this way, the adjusted clock signal can be used as the output clock signal of the phase-locked loop.

[0025] Based on the foregoing description, this embodiment adjusts the duty cycle of the clock signal by detecting the pulse width of the high and low levels of the original clock signal. In this way, the duty cycle of the phase-locked loop output clock can be effectively maintained at 50%, thereby solving the problem of the duty cycle of the output clock deviating from 50% in traditional technologies. As a result, better margin can be brought to subsequent digital systems.

[0026] After completing the overall overview of the aforementioned duty cycle adjustment circuit, this embodiment provides a specific structure of the aforementioned circuit.

[0027] Among them, a circuit structure of a pulse width detection unit is provided: In this embodiment, the pulse width detection unit may include, but is not limited to: a first time-to-digital converter and a second time-to-digital converter; wherein the first time-to-digital converter and the second time-to-digital converter are both electrically connected to the duty cycle adjustment unit for realizing data transmission with the duty cycle adjustment unit.

[0028] For specific applications, see Figure 1 As shown, the first time-to-digital converter is electrically connected to the output end of the voltage-controlled oscillator, and is used to receive the clock signal output by the voltage-controlled oscillator at a preset time interval, and detect the first pulse width of the high-level signal in the received clock signal (i.e., the time period for detecting the high-level signal, that is, the duration); similarly, the second time-to-digital converter is also electrically connected to the output end of the voltage-controlled oscillator, and is used to receive the clock signal output by the voltage-controlled oscillator at a preset time interval, and detect the second pulse width of the low-level signal in the received clock signal (i.e., the time period for detecting the low-level signal); then, the first time-to-digital converter and the second time-to-digital converter are used to send the detected first pulse width and second pulse width to the duty cycle adjustment unit, so that the duty cycle adjustment unit adjusts the duty cycle of the original clock signal according to the high and low level pulse widths in the original clock signal.

[0029] Thus, based on the aforementioned two time-to-digital converters, pulse width detection of high and low levels in the clock signal output by the voltage-controlled oscillator can be realized; and then, combined with the duty cycle adjustment unit, duty cycle adjustment of the original clock signal can be realized.

[0030] Similarly, the following provides one specific structure of the duty cycle adjustment unit.

[0031] In this embodiment, the duty cycle adjustment unit may include, but is not limited to: a comparator and a duty cycle adjuster; wherein the comparator is electrically connected to the pulse width detection unit, and is used to compare the first pulse width and the second pulse width output by the pulse width detection unit to obtain a comparison result, and generate a duty cycle adjustment signal according to the comparison result; optionally, the duty cycle adjustment signal includes a first adjustment signal or a second adjustment signal, that is, the comparator generates a first adjustment signal when the first pulse width is less than the second pulse width (the duty cycle is used to characterize the proportion of the time period of the high level in the clock signal to the time period of the entire clock signal, therefore, the first pulse width is less than the second pulse width, indicating that the duty cycle of the original clock signal is less than 50%), or is used to generate a second adjustment signal when the first pulse width is greater than the second pulse width (that is, when the duty cycle of the original clock signal is greater than 50%, a second adjustment signal is generated).

[0032] In this way, the comparator can generate different adjustment signals by comparing the pulse widths of the high and low levels in the original clock signal. Then, the duty cycle regulator can adjust the duty cycle of the original clock signal based on this. The adjustment process is as follows: In this embodiment, the duty cycle regulator is electrically connected to the comparator, and is used to adjust the duty cycle of the clock signal according to the duty cycle adjustment signal until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as the output clock signal.

[0033] Specifically, the duty cycle regulator includes a buffer, so it is equivalent to adjusting its own charging current and discharging current according to the duty cycle adjustment signal, so as to adjust the duty cycle of the clock signal by adjusting the charging current and the discharging current; wherein, see Figure 3 As shown, when the first pulse width is smaller than the second pulse width (i.e., the duty cycle of the original clock signal is smaller than 50%), the buffer is used to receive the first adjustment signal, and after receiving the first adjustment signal, based on the signal, maintains the size of the charging current, and simultaneously reduces the discharging current, so as to adjust the duty cycle of the clock signal to 50% by reducing the discharging current, thereby obtaining an adjusted clock signal; in this way, when the duty cycle of the original clock signal is smaller than 50%, at this time, it is necessary to set the charging current to be larger than the discharging current, and therefore, it is necessary to continuously reduce the discharging current until the time periods of the high and low levels in the original clock signal are the same, and then the duty cycle of the original clock signal can be adjusted to 50%.

[0034] Similarly, when the first pulse width is greater than the second pulse width, that is, the duty cycle of the original clock signal is greater than 50%, the buffer is used to receive the second adjustment signal, and after receiving it, based on the signal, to maintain the size of the discharge current and simultaneously reduce the charging current, so as to adjust the duty cycle of the clock signal to 50% by reducing the charging current, thereby obtaining an adjusted clock signal.

[0035] Also, see Figure 2 As shown, when the first pulse width is equal to the second pulse width, that is, when the duty cycle of the original clock signal (i.e., the clock signal output by the voltage-controlled oscillator) is 50%, at this time, there is no need to adjust the size of the charging current (iup) and the discharging current (idn), therefore, the duty adjustment unit can directly use the clock signal received by the pulse width detection unit as the output clock signal.

[0036] According to the above description, this embodiment detects the pulse width of the high level and the low level in the original clock signal through two time data converters, and then adjusts the charging current and the discharging current of the buffer through the comparison results of the pulse widths of the two, so as to gradually change the duty cycle of the original clock signal based on this; in this way, through the above continuous adjustment, when the time periods of the high level and the low level signals in the original clock signal are the same, the duty cycle adjustment process can be ended.

[0037] Therefore, this embodiment adjusts the duty cycle by detecting the pulse width of the high and low levels in the clock signal output by the voltage-controlled oscillator, which can effectively avoid the adverse effects introduced by the duty cycle not being 50%, thereby maintaining a relatively ideal clock output by the VCO, and further providing more margin for subsequent digital systems.

[0038] See also Figure 4 As shown, in a possible design, the second aspect of this embodiment provides a method for adjusting the duty cycle of a phase-locked loop clock signal, wherein the method is implemented based on the duty cycle adjustment circuit of the phase-locked loop clock signal described in the first aspect of the embodiment, and the operating steps of the method can be but are not limited to the following steps S1 to S3.

[0039] S1. Receive the clock signal output by the voltage-controlled oscillator according to the preset time interval.

[0040] S2. Determine a first pulse width of a high-level signal and a second pulse width of a low-level signal in the received clock signal.

[0041] S3. According to the first pulse width and the second pulse width, the duty cycle of the clock signal is adjusted until the duty cycle of the clock signal is adjusted to 50%, and an adjusted clock signal is obtained, and the adjusted clock signal is used as the output clock signal; in this embodiment, the first pulse width and the second pulse width are first compared to obtain a comparison result; then, a duty cycle adjustment signal is generated according to the comparison result; finally, based on the duty cycle adjustment signal, the charging current and the discharging current of the buffer are adjusted to adjust the duty cycle of the clock signal by adjusting the charging current and the discharging current, until the duty cycle of the clock signal is adjusted to 50%, and the adjusted clock signal is obtained.

[0042] Of course, the working process, working details and technical effects of the method provided in this embodiment can be found in the first aspect of the embodiment and will not be repeated here.

[0043] The third aspect of the present embodiment provides a phase-locked loop, wherein the phase-locked loop includes a frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider, and a duty cycle adjustment circuit of the phase-locked loop clock signal described in the first aspect of the embodiment; wherein the specific structure diagram of the phase-locked loop can be found in Figure 5 As shown; thus, introducing the duty cycle adjustment circuit in the phase-locked loop can effectively maintain the duty cycle of the phase-locked loop output clock at 50%, thereby solving the problem of the duty cycle of the output clock deviating from 50% in the traditional technology, thereby bringing better margin for the subsequent digital system.

[0044] A fourth aspect of the present embodiment provides a chip, wherein the chip includes the phase-locked loop described in the third aspect of the embodiment.

[0045] The working process, working details and technical effects of the chip provided in this embodiment can be found in the first aspect of the embodiment and will not be described in detail here.

[0046] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A duty cycle adjustment circuit for a phase-locked loop clock signal, characterized in that: The duty cycle adjustment circuit is connected in series between the voltage controlled oscillator and the frequency divider in the phase-locked loop, and the duty cycle adjustment circuit includes: A pulse width detection unit, wherein the input end of the pulse width detection unit is electrically connected to the output end of the voltage-controlled oscillator, and is used to receive the clock signal output by the voltage-controlled oscillator at a preset time interval, and determine a first pulse width of a high-level signal and a second pulse width of a low-level signal in the received clock signal; A duty cycle adjustment unit is electrically connected to the pulse width detection unit, and is used to adjust the duty cycle of the clock signal according to the first pulse width and the second pulse width, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as an output clock signal.

2. The duty cycle adjustment circuit of a phase-locked loop clock signal according to claim 1, characterized in that: The pulse width detection unit comprises: a first time-to-digital converter and a second time-to-digital converter; a first time-to-digital converter, electrically connected to the output end of the voltage-controlled oscillator, for receiving a clock signal output by the voltage-controlled oscillator at a preset time interval, and detecting a first pulse width of a high-level signal in the received clock signal; a second time-to-digital converter, electrically connected to the output end of the voltage-controlled oscillator, for receiving a clock signal output by the voltage-controlled oscillator at a preset time interval, and detecting a second pulse width of a low-level signal in the received clock signal; The first time data converter and the second time digital converter are both electrically connected to the duty cycle adjustment unit, and are used to send the detected first pulse width and second pulse width to the duty cycle adjustment unit.

3. The duty cycle adjustment circuit of a phase-locked loop clock signal according to claim 1, characterized in that: The duty cycle adjustment unit includes: a comparator and a duty cycle adjuster; a comparator, electrically connected to the pulse width detection unit, configured to compare the first pulse width and the second pulse width output by the pulse width detection unit, obtain a comparison result, and generate a duty cycle adjustment signal according to the comparison result; A duty cycle regulator, wherein the duty cycle regulator is electrically connected to the comparator, and is used to adjust the duty cycle of the clock signal according to the duty cycle adjustment signal, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as the output clock signal.

4. The duty cycle adjustment circuit of a phase-locked loop clock signal according to claim 3, characterized in that: The duty cycle regulator includes: a buffer; Among them, the buffer is electrically connected to the comparator, and is used to adjust its own charging current and discharging current according to the duty cycle adjustment signal, so as to adjust the duty cycle of the clock signal by adjusting the charging current and the discharging current, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal.

5. The duty cycle adjustment circuit of a phase-locked loop clock signal according to claim 4, characterized in that: The duty cycle adjustment signal includes a first adjustment signal or a second adjustment signal; Wherein, the comparator is used to generate a first adjustment signal when the first pulse width is smaller than the second pulse width, or to generate a second adjustment signal when the first pulse width is larger than the second pulse width; a buffer, configured to maintain the magnitude of the charging current and reduce the discharging current after receiving the first adjustment signal, so as to adjust the duty cycle of the clock signal to 50% by reducing the discharging current, thereby obtaining an adjusted clock signal; The buffer is also used to maintain the size of the discharge current and reduce the charging current after receiving the second adjustment signal, so as to adjust the duty cycle of the clock signal to 50% by reducing the charging current to obtain an adjusted clock signal.

6. The duty cycle adjustment circuit of a phase-locked loop clock signal according to claim 1, characterized in that: The duty cycle adjustment unit is further configured to use the clock signal received by the pulse width detection unit as the output clock signal when the first pulse width is equal to the second pulse width.

7. A method for adjusting the duty cycle of a phase-locked loop clock signal, characterized in that: The duty cycle adjustment circuit of the phase-locked loop clock signal according to any one of claims 1 to 6 is implemented, wherein the method comprises: receiving a clock signal output by a voltage-controlled oscillator at a preset time interval; Determine a first pulse width of a high level signal and a second pulse width of a low level signal in the received clock signal; According to the first pulse width and the second pulse width, the duty cycle of the clock signal is adjusted until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, and using the adjusted clock signal as an output clock signal.

8. The method according to claim 7, characterized in that The duty cycle adjustment circuit includes a buffer; According to the first pulse width and the second pulse width, the duty cycle of the clock signal is adjusted until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining an adjusted clock signal, including: comparing the first pulse width and the second pulse width to obtain a comparison result; generating a duty cycle adjustment signal according to the comparison result; Based on the duty cycle adjustment signal, the charging current and the discharging current of the buffer are adjusted to adjust the duty cycle of the clock signal by adjusting the charging current and the discharging current, until the duty cycle of the clock signal is adjusted to 50%, thereby obtaining the adjusted clock signal.

9. A phase-locked loop, characterized in that: The invention comprises a frequency detector, a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider and a duty cycle adjustment circuit of a phase-locked loop clock signal as claimed in any one of claims 1 to 6.

10. A chip, characterized in that: include: The phase locked loop as claimed in claim 9.

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