Electronic device and method for error recovery

Abstract

An electronic device and a method for error recovery are disclosed. The electronic apparatus includes: a port connected to a link including a plurality of channels to support communication between the electronic apparatus and another apparatus, and transmitting a flit in a flit mode; and a processor to control the link based on the link training and a status state machine (LTSSM). The processor transitions from an L0 state included in the LTSSM to an L0p state for a partial channel of the plurality of channels based on occurrence of a receiver error in the partial channel of the plurality of channels and reaching a specific data rate using an equalization bypass based on a link, and after transitioning to the L0p state, transitions from the L0 state included in the LTSSM to the L0p state. A port transmits an ordered set (OS) through the portion of the plurality of channels and microchips through the remaining channels of the plurality of channels.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0099942 filed on July 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to electronic devices and methods for error recovery. Background Art

[0003] The Peripheral Component Interconnect Express (PCIe) interface protocol has been used in the computing industry for high-speed data transmission. The PCIe interface protocol provides a bidirectional connection for simultaneously sending and receiving data. Up to and including PCIe gen 5.0, a sync header has been used to synchronize the timing of blocks, i.e., synchronize data units transmitted between channels. By synchronizing the timing between channels via the sync header, a receiving end receiving serialized data can perform de-serialization without data distortion.

[0004] Therefore, in the prior art standard, in order to distinguish the boundary between blocks transmitted and received in PCIe, a synchronization header must be transmitted for each block, resulting in performance degradation. In addition, there is a limitation that different packets cannot be transmitted between channels.

[0005] When the value of the sync header fails to match all lanes, the receiver identifies the mismatch as an error and transitions to the recovery state. However, even if only a single sync header does not match, all lanes transition to the recovery state, resulting in a period of significantly degraded performance. Summary of the invention

[0006] One aspect is to provide an apparatus for error recovery and an operating method thereof.

[0007] According to one aspect of one or more example embodiments, there is provided a device, the device comprising: a port connected to a link including a plurality of lanes to support communication between the device and another apparatus, and configured to transmit a flits in a flits mode; and a processor configured to control the link based on a link training and status state machine (LTSSM). The processor is configured to: based on a receiver error occurring in a portion of the plurality of lanes and based on the link using equalization bypass to reach a specific data rate, for the portion of the plurality of lanes, transition from an L0 state included in the LTSSM to an L0p state, and the port is configured to: after transitioning to the L0p state, transmit an ordered set (OS) through the portion of the plurality of lanes, and transmit a flits through the remaining lanes of the plurality of lanes.

[0008] According to another aspect of one or more example embodiments, a method is provided, the method comprising: based on a receiver error occurring in a portion of channels among a plurality of channels included in a link and based on the link using equalization bypass to reach a specific data rate, transitioning from an L0 state included in a link training and status state machine (LTSSM) to an L0p state for the portion of channels among the plurality of channels; and transmitting an ordered set (OS) through the portion of channels among the plurality of channels, and transmitting micro slices through the remaining channels among the plurality of channels.

[0009] According to another aspect of one or more example embodiments, there is provided a storage device, the storage device comprising: a nonvolatile memory; a port connected to a link including a plurality of channels to support communication between the storage device and another device, and configured to transmit a microchip in a microchip mode; and a controller configured to control the link based on a link training and status state machine (LTSSM). The controller is configured to: based on a receiver error occurring in the plurality of channels and based on the link using equalization bypass to reach a specific data rate, for a portion of the plurality of channels, transition the storage device from an L0 state included in the LTSSM to an L0p state, and the port is configured to: after transitioning to the L0p state, transmit an ordered set (OS) through the portion of the plurality of channels, and transmit a microchip through the remaining channels of the plurality of channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a diagram illustrating a Peripheral Component Interconnect Express (PCIe) link according to some example embodiments; Figure 2 is a diagram illustrating an example of a layer model according to some example embodiments; Figure 3 is a diagram showing a method according to some example embodiments Figure 2 A diagram of a flow control unit (flick) mode supported by logical sub-blocks of a layer model of and flits transmitting and receiving in the flitch mode; Figure 4 is a diagram illustrating an electronic system according to an example embodiment; Figure 5 is a diagram illustrating an example of a state machine according to an example embodiment; Figure 6 is a diagram showing a method according to an example embodiment Figure 5 A diagram of the sub-states of the L0 state and the L0p state of the state machine shown in; Figure 7 is a diagram showing a method according to an example embodiment Figure 6 A diagram showing the relationship between sub-states of the L0p state; Figure 8 is a diagram illustrating an operation of a second L0p sub-state according to an example embodiment; Fig. 9 is a diagram illustrating an operation of a third L0p sub-state according to an example embodiment; Fig.10 is a diagram illustrating operations of a fourth L0p sub-state and a fifth L0p sub-state according to an example embodiment; Fig.11 is a diagram illustrating a data flow for each channel transmission according to an example embodiment; Fig.12 is a diagram illustrating data flow for each lane transmission and a link training and status state machine (LTSSM) according to an example embodiment; Fig.13 is a diagram illustrating a data flow and LTSSM for each channel transmission according to an example embodiment; Fig.14 is a flow chart illustrating a method of operating a device according to an example embodiment; Fig.15 is a flow chart illustrating a method of equalization bypass operation of a device according to an example embodiment; Fig.16 is a diagram illustrating a method of transmitting packets between ports according to an example embodiment; Fig.17 is a diagram illustrating a device according to an example embodiment; and Fig.18 is a diagram illustrating a storage device according to example embodiments. DETAILED DESCRIPTION

[0011] Hereinafter, example embodiments will be described with reference to the accompanying drawings. As used in this specification, the phrase "at least one of A, B, and C" includes within its scope "only A", "only B", "only C", "both A and B", "both B and C", "both A and C", and "all of A, B, and C".

[0012] Figure 1 is a diagram illustrating a Peripheral Component Interconnect Express (PCIe) link according to some example embodiments.

[0013] Reference Figure 1, PCIe can support operations between two components. The components can send packets to each other and receive packets from each other through the link 103. The components can correspond to physical devices that send packets and receive packets through the link 103. For ease of description, the two components connected by the link 103 can be referred to as the first device 101 and the second device 102, and for convenience, the phrase "the first device 101 and the second device 102" is used to describe operations and state transitions that can be performed by each of the first device 101 and the second device 102 separately.

[0014] Link 103 may correspond to a duplex communication channel of a port connecting two components. From a logical perspective, a port may be defined as an interface between two components and link 103. For example, a first port may be defined between a first device 101 and link 103, and a second port may be defined between a second device 102 and the link. From a physical perspective, a port may be defined as a group of transceivers defining link 103. Therefore, objects located at opposite ends of link 103 may be described as ports, and objects located at opposite ends of a link may also be described as components including transceivers.

[0015] The link 103 may include one or more channels La0, La1, La2, and La3 between two ports. For example, the link 103 may include one or more channels La0, La1, La2, and La3 between a first port of the first device 101 and a second port of the second device 102. Each of the channels La0, La1, La2, and La3 may include two differentially driven signal pairs: a transmit pair and a receive pair. The data clock used in the link 103 may be embedded using an encoding scheme to achieve very high data rates. The link 103 may aggregate multiple channels La0, La1, La2, and La3 to increase bandwidth. The channels La0, La1, La2, and La3 included in the link 103 may be represented as xN (where N is the width of the channel). For example, the channels supported by PCIe may be x1, x2, x4, x8, and x16. Figure 1 It is shown based on x4 channels, but example embodiments are not limited thereto. During hardware initialization, the link 103 can be established after the two components (i.e., the first device 101 and the second device 102) on opposite ends of the link 103 negotiate the channel width and operating frequency. Each link 103 can support a symmetrical number of channels in each direction. For example, a x16 link can have 16 differential signal pairs in each direction.

[0016] Figure 2 is a diagram illustrating an example of a layer model according to some example embodiments.

[0017] Reference Figure 2, the layer model 200 may be referred to as a protocol stack. Each of the first device 101 and the second device 102 may have the layer model 200 .

[0018] The layer model 200 may include a transaction layer 205, a data link layer 210, and a physical layer 215. Each layer includes a first portion that handles outbound information for transmission (Tx) and a second portion that handles inbound information for reception (Rx).

[0019] Information is transmitted between two components (i.e., the first device 101 and the second device 102) through packets. Packets can be formed in the transaction layer 205 and the data link layer 210 to transmit information from the transmitting component to the receiving component. When the transmission packet passes through another layer, the additional information required by the layer to process the packet can be extended. The reverse process can be performed on the receiving side, and the packet can be transmitted to the transaction layer 205 through the physical layer 215 and the data link layer 210.

[0020] Transaction Layer 205 The transaction layer 205 is the top layer and is responsible for assembling and disassembling transaction layer packets (TLPs). TLPs can be used for communication transactions (such as read operations and write operations, as well as events of certain types). The transaction layer 205 can manage credit-based flow control of TLPs. All request packets that require response packets can be implemented as split transactions. Each packet can have a unique identifier that allows the response packet to be transmitted to the correct component. Depending on the transaction type (memory, I / O, configuration, and message), the packet format supports different forms of addressing. The transaction layer 205 can support four address spaces. For example, the four address spaces can include 3 PCI address spaces (memory, I / O, and configuration), and a message space can be added.

[0021] Data Link Layer 210 The data link layer 210 is an intermediate layer and serves as an intermediate layer between the transaction layer 205 and the physical layer 215. The data link layer 210 is responsible for link management and data integrity, including error detection and error correction. The transmitting side of the data link layer 210 may receive the TLP assembled by the transaction layer 205, calculate and apply the data protection code and the TLP sequence number, and transmit the data protection code and the TLP sequence number to the physical layer 215 for transmission on the link 103. The receiving side of the data link layer 210 may verify the integrity of the received TLP and transmit the integrity of the TLP to the transaction layer 205 for additional processing. When an error is detected in the TLP, the data link layer 210 may request retransmission of the TLP until it is determined that the information has been correctly received or the link 103 fails. The data link layer 210 may also generate and consume packets for managing the link 103. In order to distinguish from the packets used in the transaction layer 205, the packets of the data link layer 210 may be referred to as data link layer packets (DLP) or data link layer packets (DLLP).

[0022] Physical Layer 215 The physical layer 215 is the lowest layer and may include all circuits for interface operation (such as drivers, input buffers, parallel to serial (PS) and serial to parallel (SP) conversion, phase-locked loop (PLL), impedance matching circuits). The physical layer 215 may have logic functions related to interface initialization and maintenance. The physical layer 215 may exchange information with the data link layer 210 in an appropriate format. The physical layer 215 may convert information received from the data link layer 210 into a serial format and transmit the converted information on the link 103 at a frequency and width compatible with other components.

[0023] The physical layer 215 may include a logical sub-block 216 and an electrical sub-block 218 to physically transmit packets to other devices. The logical sub-block 216 may be responsible for the digital functions of the physical layer 215. For example, the logical sub-block 216 may include a transmit unit and a receive unit, the transmit unit prepares outbound information sent by the electrical sub-block 218, and the receive unit recognizes and prepares the received information before sending the outbound information to the data link layer 210.

[0024] The electrical sub-block 218 may include a transmitter and a receiver. A symbol may be provided to the transmitter through the logic sub-block 216, and the transmitter may serialize the provided symbol and transmit it to another device. The serialized symbol may be provided to the receiver from another device, and the receiver may convert the received signal into a bit stream. The bit stream may be deserialized and provided to the logic sub-block 216.

[0025] Each physical layer 215 may include a state machine (SM) 220 for link training. The state machine 220 may be defined as a set of states for exchanging and controlling state information of the PCIe link 103. The state machine 220 starts packet transmission by configuring and initializing the link 103 and the ports of the components (e.g., the first device 101 and the second device 102) connected by PCIe. The state machine 220 may have a plurality of states responsible for various link operations, and each of the plurality of states may have sub-states. For example, the state machine 220 may include a link training and status state machine (LTSSM).

[0026] Figure 2 An example of a PCIe stack is shown. However, example embodiments are not limited thereto. In some example embodiments, the layer model 200 may include, for example, a Quick Path Interconnect (QPI) stack, a next generation high performance computing interconnect stack, or various other types of layered protocol stacks. For example, the layer model 200 may include a first layer for assembling or decomposing packets, a second layer for stably transmitting packets between the first layer and the third layer, and a third layer for sending and receiving packets. The third layer may include a state machine 220.

[0027] Figure 3 is a diagram showing a method according to some example embodiments Figure 2 A diagram of the flow control unit (flit) mode supported by the logical sub-blocks of the layer model and the flits that send and receive in flits mode.

[0028] Reference Figure 3 , when link 103 operates at a data rate of 64.0GT / s or higher supported in PCIe 6.0 generation, micro-chip mode can be supported.

[0029] A microchip is a data unit supported in microchip mode and can be operated based on 1b / 1b encoding. A microchip may include a TLP, a DLP, a cyclic redundancy check (CRC), and an error correction code (ECC). For example, a microchip may have a size of 256 bytes (256B) (i.e., 2048 bits). In this case, a microchip may include a TLP of 236B, a DLP of 6B, a CRC of 8B, and an ECC of 6B. Microchips may be interleaved for multiple channels through a byte alignment scheme. For example, microchips may be interleaved in a 3-way manner. Interleaved microchips may include multiple ECC symbols (or ECC codewords). Multiple ECC symbols may belong to a single ECC group among multiple ECC groups. For example, among multiple ECC groups, three ECC groups may be interleaved in a 3-way manner. Each of the multiple ECC symbols may have a size of 8 bits. The ECC code belonging to each ECC group may correct errors occurring in each ECC group. When a microtile has a size of 256B and is interleaved in a 3-way manner, one ECC group among a plurality of ECC groups may include an ECC symbol of 86B, and the remaining ECC groups may each include an ECC symbol of 85B.

[0030] like Figure 3 As shown in , ECC symbols can be classified into symbols corresponding to TLP, symbols corresponding to DLP, symbols corresponding to CRC, and symbols corresponding to ECC. Symbols corresponding to ECC are symbols including RS code information in ECC symbols generated as a result of ECC encoding. In the case where symbols correspond to CRC, one ECC group may include three symbols, and the remaining ECC groups may include two symbols.

[0031] As described above, until the 5.0 generation, in the absence of a synchronization header (i.e., in the absence of a standard for synchronization timing), the microchip can determine the consistency of data by using CRC and forward error correction (FEC) of ECC within a fixed size of 256B. For example, in the microchip mode, there is no need to additionally send a synchronization header for each block or compare the value of the synchronization header for each channel.

[0032] Figure 4 is a diagram illustrating an electronic system according to example embodiments.

[0033] Reference Figure 4 , the electronic system 300 according to the example embodiment may include a processor 305, a memory 310, a root complex 315, a switch 320, and a plurality of endpoints. For example, in some example embodiments, the plurality of endpoints may include a first endpoint 325a, a second endpoint 325b, and a third endpoint 325c. For example, the processor 305, the root complex 315, the switch 320, and the first endpoints 325a to 325c may correspond to the above-mentioned components, respectively. For example, each of the processor 305, the root complex 315, the switch 320, and the first endpoints 325a to 325c may correspond to one of the above-mentioned first device 101 and the second device 102. Although Figure 4 Three endpoints are shown, but example embodiments are not limited thereto, and in some example embodiments, the number of endpoints may be less than or greater than three.

[0034] The processor 305 may control the overall operation of the electronic system 300. For example, the processor 305 may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), and a communication processor (CP). The processor 305 may transmit packets to the first to third endpoints 325a to 325c and receive packets from the first to third endpoints 325a to 325c through the root complex 315 and the switch 320.

[0035] For example, the processor 305 may correspond to or be included in a host.

[0036] Memory 310 may include any memory device, such as random access memory (RAM), non-volatile memory, or other memory device accessible by devices within electronic system 300 . Memory 310 may be connected to root complex 315 .

[0037] The root complex 315 may manage data flows of components included in the electronic system 300. For example, the root complex 315 may control data paths, schedule data transfers, or resolve communication conflicts. For example, the root complex 315 may support the creation of configuration requests as a requester.

[0038] In some example embodiments, the switch 320 may be connected to the root complex 315. In some example embodiments, the second endpoint 325b and the third endpoint 325c may be connected to the root complex 315 through the switch 320. The switch 320 may control a data path between the root complex 315 and the second endpoint 325b and the third endpoint 325c. In some example embodiments, the first endpoint 325a may be directly connected to the root complex 315.

[0039] The root complex 315 and the switch 320 may be implemented as various hardware circuits for data control and data transmission.

[0040] The first endpoint 325a to the third endpoint 325c may represent a function type, where the function type may be a requester or a completer of a PCIe transaction. For example, as described above, in some example embodiments, the first endpoint 325a may be directly connected to the root complex 315. In some example embodiments, the second endpoint 325b and the third endpoint 325c may communicate with the processor 305 through the root complex 315 and the switch 320. For example, the second endpoint 325b and the third endpoint 325c may communicate with each other in a peer-to-peer manner through the switch 320. In this case, the processor 305 may intervene in the processing of data exchanged between the second endpoint 325b and the third endpoint 325c.

[0041] For example, in some example embodiments, each of the first to third endpoints 325a to 325c may be a storage device. In some example embodiments, each of the first to third endpoints 325a to 325c may include any internal or external device or component incorporated into an electronic system (such as an I / O device, a network interface controller (NIC), an add-in card, an audio processor, a network processor, a hard disk drive, a storage device, a compact disk (CD) / digital video disk (DVD) ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices).

[0042] A data flow in a direction away from the root complex 315 may be defined as downstream, and a data flow in a direction closer to the root complex 315 may be defined as upstream. A port that transmits data in the downstream direction may be defined as a downstream port DSP, and a port that transmits data in the upstream direction may be defined as an upstream port USP. For example, a port included in the root complex 315 may be a downstream port. For example, a port included in each of the first endpoint 325a to the third endpoint 325c may be an upstream port.

[0043] For example, the switch 320 may transmit packets / messages upstream from a plurality of devices (eg, the first endpoint 325 a to the third endpoint 325 c ), or may transmit packets / messages downstream from the processor 305 .

[0044] According to various embodiments, each of the first device 101 and the second device 102 may perform an operation for configuring and initializing the link 103 therebetween to operate in a normal state (such as an L0 state). For example, each of the processor 305 and the root complex 315 may perform an operation for configuring and initializing the link between the processor 305 and the root complex 315 to operate in a normal state (such as an L0 state), each of the root complex 315 and the switch 320 may perform an operation for configuring and initializing the link between the root complex 315 and the switch 320 to operate in a normal state (such as an L0 state), each of the root complex 315 and the memory 310 may perform an operation for configuring and initializing the link between the root complex 315 and the memory 310 to operate in a normal state (such as an L0 state), and so on. The configuration and initialization may be performed through a link training operation of a physical layer. For example, at least one of a link width, a link data rate, a lane reversal, and a lane polarity may be set through a link training operation. For example, link training operations may include at least one of negotiation of link data rate, bit lock of each lane, lane polarity, symbol lock of each lane, ordering of lanes within link 103, negotiation of link width, and lane-to-lane deskew.

[0045] Link training may cause an unrelated channel of a port to become a channel forming a link 103. The first device 101 and the second device 102 may perform a training operation using a training sequence TS to properly set the channel to a desired link 103. The training sequence TS may be defined as a packet that the first device 101 and the second device 102 send to and receive from each other to share the state of the link 103 of the first device 101 and the second device 102 and manage information. In an example embodiment, the training sequence TS may include a plurality of symbols, and each of the plurality of symbols may have unique link information. For example, a symbol may correspond to a byte unit. For example, the training sequence may be TS1 and / or TS2 defined in the PCIe standard.

[0046] The first device 101 and the second device 102 may perform a training operation while sending and receiving training sequences to and from each other. The first device 101 and the second device 102 may perform a training operation based on a state machine included in the physical layer. Hereinafter, the state machine included in the above-mentioned physical layer (or third layer) will be described in detail.

[0047] Figure 5 is a diagram illustrating an example of a state machine according to some example embodiments.

[0048] Reference Figure 5The state machine may be configured for link training to exchange and control state information of the link 103. The state machine may be, for example, an LTSSM. The LTSSM may include a detection state, a polling state, a configuration state, a recovery state 420, an L0 state 400, an L0s state, an L1 state, an L2 state, a disabled state, a loopback state, and a hot reset state.

[0049] The detection state may be a state for detecting whether there is a terminal connected to the link 103. In the polling state, bit lock and symbol lock may be performed, or channel polarity may be configured. The configuration state may be a state for managing the configuration of the link 103. In the configuration state, a transmitter and a receiver included in the first device 101 and the second device 102 may send and receive data to negotiate a data rate. The recovery state 420 may recover from an error in the link 103, or may control a change in the data rate.

[0050] The L0 state 400 may be a state that a link that has successfully completed a training sequence can enter, and may be a state that can send and receive data and control packets. The L0 state 400 may include an L0p state 405. Here, the L0p state 405 may also be referred to as a loop state 405.

[0051] L0p state 405 is included in the PCIe 6.0 generation standard and can be defined as a sub-state of L0. L0p state 405 can provide power saving with short entry latency and long exit latency. Figure 3 The L0p state 405 can be supported in the above-mentioned microchip mode. The L0p state 405 allows the link to have several active channels without entering the recovery state, and allows the remaining channels to enter the electrical idle (EI) state. The EI state can be used for power saving and disabled states, and can be defined as a normal state in which the transmitter voltage is maintained at the same value in the EI state, for example.

[0052] When L0p state 405 is enabled, all ports can request a change in link width. Due to the change in link width, the number of enabled channels can increase or decrease. The link partner can send an acknowledgment Ack or a negative acknowledgment Nak in response to the request for link width change. The port can respond to the request within a specific time after receiving a valid microchip with the request. When the port does not receive a response within a specific time, the port can retry or abandon the request for link width change.

[0053] For example, according to an exemplary embodiment, the L0p state 405 may perform a fast error recovery process without entering the recovery state. The error recovery process of the L0p state 405 will be described in detail later.

[0054] The L0s and L1 states may be states for power saving, and the L2 state may be a state for maximum power saving. In the L2 state, most transmitters and receivers may be turned off. The disabled state may disable the configured link 103. The loopback state may be a state in which the link 103 of the device is isolated and maintained in a test state when the host determines that the device has encountered a fault. The hot reset state may be a state for resetting the configured link 103.

[0055] According to various examples, one of the plurality of states included in the state machine may transition to one or more other states. In addition to the state-to-state transition conditions partially mentioned in the example embodiments, the remaining state-to-state transition conditions may comply with the PCIe standard.

[0056] Figure 6 is a diagram showing a method according to an example embodiment Figure 5 . In the following description, the phrase "first device 101 and second device 102" is used with respect to a particular operation. It will be understood that the first device 101 may perform a particular operation, and the second device 102 may perform a particular operation. In other words, the phrase "first device 101 and second device 102" is used for ease of description, and does not necessarily require that the first device and the second device perform a particular operation together. For example, as further discussed below, each of the first device 101 and the second device 102 includes a state machine, and in some example embodiments, each of the first device 101 and the second device 102 may individually transition between the various states and sub-states discussed below.

[0057] Reference Figure 6 As described above, the L0 state 400 may include the L0p state 405. The L0p state 405 may include a first L0p substate (L0p.Entry) 410, a second L0p substate (L0p.RcvrLock) 415, a third L0p substate (L0p.Equalization) 420, a fourth L0p substate (L0p.RcvrCfg) 425, and a fifth L0p substate (L0p.Idle) 430.

[0058] When an error is detected in at least one channel among channels operating in the L0 state 400, the device may enter the first L0p substate (L0p.Entry) 410 for the at least one channel in which the error is detected, and may enter the first L0p substate (L0p.Entry) 410 for the at least one channel that may be configured using the at least one channel in which the error is detected and may be included in the link width (hereinafter, the channel maintained in the L0 state 400 will be referred to as a normal channel, and the channel entering the first L0p substate 410 will be referred to as a recovery channel). For example, referring to Figure 1 , when an error is detected in one of the channels La0, La1, La2, and La3 of the link 103 operating in the L0 state 400 between the first device 101 and the second device 102, the first device 101 and the second device 102 may enter the first L0p substate (L0p.Entry) 410 for at least one channel in which the error is detected, and may enter the first L0p substate (L0p.Entry) 410 for one or more other channels of the one or more channels La0, La1, La2, and La3 of the link 103 that may be configured using at least one channel in which the error is detected. Detection of an error may indicate, for example, the occurrence of one receiver error or multiple receiver errors. For example, when a symbol received from the physical layer 215 is invalid, a receiver error may have occurred. For example, the receiver error may be caused by a non-response from a device on the receiving side to a microchip sent by the transmitting side (for example, the receiving side does not transmit a training sequence to the transmitting side in response to the microchip) or the occurrence of a packet error. In some example embodiments, the occurrence of multiple receiver errors may indicate that the frequency of occurrence of receiver errors exceeds a specific standard.

[0059] In the first L0p substate (L0p.Entry) 410, the first device 101 and the second device 102 can interrupt the transmission of the flits for the recovery channel to transmit packets of different types. In the flits mode, there is no need to check the synchronization header, so that the recovery channel can transmit various ordered sets (OS), while the normal channel still transmits flits in the L0 state 400.

[0060] When the transmission of the flits is interrupted, the first device 101 and the second device 102 may transition to the second L0p substate (L0p.RcvrLock) 415 for the recovery channel. For example, the first device 101 and the second device 102 may check the interruption of the flits transmission to confirm the interruption in the flits transmission.

[0061] When transitioning from the first L0p substate (L0p.Entry) 410 to the second L0p substate (L0p.RcvrLock) 415, the first device 101 and the second device 102 may transmit an electrical idle exit ordered set (EIEOS) in the second L0p substate (L0p.RcvrLock) 415, and may check block alignment. Here, block alignment may indicate that no error has occurred. For example, EIEOS may be used to determine the beginning and end of an OS boundary in a received bit stream. The first device 101 and the second device 102 may confirm through EIEOS that the micro slice is aligned to start at the end of the first skip (SKP) OS after the start of data stream (SDS) OS. Each of the SDS OS and the SKP OS may be an OS defined in the PCIe standard, the SDS OS may be an OS for indicating the beginning of a data stream, and the SKP OS may be an OS for correcting a frequency difference between opposite ends of a link.

[0062] When the block alignment is confirmed (ie, when it is confirmed that there is no error), the first device 101 and the second device 102 may transition to the third L0p substate (L0p.Equalization) 420 or the fourth L0p substate (L0p.RcvrCfg) 425 according to whether there is an equalization history.

[0063] When there is no equalization history, for example, in the case of the first equalization attempt, the first device 101 and the second device 102 may transition to the third L0p sub-state (L0p.Equalization) 420 for the recovery channel. The first device 101 and the second device 102 may perform equalization in the third L0p sub-state (L0p.Equalization) 420. Equalization may include adjusting the transceiver configuration of each channel to improve signal quality and meet requirements for various parameters associated with transmission and reception. The first device 101 and the second device 102 may re-request optimal signal characteristics from each other through equalization to increase the possibility of returning to the L0 state 400. For example, according to an example embodiment, the first device 101 and the second device 102 enter the third L0p sub-state (L0p.Equalization) 420 to perform equalization only on the recovery channel, and thus the first device 101 and the second device 102 may maintain the L0 state 400 for the normal channel. When equalization succeeds normally, the first device 101 and the second device 102 can transition back to the second L0p sub-state (L0p.RcvrLock) 415 for the recovery channel.

[0064] When transitioning back to the second L0p sub-state (L0p.RcvrLock) 415, the first device 101 and the second device 102 may transmit EIEOS and confirm block alignment and errors. When it is confirmed that the block alignment is normal and there are no errors, the first device 101 and the second device 102 may transition to the fourth L0p sub-state (L0p.RcvrCfg) 425 for the recovery channel based on receiving continuous TS1 or TS2. In this case, TS1 or TS2 may have the same link and channel number for all channels. When the current data rate is 8GT / s or greater, the equalization control (EC) field in TS1 may be 00b. For example, the first device 101 and the second device 102 may transition to the fourth L0p sub-state (L0p.RcvrCfg) 425 after receiving eight consecutive TS1 or TS2.

[0065] In some example embodiments, when there is a history of equalization, for example, when equalization is performed at least once, the first device 101 and the second device 102 may immediately transition to the fourth L0p substate (L0p.RcvrCfg) 425 for the recovery channel after receiving consecutive TS1 or TS2 in the second L0p substate (L0p.RcvrLock) 415.

[0066] In the fourth L0p sub-state (L0p.RcvrCfg) 425, the first device 101 and the second device 102 may check the operation state of each channel before returning to the L0 state 400. For example, the first device 101 and the second device 102 may check again whether there is no operation error in the fourth L0p sub-state (L0p.RcvrCfg) 425 (i.e., block alignment may be checked). When there is no additional error in the fourth L0p sub-state (L0p.RcvrCfg) 425, the first device 101 and the second device 102 may transition to the fifth L0p sub-state (L0p.Idle) 430 for the recovery channel based on receiving continuous TS2. For example, the first device 101 and the second device 102 may receive eight continuous TS2s, and after receiving the eight continuous TS2s, may transition to the fifth L0p sub-state (L0p.Idle) 430 when the current data rate is 8 GT / s or more. In this case, TS2 may have the same link and channel numbers for all channels. When there are additional errors in the fourth L0p substate (L0p.RcvrCfg) 425, the first device 101 and the second device 102 may transmit an EIOS for the recovery channel and enter the EI state.

[0067] When the first device 101 and the second device 102 desire to transition to the L0 state 400, the first device 101 and the second device 102 may sequentially transmit the control SKP OS and the SDS OS to finally start the data flow. Then, the first device 101 and the second device 102 may send and receive idle flits for some channels to transition to the L0 state 400. The idle flits are flits in which all DLP values ​​are 0, and may be flits previously sent before transitioning to the L0 state 400. For example, the first device 101 and the second device 102 may transition to the L0 state 400 from the fifth L0p substate (L0p.Idle) 430 based on receiving N1 idle flits and sending N2 idle flits (where N1 and N2 are positive integers). For example, N1 may be 2, and N2 may be 4 or more. For example, N2 may be 4 or more in the 8b / 10b encoding scheme, and may be 8 or more in the 1b / 1b encoding scheme, but example embodiments are not limited thereto.

[0068] Then, the first device 101 and the second device 102 may transmit the SKP OS to synchronize operation timings between all channels, and may transmit a data stream defined as a group of flits that start when the SKP OS ends.

[0069] In the above embodiment, in addition to the recovery channel, the first device 101 and the second device 102 can still operate in the L0 state 400 for the normal channel. That is, the first device 101 and the second device 102 can transmit flits for the recovery channel while operating in the L0 state 400 for the normal channel.

[0070] According to the above-described embodiment, when an error occurs in a part of the channels of the link, the first device 101 and the second device 102 may attempt error recovery for the part of the channels without entering a recovery state for all the channels. In other words, when an error occurs in a part of the channels of the link, the first device 101 and the second device 102 may attempt error recovery only for the part of the channels without entering a recovery state for all the channels. The first device 101 and the second device 102 may transmit a flits in the recovery channel where error recovery should be attempted when an error occurs, while still maintaining the L0 state 400 in the remaining normal channels other than the recovery channel. Therefore, the first device 101 and the second device 102 may perform equalization within a single link to improve data communication based on the L0 state 400 and signal integrity (SI). Therefore, compared with the prior art, the first device 101 and the second device 102 may have the following advantages: ensuring the continuity of data communication, preventing the speed reduction caused by all existing channels entering recovery, and improving the flexibility of link operation.

[0071] Figure 7 is a diagram showing some example embodiments Figure 6 A diagram of the relationship between the L0p sub-states.

[0072] Reference Figure 7 , the first device 101 and the second device 102 according to an example embodiment may determine whether an error has occurred in a channel in operation (operation 505) while normally transmitting flits in the L0 state 400. When it is determined that the data stream cannot be transmitted due to one or more errors occurring in at least one channel during operation in the L0 state 400 (operation 505, yes), the first device 101 and the second device 102 cannot be maintained in the L0 state 400, but should transition to another state.

[0073] For example, the error may be the above-mentioned receiver error when viewed from the physical layer 215. For example, the error type may include a framing error, a loss of block alignment, an elastic buffer overflow / underflow, a loss of lane-to-lane de-skew, etc., as defined in the PCIe standard.

[0074] When a receiver error occurs in a portion of the channels (eg, one or more of the channels), the first device 101 and the second device 102 may transition from the L0 state 400 to a recovery state or L0p state 405 .

[0075] In an example embodiment, when a receiver error occurs in a portion of the channels, the first device 101 and the second device 102 may transition to the recovery state or L0p state 405 according to what equalization mechanism is used to enable the link to reach the current data rate. For example, the first device 101 and the second device 102 may transition to the recovery state from the L0 state 400 according to reaching the current data rate based on the full equalization mechanism. In this case, the first device 101 and the second device 102 may transition to the recovery state for all channels.

[0076] In some example embodiments, the first device 101 and the second device 102 may transition from the L0 state 400 to the L0p state 405 for the recovery channel based on using equalization bypass to achieve the current data rate. Equalization bypass may be defined as a mechanism that skips equalization for multiple data rates below a specific data rate and will be described in detail below.

[0077] According to an example embodiment, when the first device 101 and the second device 102 desire to transition to the L0p state 405, the first device 101 and the second device 102 may first transition to the first L0p sub-state 410 for the recovery channel. The first device 101 and the second device 102 may maintain the L0 state 400 for normal channels other than the recovery channel. Therefore, some channels may be maintained in the L0 state 400 so that continuity of data communication may be continuously ensured.

[0078] After transitioning to the L0p state 405 for the recovery channel, the first device 101 and the second device 102 may transmit various OSs through the recovery channel and may still transmit flits through the normal channel in the L0 state 400 .

[0079] When no error is detected (operation 505 , No), the first device 101 and the second device 102 may maintain the L0 state 400 for all channels.

[0080] Figure 7 The L0p sub-state shown in can be understood as being described with respect to the recovery channel.

[0081] For the recovery channel that has transitioned to the first L0p substate 410, the first device 101 and the second device 102 may attempt to interrupt the transmission of the flits (operation 510). In some example embodiments, the first device 101 and the second device 102 may attempt to stop the transmission of the flits.

[0082] The first device 101 and the second device 102 may determine whether the transmission of the flits for the recovery channel has stopped (operation 515). When the first device 101 and the second device 102 determine that the transmission of the flits has been interrupted (operation 515, yes), the first device 101 and the second device 102 may transition to the second L0p substate 415 for the recovery channel. When the first device 101 and the second device 102 determine that the transmission of the flits has not been interrupted (operation 515, no), the first device 101 and the second device 102 may maintain the first L0p substate 410 until the transmission of the flits is interrupted. In some example embodiments, when the transmission of the flits is not interrupted, the first device 101 and the second device 102 may transmit EIOS for the recovery channel and enter the EI state.

[0083] After transitioning to the second L0p substate 415, the first device 101 and the second device 102 may transmit EIEOS for the recovery channel (operation 520). For example, the first device 101 and the second device 102 may transmit TS1 and transmit EIEOS.

[0084] The first device 101 and the second device 102 may determine whether there is a problem (operation 525). For example, the first device 101 and the second device 102 may determine the start and end of the boundary of the OS in the bitstream received through the EIEOS, and confirm the block alignment and error. When it is determined that there is no problem (operation 525, no), the first device 101 and the second device 102 may transition to the third L0p substate 420 for the recovery channel. For example, when it is determined that the block alignment is normal and there is no error, the first device 101 and the second device 102 may transition to the third L0p substate 420 for the recovery channel. In some example embodiments, when it is determined that there is a problem (for example, when the block alignment is not confirmed as normal (ie, misaligned state) or an error is confirmed) (operation 525, yes), the first device 101 and the second device 102 may transmit the EIOS for the recovery channel and enter the EI state.

[0085] After transitioning to the third L0p sub-state 420, the first device 101 and the second device 102 may perform equalization (operation 530). In an example embodiment, the first device 101 and the second device 102 may train the link at 2.5GT / s, and then may immediately change to 32GT / s, a rate supported in PCIe 5.0 generation, and perform equalization at 32GT / s. For example, the first device 101 and the second device 102 may bypass the data rate used in PCIe generations prior to PCIe 5.0 generation.

[0086] In an example embodiment, in the third L0p substate 420, in the case of a timeout (transition to another state occurs after a certain time has passed), the first device 101 and the second device 102 may transition from the third L0p substate 420 to the second L0p substate 415 for the recovery channel but maintain the data rate. Then, the first device 101 and the second device 102 may transmit EIOS for the recovery channel and enter the EI state. In this case, even if the first device 101 and the second device 102 enter the second L0p substate 415 after the timeout occurs, it may be considered that there is an equalization execution history. For example, the variable start_equalization_w_preset indicating the equalization execution history may be set to 1b.

[0087] The variable perform_equalization_for_loopback_64GT (a variable indicating equalization associated with the loopback state) used in the recovery state may be set to 0b and / or maintained at 0b throughout the L0p state 405. For example, equalization in the L0p state 405 may be distinguished from equalization performed in the recovery state.

[0088] When equalization is successfully completed in operation 530 , the first device 101 and the second device 102 can transition back to the second L0p sub-state 415 for the recovery channel.

[0089] After transitioning back to the second L0p substate 415 from the third L0p substate 420, the first device 101 and the second device 102 may transmit EIEOS in the second L0p substate 415, and may determine whether there is a problem (operation 535). For example, the first device 101 and the second device 102 may confirm block alignment and errors. When there is no problem (for example, when block alignment is confirmed to be normal and there is no error) (operation 535, No), the first device 101 and the second device 102 may receive continuous TS1 or TS2 for the recovery channel (operation 540), and may transition to the fourth L0p substate 425 after receiving continuous TS1 or TS2 for the recovery channel.

[0090] In some example embodiments, when it is determined that there is a problem (eg, when block alignment is not confirmed as normal or an error is confirmed) (operation 535, Yes), the first device 101 and the second device 102 may transmit an EIOS for a recovery channel and enter an EI state.

[0091] After transitioning to the fourth L0p substate 425, the first device 101 and the second device 102 may transmit EIEOS and determine whether there is a problem (operation 545). For example, the first device 101 and the second device 102 may confirm block alignment and errors. For example, the first device 101 and the second device 102 may check the operation state of each channel before returning to the L0 state 400 from the fourth L0p substate 425. When there is no problem (for example, when the block alignment is normal and there is no error) (operation 545, No), the first device 101 and the second device 102 may receive continuous TS2 for the recovery channel (operation 550), and transition to the fifth L0p substate 430 after receiving continuous TS2 for the recovery channel.

[0092] In some example embodiments, when it is determined that there is a problem (for example, when block alignment is not confirmed as normal (i.e., misaligned state) or an error is confirmed) (operation 545, yes), the first device 101 and the second device 102 may transmit EIOS for the recovery channel and enter the EI state.

[0093] After transitioning to the fifth L0p substate 430, the first device 101 and the second device 102 may receive consecutive idle flits and transmit idle flits (operation 555), and may transition to the L0 state 400. For example, the first device 101 and the second device 102 may sequentially transmit a control SKP OS and an SDS OS to start a data flow before transitioning to the L0 state 400. Then, the first device 101 and the second device 102 may transition to the L0 state 400 based on receiving N1 idle flits and transmitting N2 idle flits for the recovery channel.

[0094] According to the above embodiment, even if an error occurs, not all channels enter the recovery state. Instead, only the recovery channel is converted to the L0p state 405, and the normal channel is maintained in the L0 state 400. Therefore, data communication can be maintained even in some channels.

[0095] In some example embodiments, when an error is sustained as a result of performing equalization, the first device 101 and the second device 102 do not reduce the speed of the recovery channel, but convert the recovery channel to the EI state. For example, unlike the recovery state of the prior art, the first device 101 and the second device 102 may disable the recovery channel to prevent the speed of all channels from being reduced.

[0096] When equalization is performed based on the above-mentioned equalization bypass, if the equalization fails, the returned data rate may be the data rate before the bypass data rate. For example, if the equalization fails at 64GT / s, the data rate may be reduced from 32GT / s to 2.5GT / s. However, according to example embodiments, the normal channel continues to be maintained in the L0 state 400, and the recovery channel is converted to the EI state, so that even the normal channel can operate at a high data rate (e.g., 64GT / s). That is, in some example embodiments, the normal channel continues to be maintained in the L0 state 400, and only the recovery channel is converted to the EI state, so that the normal channel can operate at a high data rate (e.g., 64GT / s).

[0097] Figure 8 is a diagram illustrating operation of the second L0p sub-state according to example embodiments.

[0098] Reference Figure 8 According to example embodiments, after transitioning from the first L0p substate 410 to the second L0p substate 415 , the first device 101 and the second device 102 may transmit EIEOS (operation 605 ), and may confirm block alignment.

[0099] After confirming the block alignment, the first device 101 and the second device 102 may check whether there is an equalization history (operation 610). When there is no equalization history (operation 610, no), the first device 101 and the second device 102 may transition to the third L0p substate 420 for the recovery channel. For example, the absence of the equalization history may indicate that the first device 101 and the second device 102 expect to perform equalization first after entering the L0p state 405. When there is an equalization history (operation 610, yes), it may be determined whether the first device 101 and the second device 102 have received eight consecutive TS1s or TS2s through the recovery channel (operation 615).

[0100] After receiving eight consecutive TS1 or TS2 (operation 615, yes), the first device 101 and the second device 102 may transition to the fourth L0p sub-state 425 for the channels among the restored channels that have received the consecutive TS1 or TS2. However, when there are channels that have not received eight consecutive TS1 or TS2 (operation 615, no), the first device 101 and the second device 102 may transition to the EI state for the channels that have not received eight consecutive TS1 or TS2. For example, the first device 101 and the second device 102 may determine the channels that have not received the consecutive TS1 or TS2 as inoperable channels, and may transition to the EI state for the inoperable channels, and transition to the fourth L0p sub-state 425 for the remaining channels.

[0101] Fig. 9 is a diagram illustrating operation of a third L0p sub-state according to example embodiments.

[0102] Reference Fig. 9 According to an example embodiment, the first device 101 and the second device 102 may perform equalization during phase 0 (705), phase 1 (715), phase 2 (725), and phase 3 (735) after transitioning from the second L0p substate 415 to the third L0p substate 420. A reference value for timeout may be set in each phase. The reference value may be set according to the type of port (e.g., DSP or USP), and a specific value may comply with the PCIe standard.

[0103] In phase 0 (705), the first device 101 and the second device 102 may exchange preset values ​​required for equalization during negotiation of a data rate at which equalization is to be performed or before negotiation of a data rate at which equalization is to be performed. In phase 0 (705), TS2 may be transmitted. It may be determined whether a timeout occurs (710). In an example embodiment, when a timeout occurs for a reference value set during phase 0 (705) (710, yes), the first device 101 and the second device 102 may return to the second L0p substate 415 and then immediately transition to the EI state. When a timeout does not occur for the reference value set during phase 0 (705) (710, no), the first device 101 and the second device 102 may transition to phase 1 (715).

[0104] In phase 1 (715), the first device 101 and the second device 102 may exchange TS1 (or TS0) to establish an operable link. It may be determined whether a timeout occurs (720). In an example embodiment, when a timeout occurs for a reference value set during phase 1 (715) (720, yes), the first device 101 and the second device 102 may return to the second L0p substate 415 and then immediately transition to the EI state. When a timeout does not occur for the reference value set during phase 1 (715) (720, no), the first device 101 and the second device 102 may transition to phase 2 (725).

[0105] In phase 2 (725), the device corresponding to the USP may send a request for setting a transmitter coefficient / preset that meets the electrical requirements of the link to the device corresponding to the DSP, and the devices may exchange TS1 (or TS0) with each other. It may be determined whether a timeout occurs (730). In an example embodiment, when a timeout occurs for a reference value set during phase 2 (725) (730, yes), the first device 101 and the second device 102 may return to the second L0p sub-state (415) and then immediately transition to the EI state. When a timeout does not occur for the reference value set during phase 2 (725) (730, no), the first device 101 and the second device 102 may transition to phase 3 (735).

[0106] In phase 3 (735), the device corresponding to the DSP may send a request for setting a transmitter coefficient / preset that meets the electrical requirements of the link to the device corresponding to the USP, and the devices may exchange TS1 (or TS0) with each other. It may be determined whether a timeout occurs (740). In an example embodiment, when a timeout occurs for a reference value set during phase 3 (735) (740, yes), the first device 101 and the second device 102 may return to the second L0p substate 415 and then immediately transition to the EI state. When a timeout does not occur for the reference value set during phase 3 (735) (740, no), the first device 101 and the second device 102 may return to the second L0p substate 415.

[0107] The operations performed in each stage may comply with the PCIe standard.

[0108] Fig.10 2 is a diagram illustrating operations of a fourth L0p sub-state and a fifth L0p sub-state according to example embodiments.

[0109] Reference Fig.10 According to an example embodiment, after transitioning from the second L0p substate 415 to the fourth L0p substate 425 , the first device 101 and the second device 102 may determine whether eight consecutive TS2s have been received through the recovery channel ( 805 ).

[0110] When eight consecutive TS2s have been received (805, Yes), the first device 101 and the second device 102 may transition to the fifth L0p sub-state 430 for the channels among the recovery channels for which the consecutive TS2s have been received. However, when there are channels for which eight consecutive TS2s have not been received (805, No), the first device 101 and the second device 102 may transition to the EI state for the channels for which eight consecutive TS2s have not been received.

[0111] The first device 101 and the second device 102 may determine whether two consecutive idle flits have been received for the recovery channel that has transitioned from the fourth L0p substate 425 to the fifth L0p substate 430, and determine whether a specific number of idle flits have been sent for the recovery channel (810). For example, as described above, the number of idle flits to be sent may be set based on an encoding method.

[0112] When two consecutive idle flits have been received and a specific number of idle flits have been sent (810, yes), the first device 101 and the second device 102 may transition to the L0 state 400. However, when two consecutive idle flits have not been received and / or a specific number of idle flits have not been sent (810, no), the first device 101 and the second device 102 may return to the detection state and retrain the link from the beginning.

[0113] Fig.11 is a diagram illustrating a data flow for each channel transmission according to an example embodiment.

[0114] Reference Fig.11 In one example embodiment, when x4 channels are set and operate in microchip mode, the first channel to the fourth channel ( Fig.11 Channels 0 to 3 of the L0 state 400 may each transmit a 3-way interleaved Nth microchip (where N is a positive integer) in the L0 state 400. For example, as described above, the first channel to the fourth channel may transmit 236B of TLP, 6B of DLP, 8B of CRC, and 8B of ECC. A data stream including TLP, DLP, CRC, and ECC may be transmitted in units of unit intervals (UIs) and symbols. A single symbol may have a size of 8 bits. For example, in the microchip mode, a single symbol may be modulated based on a pulse amplitude modulation-4 (PAM-4) scheme.

[0115] According to the above-described embodiment, when errors are detected in some channels, the remaining normal channels may still operate in the L0 state 400 except for the recovery channel transitioning to the L0p state ( 405 ) based on the error detection.

[0116] For example, when an error occurs in the third channel or the fourth channel, the first device 101 and the second device 102 may specifically operate at x2, which is the maximum width among the channel widths supported below x4. Fig.11 As shown in , the third channel and the fourth channel can be operated as recovery channels, and the first channel and the second channel can be operated as normal channels.

[0117] Then, according to the above-described embodiment, the first channel and the second channel may still sequentially transmit the N+1th microchip after the Nth microchip, and the third channel and the fourth channel may sequentially transmit various OSs in the microchips after the Nth microchip in the L0p sub-state. For example, according to an example embodiment, the third channel and the fourth channel may transmit the OS to attempt a recovery process, instead of being disabled as in the existing L0p.

[0118] Fig.12 is a diagram illustrating a data flow and LTSSM for each channel transmission according to an embodiment.

[0119] Reference Fig.12 In an example embodiment, when x4 channels are set and operate in micro-slice mode, an example may be provided in which when each of the first to fourth channels (channel 0 to channel 3) transmits 3-way interleaved micro-slices in the L0 state 400, one or more errors Err are detected in the second channel (e.g., channel 1).

[0120] Since the error Err is detected in the second channel (channel 1), the first device 101 and the second device 102 may have difficulty operating in the x2 channel width including the first channel and the second channel (channel 0 and channel 1). Therefore, the first device 101 and the second device 102 may continue to transfer microchips while the still operable first channel is maintained in the L0 state 400, and may transition to the first L0p sub-state 410 for the remaining second channel to the fourth channel. For example, the first device 101 and the second device 102 may operate with a channel width of x1.

[0121] According to the above-described embodiments for the recovery channel (eg, for the second to fourth channels), the first device 101 and the second device 102 may transmit an OS required in each L0p substate when transitioning to one of the first to fourth L0p substates 410 to 425.

[0122] For example, the first device 101 and the second device 102 may interrupt the transmission of flits for the second channel to the fourth channel after transitioning to the first L0p substate 410, and may transition to the second L0p substate 415 after the interruption of the transmission is confirmed. After the block alignment is confirmed and there is no equalization history in the second L0p substate 415, the first device 101 and the second device 102 may transition to the third L0p substate 420. The first device 101 and the second device 102 may perform equalization and return to the second L0p substate 415. The first device 101 and the second device 102 may transition to the fourth L0p substate 425 after the block alignment is confirmed and a specific number of training sequences (e.g., TS1 or TS2) are continuously received in the second L0p substate 415. The first device 101 and the second device 102 may transition to the fifth L0p substate 430 after a specific number of training sequences (e.g., TS2) are continuously received in the fourth L0p substate 425.

[0123] After transitioning to the fifth L0p sub-state 430, the first device 101 and the second device 102 may sequentially transmit the control SKP OS and the SDS OS in the second channel to the fourth channel before transitioning to the L0 state 400. Then, the first device 101 and the second device 102 may send and receive idle microchips and transition to the L0 state 400. In the L0 state 400, the first device 101 and the second device 102 may transmit the control SKP OS in response to the time point at which the first channel transmits the control SKP OS so that the operation timing is synchronized with the first channel. Then, the second channel to the fourth channel may return to the L0 state 400, and the link may have a channel width of x4 again. Therefore, all channels may normally transmit microchips (400) in the L0 state.

[0124] According to the above embodiment, when an error Err occurs in some channels, the first device 101 and the second device 102 can attempt recovery by converting only the channels that need to be recovered to the L0p state 405 (rather than converting all channels to the recovery state). Therefore, the maintainable channels (i.e., normal channels) can still transmit flits in the L0 state 400 to prevent timeouts that may otherwise occur if the communication of all channels is interrupted.

[0125] Fig.13 FIG. 1 is a diagram showing a data stream and LTSSM for each channel transmission according to an example embodiment. In order to avoid repetition and for simplicity, the LTSSM and the LTSSM are omitted. Fig.12 A detailed description of the overlapping parts.

[0126] Reference Fig.13 In an example embodiment, when x4 channels are set and operate in micro-slice mode, an example may be provided in which when each of the first to fourth channels (channel 0 to channel 3) transmits 3-way interleaved micro-slices in the L0 state 400, one or more errors Err are detected in the third channel (e.g., channel 2).

[0127] Since the error Err is detected in the third channel (channel 2), the first device 101 and the second device 102 may have difficulty operating in the x4 channel width, but the first device 101 and the second device 102 may operate in the x2 channel width including the first channel and the second channel (channel 0 and channel 1). Therefore, the first device 101 and the second device 102 may continue to transmit microchips while the first channel and the second channel that are still operable are maintained in the L0 state 400, and may transition to the first L0p sub-state 410 for the remaining third channel and the fourth channel. For example, the first device 101 and the second device 102 may operate in a channel width of x2.

[0128] According to the above-described embodiments for the recovery channel (e.g., the third channel and the fourth channel (Channel 2 and Channel 3)), the first device 101 and the second device 102 may transmit an OS required in each L0p substate when transitioning to one of the first to fourth L0p substates 410 to 425.

[0129] After transitioning to the fifth L0p substate 430 via the first L0p substate 410 and the fourth L0p substate 425, the first device 101 and the second device 102 may sequentially transmit the control SKP OS and the SDS OS in the third channel and the fourth channel before transitioning to the L0 state 400. Then, the first device 101 and the second device 102 may send and receive idle microchips and transition to the L0 state 400. Then, the first device 101 and the second device 102 may transmit the control SKP OS in response to the time point at which the first channel and the second channel transmit the control SKP OS, so that the operation timing is synchronized with the first channel and the second channel. Therefore, the third channel and the fourth channel may return to the L0 state 400, and the link may have a channel width of x4 again. Therefore, all channels may normally transmit microchips in the L0 state 400.

[0130] Although the embodiments related to the above data flow have been described with respect to a channel width of x4, the example embodiments are not limited thereto. For example, the example embodiments may be applied to all channel widths (x1, x2, x8, and x16) supported by the PCIe standard, including a channel width of x4 and a channel width greater than x16. For example, when the link is set to xN and one error Err or multiple error Errs are detected in at least one channel among the N channels, the first device 101 and the second device 102 may transition to the L0p state 405 for the recovery channel including the channel in which the error Err is detected, and may transmit microchips while the remaining channels are maintained in the L0 state 400. The first device 101 and the second device 102 may perform recovery processing while transmitting various OSs through the first L0p substate 410 to the fifth L0p substate 430 for the recovery channel, and may transition back to the L0 state 400 for the recovery channel when the recovery processing is completed.

[0131] Fig.14 is a flowchart illustrating a method of operating a device according to an example embodiment.

[0132] Reference Fig.14 In an example embodiment, in operation S105, the first device 101 and the second device 102 may transition from the L0 state 400 included in the LTSSM to the L0p state 405 for some of the channels, based on the occurrence of a receiver error in some of the channels included in the link and the link using equalization bypass to reach a specific data rate. For example, the first device 101 and the second device 102 may first transition from the L0 state 400 to the first L0p sub-state 410.

[0133] In operation S110, the first device 101 and the second device 102 may transmit the OS through some of the channels, and transmit the microchips through the remaining channels. Some of the channels may correspond to the above-mentioned recovery channels, and the remaining channels may correspond to the above-mentioned normal channels. In this case, some of the channels may interrupt the transmission of microchips and transmit the OS after transitioning to the L0p state 405, while the remaining channels may transmit the microchips while still maintaining the L0 state 400.

[0134] Fig.15 is a flow chart illustrating a method of equalization bypass operation of a device according to an example embodiment.

[0135] Reference Fig.15 In one example embodiment, in operation S205, the first device 101 and the second device 102 may train the link to the L0 state 400 at a first data rate (data rate 1). For example, the first data rate may be the lowest rate (2.5GT / s) among the data rates supported by the PCIe standard. In some example embodiments, the first device 101 and the second device 102 may advertise the highest data rate supported by each of the first device 101 and the second device 102. In some example embodiments, the first device 101 and the second device 102 may respectively announce whether the first device 101 and the second device 102 support equalization bypass.

[0136] In operation S210, the first device 101 and the second device 102 may respectively determine whether equalization bypass is supported. For example, the first device 101 may determine whether the second device 102 supports equalization bypass.

[0137] When at least one of the first device 101 and the second device 102 does not support equalization bypass (operation S210, No), the first device 101 and the second device 102 may perform sequential equalization (operation S215). In an example embodiment, when performing sequential equalization, the first device 101 and the second device 102 train the link at 2.5GT / s (a rate supported in 1.0 generation), and then may sequentially perform equalization for higher data rates (e.g., 8.0GT / s, 16GT / s, 32GT / s, and 64GT / s).

[0138] When both the first device 101 and the second device 102 support equalization bypass (operation S210, yes), the first device 101 and the second device 102 may change the speed to the highest data rate (e.g., the nth data rate (data rate n)). For example, the first device 101 and the second device 102 may skip equalization of data rates between the first data rate and the nth data rate. For example, when both the first device 101 and the second device 102 notify that the first device 101 and the second device 102 support equalization bypass, operation S220 may be performed. In operation S220, for example, the first device 101 and the second device 102 may transition to a recovery state at the first data rate, and may change the data rate to the nth data rate in the recovery state. In operation S225, for example, the first device 101 and the second device 102 may perform equalization at the nth data rate (data rate n).

[0139] In operation S230, the first device 101 and the second device 102 may determine whether equalization has been successfully performed through equalization bypass. When equalization fails (operation S230, no), the first device 101 and the second device 102 may perform sequential equalization in operation S215. In operation S215, when equalization is successfully performed through equalization bypass (S230, yes) or equalization is successfully performed through sequential equalization, in operation S235, the first device 101 and the second device 102 may complete flow control initialization for a normal channel at an nth data rate (data rate n), and may operate a link at an nth data rate (data rate n) in operation S240.

[0140] In operation S245, the first device 101 and the second device 102 may detect whether an error has occurred in the L0 state 400. When an error has occurred (S245, Yes), in operation S250, the first device 101 and the second device 102 may determine whether equalization bypass has been performed. For example, the first device 101 and the second device 102 may determine whether a current data rate (e.g., an nth data rate) has been reached based on equalization bypass.

[0141] When equalization bypass has been performed (operation S250, Yes), in operation S255, the first device 101 and the second device 102 may transition to the L0p state 405 for some channels, and may maintain the L0 state 400 for the remaining channels. When sequential equalization instead of equalization bypass is performed (S250, No), in operation S260, the first device 101 and the second device 102 may transition to the recovery state.

[0142] According to the above embodiment, when an error occurs and the current data rate is reached based on equalization bypass, the recovery channel can be converted to the L0p state 405, instead of all channels entering the recovery state, and the normal channel can be maintained in the L0 state 400, so that data communication can be maintained in some channels. For example, even if equalization fails for the recovery channel after equalization bypass, the normal channel can still be maintained in the L0 state (400) to prevent a significant reduction in rate.

[0143] Fig.16 is a diagram illustrating a method of transmitting a packet between ports according to an example embodiment. Fig.16 , an example in which equalization has been performed through the third L0p substate 420 is provided.

[0144] Reference Fig.16 In one example embodiment, in operation S305, the DSP and the USP may exchange data streams in micro-chip mode. For example, when the channel width of x4 is set, the data stream may be Figure 3 of microchips.

[0145] In operation S310, when transmitting and receiving a data stream, a receiver error may be detected for some channels in any one of the DSP port and the USP port. When the receiver error is detected, the DSP and the USP may transition from the L0 state 400 to the first L0p sub-state 410. In operation S315, the single port for which the receiver error has been detected may interrupt the transmission of the microchip for some channels and start transmitting the OS, and the single remaining port that has received the OS may also interrupt the transmission of the microchip and start transmitting the OS.

[0146] When the transmission of the flits is interrupted, the DSP and USP may transition to the second L0p substate 415 and may exchange EIEOS for block alignment for some channels in operation S320. As described above, when the equalization history already exists, the DSP and USP may exchange TS1 for some channels in operation S325.

[0147] Then, the DSP and the USP may transition to the fourth L0p sub-state 425, and TS2 may be exchanged for some channels in operation S330.

[0148] Then, the DSP and the USP may transition to the fifth L0p sub-state 430, and may exchange idle microslices for some channels in operation S335. When it is determined to transition to the L0 state 400, the DSP and the USP may sequentially exchange control SKP OS and SDS OS for some channels in operation S340. Finally, the DSP and the USP may transition back to the L0 state 400, and may exchange data streams in operation S345.

[0149] In the above embodiment, after a receiver error occurs, the DSP and the USP may still exchange data streams (eg, microslices) in the L0 state 400 for the remaining channels except for channels (ie, some channels) transmitting and receiving the OS in operations S315 to S340.

[0150] Fig.17 is a diagram illustrating a device according to example embodiments.

[0151] Reference Fig.17 , a device (or electronic device) 900 according to an example embodiment may include a processor 905 and a port 915. According to various embodiments, the device 900 may be a host (such as a main processor or a central processor, a root complex, a switch, an endpoint, or other components supporting communication with the host). That is, in some example embodiments, the device 900 may correspond to one of the first device 101 and the second device 102 described above.

[0152] The processor 905 may control the overall operation of the apparatus 900. In an example embodiment, the processor 905 may include a state machine 910 and may control a conversion operation between a plurality of states included in the state machine 910. The processor 905 may control a link based on the state machine 910 and perform, for example, a link training process and an error recovery process between the port 915 and another port 920 of another device. For example, in some example embodiments, the other device may correspond to the other of the first device 101 and the second device 102 described above.

[0153] Port 915 may be connected to another port 920 via a link. In some example embodiments, the link may correspond to the above-described link 103. Port 915 may be used to communicate with another port 920 using an interconnect protocol. Port 915 may be connected to a link to support communication between device 900 and another apparatus, and may be configured to transmit flits in a flits mode.

[0154] The device 900 can send a training sequence TS and a data stream to another port 920 through the port 915 and receive a training sequence TS and a data stream from another port 920 .

[0155] The device 900 may perform error recovery processing through the state machine 910 based on the various embodiments described above. In an example embodiment, the state machine 910 may include the L0p state 405, and the L0p state 405 includes the first L0p sub-state 410 to the fifth L0p sub-state 430. The processor 905 may transition from the L0 state 400 to the L0p state 405 for some channels based on the occurrence of a receiver error in one or more channels and the link using equalization bypass to reach a specific data rate. After transitioning to the L0p state 405, the port 915 may transmit OS through some channels and transmit micro slices through the remaining channels. The processor 905 may control the port 915 to transmit a signal to be transmitted in each sub-state when transitioning to each sub-state included in the loop state 405.

[0156] Fig.18 is a diagram illustrating a storage device according to example embodiments.

[0157] Reference Fig.18 , a storage device 1000 according to example embodiments may include a port 1005 , a controller 1010 , and a nonvolatile memory NVM 1020 . The storage device 1000 may be connected to a host 1030 .

[0158] In one example embodiment, the storage device 1000 may be a solid state drive (SSD), a universal flash memory (UFS), or an embedded multimedia controller (eMMC). In some example embodiments, the storage device 1000 may be a secure digital (SD) card, a micro SD card, a memory stick, a chip card, a universal serial bus (USB) card or a smart card, a compact flash (CF) card, etc., but example embodiments are not limited thereto.

[0159] In an example embodiment, the storage device 1000 may be implemented in any form factor (such as 3.5 inches, 2.5 inches, 1.8 inches, M.2, U.2, U.3, Enterprise and Data Center SSD Form Factor (EDSFF), New Form Factor 1 (NF1), etc.).

[0160] In an example embodiment, the storage device 1000 may be implemented using SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), and / or similar interfaces, and one or more of the following protocols: PCI, PCIe, NVMe (Non-Volatile Memory Express), NVMe-oF (NVMe over Network), Ethernet, InfiniBand, Fibre Channel, and / or similar protocols.

[0161] The controller 1010 may be connected to the nonvolatile memory 1020 and the port 1005 to control the overall operation of the memory device 1000 including the nonvolatile memory 1020. The controller 1010 may perform the operations according to the above-described various embodiments.

[0162] In an example embodiment, the controller 1010 may control the link based on the state machine 1015. The controller 1010 may control the port 1005 through the state machine 1015 to perform an error recovery process. In an example embodiment, the state machine 1015 may include an L0p state 405 including a first L0p substate 410 to a fifth L0p substate 430. The controller 1010 may transition from the L0 state 400 to the L0p state 405 for a portion of the channels based on a receiver error occurring in one or more channels in the portion of the channels and the link using equalization bypass to reach a specific data rate. After transitioning to the L0p state 405, the port 1005 may transmit OS through a portion of the channels and transmit microchips through the remaining channels in the plurality of channels. The controller 1010 may control the port 1005 to transmit a signal to be transmitted in each substate when transitioning to each substate included in the L0p state 405.

[0163] The nonvolatile memory NVM 1020 may be controlled by the controller 1010. The nonvolatile memory 1020 may store data transmitted from the host 1030, data generated by the storage device 1000, or various other data written by the controller 1010. In an example embodiment, the nonvolatile memory 1020 may include any nonvolatile memory such as a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), and a magnetic random access memory (MRAM) or a ferroelectric random access memory (FRAM), but example embodiments are not limited thereto.

[0164] As described above, according to example embodiments, an apparatus for error recovery and an operating method thereof may be provided.

[0165] While various example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made to the example embodiments without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. An electronic device, comprising: a port connected to a link including a plurality of lanes to support communication between the electronic device and another device and configured to transmit flits in a flits mode; as well as a processor configured to control the link based on link training and a status state machine, The processor is configured to: based on a receiver error occurring in a portion of the plurality of channels and based on the link using equalization bypass to reach a specific data rate, transition from an L0 state included in a link training and status state machine to an L0p state for the portion of the plurality of channels, and The port is configured to, after transitioning to the L0p state, transmit ordered sets through the portion of the plurality of channels and transmit flits through the remaining channels of the plurality of channels.

2. The electronic device according to claim 1, wherein: Equalization bypass skips equalization for multiple data rates below a certain data rate.

3. The electronic device according to claim 1, wherein: The L0p state includes a first L0p sub-state, a second L0p sub-state, a third L0p sub-state, a fourth L0p sub-state, and a fifth L0p sub-state.

4. The electronic device according to claim 3, wherein: The processor is configured as: Based on the transition to the first L0p sub-state for the portion of the plurality of channels, the control port interrupts transmission of the flits for the portion of the plurality of channels; as well as Based on interrupting the transmission of the microchips for the part of the plurality of channels, transitioning to the second L0p sub-state.

5. The electronic device according to claim 3, wherein: The processor is configured to, based on transitioning to the second L0p sub-state for the portion of the plurality of channels, control a port to transmit an electrical idle exit ordered-set for the portion of the plurality of channels.

6. The electronic device according to claim 3, wherein: The processor is configured to, after transitioning to the second L0p sub-state for the portion of the plurality of channels, transition from the second L0p sub-state to a third L0p sub-state for the portion of the plurality of channels when there is no equalization history.

7. The electronic device according to claim 3, wherein: The processor is configured as: performing equalization based on transitioning to a third L0p sub-state for the portion of the plurality of channels; as well as Based on successfully performing the equalization, transitioning from the third L0p sub-state to the second L0p sub-state is performed for the portion of the plurality of channels.

8. The electronic device according to claim 7, wherein: The processor is configured to, based on a timeout occurring during equalization, transition from the third L0p sub-state to the second L0p sub-state for the portion of the plurality of lanes, and maintain a data rate in the transition.

9. The electronic device according to claim 3, wherein: The processor is configured to transition from the second L0p substate to a fourth L0p substate for the portion of the plurality of lanes based on performing at least one equalization and based on receiving a specific number of training sequences after transitioning to the second L0p substate.

10. The electronic device according to claim 3, wherein: The processor is configured as: Based on transitioning to a fourth L0p sub-state for the portion of the plurality of channels, controlling a port to receive a training sequence for the portion of the plurality of channels; as well as Based on receiving a specific number of training sequences, transitioning from the fourth L0p sub-state to the fifth L0p sub-state is performed for the portion of the plurality of channels.

11. The electronic device according to claim 3, wherein: The processor is configured to, based on the transition to the fifth L0p sub-state for the portion of the plurality of lanes, control the port to sequentially transmit a control skip ordered set and a data flow start ordered set.

12. The electronic device according to claim 3, wherein: The processor is configured to transition from the fifth L0p sub-state to the L0 state based on receiving N1 idle flits and sending N2 idle flits for the portion of the plurality of channels, where N1 and N2 are positive integers.

13. The electronic device according to claim 5, wherein: The processor is configured to transition from the second L0p sub-state to the electrical idle state for the portion of the channels based on not confirming the block alignment when exiting the ordered set from electrical idle.

14. The electronic device according to claim 8, wherein: The processor is configured to transition from the second L0p sub-state to the electrical idle state based on transitioning to the second L0p sub-state in accordance with the timeout.

15. A method for error recovery, the method comprising: transitioning from an L0 state included in a link training and status state machine to an L0p state for the portion of the plurality of lanes based on receiver errors occurring in the portion of the lanes included in the link and based on the link reaching a particular data rate using equalization bypass; as well as The ordered sets are transmitted through the portion of the plurality of channels, and the flits are transmitted through the remaining portions of the plurality of channels.

16. The method according to claim 15, wherein: The L0p state includes a first L0p sub-state, a second L0p sub-state, a third L0p sub-state, a fourth L0p sub-state, and a fifth L0p sub-state. Wherein, the method further comprises: For the part of the plurality of channels, interrupting transmission of flits in a first L0p sub-state; and Based on interrupting the transmission of the microchips for the part of the plurality of channels, transitioning to the second L0p sub-state.

17. The method according to claim 16, further comprising: For the portion of the plurality of channels, transmitting an electrical idle exit ordered set in a second L0p substate; as well as Based on not confirming the block alignment when exiting the ordered set from electrical idle, transitioning from the second L0p sub-state to the electrical idle state for the portion of the channels.

18. The method according to claim 16, further comprising: determining whether an equalization history exists after transitioning to the second L0p sub-state; as well as Based on the absence of equilibrium history, transition to the third L0p sub-state.

19. The method according to claim 18, further comprising: performing equalization based on transitioning to a third L0p sub-state for the portion of the plurality of channels; Based on a timeout occurring during the equalization period, transitioning from a third L0p sub-state to a second L0p sub-state for the portion of the plurality of lanes, and maintaining a data rate during the transition; as well as Transitioning from the second L0p sub-state to the electrical idle state is performed for the portion of the plurality of channels.

20. A storage device, comprising: Non-volatile memory; a port connected to a link including a plurality of lanes to support communication between the storage device and another device and configured to transmit flits in a flits mode; as well as a controller configured to control the link based on link training and a status state machine, in, The controller is configured to: transition from an L0 state included in a link training and status state machine to an L0p state for a portion of the plurality of lanes based on a receiver error occurring in the plurality of lanes and based on the link using equalization bypass to reach a specific data rate, and The port is configured to, after transitioning to the L0p state, transmit ordered sets through the portion of the plurality of channels and transmit flits through the remaining channels of the plurality of channels.

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