Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device, which are favorable for realizing a narrow frame design. The display substrate comprises a substrate and a gate drive circuit arranged on the substrate. The gate drive circuit comprises a plurality of shift register circuits. The shift register circuit comprises an input control circuit and an output circuit. The input control circuit is connected with the first node, the second node, the input end and the clock end and is configured to control the potentials of the first node and the second node under the control of the clock end and the input end. And the output circuit is connected with the first node, the second node, the output end, the first voltage end and the third voltage end, and is configured to transmit a signal provided by the first voltage end or the third voltage end to the output end under the control of the first node and the second node. The input control circuit is located on one side of the output circuit in the first direction. The maximum length of the orthographic projection of the input control circuit on the substrate along the first direction is smaller than the maximum length of the orthographic projection of the output circuit on the substrate along the first direction.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) are active light emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present application provide a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, comprising: a substrate and a gate driving circuit disposed on the substrate, the gate driving circuit comprising a plurality of shift register circuits, and the shift register circuit comprising: an input control circuit and an output circuit. The input control circuit is connected to a first node, a second node, an input terminal, a clock terminal, a first voltage terminal, a second voltage terminal, and a fourth voltage terminal, and is configured to control the potential of the first node and the second node under the control of the clock terminal and the input terminal. The output circuit is connected to the first node, the second node, the output terminal, the first voltage terminal, and a third voltage terminal, and is configured to transmit a signal provided by the first voltage terminal or the third voltage terminal to the output terminal under the control of the first node and the second node. The input control circuit is located on one side of the output circuit along a first direction, and the maximum length of the orthographic projection of the input control circuit on the substrate along the first direction is less than the maximum length of the orthographic projection of the output circuit on the substrate along the first direction.

[0006] In some exemplary embodiments, the input control circuit includes: an input subcircuit, a first control subcircuit, a second control subcircuit, and a third control subcircuit. The input subcircuit is connected to the input terminal, the clock terminal, and the third node, and is configured to transmit the signal of the input terminal to the third node under the control of the clock terminal. The first control subcircuit is connected to the third node, the second node, and the first voltage terminal, and is configured to transmit the signal provided by the first voltage terminal to the second node under the control of the third node; or, the first control subcircuit is connected to the first node, the second node, and the first voltage terminal, and is configured to transmit the signal provided by the first voltage terminal to the second node under the control of the first node. The second control subcircuit is connected to the third node, the second node, and the fourth voltage terminal, and is configured to transmit the signal provided by the fourth voltage terminal to the second node under the control of the third node; or, the second control subcircuit is connected to the first node, the second node, and the fourth voltage terminal, and is configured to transmit the signal provided by the fourth voltage terminal to the second node under the control of the first node. The third control subcircuit is connected to the third node, the first node and the second voltage terminal, and is configured to conduct the third node and the first node under the control of the second voltage terminal.

[0007] In some exemplary embodiments, the fourth voltage terminal is connected to the second voltage terminal, or the fourth voltage terminal is connected to the third voltage terminal.

[0008] In some exemplary embodiments, a voltage value of a first voltage signal transmitted by the first voltage terminal is greater than a voltage value of a second voltage signal transmitted by the second voltage terminal, and a voltage value of the second voltage signal transmitted by the second voltage terminal is greater than a voltage value of a third voltage signal transmitted by the third voltage terminal; the clock signal provided by the clock terminal includes a first clock voltage value and a second clock voltage value, the first clock voltage value is greater than the second clock voltage value, and the voltage value of the third voltage signal is greater than the second clock voltage value of the clock signal.

[0009] In some exemplary embodiments, the first control subcircuit includes: a first control transistor. The second control subcircuit includes: a second control transistor. The third control subcircuit includes: a third control transistor. The transistor type of the second control transistor is different from the transistor type of the first control transistor, and the third control transistor and the first control transistor are of the same transistor type.

[0010] In some exemplary embodiments, the second control transistor is located between the third control transistor and the first control transistor along a second direction, the second direction intersecting the first direction. The active layer of the third control transistor extends along the first direction, and the active layer of the first control transistor and the active layer of the second control transistor both extend along the second direction.

[0011] In some exemplary embodiments, the second voltage terminal is connected to a second voltage line, the second voltage line is located on a side of the second control transistor away from the substrate, and the orthographic projection of the second voltage line on the substrate covers the orthographic projection of the active layer of the second control transistor on the substrate.

[0012] In some example embodiments, a width-to-length ratio of the third control transistor is greater than a width-to-length ratio of the second control transistor, and a width-to-length ratio of the second control transistor is greater than 1.

[0013] In some exemplary embodiments, the first control transistor and the third control transistor are P-type transistors, and the second control transistor is an N-type transistor.

[0014] In some exemplary embodiments, the display substrate further includes: an inorganic insulating layer and a plurality of first auxiliary semiconductor blocks, the plurality of first auxiliary semiconductor blocks being arranged on the same layer as the active layer of the first control transistor and the third control transistor, the inorganic insulating layer being located on a side of the plurality of first auxiliary semiconductor blocks away from the substrate, and the plurality of first auxiliary semiconductor blocks being located around the active layer of the second control transistor; the inorganic insulating layer being provided with a plurality of auxiliary vias, an orthographic projection of an auxiliary via on the substrate being located within the orthographic projection range of a first auxiliary semiconductor block on the substrate.

[0015] In some exemplary embodiments, the display substrate further includes: a plurality of second auxiliary semiconductor blocks, the plurality of second auxiliary semiconductor blocks being arranged on the same layer as the active layer of the second control transistor, the plurality of second auxiliary semiconductor blocks being located around the active layer of the second control transistor, and being located at the periphery of the plurality of first auxiliary semiconductor blocks away from the active layer of the second control transistor.

[0016] In some exemplary embodiments, the gate of the first control transistor is connected to the third node or the first node, the first electrode of the first control transistor is connected to the first voltage terminal, and the second electrode of the first control transistor is connected to the second node. The gate of the second control transistor is connected to the third node or the first node, the first electrode of the second control transistor is connected to the fourth voltage terminal, and the second electrode of the second control transistor is connected to the second node. The gate of the third control transistor is connected to the second voltage terminal, the first electrode of the third control transistor is connected to the third node, and the second electrode of the third control transistor is connected to the first node.

[0017] In some exemplary embodiments, the input subcircuit includes: an input transistor, a gate of the input transistor is connected to the clock terminal, a first electrode of the input transistor is connected to the input terminal, and a second electrode of the input transistor is connected to the third node. The input transistor is located on a side of the third control transistor away from the output circuit along the first direction, and an active layer of the input transistor extends along a second direction, and the second direction intersects the first direction.

[0018] In some exemplary embodiments, the output circuit includes: a first output transistor, a second output transistor, a first capacitor, and a second capacitor. The gate of the first output transistor is connected to the first node, the first electrode of the first output transistor is connected to the third voltage terminal, and the second electrode of the first output transistor is connected to the output terminal. The gate of the second output transistor is connected to the second node, the first electrode of the second output transistor is connected to the first voltage terminal, and the second electrode of the second output transistor is connected to the output terminal. The first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the first voltage terminal. The first output transistor and the second output transistor are arranged along the second direction, the first capacitor and the second capacitor are arranged along the second direction, the first capacitor is located along the first direction on the side of the first output transistor close to the input control circuit, the second capacitor is located along the first direction on the side of the second output transistor close to the input control circuit, and the second direction intersects with the first direction.

[0019] In some exemplary embodiments, a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is greater than or equal to 2.

[0020] In some example embodiments, a width-to-length ratio of the first output transistor is greater than a width-to-length ratio of a transistor included in the input control circuit, and a width-to-length ratio of the second output transistor is greater than a width-to-length ratio of a transistor included in the input control circuit.

[0021] In some exemplary embodiments, the second voltage terminal is connected to the second voltage line, the third voltage terminal is connected to the third voltage line, the first voltage terminal connected to the second capacitor is connected to the first first voltage line, and the first voltage terminal connected to the second output transistor is connected to the second first voltage line. The third voltage line is located between the second voltage line and the second first voltage line, and the first first voltage line is located on the side of the second voltage line away from the third voltage line. The orthographic projections of the third voltage line and the second first voltage line on the substrate overlap with the orthographic projection of the output circuit on the substrate; the orthographic projection of the second voltage line on the substrate overlaps with the orthographic projection of the input control circuit on the substrate.

[0022] In some exemplary embodiments, the line width of the third voltage line is greater than the line width of the second voltage line; the line width of the second first voltage line is greater than the line width of the first first voltage line, and greater than the line width of the third voltage line.

[0023] In some exemplary embodiments, the second voltage line, the third voltage line and the second first voltage line are arranged in the same layer, and the conductive layer where the first first voltage line is located is located on a side of the conductive layer where the second first voltage line is located close to the substrate.

[0024] In some exemplary embodiments, the clock end is connected to the first clock signal line or the second clock signal line, the first clock signal line and the second clock signal line are located on the side of the first first voltage line away from the second voltage line, and the first clock signal line and the second clock signal line are double-layer routing.

[0025] On the other hand, this embodiment provides a display device, including the display substrate as mentioned above.

[0026] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0028] Figure 1 is a schematic structural diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0029] Figure 2 is an equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0030] Figure 3 for Figure 2 The working timing diagram of the shift register circuit shown;

[0031] Figure 4 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0032] Figure 5 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0033] Figure 6 for Figure 5 A schematic top view of a shift register circuit of a gate drive circuit in FIG.

[0034] Figure 7 for Figure 6 A schematic diagram of a display substrate after forming a first semiconductor layer;

[0035] Fig. 8A for Figure 6 A schematic diagram of a display substrate after forming a first conductive layer;

[0036] Figure 8B for Fig. 8A A schematic diagram of a first conductive layer in FIG.

[0037] Fig. 9A for Figure 6 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0038] Fig. 9B for Fig. 9A A schematic diagram of a second conductive layer in FIG.

[0039] Fig. 10A for Figure 6 A schematic diagram of a display substrate after forming a second semiconductor layer;

[0040] Fig. 10B for Fig. 10A A schematic diagram of a second semiconductor layer in FIG.

[0041] Fig.11 for Figure 6 A schematic diagram of a display substrate after a third conductive layer is formed;

[0042] Fig.12 for Figure 6A schematic diagram of a display substrate after a fourth insulating layer is formed;

[0043] Fig.13 for Figure 6 A schematic diagram of a fourth conductive layer in FIG.

[0044] Fig.14 for Figure 5 A schematic diagram of a display substrate after a fifth insulating layer is formed;

[0045] Fig.15 for Figure 5 A schematic diagram of a fifth conductive layer;

[0046] Fig.16 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure;

[0047] Fig.17A is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0048] Fig. 17B for Fig.17A A top view schematic diagram of a shift register circuit in FIG.

[0049] Fig.18 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure;

[0050] Fig.19A is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0051] Fig.19B for Fig.19A A top view schematic diagram of a shift register circuit in FIG.

[0052] Fig. 20 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure;

[0053] Fig.21A is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0054] Fig. 21B for Fig.21A A top view schematic diagram of a shift register circuit;

[0055] Fig. 22 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure;

[0056] Fig.23 is another schematic top view of a shift register circuit according to at least one embodiment of the present disclosure;

[0057] Fig.24is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure;

[0058] Fig.25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0060] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0061] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0062] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0063] In this specification, unless otherwise clearly stipulated and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or the internal connection of two elements. Among them, "connection" includes "electrical connection". "Electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as the transmission of electrical signals between the connected constituent elements can be carried out. Examples of "elements with some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions. For ordinary technicians in this field, the meaning of the above terms in this disclosure can be understood according to the circumstances.

[0064] In this specification, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region or a drain electrode) and a source (source electrode terminal, a source region or a source electrode), and current can flow through the drain, the channel region and the source. In this specification, a channel region refers to an area where current mainly flows. In this specification, the aspect ratio of a transistor refers to the ratio between the width and length of the channel region of the transistor.

[0065] In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In addition, the gate electrode may also be referred to as a control electrode. In the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0066] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0067] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0068] In this specification, "about" and "substantially" mean that the limits are not strictly defined and the situation within the range of process and measurement errors is allowed. In this disclosure, "same" includes the situation where the numerical value differs within 10%.

[0069] In this specification, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" means "the main part of A extends along direction B". In this specification, the line width of the routing refers to the dimension of the routing in the direction that is in the same plane and perpendicular to the extension direction.

[0070] In this specification, "A and B are of the same layer structure" or "A and B are arranged in the same layer" means that A and B are formed simultaneously by the same patterning process. "Same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.

[0071] In some implementations, with the development of pixel circuits, multiple transistors of the pixel circuits require multiple gate control signals, and the multiple gate control signals need to be provided by multiple gate drive circuits. The current gate drive circuits have a large number of transistors and capacitors, and the layout space occupied by the gate drive circuits increases, which is not conducive to narrowing the frame.

[0072] The present embodiment provides a display substrate, comprising: a substrate and a gate drive circuit arranged on the substrate. The gate drive circuit comprises a plurality of shift register circuits, and the shift register circuit comprises an input control circuit and an output circuit. The input control circuit is connected to a first node, a second node, an input terminal, a clock terminal, a first voltage terminal, a second voltage terminal and a fourth voltage terminal, and is configured to control the potential of the first node and the second node under the control of the clock terminal and the input terminal. The output circuit is connected to a first node, a second node, an output terminal, a first voltage terminal and a third voltage terminal, and is configured to transmit a signal provided by the first voltage terminal or the third voltage terminal to the output terminal under the control of the first node and the second node. The input control circuit is located on one side of the output circuit along the first direction, and the maximum length of the orthographic projection of the input control circuit on the substrate along the first direction is less than the maximum length of the orthographic projection of the output circuit on the substrate along the first direction.

[0073] The display substrate provided in this embodiment sets the input control circuit and the output circuit separately, which can reduce the influence of the input control circuit on the output signal of the output end, is conducive to stabilizing the signal output, and can save the layout space occupied by the gate drive circuit to achieve a narrower frame size.

[0074] In some exemplary embodiments, the input control circuit may include: an input subcircuit, a first control subcircuit, a second control subcircuit, and a third control subcircuit. The input subcircuit may be connected to the input terminal, the clock terminal, and the third node, and configured to transmit the signal of the input terminal to the third node under the control of the clock terminal. The first control subcircuit may be connected to the third node, the second node, and the first voltage terminal, and configured to control the potential of the second node under the control of the third node; or, the first control subcircuit may be connected to the first node, the second node, and the first voltage terminal, and configured to control the potential of the second node under the control of the first node. The second control subcircuit may be connected to the third node, the second node, and the fourth voltage terminal, and configured to control the potential of the second node under the control of the third node; or, the second control subcircuit may be connected to the first node, the second node, and the fourth voltage terminal, and configured to control the potential of the second node under the control of the first node. The third control subcircuit may be connected to the third node, the first node, and the second voltage terminal, and configured to conduct the third node and the first node under the control of the second voltage terminal. The structure of the shift register circuit of this example can be conducive to stable signal output to achieve normal driving of the pixel circuit.

[0075] In some exemplary embodiments, the first control subcircuit may include: a first control transistor, the gate of the first control transistor is connected to the third node or the first node, the first electrode of the first control transistor is connected to the first voltage terminal, and the second electrode of the first control transistor is connected to the second node. The second control subcircuit may include: a second control transistor, the gate of the second control transistor is connected to the third node or the first node, the first electrode of the second control transistor is connected to the fourth voltage terminal, and the second electrode of the second control transistor is connected to the second node. The third control subcircuit may include: a third control transistor, the gate of the third control transistor is connected to the second voltage terminal, the first electrode of the third control transistor is connected to the third node, and the second electrode of the third control transistor is connected to the first node. The transistor type of the second control transistor may be different from the transistor type of the first control transistor, and the transistor type of the third control transistor and the first control transistor may be the same. For example, the first control transistor and the third control transistor may be P-type transistors, and the second control transistor may be N-type transistors.

[0076] In some exemplary embodiments, the second voltage terminal is connected to a second voltage line, and the second voltage line may be located on a side of the second control transistor away from the substrate. The orthographic projection of the second voltage line on the substrate may cover the orthographic projection of the active layer of the second control transistor on the substrate. The arrangement of this example can prevent the external ambient light from affecting the characteristics of the second control transistor.

[0077] In some exemplary embodiments, the width-to-length ratio of the third control transistor may be greater than the width-to-length ratio of the second control transistor, and the width-to-length ratio of the second control transistor may be greater than 1. For example, the width-to-length ratio of the second control transistor may be approximately 10 / 8 or 12 / 8; the width-to-length ratio of the third control transistor may be greater than or equal to 2, for example, may be approximately 8 / 4 or 10 / 4. The configuration of this example can reduce the characteristic drift of the third control transistor and ensure the response speed of the second control transistor.

[0078] In some exemplary embodiments, the output circuit may include: a first output transistor, a second output transistor, a first capacitor, and a second capacitor. The gate of the first output transistor is connected to the first node, the first electrode of the first output transistor is connected to the third voltage terminal, and the second electrode of the first output transistor is connected to the output terminal. The gate of the second output transistor is connected to the second node, the first electrode of the second output transistor is connected to the first voltage terminal, and the second electrode of the second output transistor is connected to the output terminal. The first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the first voltage terminal. The first output transistor and the second output transistor may be arranged along the second direction, the first capacitor and the second capacitor may be arranged along the second direction, the first capacitor may be located along the first direction on the side of the first output transistor close to the input control circuit, and the second capacitor may be located along the first direction on the side of the second output transistor close to the input control circuit. The second direction may intersect with the first direction, for example, the second direction may be perpendicular to the first direction. The arrangement of this example may be beneficial to saving the space occupied by the arrangement of the gate drive circuit.

[0079] The solution of this embodiment is described below by means of some examples.

[0080] In some examples, the display substrate may include: a display area and a non-display area. For example, the non-display area may be located at the periphery of the display area. The non-display area may be a frame area surrounding the display area. In other examples, the non-display area may be located between adjacent display areas.

[0081] In some examples, the display area may include multiple sub-pixels. A pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In other examples, a pixel unit may include four sub-pixels, and the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. In other examples, a pixel unit may include four sub-pixels, and the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels.

[0082] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit. The shape of the orthographic projection of the light-emitting element on the substrate may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a herringbone manner; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a square manner. However, this embodiment is not limited to this.

[0083] In some examples, the display area may include at least: a plurality of pixel circuits arranged in an array, a plurality of gate lines extending along a first direction (for example, including: a scan line, a reset signal line, a light emitting control line), and a plurality of data lines extending along a second direction. The plurality of gate lines may be arranged along the second direction and connected to the plurality of pixel circuits; the plurality of data lines may be arranged along the first direction and connected to the plurality of pixel circuits. The first direction and the second direction may be located in the same plane, and the first direction may intersect with the second direction, for example, the first direction may be perpendicular to the second direction. For example, a plurality of pixel circuits arranged in sequence along the first direction is a row of pixel circuits, and a plurality of pixel circuits arranged in sequence along the second direction is a column of pixel circuits.

[0084] In some examples, the pixel circuit can be configured to drive the connected light-emitting element. For example, the pixel circuit can be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may all be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0085] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0086] In some examples, the non-display area may be provided with a timing controller, a data driving circuit, and a plurality of gate driving circuits. Among them, the plurality of gate driving circuits may be provided on opposite sides of the display area, for example, on the left and right sides of the display area (such as the left frame area and the right frame area); the timing controller and the data driving circuit may be provided on one side of the display area, for example, on the lower side of the display area (such as the lower frame area). However, this embodiment is not limited to this. In other examples, the gate driving circuit may be located in the display area.

[0087] In some examples, the data driving circuit can provide data signals to multiple sub-pixels in the display area through multiple data lines. The timing controller can provide driving signals to the data driving circuit and the gate driving circuit. Among them, the actions of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide the data driving circuit with grayscale data specifying the grayscale to be displayed in the sub-pixel. The data driving circuit can provide a data signal with a potential corresponding to the grayscale data of the sub-pixel to the sub-pixel of the row selected by the gate driving circuit via the data line.

[0088] In some examples, the display substrate may include multiple gate drive circuits, for example, a gate drive circuit for outputting a scan signal, a gate drive circuit for outputting a light-emitting control signal, and the like. For example, the gate drive circuit for outputting a scan signal may provide a scan signal to a plurality of sub-pixels through a plurality of gate lines (such as scan lines), and provide a reset signal to a plurality of sub-pixels through a plurality of gate lines (such as reset signal lines); the gate drive circuit for outputting a light-emitting control signal may provide a light-emitting control signal to a plurality of sub-pixels through a plurality of gate lines (such as light-emitting control lines). Each gate drive circuit may include a plurality of cascaded shift register circuits. The output end of each stage of the shift register circuit may be respectively connected to a plurality of pixel circuits in a corresponding row of pixel circuits through a gate line, and configured to provide a gate control signal (such as a scan signal) to the row of pixel circuits.

[0089] Figure 1 FIG. 1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure. Figure 1 As shown, the shift register circuit of this example may include: an input control circuit 11 and an output circuit 12. The input control circuit 11 may be connected to the input terminal IN, the clock terminal CK, the first node N1, the second node N2, the first voltage terminal VGH, the second voltage terminal VGL1 and the fourth voltage terminal VGL3, and is configured to control the potential of the first node N1 and the second node N2 under the control of the input terminal IN and the clock terminal CK. The output circuit 12 may be connected to the output terminal OUT, the first node N1, the second node N2, the first voltage terminal VGH and the third voltage terminal VGL2, and is configured to transmit the signal provided by the first voltage terminal VGH or the third voltage terminal VGL2 to the output terminal OUT under the control of the first node N1 and the second node N2.

[0090] In some examples, the first voltage terminal VGH can be connected to the first voltage line and configured to continuously provide a high-level first voltage signal. The second voltage terminal VGL1 can be connected to the second voltage line and configured to continuously provide a low-level second voltage signal, and the third voltage terminal VGL2 can be connected to the third voltage line and configured to continuously provide a low-level third voltage signal. The third voltage signal can be less than the second voltage signal, and the second voltage signal can be less than the first voltage signal. The fourth voltage terminal VGL3 can be connected to the second voltage terminal VGL1 or the third voltage terminal VGL2. The "high level" and "low level" mentioned in this article are relative.

[0091] In some examples, the clock signal provided by the clock terminal CK may be a square wave signal. The clock signal may have two alternating levels, the voltage values ​​of the two alternating levels are respectively a first clock voltage value and a second clock voltage value, and the first clock voltage value is greater than the second clock voltage value. The first clock voltage value may be the same as the voltage value of the first voltage signal, and the second clock voltage value may be less than the voltage value of the third voltage signal.

[0092] Figure 2 is an equivalent circuit diagram of a shift register circuit of at least one embodiment of the present disclosure. In some examples, such as Figure 2 As shown, the input control circuit 11 may include: an input subcircuit 110 , a first control subcircuit 111 , a second control subcircuit 112 and a third control subcircuit 113 .

[0093] In some examples, the input subcircuit 110 may be connected to the input terminal IN, the clock terminal CK, and the third node N3, and configured to transmit the input signal provided by the input terminal IN to the third node N3 under the control of the clock terminal CK. The first control subcircuit 111 may be connected to the third node N3, the second node N2, and the first voltage terminal VGH, and configured to transmit the signal provided by the first voltage terminal VGH to the second node N2 under the control of the third node N3. The second control subcircuit 112 may be connected to the third node N3, the second node N2, and the fourth voltage terminal, and configured to transmit the signal provided by the fourth voltage terminal to the second node N2 under the control of the third node N3. The fourth voltage terminal of this example is connected to the second voltage terminal VGL1. The third control subcircuit 113 may be connected to the third node N3, the first node N1, and the second voltage terminal VGL1, and configured to conduct the first node N1 and the third node N3 under the control of the second voltage terminal VGL1.

[0094] In some examples, such as Figure 2As shown, the input subcircuit 110 may include: an input transistor T3. The gate of the input transistor T3 is connected to the clock terminal CK, the first electrode of the input transistor T3 is connected to the input terminal IN, and the second electrode of the input transistor T3 is connected to the third node N3. The first control subcircuit 111 may include: a first control transistor T4, the gate of the first control transistor T4 is connected to the third node N3, the first electrode of the first control transistor T4 is connected to the first voltage terminal VGH, and the second electrode of the first control transistor T4 is connected to the second node N2. The second control subcircuit 112 may include: a second control transistor T5; the gate of the second control transistor T5 is connected to the third node N3, the first electrode of the second control transistor T5 is connected to the second voltage terminal VGL1, and the second electrode of the second control transistor T5 is connected to the second node N2. The third control subcircuit 113 may include: a third control transistor T6; the gate of the third control transistor T6 is connected to the second voltage terminal VGL1, the first electrode of the third control transistor T6 is connected to the third node N3, and the second electrode of the third control transistor T6 is connected to the first node N1.

[0095] In some examples, such as Figure 2 As shown, the output circuit 12 may include: a first output transistor T1, a second output transistor T2, a first capacitor C1, and a second capacitor C2. The gate of the first output transistor T1 is connected to the first node N1, the first electrode of the first output transistor T1 is connected to the third voltage terminal VGL2, and the second electrode of the first output transistor T1 is connected to the output terminal OUT. The gate of the second output transistor T2 is connected to the second node N2, the first electrode of the second output transistor T2 is connected to the first voltage terminal VGH, and the second electrode of the second output transistor T2 is connected to the output terminal OUT. The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode of the first capacitor C1 is connected to the output terminal OUT. The first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode of the second capacitor C2 is connected to the first voltage terminal VGH.

[0096] In this example, the first node N1, the second node N2 and the third node N3 do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are nodes equivalent to the junction points of related electrical connections in the circuit diagram.

[0097] Figure 2 An exemplary structure of the input subcircuit 110, the first control subcircuit 111, the second control subcircuit 112, the third control subcircuit 113 and the output circuit 12 is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the input subcircuit 110, the first control subcircuit 111, the second control subcircuit 112, the third control subcircuit 113 and the output circuit 12 is not limited thereto, as long as the functions thereof can be achieved.

[0098] In some examples, the shift register circuit may include: at least one first type transistor and at least one second type transistor. The transistor types of the first type transistor and the second type transistor are different. For example, the first type transistor may include: an input transistor T3, a first control transistor T4, a third control transistor T6, a first output transistor T1 and a second output transistor T2, and the second type transistor may include: a second control transistor T5. For example, the second type transistor may be an N-type transistor, such as an oxide transistor; the first type transistor may be a P-type transistor, such as a low temperature polysilicon transistor.

[0099] The working process of the first-stage shift register circuit is taken as an example for description below. The input terminal IN of the first-stage shift register circuit can be connected to the start signal line STV. Figure 3 for Figure 2 The working timing diagram of the shift register circuit is shown below. Figure 2 The second control transistor T5 in the shift register circuit shown is an N-type transistor, and the other transistors are P-type transistors. The clock terminal CK connected to the first stage shift register circuit is connected to the first clock signal line CLK.

[0100] like Figure 3 As shown, the working process of the shift register circuit provided in this example may include the following stages.

[0101] In the first phase A1, when the start signal line STV provides a high-level first voltage signal and the first clock signal line CLK provides a low-level signal, the input transistor T3 is turned on under the control of the low-level signal provided by the first clock signal line CLK, and the high-level first voltage signal provided by the start signal line STV is provided to the third node N3, so that the second control transistor T5 is turned on and the first control transistor T4 is turned off. The low-level second voltage signal provided by the second voltage terminal VGL1 can be provided to the second node N2 through the turned-on second control transistor T5, so that the second output transistor T2 is turned on. The third control transistor T6, under the control of the low-level second voltage signal provided by the second voltage terminal VGL1, turns on the third node N3 and the first node N1, so that the high-level first voltage signal provided by the start signal line STV can be provided to the first node N1, and the first output transistor T1 is turned off. Since the first output transistor T1 is turned off and the second output transistor T2 is turned on, the first voltage signal provided by the first voltage terminal VGH can be provided to the output terminal OUT.

[0102] When the start signal line STV provides a high-level first voltage signal, and the first clock signal line CLK switches from a low-level signal to a high-level signal, the input transistor T3 is turned off under the control of the first voltage signal provided by the first clock signal line CLK. The first node N1 maintains a high potential under the action of the first capacitor C1; the second node N2 maintains a low potential under the action of the second capacitor C2, thereby ensuring that the output terminal OUT outputs a high-level signal.

[0103] In the second phase A2, when the start signal line STV provides a low level signal and the first clock signal line CLK provides a low level signal, the input transistor T3 is turned on under the control of the low level signal provided by the first clock signal line CLK, and the low level signal provided by the start signal line STV is provided to the third node N3, so that the second control transistor T5 is turned off and the first control transistor T4 is turned on. The first voltage signal provided by the first voltage terminal VGH can be provided to the second node N2 through the turned-on first control transistor T4, so that the second output transistor T2 is turned off. The third control transistor T6 is controlled by the low level second voltage signal provided by the second voltage terminal VGL1, and the third node N3 and the first node N1 are turned on, so that the low level signal provided by the start signal line STV can be provided to the first node N1, and the first output transistor T1 is turned on. Since the first output transistor T1 is turned on and the second output transistor T2 is turned off, the low level third voltage signal provided by the third voltage terminal VGL2 can be provided to the output terminal OUT.

[0104] When the start signal line STV provides a low level signal and the first clock signal line CLK switches from a low level signal to a high level signal, the input transistor T3 is turned off under the control of the high level signal provided by the first clock signal line CLK. The first node N1 maintains a low potential under the action of the first capacitor C1; the second node N2 maintains a high potential under the action of the second capacitor C2, thereby ensuring that the output terminal OUT outputs a low level signal.

[0105] In some examples, the first voltage terminal VGH may provide a first voltage signal of a high level. The high level signal provided by the start signal line STV may have the same voltage value as the first voltage signal, and the low level signal provided by the start signal line STV may have the same voltage value as the third voltage signal provided by the third voltage terminal. The voltage value of the high level signal of the clock signal provided by the first clock signal line CLK and the second clock signal line CLB may be a first clock voltage value, and the voltage value of the low level signal of the clock signal may be a second clock voltage value. The first clock voltage value may be greater than the second clock voltage value. The first clock voltage value may be the same as the voltage value of the first voltage signal. For example, the first clock voltage value may range from 6V to 16V, such as approximately 14V; the second clock voltage value may range from -6V to -16V, such as approximately -12V.

[0106] In some examples, the voltage value of the second voltage signal provided by the second voltage terminal VGL1 may be greater than the voltage value of the third voltage signal provided by the third voltage terminal VGL2, and the voltage value of the third voltage signal provided by the third voltage terminal VGL2 may be greater than the second clock voltage value. The third voltage signal provided by the third voltage terminal VGL2 may also be configured to be provided to the light-emitting element of the display area, for example, it may be provided to the cathode of the light-emitting element of the display area. For example, the voltage value range of the third voltage signal may be -4.5V to -12.5V, such as approximately -6V. For example, the voltage value range of the second voltage signal may be -4V to -12V.

[0107] In some examples, when the gate of the second control transistor T5 receives a low-level signal of the input signal (for example, the voltage value is the same as the voltage value of the third voltage signal), the first electrode of the second control transistor T5 is connected to the second voltage terminal VGL1 to receive the second voltage signal, and the gate-source voltage difference Vgs of the second control transistor T5 is the difference between the voltage values ​​of the third voltage signal and the second voltage signal. For example, the voltage value of the second voltage signal is -5.5V, and the voltage value of the third voltage signal is -6V, Vgs=-6-(-5.5)=-0.5V, which can prevent the gate-source voltage difference Vgs of the second control transistor T5, which is an N-type transistor, from being kept at 0 for a long time, thereby preventing the gate node of the second output transistor from leaking and causing output instability.

[0108] Figure 4 Schematic diagram of a gate drive circuit of at least one embodiment of the present disclosure. Figure 4 As shown, the gate driving circuit may include a plurality of cascaded shift register circuits (such as the first-stage shift register circuit GOA(1) to the fourth-stage shift register circuit GOA(4)). For example, the i-th stage shift register circuit and the i+1-th stage shift register circuit may be cascaded, and i may be an integer greater than 0.

[0109] In some examples, the input terminal IN of the first-stage shift register circuit GOA (1) is connected to the start signal line STV, the input terminal IN of the second-stage shift register circuit GOA (2) can be connected to the output terminal OUT of the first-stage shift register circuit GOA (1), the output terminal OUT of the second-stage shift register circuit GOA (2) is connected to the input terminal IN of the third-stage shift register circuit GOA (3). The output terminal OUT of the third-stage shift register circuit GOA (3) can be connected to the input terminal IN of the fourth-stage shift register circuit GOA (4).

[0110] In some examples, the clock terminal CK of the odd-numbered shift register circuits (e.g., the first-level shift register circuit GOA(1) and the third-level shift register circuit GOA(3)) can be connected to the first clock signal line CLK, and the clock terminal CK of the even-level shift register circuits (e.g., the second-level shift register circuit GOA(2) and the fourth-level shift register circuit GOA(4)) can be connected to the second clock signal line CLB.

[0111] In some examples, the first voltage terminal VGH of each shift register circuit can be connected to the first voltage line VH, the second voltage terminal VGL1 of each shift register circuit can be connected to the second voltage line VL1, and the third voltage terminal VGL2 of each shift register circuit can be connected to the third voltage line VL2.

[0112] Figure 5 It is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 6 for Figure 5 Schematic diagram of a top view of a shift register circuit of a gate drive circuit in FIG. Figure 5 and Figure 6 The circuit diagram of the shift register circuit shown can be Figure 2 In some examples, such as Figure 5 and Figure 6 As shown, in a plane parallel to the display substrate, the outer contour of a single shift register circuit can be roughly rectangular. The setting area of ​​the gate drive circuit can be divided into a first area S1 and a second area S2 arranged in sequence along the first direction D1. The first area S1 and the second area S2 can be arranged in the direction close to the display area along the first direction D1. The positive projection of the input control circuit 11 of the shift register circuit on the substrate can be located in the first area S1; the positive projection of the output circuit 12 on the substrate can be located in the second area S2. In the first area S1, the third control transistor T6, the second control transistor T5 and the first control transistor T4 of the input control circuit 11 can be arranged in sequence along the second direction D2, and the input transistor T3 can be located on the side of the third control transistor T6 away from the output circuit 12 along the first direction D1. In the second region S2, the first capacitor C1 and the second capacitor C2 may be arranged in sequence along the second direction D2, the first output transistor T1 and the second output transistor T2 may be arranged in sequence along the second direction D2, the first capacitor C1 may be located along the first direction D1 on the side of the first output transistor T1 close to the input control circuit 11, and the second capacitor C2 may be located along the first direction D1 on the side of the second output transistor T2 close to the input control circuit 11. The maximum length L1 of the orthographic projection of the input control circuit 11 on the substrate along the first direction D1 may be less than the maximum length L2 of the orthographic projection of the output circuit 12 on the substrate along the first direction D1. The arrangement of this example can make full use of the arrangement space.

[0113] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, a first semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a second semiconductor layer, a third conductive layer (also referred to as a third gate metal layer), a fourth conductive layer (also referred to as a first source-drain metal layer), and a fifth conductive layer (also referred to as a second source-drain metal layer) sequentially disposed on the substrate. Among them, a first insulating layer (also referred to as a first gate insulating layer) may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer (also referred to as a second gate insulating layer) may be disposed between the first conductive layer and the second conductive layer, a third insulating layer (also referred to as a third gate insulating layer) may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer (also referred to as a fourth gate insulating layer) may be disposed between the second semiconductor layer and the third conductive layer, a fourth insulating layer (also referred to as an interlayer insulating layer) may be disposed between the third conductive layer and the fourth conductive layer, and a fifth insulating layer (also referred to as a planarizing layer) may be disposed between the fourth conductive layer and the fifth conductive layer. In some examples, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may all be inorganic insulating layers, and the fifth insulating layer may be an organic insulating layer. However, this embodiment is not limited thereto.

[0114] The preparation process of the display substrate is exemplified below. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0115] The preparation process of the display substrate of this example may include the following steps.

[0116] (1) Provide a substrate. In some examples, the substrate may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0117] (2) Forming a first semiconductor layer. In some examples, a first semiconductor film is deposited on a substrate, and the first semiconductor film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0118] Figure 7 for Figure 6 Schematic diagram of a display substrate after forming a first semiconductor layer in FIG. Figure 6 and Figure 7 As shown, the first semiconductor layer of the display substrate may include: active layers of multiple first type transistors of the shift register circuit (for example, including: active layers T10-1 and T10-2 of the first output transistor T1, active layers T20-1 and T20-2 of the second output transistor T2, active layer T30 of the input transistor T3, active layer T40 of the first control transistor T4, active layer T50 of the second control transistor T5, and active layer T60 of the third control transistor T6), and multiple first auxiliary semiconductor blocks 201.

[0119] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the semiconductor layer may include, for example, polysilicon. The channel region of the transistor may not be doped with impurities and may have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region and may be doped with impurities and may therefore be conductive. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. For example, the first region of the active layer may be interpreted as a first pole of the transistor, and the second region of the active layer may be interpreted as a second pole of the transistor. Portions of the active layer between transistors may be interpreted as wiring doped with impurities, which may be used to electrically connect transistors. This embodiment is not limited to this.

[0120] In some examples, such as Figure 6 and Figure 7 As shown, the active layers T10-1 and T10-2 of the first output transistor T1 may be disposed adjacently along the first direction D1 and extend along the second direction D2. The active layers T20-1 and T20-2 of the second output transistor T2 may be disposed adjacently along the first direction D1 and extend along the second direction D2. The active layer T10-1 of the first output transistor T1 and the active layer T20-1 of the second output transistor T2 may be an integrated structure, and the active layer T10-2 of the first output transistor T1 and the active layer T20-2 of the second output transistor T2 may be an integrated structure.

[0121] In some examples, the active layer T60 of the third control transistor T6 may be located on a side of the active layer T30 of the input transistor T3 close to the active layer T10-1 of the first output transistor T1. The active layer T40 of the first control transistor T4 may be located on a side of the active layer T60 of the third control transistor T6 along the second direction D2. The positive projection of the plurality of first auxiliary semiconductor blocks 201 on the substrate may be located between the active layer T40 of the first control transistor T4 and the active layer T60 of the third control transistor T6. The positive projection of at least one first auxiliary semiconductor block 201 on the substrate may be a rectangle. The plurality of first auxiliary semiconductor blocks 201 may be arranged in two columns, one column including two first auxiliary semiconductor blocks 201, and the other column including three first auxiliary semiconductor blocks 201.

[0122] In some examples, the orthographic projection of the active layer T30 of the input transistor T3 on the substrate may be a dumbbell-shaped extending along the second direction D2. The orthographic projection of the active layer T40 of the first control transistor T4 on the substrate may be a dumbbell-shaped extending along the second direction D2. The orthographic projection of the active layer T60 of the third control transistor T6 on the substrate may be a strip-shaped extending along the first direction D1.

[0123] This example can effectively utilize the arrangement space and reduce the space waste of the display substrate by reasonably arranging the positions of the active layers of the plurality of first-type transistors.

[0124] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate having the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer.

[0125] Fig. 8A for Figure 6 Schematic diagram of a display substrate after forming a first conductive layer. Figure 8B for Fig. 8A Schematic diagram of the first conductive layer in FIG. Fig. 8A and Figure 8B As shown, the first conductive layer of the display substrate may include: gates of multiple first-type transistors of the shift register circuit (for example, including: gate T11 of the first output transistor T1, gate T21 of the second output transistor T2, gate T31 of the input transistor T3, gate T41 of the first control transistor T4, gate T61 of the third control transistor T6), and first electrodes of multiple capacitors of the shift register circuit (for example, including: first electrode C1-1 of the first capacitor C1, first electrode C2-1 of the second capacitor C2), and multiple transfer electrodes (for example, including first transfer electrode 211 and second transfer electrode 212).

[0126] In some examples, the gate T11 of the first input transistor T1 may include: a first gate bar T11-1, a second gate bar T11-2, a third gate bar T11-3, and a fourth gate bar T11-4. The first gate bar T11-1, the second gate bar T11-2, the third gate bar T11-3, and the fourth gate bar T11-4 may all extend along the first direction D1 and be arranged in sequence along the second direction D2. The lengths of the first gate bar T11-1 to the fourth gate bar T11-4 along the first direction D1 may be the same. The gate T11 of the first transistor T1 and the first electrode C1-1 of the first capacitor C1 may be an integral structure.

[0127] In some examples, the gate T21 of the second output transistor T2 may include: a fifth gate bar T21-1, a sixth gate bar T21-2, and a seventh gate bar T21-3. The fifth gate bar T21-1, the sixth gate bar T21-2, and the seventh gate bar T21-3 may all extend along the first direction D1 and be arranged in sequence along the second direction D2. The fifth gate bar T21-1 may be adjacent to the fourth gate bar T11-4 in the second direction D2. The lengths of the fifth gate bar T21-1, the sixth gate bar T21-2, and the seventh gate bar T21-3 along the first direction D1 may be the same and greater than the length of the first gate bar T11-1 along the first direction D1. The fifth gate bar T21-1, the sixth gate bar T21-2, and the seventh gate bar T21-3 may be an integral structure with the first electrode C2-1 of the second capacitor C2.

[0128] In some examples, the orthographic projection of the gate T31 of the input transistor T3 on the substrate may be a strip extending along the first direction D1. The orthographic projection of the gate T41 of the first control transistor T4 on the substrate may be a strip extending along the first direction D1. The orthographic projection of the gate T61 of the third control transistor T6 on the substrate may be a strip extending along the second direction D2. The gate T31 of the input transistor T3 may be located on a side of the gate T61 of the third control transistor T6 that is away from the first electrode C1-1 of the first capacitor C1 in the first direction D1. The gate T41 of the first control transistor T4 is adjacent to the first electrode C2-1 of the second capacitor C2 in the first direction D1.

[0129] In some examples, the width-to-length ratio of the third control transistor T6 may be W6 / H6, which may be greater than 1. For example, the width-to-length ratio of the third control transistor T6 may be approximately 8 / 4 or 10 / 4. In this example, the width-to-length ratio of the third control transistor is set larger, which can ensure that the signal is better transmitted to the first output transistor T1 and the second output transistor T2, and at the same time, the characteristic drift of the third control transistor T6 can be reduced.

[0130] In some examples, the width-to-length ratio of the first output transistor T1 and the width-to-length ratio of the second output transistor T2 can be greater than the width-to-length ratio of the other first-type transistors. For example, the width-to-length ratio of the first output transistor T1 and the second output transistor T2 can be about 150 / 3. The configuration of this example can ensure stable output.

[0131] In some examples, the first switching electrode 211 is connected to the side of the first electrode C1-1 of the first capacitor C1 facing the gate T61 of the third control transistor T6. The first switching electrode 211 and the first electrode C1-1 of the first capacitor C1 are an integral structure. The second switching electrode 212 is connected to the side of the first electrode C2-1 of the second capacitor C2 facing the gate T41 of the first control transistor T4. The second switching electrode 212 and the first electrode C2-1 of the second capacitor C2 are an integral structure.

[0132] In some examples, a maximum length W1 of the first electrode C1-1 of the first capacitor C1 along the first direction D1 may be the same as a maximum length W2 of the first electrode C2-1 of the second capacitor C2 along the first direction D1. A maximum length H1 of the first electrode C1-1 of the first capacitor C1 along the second direction D2 may be greater than a maximum length H2 of the first electrode C2-1 of the second capacitor C2 along the second direction D2.

[0133] In this example, the gate T61 of the third control transistor T6 of the shift register circuit extends along the second direction D2, and the gates of the other first type transistors extend along the first direction D1, which can reduce wiring space and help optimize the spatial layout of the overall circuit.

[0134] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer.

[0135] Fig. 9A for Figure 6 Schematic diagram of a display substrate after a second conductive layer is formed. Fig. 9B for Fig. 9A Schematic diagram of the second conductive layer in FIG. Fig. 9A and Fig. 9B As shown, the second conductive layer of the display substrate may include: second electrodes of multiple capacitors of the shift register circuit (for example, including: the second electrode C1-2 of the first capacitor C1, the second electrode C2-2 of the second capacitor C2), the bottom gate of the second type transistor (for example, including the bottom gate T52 of the second control transistor T5), and an output electrode (for example, the output electrode 22).

[0136] In some examples, the second electrode C1-2 of the first capacitor C1 and the second electrode C2-2 of the second capacitor C2 may be arranged sequentially along the second direction D2. The orthographic projection of the second electrode C1-2 of the first capacitor C1 on the substrate may be located within the orthographic projection range of the first electrode C1-1 of the first capacitor C1 on the substrate. The orthographic projection of the second electrode C2-2 of the second capacitor C2 on the substrate may be located within the orthographic projection range of the first electrode C2-1 of the second capacitor C2 on the substrate.

[0137] In some examples, the maximum length W3 of the second electrode C1-2 of the first capacitor C1 along the first direction D1 may be greater than or equal to the maximum length W4 of the second electrode C2-2 of the second capacitor C2 along the first direction D1. The maximum length H3 of the second electrode C1-2 of the first capacitor C1 along the second direction D2 may be greater than the maximum length H4 of the second electrode C2-2 of the second capacitor C2 along the second direction D2. For example, the capacitance value of the first capacitor C1 may be greater than the capacitance value of the second capacitor C2. For example, the ratio of the capacitance value of the first capacitor C1 to the capacitance value of the second capacitor C2 may be greater than or equal to 2, for example, the ratio range may be 2 to 4. The capacitance value of the first capacitor C1 may be 500fF to 1400fF, and the capacitance value of the second capacitor C2 may be 200fF to 700fF. The setting method of this example can be conducive to stabilizing the output by pulling down the gate of the first output transistor through the first capacitor coupling when outputting a low-level signal to output a low-level third voltage signal.

[0138] In some examples, the orthographic projection of the bottom gate T52 of the second control transistor T5 on the substrate may be a strip extending along the first direction D1. The bottom gate T52 of the second control transistor T5 may be adjacent to the second electrode C1-2 of the first capacitor C1 along the first direction D1, and may be located between the first control transistor T4 and the third control transistor T6 along the second direction D2. The orthographic projection of the bottom gate T52 of the second control transistor T5 on the substrate may not overlap with the orthographic projection of the plurality of first auxiliary semiconductor blocks 201 on the substrate. The plurality of first auxiliary semiconductor blocks 201 may be arranged around the bottom gate T52 of the second control transistor T5.

[0139] In some examples, the output electrode 22 may be adjacent to the second output transistor T2 in the first direction D1 and located on a side of the second output transistor T2 away from the second capacitor C2 .

[0140] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate forming the aforementioned structure, and the second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include an oxide, such as indium gallium zinc oxide (IGZO).

[0141] Fig. 10A for Figure 6 Schematic diagram of a display substrate after forming a second semiconductor layer. Fig. 10B for Fig. 10A Schematic diagram of the second semiconductor layer in FIG. Fig. 10A and Fig. 10B As shown, the second semiconductor layer of the display substrate may include: an active layer of the second type transistor of the shift register circuit (eg, an active layer T50 including the second control transistor T5 ), and a plurality of second auxiliary semiconductor blocks 202 .

[0142] In some examples, the orthographic projection of the active layer T50 of the second control transistor T5 on the substrate may be a strip extending along the second direction D2. The orthographic projection of the active layer T50 of the second control transistor T5 on the substrate may be located between the active layer T40 of the first control transistor T4 and the active layer T60 of the third control transistor T6, and partially overlap with the orthographic projection of the bottom gate T52 of the second control transistor T5 on the substrate. For example, the active layer T50 of the second control transistor T5 may be aligned with the gate T61 of the third control transistor T6 along the second direction D2.

[0143] In some examples, the orthographic projection of a single second auxiliary semiconductor block 202 on the substrate may be a rectangle, such as a rounded rectangle. The orthographic projections of multiple second auxiliary semiconductor blocks 202 on the substrate may be arranged around the active layer T50 of the second control transistor T5. The orthographic projections of the multiple second auxiliary semiconductor blocks 202 on the substrate may not overlap with the orthographic projections of the multiple first auxiliary semiconductor blocks 201 on the substrate, and are located at the periphery of the multiple first auxiliary semiconductor blocks 201 away from the active layer T50 of the second control transistor T5. The orthographic projection of the active layer T50 of the second control transistor T5 on the substrate does not overlap with the orthographic projections of the multiple first auxiliary semiconductor blocks 201 and the multiple second auxiliary semiconductor blocks 202 on the substrate.

[0144] In this example, by providing a plurality of second auxiliary semiconductor blocks, it is advantageous to ensure that the width-to-length ratio of the second control transistor meets the design value and ensures uniformity.

[0145] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer.

[0146] Fig.11 for Figure 6 Schematic diagram of a display substrate after forming a third conductive layer. In some examples, such as Fig.11 As shown, the third conductive layer of the display substrate may include: a gate of a second type transistor of the shift register circuit (eg, including a gate T51 of the second control transistor T5).

[0147] In some examples, the orthographic projection of the gate T51 of the second control transistor T5 on the substrate may be a strip extending along the first direction D1. The orthographic projection of the gate T51 of the second control transistor T5 on the substrate may be located within the orthographic projection range of the bottom gate T52 on the substrate. The maximum length of the gate T51 of the second control transistor T5 along the first direction D1 may be less than the maximum length of the bottom gate T52 along the first direction D1.

[0148] In some examples, the width-to-length ratio of the second control transistor T5 may be W5 / L5. W5 may be greater than L5. The width-to-length ratio of the second control transistor T5 may be greater than 1, such as approximately 10 / 8 or 12 / 8. In this example, the width-to-length ratio of the second control transistor is set larger to ensure response speed.

[0149] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer.

[0150] Fig.12 for Figure 6 Schematic diagram of a display substrate after forming a fourth insulating layer in FIG. Fig.12 As shown, a plurality of vias are provided on the fourth insulating layer. Among them, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the first via V1 to the twenty-third via V23 are removed, exposing a portion of the surface of the first semiconductor layer; the fourth insulating layer, the third insulating layer and the second insulating layer in the thirty-first via V31 to the thirty-fifth via V35 are removed, exposing a portion of the surface of the first conductive layer; the fourth insulating layer, the third insulating layer and the second insulating layer in the thirty-sixth via V36 to the thirty-ninth via V39 are removed, exposing a portion of the surface of the second conductive layer; the fourth insulating layer and the third insulating layer in the forty-first via V41 and the forty-second via V42 are removed, exposing a portion of the surface of the second semiconductor layer; the fourth insulating layer in the forty-third via V43 is removed, exposing a portion of the surface of the third conductive layer.

[0151] In some examples, the twenty-third via hole V23 may expose a portion of the surface of the first auxiliary semiconductor block 201. In this example, by providing an auxiliary via hole (i.e., the twenty-third via hole) at a position corresponding to the first auxiliary semiconductor block, the inorganic insulating layer (e.g., including the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer) in the auxiliary via hole may be removed, which may be beneficial to ensure the uniformity of the film layer near the second control transistor and ensure that the characteristics of the second control transistor will not be significantly negatively biased.

[0152] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned structure, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the fourth insulating layer.

[0153] Fig.13 for Figure 6 Schematic diagram of the fourth conductive layer in FIG. In some examples, such as Figure 6 and Fig.13 As shown, the fourth conductive layer of the display substrate may include: a plurality of connecting electrodes (for example, including the first connecting electrode 241 to the ninth connecting electrode 249), a plurality of signal lines (for example, including the first first voltage line VH1, the start signal line STV, the first sub-line CLK-1 of the first clock signal line CLK, and the third sub-line CLB-1 of the second clock signal line CLB).

[0154] In some examples, the first connection electrode 241 can be used as an input terminal and connected to the first region of the active layer T30 of the input transistor T3 through the first via hole V1. For example, the first connection electrode 241 and the eighth connection electrode of the previous stage shift register circuit can be an integrated structure to achieve connection with the output terminal of the previous stage shift register circuit.

[0155] In some examples, the orthographic projection of the second connection electrode 242 on the substrate may be a strip extending along the first direction D1. The second connection electrode 242 may be connected to the second region of the active layer T60 of the third control transistor T6 through the fourth via hole V4, and may also be connected to the first transfer electrode 211 through the thirty-third via hole V33, thereby achieving electrical connection with the first electrode C1-1 of the first capacitor C1.

[0156] In some examples, the positive projection of the third connection electrode 243 on the substrate may be an E-shaped. The third connection electrode 243 may be adjacent to the first first voltage line VH1 in the first direction D1. The third connection electrode 243 may be connected to the second region of the active layer T30 of the input transistor T3 through the second via V2, and may also be connected to the first region of the active layer T60 of the third control transistor T6 through the third via V3, and may also be connected to the gate T41 of the first control transistor T4 through the thirty-fifth via V35, and may also be connected to the bottom gate T52 of the second control transistor T5 through the thirty-sixth via V36, and may also be connected to the gate T51 of the second control transistor T5 through the forty-third via V43. The third connection electrode 243 may serve as a third node to realize the electrical connection of the input transistor T3, the first control transistor T4, the second control transistor T5, and the third control transistor T6. The positive projection of the third connection electrode 243 on the substrate may not overlap with the positive projections of the plurality of first auxiliary semiconductor blocks 201 and the plurality of second auxiliary semiconductor blocks 202 on the substrate.

[0157] In some examples, the orthographic projection of the fourth connection electrode 244 on the substrate may be T-shaped. One end of the fourth connection electrode 244 may be connected to the gate T61 of the third control transistor T6 through the thirty-second via hole V32, and the other end may be connected to the first region of the active layer T50 of the second control transistor T5 through the forty-first via hole V41. The fourth connection electrode 244 may enable the second control transistor T5 and the third control transistor T6 to be connected to the same second voltage line.

[0158] In some examples, the orthographic projection of the fifth connection electrode 245 on the substrate may be roughly T-shaped. The fifth connection electrode 245 may be connected to the second region of the active layer T40 of the first control transistor T4 through the fifth via hole V5, and may also be connected to the second region of the active layer T50 of the second control transistor T5 through the forty-second via hole V42, and may also be connected to the second transfer electrode 212 through the thirty-fourth via hole V34, thereby achieving electrical connection with the first electrode C201 of the second capacitor C2 and the gate of the second output transistor T2. The fifth connection electrode 245 may serve as a second node to achieve electrical connection between the second control transistor T5, the first control transistor T4, the second capacitor C2, and the second output transistor T2.

[0159] In some examples, the orthographic projection of the sixth connection electrode 246 on the substrate may be substantially C-shaped. The sixth connection electrode 246 may be connected to the active layer T10-1 of the first output transistor T1 through a plurality of (e.g., three) ninth via holes V9 arranged side by side and a plurality of (e.g., three) thirteenth via holes V13 arranged side by side, and may also be connected to the active layer T10-2 of the first output transistor T1 through a plurality of (e.g., three) tenth via holes V10 arranged side by side and a plurality of (e.g., three) fourteenth via holes V14 arranged side by side.

[0160] In this example, “arranged side by side” may mean arranged in sequence along a first direction X, and “arranged vertically” may mean arranged in sequence along a second direction Y.

[0161] In some examples, the orthographic projection of the seventh connection electrode 247 on the substrate may be substantially C-shaped. The seventh connection electrode 247 may be connected to the active layer T20-1 of the second output transistor T2 through a plurality of (e.g., four) seventeenth via holes V17 arranged side by side and a plurality of (e.g., four) twenty-first via holes V21 arranged side by side, and may also be connected to the active layer T20-2 of the second output transistor T2 through a plurality of (e.g., four) eighteenth via holes V18 arranged side by side and a plurality of (e.g., four) twenty-second via holes V22 arranged side by side.

[0162] In some examples, the orthographic projection of the eighth connection electrode 248 on the substrate may be roughly comb-shaped. The eighth connection electrode 248 may be connected to the second electrode C1-2 of the first capacitor C1 through a plurality of thirty-seventh vias V37 arranged in an array, and may also be connected to the active layer T10-1 of the first output transistor T1 through a plurality of (e.g., three) seventh vias V7 arranged side by side and a plurality of (e.g., three) eleventh vias V11 arranged side by side, and may also be connected to the active layer T10-1 of the first output transistor T1 through a plurality of (e.g., three) eighth vias V8 arranged side by side and a plurality of (e.g., three) twelfth vias V12 arranged side by side. 10-2 is connected, and it can also be connected to the active layer T20-1 of the second output transistor T2 through a plurality of (for example, four) fifteenth via holes V15 arranged side by side and a plurality of (for example, four) nineteenth via holes V19 arranged side by side, and it can also be connected to the active layer T20-2 of the second output transistor T2 through a plurality of (for example, four) sixteenth via holes V16 arranged side by side and a plurality of (for example, four) twentieth via holes V20 arranged side by side, and it can also be connected to the output electrode 22 through two thirty-ninth via holes V29 arranged in a vertical row.

[0163] In some examples, the orthographic projection of the ninth connection electrode 249 on the substrate may be substantially T-shaped. The ninth connection electrode may be connected to the second electrode C2-2 of the second capacitor C2 through a plurality of thirty-eighth via holes V38 arranged in an array, and may also be connected to the first region of the active layer T40 of the first control transistor T4 through a sixth via hole V6. The ninth connection electrode 249 and the first first voltage line VH1 may be an integral structure.

[0164] In some examples, the start signal line STV, the first sub-line CLK-1 of the first clock signal line CLK, the third sub-line CLB-1 of the second clock signal line CLB, and the first first voltage line VH1 can be arranged in sequence along the first direction D1 and located on a side of the input control circuit away from the output circuit. The first sub-line CLK-1 of the first clock signal line CLK can be connected to the gate T31 of the input transistor T3 through two thirty-first vias V31 arranged vertically.

[0165] In some examples, the line width (e.g., the length along the first direction D1) of the first first voltage line VH1 may be greater than the line width of the start signal line STV. The line width of the first sub-line CLK-1 of the first clock signal line CLK and the line width of the third sub-line CLB-1 of the second clock signal line CLB may be the same and greater than the line width of the first first voltage line VH1.

[0166] (9) Forming a fifth insulating layer. In some examples, a fifth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer.

[0167] Fig.14 for Figure 5 Schematic diagram of a display substrate after a fifth insulating layer is formed in FIG. Figure 6 and Fig.14 As shown, the fifth insulating layer is provided with a plurality of vias and a plurality of grooves. For example, the plurality of vias may include: the fifty-first via V51 to the fifty-third via V53, and the plurality of grooves may include a first groove V61 and a second groove V62. The fifth insulating layer in the fifty-first via V51 to the fifty-third via V53, the first groove V61 and the second groove V62 may be removed to expose a portion of the surface of the fourth conductive layer.

[0168] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the fifth insulating layer.

[0169] Fig.15 for Figure 5 Schematic diagram of the fifth conductive layer in FIG. Figure 5 and Fig.15 As shown, the fifth conductive layer of the display substrate may include: multiple signal lines (for example, including: a second first voltage line VH2, a second voltage line VL1, a third voltage line VL2, a second sub-line CLK-2 of the first clock signal line CLK, and a fourth sub-line CLB-2 of the second clock signal line CLB).

[0170] In some examples, the fourth sub-route CLB-2 of the second clock signal line CLB, the second sub-route CLK-2 of the first clock signal line CLK, the second voltage line VL1, the third voltage line VL2, and the second first voltage line VH2 may be sequentially arranged along the first direction D1.

[0171] In some examples, the fourth sub-route CLB-2 of the second clock signal line CLB can be connected to the third sub-route CLB-1 of the second clock signal line CLB through the first groove V61. The orthographic projection of the fourth sub-route CLB-2 of the second clock signal line CLB on the substrate can overlap with the orthographic projection of the third sub-route CLB-1 of the second clock signal line CLB on the substrate. The second sub-route CLK-2 of the first clock signal line CLK can be connected to the first sub-route CLK-1 of the first clock signal line CLK through the second groove V62. The orthographic projection of the second sub-route CLK-2 of the first clock signal line CLK on the substrate can overlap with the orthographic projection of the first sub-route CLK-1 of the first clock signal line CLK on the substrate. The first clock signal line and the second clock signal line of this example use double-layer routing to reduce the load.

[0172] In some examples, the second voltage line VL1 can be connected to the fourth connection electrode 244 through the fifty-first via hole V51 to achieve electrical connection with the third control transistor T6 and the second control transistor T5. The third voltage line VL2 can be connected to the sixth connection electrode 246 through three fifty-second via holes V52 arranged vertically to achieve electrical connection with the first output transistor T1. The second first voltage line VH2 can be connected to the seventh connection electrode 247 through three fifty-third via holes V53 arranged side by side to achieve electrical connection with the second output transistor T2.

[0173] In some examples, the orthographic projection of the second voltage line VL1 on the substrate may overlap with the orthographic projection of the input control circuit 11 located in the first region S1 on the substrate. The orthographic projection of the second voltage line VL1 on the substrate may cover the orthographic projection of the active layer T50 of the second control transistor T5 on the substrate, thereby preventing the external ambient light from affecting the characteristics of the second control transistor T5.

[0174] In some examples, the orthographic projections of the third voltage line VL2 and the second first voltage line VH2 on the substrate may overlap with the orthographic projections of the output circuit 12 located in the second region S2 on the substrate, and do not overlap with the orthographic projections of the input control circuit 11 on the substrate. The orthographic projection of the third voltage line VL2 on the substrate may overlap with the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate. The orthographic projection of the second first voltage line VH2 on the substrate overlaps with the orthographic projections of the first output transistor T1 and the second output transistor T2 on the substrate.

[0175] In some examples, the line width (e.g., the length along the first direction D1) of the second first voltage line VH2 may be greater than the line width of the third voltage line VL2, and the line width of the third voltage line VL2 may be greater than the line width of the second voltage line VL1. For example, the line widths of the second first voltage line VH2 and the third voltage line VL2 may range from 20 microns to 50 microns. In this example, by increasing the line widths of the third voltage line VL2 and the second first voltage line VH2, the capacitance may be reduced.

[0176] In this example, by setting the second first voltage line VH2, the second voltage line VL1 and the third voltage line VL2 in the fifth conductive layer, that is, on the side of the gate drive circuit away from the substrate, and by reasonably setting the vertical routing, the layout space can be optimized, the layout difficulty can be reduced, and the capacitance caused by node overlap and the unstable output signal can be improved.

[0177] In some examples, after forming the fifth conductive layer, a sixth insulating layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer and an encapsulation layer pattern may be sequentially formed in the display area. In some examples, an anode film is deposited on a substrate in the display area where the aforementioned pattern is formed, and the anode film is patterned by a patterning process to form an anode pattern on the sixth insulating layer. Then, a pixel definition film is coated on the substrate where the aforementioned pattern is formed, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed by masking, exposure and development processes. The pixel definition layer is formed in each sub-pixel in the display area, and the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode. Subsequently, an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode pattern, and the cathode is respectively connected to the organic light-emitting layer and the second power line. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material. In some possible implementations, the cathode can be connected to the power connection line in a variety of ways, such as laser drilling.

[0178] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The fifth insulating layer and the sixth insulating layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. However, this embodiment is not limited to this.

[0179] The structure and preparation process shown in this example are only an exemplary description. In some examples, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, can be well compatible with existing preparation processes, and has simple process implementation, easy implementation, high production efficiency, low production cost, and high yield rate.

[0180] The display substrate of this example can reduce the influence of the signal coupling jump of the input control circuit 11 on the output signal by arranging the input control circuit 11 and the output circuit 12 of the shift register circuit separately, thereby stabilizing the signal output; and can save the space occupied by the shift register circuit, which is conducive to realizing a display substrate with a narrow frame. The orthographic projection of the second first voltage line VH2 and the third voltage line VL2 on the substrate does not overlap with the orthographic projection of the input control circuit 11 on the substrate, which can reduce the influence of the coupling jump of the input control circuit on the DC signal.

[0181] In the display substrate of this example, the second voltage line VL1 connected to the third control transistor T6 is located in the fifth conductive layer, and its orthographic projection on the substrate can cover the orthographic projection of the active layer of the second control transistor T5 on the substrate, so as to shield the active layer of the second control transistor T5, prevent the influence of external ambient light on the transistor characteristics, and save lateral arrangement space.

[0182] In the display substrate of this example, the width-to-length ratio of the second control transistor T5 is set relatively large, which can ensure the response speed. The width-to-length ratio of the third control transistor T6 is set relatively large, which can ensure that the signal is well transmitted to the first output transistor T1 and the second output transistor T2, and reduce the characteristic drift of the third control transistor T6. The width-to-length ratio of the first output transistor T1 and the second output transistor T2 is set relatively large, which can ensure stable output.

[0183] In the display substrate of this example, the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2, which can help to pull down the gate potential of the first output transistor T1 through coupling through the first capacitor C1, so that the output terminal outputs a low-level signal.

[0184] In the display substrate of this example, a plurality of first auxiliary semiconductor blocks 201 and a plurality of second auxiliary semiconductor blocks 202 are arranged around the second control transistor T5, which can ensure the uniformity of the surrounding environment of the second control transistor T5, ensure that the transistor characteristics will not be significantly negatively biased, and make the width-to-length ratio of the second control transistor T5 meet the design value.

[0185] Fig.16 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure. In some examples, such as Fig.16 As shown, the shift register circuit of this example may include: an input control circuit 11 and an output circuit 12. The input control circuit 11 may include: an input transistor T3, a first control transistor T4, a second control transistor T5 and a third control transistor T6. Among them, the gate of the second control transistor T5 is connected to the third node N3, the first electrode is connected to the third voltage terminal VGL2, and the second electrode is connected to the second node N2. The fourth voltage terminal of this example is connected to the third voltage terminal VGL2. The rest of the description of the shift register circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0186] Fig.17A FIG. 4 is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig. 17B for Fig.17A The schematic diagram of the shift register circuit in FIG. 1 is a top view of the shift register circuit in FIG. Fig.16 In some examples, such as Fig.17A and Fig. 17B As shown, the maximum length L1 of the input control circuit 11 along the first direction D1 can be less than the maximum length L2 of the output circuit 12 along the first direction D1. The fourth connection electrode 244 located in the fourth conductive layer can be connected to the gate of the third control transistor T6 and electrically connected to the second voltage line VGL1 located in the fifth conductive layer. The fourth conductive layer of the display substrate also includes: a tenth connection electrode 250. The orthographic projection of the tenth connection electrode 250 on the substrate is a strip extending along the first direction D1. The tenth connection electrode 250 and the sixth connection electrode 246 are an integral structure. The tenth connection electrode 250 is connected to the first area of ​​the active layer of the second control transistor T5, so that the second control transistor T5 is connected to the third voltage line VGL2 through the sixth connection electrode 246. The remaining structure of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0187] Fig.18is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure. In some examples, such as Fig.18 As shown, the shift register circuit of this example may include: an input control circuit 11 and an output circuit 12. The input control circuit 11 may include: an input transistor T3, a first control transistor T4, a second control transistor T5 and a third control transistor T6. Among them, the gate of the second control transistor T5 is connected to the first node N1, the first electrode is connected to the second voltage terminal VGL1, and the second electrode is connected to the second node N2. The fourth voltage terminal of this example is connected to the second voltage terminal VGL1. The rest of the description of the shift register circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0188] Fig.19A FIG. 4 is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig.19B for Fig.19A The schematic diagram of the shift register circuit in FIG. 1 is a top view of the shift register circuit in FIG. Fig.18 In some examples, such as Fig.19A and Fig.19B As shown, the maximum length L1 of the input control circuit 11 along the first direction D1 can be less than the maximum length L2 of the output circuit 12 along the first direction D1. The orthographic projections of the third connection electrode 243 and the second connection electrode 242 located in the fourth conductive layer on the substrate can be roughly C-shaped. The notch of the second connection electrode 242 can face the notch of the third connection electrode 243. The second connection electrode 242 can be connected to the second area of ​​the active layer of the third control transistor T6, the first electrode of the first capacitor C1, and the bottom gate and gate of the second control transistor T5. The third connection electrode 243 can be connected to the second area of ​​the active layer of the input transistor T3, the first area of ​​the active layer of the third control transistor T6, and the gate of the first control transistor T4. The remaining structure of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0189] Fig. 20 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure. In some examples, such as Fig. 20As shown, the shift register circuit of this example may include: an input control circuit 11 and an output circuit 12. The input control circuit 11 may include: an input transistor T3, a first control transistor T4, a second control transistor T5 and a third control transistor T6. Among them, the gate of the second control transistor T5 is connected to the first node N1, the first electrode is connected to the second voltage terminal VGL1, and the second electrode is connected to the second node N2. The gate of the first control transistor T1 is connected to the first node N1, the first electrode is connected to the first voltage terminal VGH, and the second electrode is connected to the second node N2. The fourth voltage terminal of this example is connected to the second voltage terminal VGL1. The rest of the description of the shift register circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0190] Fig.21A FIG. 4 is another partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig. 21B for Fig.21A The schematic diagram of the top view of the shift register circuit in FIG. The circuit diagram of the shift register circuit in this example can be as follows Fig. 20 In some examples, such as Fig.21A and Fig. 21B As shown, the positive projection of the third connection electrode 243 located in the fourth conductive layer on the substrate can be a rectangle extending along the first direction D1. The third connection electrode 243 can be connected to the second area of ​​the active layer of the input transistor T3 and the first area of ​​the active layer of the third control transistor T6. The positive projection of the second connection electrode 242 located in the fourth conductive layer on the substrate can be roughly a bent shape extending along the second direction D2. The second connection electrode 242 can be connected to the second pole of the third control transistor T6, the first electrode of the first capacitor C1, the gate of the first control transistor T1, and the bottom gate and gate of the second control transistor T5. The second connection electrode 242 can be used as a first node to realize the electrical connection of the first control transistor T1, the second control transistor T5, the third control transistor T6, the first capacitor C1 and the first output transistor T1. The remaining structure of the display substrate of this example can refer to the description of the aforementioned embodiment, so it is not repeated here.

[0191] Fig. 22 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure. In some examples, such as Fig. 22As shown, the shift register circuit of this example may include: an input control circuit 11 and an output circuit 12. The input control circuit 11 may include: an input transistor T3, a first control transistor T4, a second control transistor T5 and a third control transistor T6. Among them, the gate of the second control transistor T5 is connected to the first node N1, the first electrode is connected to the third voltage terminal VGL2, and the second electrode is connected to the second node N2. The fourth voltage terminal of this example is connected to the third voltage terminal VGL2. The rest of the description of the shift register circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0192] Fig.23 FIG. 1 is another schematic top view of a shift register circuit according to at least one embodiment of the present disclosure. Fig. 22 In some examples, such as Fig.23 As shown, the orthographic projections of the second connection electrode 242 and the third connection electrode 243 located in the fourth conductive layer on the substrate may be approximately C-shaped, and the notch of the second connection electrode 242 faces the notch of the third connection electrode 243. The second connection electrode 242 may be connected to the second region of the active layer of the third control transistor T6, the first electrode of the first capacitor C1, and the bottom gate and gate of the second control transistor T5. The third connection electrode 243 may be connected to the second region of the active layer of the input transistor T3, the first region of the active layer of the third control transistor T6, and the gate of the first control transistor T4. The orthographic projection of the fourth connection electrode 244 located in the fourth conductive layer on the substrate may be approximately a rectangle extending along the first direction D1. The fourth connection electrode 244 may be connected to the gate of the third control transistor T6. The tenth connection electrode 250 and the sixth connection electrode 246 located in the fourth conductive layer may be an integral structure. The orthographic projection of the tenth connection electrode 250 on the substrate may be a fold line extending along the first direction D1. The tenth connection electrode 250 may be connected to the first region of the active layer of the second control transistor T5. The remaining structures of the display substrate of this example can refer to the description of the aforementioned embodiment, so they will not be described again here.

[0193] Fig.24 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure. In some examples, such as Fig.24As shown, the shift register circuit of this example may include: an input control circuit 11 and an output circuit 12. The input control circuit 11 may include: an input transistor T3, a first control transistor T4, a second control transistor T5 and a third control transistor T6. Among them, the gate of the second control transistor T5 is connected to the first node N1, the first electrode is connected to the third voltage terminal VGL2, and the second electrode is connected to the second node N2. The gate of the first control transistor T1 is connected to the first node N1, the first electrode is connected to the first voltage terminal VGH, and the second electrode is connected to the second node N2. The fourth voltage terminal of this example is connected to the third voltage terminal VGL2. The rest of the description of the shift register circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0194] Fig.25 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.25 As shown, this embodiment provides a display device 91, including: a display substrate 910. The display substrate 910 is the display substrate provided in the above embodiment. Among them, the display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be: an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. However, this embodiment is not limited to this.

[0195] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0196] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate and a gate driving circuit disposed on the substrate, wherein the gate driving circuit includes a plurality of shift register circuits, and the shift register circuit includes: an input control circuit and an output circuit; The input control circuit is connected to the first node, the second node, the input terminal, the clock terminal, the first voltage terminal, the second voltage terminal and the fourth voltage terminal, and is configured to control the potentials of the first node and the second node under the control of the clock terminal and the input terminal; The output circuit is connected to the first node, the second node, the output terminal, the first voltage terminal and the third voltage terminal, and is configured to transmit a signal provided by the first voltage terminal or the third voltage terminal to the output terminal under the control of the first node and the second node; The input control circuit is located at one side of the output circuit along a first direction, and a maximum length of an orthographic projection of the input control circuit on the substrate along the first direction is smaller than a maximum length of an orthographic projection of the output circuit on the substrate along the first direction.

2. The display substrate according to claim 1, characterized in that: The input control circuit comprises: an input subcircuit, a first control subcircuit, a second control subcircuit and a third control subcircuit; The input subcircuit is connected to the input terminal, the clock terminal and the third node, and is configured to transmit the signal of the input terminal to the third node under the control of the clock terminal; The first control subcircuit is connected to the third node, the second node and the first voltage terminal, and is configured to transmit the signal provided by the first voltage terminal to the second node under the control of the third node; or the first control subcircuit is connected to the first node, the second node and the first voltage terminal, and is configured to transmit the signal provided by the first voltage terminal to the second node under the control of the first node; The second control subcircuit is connected to the third node, the second node and the fourth voltage terminal, and is configured to transmit the signal provided by the fourth voltage terminal to the second node under the control of the third node; or the second control subcircuit is connected to the first node, the second node and the fourth voltage terminal, and is configured to transmit the signal provided by the fourth voltage terminal to the second node under the control of the first node; The third control subcircuit is connected to the third node, the first node and the second voltage terminal, and is configured to conduct the third node and the first node under the control of the second voltage terminal.

3. The display substrate according to claim 2, characterized in that: The fourth voltage terminal is connected to the second voltage terminal, or the fourth voltage terminal is connected to the third voltage terminal.

4. The display substrate according to claim 3, characterized in that: The voltage value of the first voltage signal transmitted by the first voltage terminal is greater than the voltage value of the second voltage signal transmitted by the second voltage terminal, and the voltage value of the second voltage signal transmitted by the second voltage terminal is greater than the voltage value of the third voltage signal transmitted by the third voltage terminal; The clock signal provided by the clock terminal includes a first clock voltage value and a second clock voltage value, the first clock voltage value is greater than the second clock voltage value, and the voltage value of the third voltage signal is greater than the second clock voltage value of the clock signal.

5. The display substrate according to any one of claims 2 to 4, characterized in that: The first control subcircuit includes: a first control transistor; the second control subcircuit includes: a second control transistor; the third control subcircuit includes: a third control transistor; the transistor type of the second control transistor is different from the transistor type of the first control transistor, and the transistor type of the third control transistor is the same as that of the first control transistor.

6. The display substrate according to claim 5, characterized in that: The second control transistor is located between the third control transistor and the first control transistor along a second direction, and the second direction intersects the first direction; The active layer of the third control transistor extends along the first direction, and the active layer of the first control transistor and the active layer of the second control transistor both extend along the second direction.

7. The display substrate according to claim 5, characterized in that: The second voltage terminal is connected to a second voltage line, the second voltage line is located on a side of the second control transistor away from the substrate, and an orthographic projection of the second voltage line on the substrate covers an orthographic projection of an active layer of the second control transistor on the substrate.

8. The display substrate according to claim 5, characterized in that: The width-to-length ratio of the third control transistor is greater than the width-to-length ratio of the second control transistor, and the width-to-length ratio of the second control transistor is greater than 1.

9. The display substrate according to claim 5, characterized in that: The first control transistor and the third control transistor are P-type transistors, and the second control transistor is an N-type transistor.

10. The display substrate according to claim 5, characterized in that: The display substrate also includes: an inorganic insulating layer and a plurality of first auxiliary semiconductor blocks, wherein the plurality of first auxiliary semiconductor blocks are arranged on the same layer as the active layer of the first control transistor and the third control transistor, the inorganic insulating layer is located on a side of the plurality of first auxiliary semiconductor blocks away from the substrate, and the plurality of first auxiliary semiconductor blocks are located around the active layer of the second control transistor; the inorganic insulating layer is provided with a plurality of auxiliary vias, and the orthographic projection of an auxiliary via on the substrate is located within the orthographic projection range of a first auxiliary semiconductor block on the substrate.

11. The display substrate according to claim 10, characterized in that: The display substrate also includes: a plurality of second auxiliary semiconductor blocks, which are arranged on the same layer as the active layer of the second control transistor, and are located around the active layer of the second control transistor, and are located at the periphery of the plurality of first auxiliary semiconductor blocks away from the active layer of the second control transistor.

12. The display substrate according to claim 5, characterized in that: The gate of the first control transistor is connected to the third node or the first node, the first electrode of the first control transistor is connected to the first voltage terminal, and the second electrode of the first control transistor is connected to the second node; The gate of the second control transistor is connected to the third node or the first node, the first electrode of the second control transistor is connected to the fourth voltage terminal, and the second electrode of the second control transistor is connected to the second node; A gate of the third control transistor is connected to the second voltage terminal, a first electrode of the third control transistor is connected to the third node, and a second electrode of the third control transistor is connected to the first node.

13. The display substrate according to claim 5, characterized in that: The input subcircuit comprises: an input transistor, a gate of the input transistor is connected to the clock terminal, a first electrode of the input transistor is connected to the input terminal, and a second electrode of the input transistor is connected to the third node; The input transistor is located on a side of the third control transistor away from the output circuit along the first direction, and an active layer of the input transistor extends along a second direction intersecting the first direction.

14. The display substrate according to claim 1, characterized in that: The output circuit comprises: a first output transistor, a second output transistor, a first capacitor and a second capacitor; The gate of the first output transistor is connected to the first node, the first electrode of the first output transistor is connected to the third voltage terminal, and the second electrode of the first output transistor is connected to the output terminal; The gate of the second output transistor is connected to the second node, the first electrode of the second output transistor is connected to the first voltage terminal, and the second electrode of the second output transistor is connected to the output terminal; A first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to the output terminal; A first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the first voltage terminal; The first output transistor and the second output transistor are arranged along a second direction, the first capacitor and the second capacitor are arranged along the second direction, the first capacitor is located along the first direction on a side of the first output transistor close to the input control circuit, the second capacitor is located along the first direction on a side of the second output transistor close to the input control circuit, and the second direction intersects with the first direction.

15. The display substrate according to claim 14, characterized in that: A ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is greater than or equal to 2.

16. The display substrate according to claim 14, characterized in that: The width-to-length ratio of the first output transistor is greater than the width-to-length ratio of the transistor included in the input control circuit, and the width-to-length ratio of the second output transistor is greater than the width-to-length ratio of the transistor included in the input control circuit.

17. The display substrate according to claim 14, characterized in that: The second voltage terminal is connected to the second voltage line, the third voltage terminal is connected to the third voltage line, the first voltage terminal connected to the second capacitor is connected to the first first voltage line, and the first voltage terminal connected to the second output transistor is connected to the second first voltage line; The third voltage line is located between the second voltage line and the second first voltage line, and the first first voltage line is located on a side of the second voltage line away from the third voltage line; The orthographic projections of the third voltage line and the second first voltage line on the substrate overlap with the orthographic projection of the output circuit on the substrate; An orthographic projection of the second voltage line on the substrate overlaps with an orthographic projection of the input control circuit on the substrate.

18. The display substrate according to claim 17, characterized in that: The line width of the third voltage line is greater than the line width of the second voltage line; the line width of the second first voltage line is greater than the line width of the first first voltage line, and greater than the line width of the third voltage line.

19. The display substrate according to claim 17, characterized in that: The second voltage line, the third voltage line and the second first voltage line are arranged in the same layer, and the conductive layer where the first first voltage line is located is located on a side of the conductive layer where the second first voltage line is located close to the substrate.

20. The display substrate according to claim 18, characterized in that The clock end is connected to the first clock signal line or the second clock signal line. The first clock signal line and the second clock signal line are located on the side of the first first voltage line away from the second voltage line. The first clock signal line and the second clock signal line are double-layer routing.

21. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 20.

Images