Electrical isolation structure, manufacturing method thereof and multi-die package structure
By forming conductive layers on the glass substrate and stacking isolation structures, the problem of insufficient isolation performance in multi-chip packaging is solved, and higher voltage resistance and lower manufacturing costs are achieved.
Patent Information
- Application Number
- CN202410902710.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-05
- Publication Date
- 2025-02-14
AI Technical Summary
In existing multi-die packages, the coupling performance of high and low voltage isolation technology is poor and the voltage resistance is unstable, making it difficult to meet the connection and isolation requirements between multiple dies.
A single-sided process is used to form a conductive layer on one surface of the glass substrate to form an isolation structure, and two isolation structures are stacked. A glass substrate is sandwiched between the two conductive layers to form an electrical isolation structure.
The voltage withstand performance and coupling performance of the electrical isolation structure are improved, the connection and isolation requirements between multiple dies are met, and the manufacturing cost of the packaging structure is reduced.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to an electrical isolation structure and a manufacturing method thereof and a multi-die packaging structure. Background Art
[0002] Multi-die packaging is an integrated circuit packaging technology in which multiple dies, each containing a specific functional module or part of the circuit, are manufactured independently and then combined together in the packaging process to form a complete chip.
[0003] In multi-die packaging, the high-voltage die needs to be isolated from the low-voltage die to improve the stability and safety of the circuit. Common high- and low-voltage isolation technologies mainly include magnetic isolation, capacitive isolation, and inductive isolation. For example, two dies made of a silicon substrate are stacked and packaged, and the two stacked dies are connected by organic materials. The conductive layers in the two dies and the organic materials form an isolator to achieve high and low voltage isolation. However, the silicon substrate located between the two conductive layers is a semiconductor material rather than an insulating material. Therefore, the coupling performance of the isolator is poor, and because the thickness uniformity of the organic material is difficult to control and holes are easily formed, the overall voltage resistance performance of the isolator and the stacked die is not stable.
[0004] Therefore, a new electrical isolation structure and a method for manufacturing a multi-die packaging structure are needed to solve the above problems. Summary of the invention
[0005] In view of the above problems, the purpose of the present disclosure is to provide an electrical isolation structure, a manufacturing method thereof and a multi-die packaging structure, which adopts a single-sided process to form a conductive layer on one surface of a glass substrate to form an isolation structure, and stacks two isolation structures. A glass substrate is sandwiched between the two conductive layers to form an electrical isolation structure, which can not only meet the connection and isolation requirements between multiple dies, but also improve the voltage resistance performance of the electrical isolation structure.
[0006] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing an electrical isolation structure is provided, comprising: forming a first isolation structure and a second isolation structure and fixing the first isolation structure and the second isolation structure together through an adhesive layer:
[0007] Wherein, forming the first isolation structure includes:
[0008] forming a first connection layer on the first surface of the first glass substrate; and
[0009] forming a first conductive layer on the first connecting layer,
[0010] Forming the second isolation structure includes:
[0011] forming a second connecting layer on the first surface of the second glass substrate; and
[0012] forming a second conductive layer on the second connecting layer,
[0013] The adhesive layer is located between the first glass substrate and the second conductive layer.
[0014] At least one of the first conductive layer and the second conductive layer forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer.
[0015] Optionally, the first glass substrate and the second glass substrate are formed based on the same glass substrate, the first connecting layer and the second connecting layer are connecting layers formed synchronously, and the first conductive layer and the second conductive layer are conductive layers formed synchronously.
[0016] Optionally, it also includes:
[0017] forming a photoresist layer on the connection layer; and
[0018] patterning the photolithography layer to form a photolithography mask to expose a portion of the connection layer,
[0019] The conductive layer is electroplated on the exposed connecting layer through the photolithography mask, thereby forming a patterned conductive layer.
[0020] Optionally, the connection layer is formed on the first surface by using a chemical metal plating process or a sputtering metal process.
[0021] The material of the connection layer includes a titanium compound.
[0022] Optionally, the method further includes: forming a metal coating layer on the patterned conductive layer through the photolithography mask.
[0023] Optionally, it also includes:
[0024] Before forming the connecting layer, forming a protective layer on the second surface of the glass substrate;
[0025] removing the photolithography mask after forming the patterned conductive layer;
[0026] removing the exposed connecting layer and the protective layer to expose the cutting portion of the glass substrate; and
[0027] The glass substrate is cut to separate the first isolation structure from the second isolation structure.
[0028] Optionally, the conductive layer is a single conductive layer or a plurality of conductive stacked layers.
[0029] Optionally, the method further includes: forming an interlayer dielectric layer and an interlayer connection layer between two adjacent conductive stacked layers.
[0030] Optionally, the method further includes: before forming the connection layer, roughening the glass substrate to enhance the adhesion of the metal and / or metal compound on the surface of the glass substrate.
[0031] According to a second aspect of an embodiment of the present disclosure, there is provided an electrical isolation structure, comprising: a first isolation structure, a second isolation structure, and an adhesive layer located between the first isolation structure and the second isolation structure.
[0032] Wherein, the first isolation structure comprises:
[0033] a first glass substrate;
[0034] A first connecting layer, located on the first glass substrate; and
[0035] a first conductive layer, located on the first connecting layer,
[0036] The second isolation structure comprises:
[0037] a second glass substrate;
[0038] a second connecting layer, located on the second glass substrate; and
[0039] a second conductive layer, located on the second connecting layer,
[0040] The adhesive layer is located between the first glass substrate and the second conductive layer, and is used to fix the first isolation structure and the second isolation structure.
[0041] At least one of the first conductive layer and the second conductive layer forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer.
[0042] Optionally, the first conductive layer is a single conductive layer or a plurality of conductive stacked layers, and the second conductive layer is a single conductive layer or a plurality of conductive stacked layers.
[0043] Optionally, the method further includes an interlayer dielectric layer and an interlayer connection layer, which are located between two adjacent conductive stacked layers.
[0044] According to a third aspect of an embodiment of the present disclosure, a multi-die packaging structure is provided, including a first die, a second die, and an electrical isolation structure formed by the manufacturing method as described above, wherein the electrical isolation structure is electrically connected to the first die and the second die respectively.
[0045] One of the above technical solutions has the following beneficial effects:
[0046] The isolation structure is made by a single-sided process. The isolation structure forms a conductive layer on one surface of a glass substrate, and then two isolation structures are stacked. A glass substrate is sandwiched between the two conductive layers to form an electrical isolation structure. Compared with the solution of stacking two tube cores made of silicon substrates, the glass substrate is hard and the thickness uniformity is easy to control, and it is not easy to have holes. The pressure resistance of the glass material can reach 35V / μm, so it can improve the coupling performance and overall pressure resistance of the electrical isolation structure. In addition, the price of glass is relatively cheap, which can reduce the manufacturing cost of the packaging structure.
[0047] In some optional embodiments, the two isolation structures are made based on the same glass substrate, and the connecting layer and the conductive layer are also completed in the same process step. The two isolation structures are separated by cutting the glass substrate and then stacked and bonded. Not only are the various indicators of the two isolation structures very similar, the yield of the electrical isolation structure is increased after the combination, but the two isolation structures are also formed simultaneously, greatly reducing the process cost.
[0048] In the multi-die packaging structure, the separately manufactured electrical isolation structure is electrically connected to the first die and the second die respectively, thereby meeting the requirements of connection and signal isolation transmission between the first die and the second die. In addition, the first die, the second die and the electrical isolation structure are manufactured separately, which reduces the manufacturing difficulty of the first die, the second die and the electrical isolation structure and improves the yield rate.
[0049] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0051] Figure 1 A schematic diagram of a multi-die packaging structure in the related art is shown;
[0052] Figure 2 A schematic structural diagram of an electrical isolation structure according to a first embodiment of the present disclosure is shown;
[0053] Figure 3 A schematic structural diagram of a multi-die packaging structure according to a first embodiment of the present disclosure is shown;
[0054] Figures 4 to 10 A cross-sectional schematic diagram showing a portion of the stages in the method for manufacturing the first isolation structure of the first embodiment of the present disclosure;
[0055] Fig.11 A schematic structural diagram of a first isolation structure of a second embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0056] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0057] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0058] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.
[0059] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".
[0060] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.
[0061] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0062] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0063] Figure 1 A schematic structural diagram of a multi-die packaging structure in the related art is shown.
[0064] like Figure 1 As shown, in the related art, the multi-die package structure includes a first die 10, a second die 20 and a dielectric layer 30. The first die 10 includes a silicon substrate 11 and a FAB top metal 12 located on the silicon substrate 11. The second die 20 includes a silicon substrate 21 and a FAB top metal 22 located on the silicon substrate 21, wherein the FAB top metal is a metal layer added in the last stage of the manufacturing process of the die. The die is a crystal grain before the chip is packaged, which is a small piece cut from a wafer.
[0065] The first tube core 10 and the second tube core 20 are stacked and packaged, and the dielectric layer 30 is located between the FAB top metal 12 and the silicon substrate 21, and is used to fix the stacked first tube core 10 and the second tube core 20. The material of the dielectric layer 30 is pre-impregnated resin fiberglass cloth (prepreg, PP), which is an organic insulating material, and serves as an electrical isolation medium between the FAB top metal 12 and the FAB top metal 22.
[0066] See also Figure 1 In addition to the electrical isolation medium composed of PP material, there is also a silicon substrate 21 between the FAB top metal 12 and the FAB top metal 22. The thickness of the silicon substrate 21 increases the distance between the FAB top metal 12 and the FAB top metal 22. Moreover, the silicon substrate 21 is a semiconductor material and is also conductive, resulting in poor coupling performance of the isolator. In addition, since the PP material is an organic material, its thickness uniformity is difficult to control and it is easy to form holes. If the withstand voltage of the isolator is required to reach 3000V, the holes or process impurities in the PP material can easily cause the area to be easily broken down, resulting in the overall withstand voltage performance of the isolator being unstable.
[0067] In view of the above problems, the purpose of the present disclosure is to provide an electrical isolation structure, a manufacturing method thereof and a multi-die packaging structure, which adopts a single-sided process to form a conductive layer on one surface of a glass substrate to form an isolation structure, and stacks two isolation structures. A glass substrate is sandwiched between the two conductive layers to form an electrical isolation structure, which can not only meet the connection and isolation requirements between multiple dies, but also improve the voltage resistance performance of the electrical isolation structure.
[0068] Figure 2 shows a schematic structural diagram of the electrical isolation structure of the first embodiment of the present disclosure, Figure 3 A schematic structural diagram of a multi-die packaging structure according to a first embodiment of the present disclosure is shown.
[0069] like Figure 2 As shown, the multi-die package structure of the first embodiment of the present disclosure includes: an electrical isolation structure 104 , a first die 600 and a second die 400 .
[0070] In this embodiment, the electrical isolation structure 104 includes: a first isolation structure 100 , a second isolation structure 200 and an adhesive layer 300 , wherein the adhesive layer 300 is located between the first isolation structure 100 and the second isolation structure 200 for fixing the first isolation structure 100 and the second isolation structure 200 .
[0071] The first isolation structure 100 includes: a first glass substrate 110, a first connection layer 120, a first conductive layer 130 and a first metal coating layer 140, wherein the first connection layer 120, the first conductive layer 130 and the first metal coating layer 140 are sequentially stacked on the same surface of the first glass substrate 110 along the thickness direction of the first glass substrate 110. The second isolation structure 200 includes: a second glass substrate 210, a second connection layer 220, a second conductive layer 230 and a second metal coating layer 240, wherein the second connection layer 220, the second conductive layer 230 and the second metal coating layer 240 are sequentially stacked on the same surface of the second glass substrate 210 along the thickness direction of the second glass substrate 210. The first glass substrate 110 and the second metal coating layer 240 are fixedly connected by an adhesive layer 300.
[0072] The first conductive layer 130, the first glass substrate 110, and the second conductive layer 230 in the electrical isolation structure 104 constitute an isolator, wherein the first conductive layer 130 and the second conductive layer 230 are electrically isolated through the first glass substrate 110. At least one of the first conductive layer 130 and the second conductive layer 230 forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer. In some specific embodiments, the first conductive layer 130 and the second conductive layer 230 are two plates of an isolation capacitor, or the first conductive layer 130 and the second conductive layer 230 are two inductor coils of an isolation transformer.
[0073] The material of the adhesive layer 300 includes at least one of insulating film adhesive, polyimide, and pre-impregnated resin glass fiber cloth. The material of the first connecting layer 120 and the second connecting layer 220 includes titanium compounds, such as TiW, TiCu, etc., and the material of the first conductive layer 130 and the second conductive layer 230 is metal, such as Cu, Al, Ag, etc. The material of the first metal coating layer 140 and the second metal coating layer 240 is, for example, Ni, Au, etc., wherein, when the material of the first conductive layer 130 and the second conductive layer 230 is Cu, since the material of Cu is very hard, it is not conducive to the subsequent wire bonding process, so it is necessary to form a metal coating layer on the surface of the first conductive layer 130 and the second conductive layer 230. If the material of the first conductive layer 130 and the second conductive layer 230 is Al, which is a softer material, the metal coating layer may not be provided.
[0074] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the materials of the adhesive layer, the connecting layer, the conductive layer, and the metal plating layer as required.
[0075] like Figure 3 As shown, in this embodiment, the multi-die packaging structure includes: an electrical isolation structure 104, a first die 600, a second die 400, a packaging frame 501, a packaging frame 502 and a packaging layer (not shown), wherein the electrical isolation structure 104 is electrically connected to the first die 600 and the second die 400, respectively.
[0076] The first tube core 600 and the second tube core 400 include, for example, a semiconductor layer and a FAB top metal layer located above the semiconductor layer, wherein the semiconductor layer is, for example, a Si or SiC substrate or a stacked structure composed of a substrate and an epitaxial layer, wherein a CMOS circuit is formed by processes such as doping, etc. The electrical isolation structure 104 and the first tube core 600 are connected by mounting, for example.
[0077] The first tube core 600 carries the electrical isolation structure 104 and is located on the packaging frame 501, and the first tube core 600 is connected to the pad 520 on the packaging frame 501 by wire bonding. The second tube core 400 is located on the packaging frame 502, and the second tube core 400 is located on the packaging frame 502, and the pad 510 on the packaging frame 502 is connected to the first metal coating layer 140 of the electrical isolation structure 104 by wire bonding. The packaging layer is used to cover the first tube core 600, the second tube core 400 and the electrical isolation structure 104.
[0078] The present disclosure also provides a chip having the following Figure 3In the multi-die packaging structure shown, the high and low voltage isolation circuit of the chip is generally composed of a transmitting end, a receiving end and an isolator, the transmitting end is composed of a circuit in the first die 600, for example, and the receiving end is composed of a circuit in the second die 400, for example, wherein the first die 600 is one of the high voltage die and the low voltage die, and the second die 400 is the other of the high voltage die and the low voltage die. The types of the first die 600 and the second die 400 are not limited here, and those skilled in the art can set them according to the specific requirements of the circuit function.
[0079] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the connection between the lead frame, the electrical isolation structure 104 , and the first tube core 600 and the second tube core 400 as needed.
[0080] Figures 4 to 10 A schematic cross-sectional view showing a portion of a method for manufacturing a first isolation structure according to a first embodiment of the present disclosure is shown.
[0081] The first isolation structure of the first embodiment of the present disclosure is formed based on a glass substrate 110, and the glass substrate 110 has a first surface 101 and a second surface 102 opposite to each other. The glass substrate 110 needs to be pre-treated, including cleaning and roughening the glass substrate 110, so as to ensure the surface cleanliness of the glass substrate 110, increase the surface activity of the glass substrate 110, and improve the adhesion of metals and / or metal compounds on the surface of the glass substrate 110 in subsequent processes.
[0082] Furthermore, a protective layer 180 is formed on the second surface 102 and the sidewall of the glass substrate 110. Figure 4 The protective layer 180 is a shielding material, such as a chemically resistant tape or layer, which is used to prevent the electroplating solution from contacting the second surface 102 and the side wall of the glass substrate 110 in subsequent steps.
[0083] Furthermore, a connection layer 120 is formed on the first surface 101 of the glass substrate 110, such as Figure 5 shown.
[0084] In this step, for example, a chemical metal plating process or a sputtering metal process is used to form the connection layer 120. In the present embodiment, the material of the connection layer 120 includes titanium compounds, such as TiW, TiCu, etc. Among them, the connection layer 120 is, for example, a seed layer, which refers to a small piece of already formed crystal layer introduced during the crystal growth process, which is used as the starting point for crystal growth. During the crystal growth process, the seed layer can help control the orientation, shape and size of the crystal, thereby improving the quality and uniformity of the crystal. In the subsequent electroplating process, the connection layer 120 can increase the adhesion of the metal to the glass substrate 110. However, the embodiments of the present disclosure are not limited to this, and those skilled in the art can make other settings for the material of the connection layer 120 as needed.
[0085] Further, a photolithography layer 40 is formed on the connection layer 120, such as Figure 6 The photoresist layer 40 is formed by, for example, a spin-on photoresist process.
[0086] Further, the patterned photolithography layer 40 forms a photolithography mask 50, such as Figure 7 shown.
[0087] In this step, the photoresist layer 40 is patterned, for example, by exposure and development, so as to expose a portion of the connection layer 120 .
[0088] Furthermore, a patterned conductive layer 130 is formed on the connection layer 120 through the photolithography mask 50, such as Figure 8 shown.
[0089] In this step, for example, a metal is electroplated on the exposed connection layer 120 by using an electroplating process, and a solution containing an electrolyte is set in the electroplating tank. The solution is, for example, a mixture of copper sulfate (CuSO4) and sulfuric acid (H2SO4). Preferably, other additives are added to improve the quality of the electroplated layer. A pure copper plate is used as an anode and connected to the positive pole of a power supply. Copper loses electrons (oxidizes) at the anode to form copper ions (Cu 2+ ) into the solution. Then, a copper conductive layer is formed on the exposed connection layer 120.
[0090] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings for the material of the conductive layer as needed, for example, the conductive layer may also be Al or Ag.
[0091] Further, a metal plating layer 140 is formed on the patterned conductive layer through a photolithography mask 50, such as Figure 8 shown.
[0092] In this step, for example, a metal is electroplated on the conductive layer 130 by an electroplating process to form a metal plating layer 140. In this embodiment, the material of the metal plating layer 140 is, for example, Ni, Au, etc. When the material of the conductive layer 130 is Cu, since Cu is very hard and is not conducive to the subsequent wire bonding process, it is necessary to form the metal plating layer 140 on the surface of the conductive layer 130. If the material of the conductive layer 130 is Al, which is a softer material, the metal plating layer 140 may not be provided.
[0093] Further, the photolithography mask is removed to expose the connection layer 120 not covered by the conductive layer 130, such as Fig. 9 shown.
[0094] Further, for example, an etching process is used to remove the exposed connection layer 120, and the protective layer is removed to expose the cut portion of the glass substrate 110, such as Fig.10 As shown. The glass substrate 110 is then cut to separate the plurality of isolation structures. In some optional embodiments, the first isolation structure 100 and the second isolation structure 200 are made based on the same glass substrate, and after the cutting step, the first isolation structure 100 and the second isolation structure 200 are separated. In other optional embodiments, the first isolation structure 100 and the second isolation structure 200 may also be made based on different glass substrates, and the manufacturing steps of the second isolation structure 200 are similar to those of the first isolation structure 100, which will not be repeated here.
[0095] The first isolation structure 100 and the second isolation structure 200 are fixedly connected by the adhesive layer 300 to form an electrical isolation structure 104, and at least one of the first conductive layer 130 and the second conductive layer 230 forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer. Afterwards, the electrical isolation structure 104 is electrically connected to the first tube core 600 and the second tube core 400 respectively by mounting and / or wire bonding.
[0096] Fig.11 FIG. 2 shows a schematic diagram of the structure of the first isolation structure of the second embodiment of the present disclosure. Fig.11As shown, the similarities between the first isolation structure 100a of the second embodiment of the present disclosure and the first isolation structure 100 of the first embodiment are not repeated here. The difference is that the first isolation structure 100a has a stacked structure 103, the stacked structure 103 is located on the first connection layer 120, the stacked structure 103 is composed of alternately stacked conductive layers 131, interlayer dielectric layers 150 and interlayer connection layers 160, and the top layer of the stacked structure 103 is the conductive layer 131. The first metal plating layer 140 is located on the surface of the top conductive layer 131 of the stacked structure 103. Among them, the conductive layer 131 is a metal material, such as Cu, Al, Ag, etc., the interlayer isolation layer 150 is, for example, PP material, ABF material, and the interlayer connection layer 160 is a titanium compound, such as TiCu, TiW, etc. The multiple conductive layers 131 stacked in the stacked structure 103 of this embodiment can replace the first conductive layer 130 of the first embodiment, or the first conductive layer 130 includes multiple conductive stacks. Similarly, the second conductive layer 230 in the first embodiment may also include a plurality of conductive stacks, and the plurality of conductive stacks serve as one of the plates of an isolation capacitor or one of the inductors of an isolation transformer.
[0097] According to the embodiments of the present disclosure as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modifications based on the present disclosure. The scope of protection of the present disclosure shall be based on the scope defined by the claims of the present disclosure and their equivalents.
Claims
1. A method for manufacturing an electrical isolation structure, comprising: Forming a first isolation structure and a second isolation structure and fixing the first isolation structure and the second isolation structure together through an adhesive layer: Wherein, forming the first isolation structure includes: forming a first connection layer on the first surface of the first glass substrate; and forming a first conductive layer on the first connecting layer, Forming the second isolation structure includes: forming a second connecting layer on the first surface of the second glass substrate; and forming a second conductive layer on the second connecting layer, The adhesive layer is located between the first glass substrate and the second conductive layer. At least one of the first conductive layer and the second conductive layer forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer.
2. The manufacturing method according to claim 1, wherein: The first glass substrate and the second glass substrate are formed based on the same glass substrate, the first connecting layer and the second connecting layer are connecting layers formed synchronously, and the first conductive layer and the second conductive layer are conductive layers formed synchronously.
3. The manufacturing method according to claim 2, further comprising: forming a photolithography layer on the connection layer; as well as patterning the photolithography layer to form a photolithography mask to expose a portion of the connection layer, The conductive layer is electroplated on the exposed connecting layer through the photolithography mask, thereby forming a patterned conductive layer.
4. The manufacturing method according to claim 3, wherein: The connection layer is formed on the first surface by using a chemical metal plating process or a sputtering metal process, The material of the connection layer includes a titanium compound.
5. The manufacturing method according to claim 3, further comprising: A metal plating layer is formed on the patterned conductive layer through the photolithography mask.
6. The manufacturing method according to claim 3, further comprising: Before forming the connecting layer, forming a protective layer on the second surface of the glass substrate; removing the photolithography mask after forming the patterned conductive layer; removing the exposed connecting layer and the protective layer to expose the cutting portion of the glass substrate; as well as The glass substrate is cut to separate the first isolation structure from the second isolation structure.
7. The manufacturing method according to claim 2, wherein: The conductive layer is a single conductive layer or a plurality of conductive stacked layers.
8. The manufacturing method according to claim 7, further comprising: An interlayer dielectric layer and an interlayer connection layer are formed between two adjacent conductive stacked layers.
9. The manufacturing method according to claim 2, further comprising: Before forming the connection layer, the glass substrate is roughened to enhance the adhesion of the metal and / or metal compound on the surface of the glass substrate.
10. An electrical isolation structure, comprising a first isolation structure, a second isolation structure, and an adhesive layer located between the first isolation structure and the second isolation structure, in, The first isolation structure comprises: a first glass substrate; A first connecting layer, located on the first glass substrate; and a first conductive layer, located on the first connecting layer, The second isolation structure comprises: a second glass substrate; a second connecting layer, located on the second glass substrate; and a second conductive layer, located on the second connecting layer, The adhesive layer is located between the first glass substrate and the second conductive layer, and is used to fix the first isolation structure and the second isolation structure. At least one of the first conductive layer and the second conductive layer forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer.
11. The electrical isolation structure according to claim 10, wherein: The first conductive layer is a single conductive layer or a plurality of conductive stacked layers, and the second conductive layer is a single conductive layer or a plurality of conductive stacked layers. 12 . The electrical isolation structure according to claim 10 , further comprising an interlayer dielectric layer and an interlayer connection layer located between two adjacent conductive stacked layers.
13. A multi-die packaging structure, comprising a first die, a second die and the electrical isolation structure formed by the manufacturing method according to any one of claims 1 to 9, wherein the electrical isolation structure is electrically connected to the first die and the second die respectively.