Multi-mode frequency dividing circuit

Abstract

The invention provides a multi-mode frequency dividing circuit. The multi-mode frequency dividing circuit comprises a frequency dividing factor processor, a frequency divider and a logic arithmetic unit, the frequency division factor processor receives a frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. A frequency divider performs frequency division on a clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency-divided clock signal. The logic arithmetic unit samples the frequency division clock signal in sequence according to the rising edge and the falling edge of the clock signal to generate a first signal and a second signal, and the logic arithmetic unit generates an output clock signal according to the first signal, the second signal and an indication signal.

Description

Technical Field

[0001] The present invention relates to a multi-mode frequency division circuit, in particular to a multi-mode frequency division circuit capable of generating an output clock signal with a duty cycle of 50%. Background Art

[0002] In the prior art, multi-mode dividers can be mainly divided into synchronous prescaler-counter based structures and asynchronous cascade structures. Ordinary asynchronous cascade structures will accumulate jitter. Therefore, the prior art proposes a prescaler based on divide-by-2 / 3 to use the first stage as the output to avoid accumulated jitter. However, whether it is a multi-mode divider based on a synchronous prescaler-counter structure or an asynchronous cascade structure, it is impossible to output a clock signal with a duty cycle of 50% at any division ratio. Summary of the invention

[0003] The purpose of the present application is to provide a multi-mode frequency division circuit, which can generate an output clock signal with a duty cycle of 50% under any frequency division ratio.

[0004] According to an embodiment of the present invention, a multi-mode frequency division circuit includes a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and selects to output the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The frequency divider is coupled to the frequency division factor processor, and divides the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator samples the frequency division clock signal in sequence according to the rising edge and the falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and the indication signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram of a multi-mode frequency division circuit according to an embodiment of the present invention is shown.

[0006] Figure 2 A block diagram showing a multi-mode frequency division circuit according to another embodiment of the present invention.

[0007] Figure 3 Showing the present invention Figure 2 A timing diagram of the multi-mode frequency division circuit of an embodiment.

[0008] Figure 4A A schematic diagram showing a first frequency division device in a multi-mode frequency division circuit according to an embodiment of the present invention is shown.

[0009] Figure 4B Show Figure 4A A timing diagram of the first frequency dividing device of the embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the embodiments will be clearly and completely described below in conjunction with the drawings of the disclosed embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. Please refer to Figure 1 , Figure 1 A block diagram of a multi-mode frequency division circuit according to an embodiment of the present invention is shown. The multi-mode frequency division circuit 100 includes a frequency division factor processor 110, a frequency divider 120, and a logic operator 130. The frequency division factor processor 110 receives a frequency division factor N, and obtains a first sub-frequency division factor M1 and a second sub-frequency division factor M2 by decomposing the frequency division factor N. The frequency division factor processor 110 selects to output the first sub-frequency division factor M1 or the second sub-frequency division factor M2 to the frequency divider 120 according to the frequency division clock signal CK_MMD. The frequency divider 120 is coupled to the frequency division factor processor 110. The frequency divider 120 receives a clock signal CKin, and divides the received clock signal CKin based on the first sub-frequency division factor M1 or the second sub-frequency division factor M2 to generate a frequency division clock signal CK_MMD. The logic operator 130 is coupled to the frequency division factor processor 110 and the frequency divider 120. The logic operator 130 samples the divided clock signal CK_MMD in sequence according to the rising edge and the falling edge of the clock signal CKin to generate a first signal and a second signal. The logic operator 130 generates an output clock signal CKout according to the first signal, the second signal and the indication signal ID.

[0011] Specifically, the frequency division factor processor 110 generates a first sub-frequency division factor M1 and a second sub-frequency division factor M2 by decomposing the frequency division factor N, wherein the sum of the first sub-frequency division factor M1 and the second sub-frequency division factor M2 is equal to the frequency division factor N. Furthermore, when the frequency division factor N is an even number, the first sub-frequency division factor M1 and the second sub-frequency division factor M2 are equal; when the frequency division factor N is an odd number, the absolute value of the difference between the second sub-frequency division factor M2 and the first sub-frequency division factor M1 is 1.

[0012] In principle, the frequency division factor processor 110 can divide the frequency division factor N by 2 and round it down to generate the first sub-frequency division factor M1. Furthermore, when the above-mentioned N is an even number, the second sub-frequency division factor M2 is equal to the first sub-frequency division factor M1. When N is an odd number, the first sub-frequency division factor M1 can be added by 1 to generate the second sub-frequency division factor M2. In an actual circuit, in order to reduce the complexity of the circuit, the frequency division factor processor 110 can generate the effect of division by 2 by discarding the least significant bit (LSB) of the frequency division factor N, and obtain the first sub-frequency division factor M1. Then, the first sub-frequency division factor M1 is added to the least significant bit of the frequency division factor N to generate the second sub-frequency division factor M2.

[0013] On the other hand, the frequency division factor processor 110 selectively outputs the first sub-frequency division factor M1 or the second sub-frequency division factor M2 to the frequency divider 120 according to the logic value of the frequency division clock signal CK_MMD. In this embodiment, when the frequency division clock signal CK_MMD is a first logic value, the frequency division factor processor 110 can output the first sub-frequency division factor M1 to the frequency divider 120, and conversely, when the frequency division clock signal CK_MMD is a second logic value, the frequency division factor processor 110 can output the second sub-frequency division factor M2 to the frequency divider 120. The first logic value can be logic 0 (or 1), and the second logic value can be logic 1 (or 0).

[0014] The frequency divider 120 may receive the clock signal CKin and perform a frequency division operation on the clock signal CKin according to the received first sub-frequency division factor M1 or second sub-frequency division factor M2. The frequency divider 120 divides the frequency of the clock signal CKin by the first sub-frequency division factor M1 when the generated divided clock signal CK_MMD is a first logic value; and divides the frequency of the clock signal CKin by the second sub-frequency division factor M2 when the divided clock signal CK_MMD is a second logic value.

[0015] Furthermore, the frequency divider 120 obtains a frequency division signal (i.e., the "flag signal FLAG" mentioned below) by dividing the frequency of the clock signal CKin by the first sub-frequency division factor M1 and the second frequency division factor M2 in turn, and triggers the frequency division by two with the rising edge of the frequency division signal, thereby obtaining an N-frequency division signal, i.e., the frequency division clock signal CK_MMD. In this way, the duty cycle of the frequency division clock signal CK_MMD is M1 / M2, which has a duty cycle close to 50%.

[0016] The logic operator 130 can receive the divided clock signal CK_MMD and the clock signal CKin. The logic operator 130 can sample the divided clock signal CK_MMD in sequence according to the rising edge and the falling edge of the clock signal CKin, and generate a first signal and a second signal with a phase difference respectively. The logic operator 130 then generates an output clock signal CKout according to the indication signal ID, the first signal and the second signal, wherein the duty cycle of the output clock signal CKout is 50%. In this embodiment, the indication signal ID is used to indicate whether the division factor N is an odd number or an even number. Specifically, when the indication signal ID is logic 1, it indicates that the division factor N is an odd number; when the indication signal ID is logic 0, it indicates that the division factor N is an even number. In actual circuit design, the indication signal ID can be the least significant bit of the division factor N.

[0017] When the frequency division factor N is an even number, the logic operator 130 can output an output clock signal CKout equal to the first signal; conversely, when the frequency division factor N is an odd number, the logic operator 130 can perform an OR operation on the first signal and the second signal to generate the output clock signal CKout. Thus, regardless of whether the frequency division factor N is an odd number or an even number, the logic operator 130 can generate an output clock signal Ckout with a duty cycle of 50%.

[0018] Please refer to Figure 2 , Figure 2 A block diagram of a multi-mode frequency division circuit according to another embodiment of the present invention is shown. The multi-mode frequency division circuit 200 includes a frequency division factor processor 210, a frequency divider 220, and a logic operator 230. The frequency division factor processor 210 includes buffers 211, 212, and a selector (MUX) 213. The buffers 211, 212 store a first sub-frequency division factor M1 and a second sub-frequency division factor M2, respectively, wherein the first sub-frequency division factor M1 and the second sub-frequency division factor M2 are obtained by decomposing a frequency division factor N. The decomposition method of the frequency division factor N has been described in detail in the aforementioned embodiment, and will not be described in detail below.

[0019] The selector 213 is coupled to the registers 211 and 212, and receives the first sub-frequency division factor M1 and the second sub-frequency division factor M2 respectively stored in the registers 211 and 212. The selector 213 also receives the divided clock signal CK_MMD, and selectively outputs the first sub-frequency division factor M1 or the second sub-frequency division factor M2 to the frequency divider 220 according to the logic value of the divided clock signal CK_MMD. In the present embodiment, when the divided clock signal CK_MMD is logic 1, the selector 213 can select to output the first sub-frequency division factor M1 to the frequency divider 220; in addition, when the divided clock signal CK_MMD is logic 0, the selector 213 can select to output the second sub-frequency division factor M2 to the frequency divider 220.

[0020] The frequency divider 220 includes a first frequency divider 221 and a second frequency divider 222 connected in series. In this embodiment, the first frequency divider 221 may be a multi-mode frequency divider MMD, and the second frequency divider 222 may be a D-type flip-flop. The first frequency divider 221 receives the clock signal CKin and the first sub-frequency division factor M1 or the second sub-frequency division factor M2, and divides the frequency of the clock signal CKin by the first sub-frequency division factor M1 or the second sub-frequency division factor M2 to generate a flag signal FLAG. The first frequency divider 221 transmits the flag signal FLAG to the second frequency divider 222.

[0021] The second frequency dividing device 222 is used to divide the flag signal FLAG by two to generate the divided clock signal CK_MMD. The second frequency dividing device can use the rising edge of the flag signal as a trigger signal to achieve the two-way frequency division. Specifically, the second frequency dividing device 222 can use the rising edge of the flag signal FLAG obtained by dividing the frequency of the clock signal CKin by the first sub-frequency division factor M1 and the rising edge of the flag signal FLAG obtained by dividing the frequency of the clock signal CKin by the second sub-frequency division factor M2 as trigger signals to achieve the two-way frequency division operation, thereby generating the divided clock signal CK_MMD. In this embodiment, the second frequency dividing device 222 can be implemented by a D-type flip-flop DFF1. Among them, the inverting output terminal QB of the D-type flip-flop DFF1 is coupled to its data terminal D; the clock terminal of the D-type flip-flop DFF1 receives the flag signal FLAG; the output terminal Q of the D-type flip-flop DFF1 generates the divided clock signal CK_MMD.

[0022] Through the divide-by-two operation of the second frequency dividing device 222 , the duty cycle of the divided clock signal CK_MMD can be close to 50%.

[0023] The logic operator 230 includes flip-flops DFF2 and DFF3, an AND gate AN1, and an OR gate OR1. The data terminal D of the flip-flop DFF2 receives the divided clock signal CK_MMD; the clock terminal of the flip-flop DFF2 receives the clock signal CKin; the output terminal Q of the flip-flop DFF2 generates the first signal S1. In addition, the flip-flop DFF3 is coupled to the rear end of the flip-flop DFF2, wherein the data terminal D of the flip-flop DFF3 receives the first signal S1; the clock terminal of the flip-flop DFF3 receives the inverted signal of the clock signal CKin, i.e., the inverted clock signal CKinb; the output terminal Q of the flip-flop DFF3 generates the second signal S2. In this embodiment, the inverted clock signal CKinb can be generated by the inverter IV1 inverting the clock signal CKin.

[0024] One input terminal of the AND gate AN1 receives the second signal S2, and the other input terminal of the AND gate AN1 receives the least significant bit N of the frequency division factor N. <0> The output terminal of the AND gate AN1 is coupled to an input terminal of the OR gate OR1. The other input terminal of the OR gate OR1 receives the first signal S1. The output terminal of the OR gate OR1 can generate an output clock signal CKout.

[0025] The triggers DFF2 and DFF3 are used to sample the divided clock signal CK_MMD in sequence. In one embodiment, the triggers DFF2 and DFF3 respectively sample the clock signal CKin and the inverted clock signal CKinb which are in opposite phases to each other, wherein the trigger DFF2 can sample the divided clock signal CK_MMD according to the rising edge of the clock signal CKin to obtain the first signal S1, and the trigger DFF3 can continue to sample the first signal S1 according to the rising edge of the inverted clock signal CKinb (which can also be considered as the falling edge of the clock signal CKin) to obtain the second signal S2. On the other hand, when the least significant bit N of the frequency division factor N is <0> When it is logic 0, it means that the frequency division factor N is an even number. At this time, the AND gate AN1 outputs logic 0, and the OR gate OR1 can directly output the first signal S1 as the output clock signal CKout. <0> When it is logic 1, it means that the frequency division factor N is an odd number. At this time, the AND gate AN1 outputs the second signal S2, and the OR gate OR1 can perform an OR operation on the first signal S1 and the second signal S2 to generate the output clock signal CKout. Accordingly, the output clock signal CKout can have a duty cycle of 50%.

[0026] Please refer to the following synchronously Figure 2 as well as Figure 3 ,in Figure 3 Showing the present invention Figure 2 Timing diagram of the multi-mode frequency division circuit of the embodiment. In this embodiment, the frequency division factor N is equal to 15, for example, the first sub-frequency division factor M1 is 7, the second sub-frequency division factor M2 is 8, and the least significant bit N of the frequency division factor N is <0> is logic 1. T1 is 7 CKin clock cycles, and T2 is 8 CKin clock cycles. In the time interval T1, based on the frequency-divided clock signal CK_MMD jumping to logic 1, the first sub-frequency-dividing factor M1 is output to the first frequency-dividing device 221. The first frequency-dividing device 221 divides the frequency of the clock signal CKin by 7 to generate the flag signal FLAG. The second frequency-dividing device 222 divides the flag signal FLAG by two to generate the frequency-divided clock signal CK_MMD.

[0027] Next, at time point t11, at the rising edge of the clock signal CKin, the trigger DFF2 can sample the divided clock signal CK_MMD and generate a first signal S1 of logic 1. At this time, the second signal is logic 0, because the least significant bit N of the frequency division factor N is <0> is logic 1, and the AND gate AN1 outputs the second signal of logic 0; the OR gate OR1 performs an OR operation on the first signal S1 and the second signal S2 to output the first signal S1 (logic 1) as the output clock signal CKout. Afterwards, at time point t12, at the falling edge of the clock signal CKin, the flip-flop DFF3 can sample the first signal S1 and generate the second signal S2 of logic 1. <0> is logic 1, and the AND gate AN1 outputs the second signal S2. In the time interval T1, the OR gate OR1 can perform an OR operation on the first signal S1 and the second signal S2 to generate an output clock signal Ckout with a logic value of 1, and increase the time when the output clock signal Ckout is logic 1 by half a cycle of the clock signal CKin.

[0028] In the time interval T2, based on the divided clock signal CK_MMD jumping to logic 0, the second sub-division factor M2 is output to the first frequency division device 221. The first frequency division device 221 divides the frequency of the clock signal CKin by 8 to generate the flag signal FLAG. The second frequency division device 222 divides the flag signal FLAG by two to generate the divided clock signal CK_MMD.

[0029] Next, at time point t21, at the rising edge of the clock signal CKin, the flip-flop DFF2 can sample the divided clock signal CK_MMD and generate a first signal S1 of logic 0. Afterwards, at time point t22, at the falling edge of the clock signal CKin, the flip-flop DFF3 can sample the first signal S1 and generate a second signal S2 of logic 0. The least significant bit N of the frequency division factor N (N=15) is <0> is logic 1, and the AND gate AN1 outputs the second signal S2 which is logic 0. The OR gate OR1 performs an OR operation on the first signal S1 and the second signal S2 so that the output clock signal CKout is logic 0.

[0030] from Figure 3 It can be seen that the time when the output clock signal CKout is logic 0 is equal to the time when it is logic 1. Although the operating principle of the present application is described by taking the frequency division factor as an odd number as an example, the present application is not limited thereto, and the frequency division factor can be any positive integer.

[0031] According to the above description, it can be known that the positive and negative cycles of the output clock signal CKout can have the same time length. In other words, the output clock signal CKout has a duty cycle of 50%.

[0032] Please refer to the following Figure 4A as well as Figure 4B , Figure 4A A schematic diagram showing a first frequency division device in a multi-mode frequency division circuit according to an embodiment of the present invention is shown, Figure 4B Show Figure 4A Timing diagram of the first frequency dividing device of the embodiment. The first frequency dividing device 400 can be a multi-mode frequency divider. The first frequency dividing device 400 includes a prescaler 410 and a counter 420. The prescaler 410 receives the clock signal CKin, and performs a pre-dividing operation on the clock signal CKin according to the fed-back flag signal FLAG to generate a pre-dividing signal CKd. Specifically, when the flag signal FLAG is logic 0, the prescaler 410 divides the frequency of the clock signal CKin by k so that the logic 0 of the flag signal FLAG is maintained for k cycles of CKin. On the other hand, when the flag signal FLAG is logic 1, the prescaler 410 divides the frequency of the clock signal CKin by k+1 so that the logic 1 of the flag signal FLAG is maintained for k+1 cycles of CKin, where k is the pre-dividing factor, which can be any positive integer.

[0033] The counter 420 is coupled to the rear end of the prescaler 410 and is used to count the prescaler signal CKd to generate the flag signal FLAG. The counter 420 counts the rising edges of the prescaler signal according to the first division factor or the second division factor to generate the flag signal FLAG.

[0034] Please refer to this Figure 4B , the frequency division factor N is also equal to 15, the first sub-frequency division factor M1 is 7, the second sub-frequency division factor M2 is 8, and k is equal to 2 as an example. In the time interval T1, the first sub-frequency division factor M1 (=7) is output to the first frequency division device 400. In the time interval T41, based on the flag signal FLAG being logic 1, the prescaler 410 divides the frequency of the clock signal CKin by k+1 (=3) so that the logic 1 of the flag signal FLAG is maintained for k+1 cycles of CKin. In the subsequent time interval T42, based on the flag signal FLAG being logic 0, the prescaler 410 divides the frequency of the clock signal CKin by k (=2) so that the logic 0 of the flag signal FLAG is maintained for k cycles of CKin.

[0035] In the time interval T2, the second sub-division factor M2 (=8) is output to the first frequency division device 400. In the time interval T43, based on the flag signal FLAG being logic 1, the pre-divider 410 divides the frequency of the clock signal CKin by k+1 (=3) so that the logic 1 of the flag signal FLAG is maintained for k+1 cycles of CKin. In the subsequent time interval T44, based on the flag signal FLAG being logic 0, the pre-divider 410 divides the frequency of the clock signal CKin by k (=2) so that the logic 0 of the flag signal FLAG is maintained for k cycles of CKin.

[0036] It is worth mentioning that Figure 4A The first frequency dividing device 400 is only an example for illustration and is not intended to limit the scope of the present invention. In other embodiments of the present invention, the first frequency dividing device may be any conventional synchronous or asynchronous multi-mode frequency divider without any specific limitation.

[0037] The embodiment of the present application decomposes the frequency division factor N into two values ​​M1 and M2 that are closest to each other (when N is an even number, M1=M2, when N is an odd number, M2=M1+1), and uses a multi-mode divider MMD to perform M1 division and M2 division on the input clock signal CKin in turn, so as to obtain the flag signal FLAG with the closest length of two adjacent cycles. Then, the rising edge of the flag signal FLAG is used as a trigger signal for two-division, and an N-divided signal, that is, the divided clock signal CK_MMD, can be obtained. The duty cycle of the divided clock signal CK_MMD is M1 / M2. Then, the divided clock signal CK_MMD is sampled in turn according to the rising edge and falling edge of the clock signal CKin to obtain the first signal S1 and the second signal S2, and the first signal S1 and the second signal S2 are or-operated to generate the output clock signal Ckout, so that an output clock signal with a duty cycle of 50% can be output for any frequency division factor N.

[0038] The present application decomposes the division factor N based on the existing multi-mode divider MMD, and corrects the duty cycle of the output clock signal in combination with a simple logic circuit, thereby achieving an output clock signal with a duty cycle of 50% for any division factor. The implementation method is simple, and at the same time, the decomposed division factor is halved, so that the number of bits of the counter is reduced by 1, which optimizes the timing margin and reduces the design difficulty.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-mode frequency division circuit, characterized in that: include: A frequency division factor processor receives a frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and selects to output the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal; A frequency divider, coupled to the frequency division factor processor, receives a clock signal, and divides the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the divided clock signal; as well as A logic operator samples the divided clock signal in sequence according to the rising edge and the falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal and the indication signal.

2. The multi-mode frequency division circuit according to claim 1, characterized in that: The duty cycle of the output clock signal is 50%.

3. The multi-mode frequency division circuit according to claim 1, characterized in that: The frequency division factor processor removes the least significant bit of the frequency division factor to obtain the first sub-frequency division factor, and adds the first sub-frequency division factor to the least significant bit of the frequency division factor to obtain the second sub-frequency division factor.

4. The multi-mode frequency division circuit according to claim 3, characterized in that: The frequency division factor processor comprises: A first buffer, used for storing the first sub-frequency division factor; A second register is used to store the second sub-frequency division factor; and The selector is coupled to the first register and the second register, and selects and outputs the first sub-frequency division factor or the second sub-frequency division factor according to the frequency-divided clock signal.

5. The multi-mode frequency division circuit according to claim 1, characterized in that: The frequency divider comprises: a first frequency dividing device, dividing the clock signal according to the first sub-frequency dividing factor or the second sub-frequency dividing factor to generate a flag signal; and The second frequency dividing device is coupled to the first frequency dividing device, and divides the flag signal by two to generate the divided clock signal.

6. The multi-mode frequency division circuit according to claim 5, characterized in that: The first frequency dividing device comprises: a pre-divider, for pre-dividing the clock signal according to the flag signal to generate a pre-divided signal; and A counter is configured to count rising edges of the pre-divided frequency signal according to the first sub-divided frequency factor or the second sub-divided frequency factor to generate the flag signal.

7. The multi-mode frequency division circuit according to claim 6, characterized in that: The pre-divider divides the frequency of the clock signal by k when the flag signal is logic 0, and divides the frequency of the clock signal by k+1 when the flag signal is logic 1, wherein k is a pre-divider frequency division factor, which is a positive integer.

8. The multi-mode frequency division circuit according to claim 5, characterized in that: The second frequency dividing device is a D-type flip-flop.

9. The multi-mode frequency division circuit according to claim 1, characterized in that: The logic operator comprises: a first trigger, sampling the divided clock signal according to a rising edge of the clock signal to generate the first signal; a second trigger, sampling the first signal according to a falling edge of the clock signal to generate the second signal; an AND gate, receiving the second signal and the indication signal to generate a third signal; and An OR gate receives the first signal and the third signal to generate the output clock signal.

10. The multi-mode frequency division circuit according to claim 8, characterized in that: The indication signal is the least significant bit of the frequency division factor.

11. The multi-mode frequency division circuit according to claim 1, characterized in that: When the frequency division factor is an even number, the first sub-frequency division factor is equal to the second sub-frequency division factor, and when the frequency division factor is an odd number, the difference between the second sub-frequency division factor and the first sub-frequency division factor is 1.

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