Method and apparatus for reducing creak in transmission signals

Abstract

The invention discloses a method and an apparatus for reducing crests in a transmission signal. An example apparatus (202) for reducing crests in an input signal includes: a memory (320); and instructions that cause the programmable circuitry (316) to at least: store the first copy and the second copy of the normalized window waveform in the memory (320); generating weights (325) corresponding to peaks in the input signal (201) using a first copy of the normalized window waveform; generating an output waveform (326) using the weights and the second copy of the normalized window waveform; generating a peak limit waveform (317) in response to the output waveform; and combining (304) the peak limit waveform (317) with the input signal (201) to reduce the magnitude (203) of the peak.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit and priority of Indian Provisional Patent Application No. 202341051102 filed on July 28, 2023, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The present description relates generally to transmitters and, more particularly, to methods and apparatus for reducing peaks in transmission signals. Background Art

[0004] Wireless communication technologies enable a variety of electronic devices (e.g., mobile phones, tablet computers, laptop computers, etc.) to support the execution of increasingly diverse and complex workloads. The secure, efficient, and accurate exchange of information over a wireless medium involves technical challenges. One such technical challenge is power consumption. Typically, the amount of power consumed by a transmitter device increases as the amplitude of its output signal increases. Summary of the invention

[0005] For a method and apparatus for reducing peaks in a transmission signal, an example apparatus includes a memory; and a programmable circuit system configured to: store a first copy and a second copy of a normalized window waveform in the memory, the first copy of the normalized window waveform including more data points than the second copy of the normalized window waveform; use the second copy of the normalized window waveform to generate weights corresponding to peaks in an input signal; use the weights and the first copy of the normalized window waveform to generate an output waveform; generate a peak limiting waveform in response to the output waveform; and combine the peak limiting waveform with the input signal to reduce the amplitude of the peak. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of an example environment including a client device and a base station.

[0007] Figure 2 yes Figure 1 A block diagram of an example implementation of a transmitter circuit system.

[0008] Figure 3 yes Figure 2 A block diagram of an example implementation of a crest factor reduction (CFR) circuit system.

[0009] Figure 4 yes Figure 3 A block diagram of an example implementation of a mode switcher circuit system.

[0010] Figure 5A is a graph of an illustrative example of a half replica of a normalized window function.

[0011] Figure 5B yes Figure 4 A block diagram of an example implementation of an effective waveform weight generation (EWG) circuit system using Figure 5A waveform.

[0012] Fig. 6A is a graph of an illustrative example of a full copy of a normalized window function.

[0013] Figure 6B yes Figure 4 A block diagram of an example implementation of a composite waveform generation (CWG) circuit system using Fig. 6A waveform.

[0014] Figure 7 Is Figure 4 Graphs of illustrative examples of operations performed by EWG circuitry and CWG circuitry.

[0015] Figure 8 yes Figure 4 A block diagram of an example implementation of a pulse cancellation circuit system.

[0016] Fig. 9 Yes means you can use Figure 1 A flowchart of example machine-readable instructions or example operations executed, instantiated, or performed by an example programmable circuit system implementation of a transmitter circuit system.

[0017] Fig.10 It is meant to be performed, instantiated or implemented using the example programmable circuit system to use as described in connection with Figure 8 The invention also provides a flow chart of example machine readable instructions or example operations for describing a memory and a multiplier to generate a peak limited waveform (PLW).

[0018] Fig.11 is a block diagram of an example processing platform including programmable circuitry configured to execute, instantiate, or implement example machine-readable instructions or to implement Fig. 9 and Fig.10 Example operations to implement Figure 2 Transmitter circuit system 110.

[0019] The same reference numbers or other reference identifiers are used in the drawings to indicate the same or similar (functionally or structurally) features. DETAILED DESCRIPTION

[0020] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings (one or more) and in this description refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries and lines may not be observed, may be blended together, or may be irregular.

[0021] One parameter that significantly affects the power consumption of a transmitter device is the peak-to-average power ratio (PAR). PAR is determined by: a) squaring the peak amplitude of the transmitter output signal to obtain the peak power consumed; b) calculating the mean square value of the transmitter output signal to obtain the average power consumed; and c) dividing the peak power consumed by the average power consumed. In general, the performance of the power amplifier circuitry within a transmitter device decreases as PAR increases. Therefore, the industry is committed to producing transmitters with low PAR.

[0022] Some transmitter devices maintain low PAR by reducing the magnitude (e.g., amplitude) of peaks within an input signal prior to transmitting the output signal across a transmission medium. Reducing the amplitude of the peaks of the input signal reduces the PAR and improves the performance of the transmitter. As used herein, the technique for modifying the input signal as described above may be referred to as crest factor reduction (CFR).

[0023] Various CFR techniques are used by the industry to reduce PAR. One such technique is the pulse cancellation CFR (PC-CFR) technique, which may also be referred to as the peak cancellation CFR (PC-CFR). The PC-CFR technique involves calculating a cancellation pulse by using a peak cancellation waveform (PCW) in response to the properties of the input signal, and adding the cancellation pulse to the input signal in the opposite direction of the peak. To ensure that other quality indicators of the output signal (e.g., error vector magnitude (EVM), adjacent channel leakage ratio (ACLR)) remain within acceptable limits after such operations, a transmitter device using the PC-CFR technique is required to ensure that the energy in the PCW is within the same frequency band as the original input signal. While some transmitter devices are implemented in systems that provide such frequency profile information required to calculate the PCW, other transmitter devices are implemented in systems that do not provide frequency profile information. Therefore, transmitter devices that rely solely on PC-CFR to maintain low PAR can only be implemented in a limited number of use cases.

[0024] As used herein, frequency distribution information includes information about the spectrum occupancy of the signal to be transmitted. The frequency distribution information may include, but is not limited to, the number of carriers used to transmit the signal, the bandwidth of the carriers, and the relative power levels of the carriers. Figure 8 PC-CFR is further described.

[0025] Some transmitter devices use windowed CFR (W-CFR) techniques as an alternative to PC-CFR. W-CFR involves calculating a peak-limited waveform (PLW) in response to the properties of the input signal and multiplying the PLW by the input signal. Because pulse cancellation is additive, PC-CFR techniques require designing a PCW that matches the frequency distribution of the transmitted signal to avoid violating spectral emission limits. In contrast, W-CFR techniques multiply the PLW by the attenuated peak. Multiplication in time corresponds to convolution in frequency, which can result in a form of noise known as spectral smearing. However, the smearing effect occurs regardless of the underlying signal frequency distribution. Therefore, the transmitter device can avoid violating spectral emission requirements by selecting an appropriate PLW that is independent of the signal frequency distribution. Such versatility of W-CFR comes at the cost of the fact that for a given PAR target and acceptable emission (ACLR) level, W-CFR techniques generally perform worse than PC-CFR techniques (e.g., have higher EVM). However, the transmitter device can generate PLW without frequency distribution information, so the W-CFR technique can be applied to a wider range of use cases compared to the PC-CFR technique. In some examples, a window function is used to generate the PLW because the PLW is a relatively smooth function with non-zero values ​​within a finite duration.

[0026] Some W-CFR techniques generate PLW by scaling a window function with a scaling factor generated during peak detection. Such W-CFR techniques employ a finite impulse response (FIR) filter to generate such scaling factors. In such techniques, the coefficients forming the FIR filter are filled by successive window function samples, and the input to the FIR filter is an attenuation indication signal (AIS). The AIS consists of pulses marking peak positions, where the amplitude at each peak position corresponds to the overshoot level of the peak relative to the target peak limit. A designer or manufacturer of such a transmitter device may implement a FIR filter with sufficient memory registers to store a buffer of AIS samples that runs through the duration of the window function. Therefore, the value of the PLW at any point in time is the cumulative result of multiple previous peaks that still affect the value of the PLW at that point in time. As described above and herein, the terms "scaling factor" and "weight" may be used interchangeably.

[0027] In order to store enough AIS samples throughout the duration of the window function, the amount of memory required to implement the FIR filter in the W-CFR technique is relatively high (e.g., enough memory to store approximately 1000 samples). In addition, a given type or shape of window waveform used in the W-CFR technique may be more efficient in some use cases than in other use cases. Therefore, the FIR filters used in such techniques are typically programmable so that the designer or manufacturer of system-level devices (e.g., mobile devices, vehicles, cellular towers, etc.) including transmitters can select the type or shape of window function that best suits their use case. The above-mentioned memory requirements and programmability increase both the power consumption of the FIR filter and the space dedicated to implementing the FIR filter on an integrated circuit (IC).

[0028] When two peaks within the input signal occur close to each other in time, the first window function corresponding to the first peak and generated by the FIR filter may overlap with the second window function corresponding to the second peak and generated by the FIR filter. The overlap results in the generation of PLW, which causes excessive attenuation of the output signal, which reduces signal quality (increasing EVM as described above).

[0029] Some transmitter devices attempt to mitigate excessive attenuation of the output signal by adding a feedback compensation path. The feedback compensation path enables pre-compensation of the attenuation indicator signal for a new peak detected at any point in time. To this end, the feedback compensation path enables the transmitter device to take into account the impact of multiple previous peaks that still affect the value of the PLW at that point in time. While adding such feedback compensation improves the signal quality of the output signal (e.g., reduces EVM), feedback compensation requires additional programmable FIR filters that consume a lot of space and power.

[0030] The example methods, apparatus, and systems described herein provide a transmitter device that can switch between PC-CFR techniques and W-CFR techniques in response to the availability of frequency distribution information. The example transmitter circuit system includes a shared set of computing resources (e.g., multipliers and storage registers) and uses the shared resources to implement the PC-CFR technique or the W-CFR technique in response to the operating mode. When generating a PLW in the W-CFR mode, the example transmitter circuit system calculates the scaling factor of the current peak in response to the overshoot factor of the current peak, the sample value of the half-copy waveform from the previous peak, and the scaling factor of the previous peak. Then, the example transmitter circuit system uses the scaling factor of the current peak and the sample value of the full-copy waveform from the previous peak to calculate the overall PLW. Therefore, the example transmitter circuit system can implement W-CFR programmatically without the power consumption or space required by the previous W-CFR technique using an FIR filter. The example transmitter circuit system can operate in the system regardless of whether the system provides frequency distribution information, so that the example transmitter circuit system can be applied to a wider range of use cases than other transmitter devices that rely only on PC-CFR.

[0031] Figure 1 is an example block diagram of a communication system. Figure 1 An example network 100, an example network device 102, an example client device 104, and an example transmission medium 106 are included. Network device 102 includes example controller circuitry 108, example transmitter circuitry 110, and example receiver circuitry 112. Similarly, client device 104 includes example controller circuitry 118, example receiver circuitry 114, and example transmitter circuitry 116. Figure 1 is an example of a transmitter device implemented within a telecommunications use case. More generally, a transmitter device implemented in the teachings described herein may be implemented in any type of use case or application.

[0032] The network 100 connects various endpoint devices and facilitates communication between various endpoint devices to support the Internet or telephone equipment. In this example, the network 100 is a cellular network. However, the example network 100 can be implemented using (one or more) any suitable wired or wireless network including, for example, the following items: one or more data buses, one or more local area networks (LANs), one or more wireless LANs (WLANs), one or more coaxial cable networks, one or more satellite networks, one or more private networks, one or more public networks, etc. As used above and in this article, the term "communication" (including its variants (such as secure or non-secure communication, compressed or non-compressed communication, etc.)) covers direct communication or indirect communication through one or more intermediate components, and does not require direct physical (such as wired) communication or continuous communication, but includes selective communication at regular or irregular intervals and one-time events.

[0033] Network device 102 may refer to any device that connects client device 104 to other devices within network 100. Figure 1 In the example, the network device 102 has a direct connection with the client device 104 via the transmission medium 106. In other examples, the network device 102 can communicate with the client device 104 indirectly by exchanging data across one or more intermediate devices. The network device 102 can operate using various network communication protocols and perform various cellular network operations. For example, the network device 102 can be implemented as one or more of a base station, a cellular tower, a signal repeater, a macro remote radio unit (RRU), a multiple input multiple output (MIMO) antenna system, a distributed antenna system (DAS), etc. Therefore, the network device 102 does provide frequency distribution information in some examples and does not provide frequency distribution information in other examples.

[0034] Client device 104 refers to any endpoint device capable of connecting to network 100. Thus, client device 104 may form a request for data in response to input from a user and transmit the request over network 100. Example devices that may implement client device 104 may include, but are not limited to, mobile phones, smart vehicles, wearable devices, and the like.

[0035] exist Figure 1 In the example, the network device 102 and the client device 104 communicate with each other using a cellular network protocol (e.g., 3G, 4G LTE, 5G, etc.). In other examples, the network device 102 and the client device 104 may use different wireless or wired communication protocols, including but not limited to Universal Serial Bus (USB), Ethernet, Wi-Fi, etc. Near Field Communication (NFC), Orthogonal Frequency Division Multiplexing (OFDM), Code Division Multiple Access (CDMA), etc. In some examples, the type of communication protocol used between network device 102 and client device 104 is based in part on whether transmission medium 106 is a wired or wireless medium.

[0036] Controller circuitry 108 receives data from a source (e.g., internal memory, client device 104, etc.) and performs operations in response to the data. For example, controller circuitry 108 generates a digital input signal x(n) to be provided to client device 104. Controller circuitry 108 also determines whether transmitter circuitry 110 performs PC-CFR operation or W-CFR, as taught herein. Similarly, controller circuitry 118 receives data from a source and performs operations in response to the data. Controller circuitry 108 and 118 can be implemented by any type of programmable circuitry. Examples of programmable circuitry include a programmable microprocessor, a field programmable gate array (FPGA) that can instantiate instructions, a central processor unit (CPU), a graphics processor unit (GPU), a digital signal processor (DSP) or a microcontroller and an integrated circuit (IC), such as an application-specific integrated circuit (ASIC).

[0037] Transmitter circuitry 110 and transmitter circuitry 116 receive digital signals from controller circuitry 108 and controller circuitry 118, respectively. Transmitter circuitry 110 and transmitter circuitry 116 each perform signal processing operations including CFR as taught herein. Thus, example transmitter circuitry 110 and transmitter circuitry 116 may be implemented within network device 102 and client device 104, respectively, at a lower cost and in a smaller size than other transmitter devices. Figure 2 Transmitter circuitry 110 is further described.

[0038] Receiver circuitry 112 receives analog signals transmitted by transmitter circuitry 116, converts the analog signals to digital signals, and provides the digital signals to controller circuitry 108. Similarly, receiver circuitry 114 receives analog signals transmitted by transmitter circuitry 110, converts the analog signals to digital signals, and provides the digital signals to controller circuitry 118.

[0039] Figure 2 yes Figure 11 is a block diagram of an example implementation of a transmitter circuit system. The transmitter circuit system 110 includes an example CFR circuit system 202, an example digital pre-distortion (DPD) corrector circuit system 204, an example DPD estimator circuit system 206, an example capture subsystem circuit system 208, an example transmitter (TX) digital circuit system 210, an example TX digital-to-analog converter (DAC) circuit system 212, an example TX digital step attenuator (DSA) circuit system 218, an example power amplifier (PA) circuit system 220, an example antenna 224, an example feedback (FB) DSA 226, an example FB analog-to-digital conversion circuit system (ADC) 228, and an example FB digital circuit system 230. Figure 2 Also included are an example mode selection signal 200, an example input signal 201 (referred to herein as x(n) 201) and an example modified signal 203 (which may be referred to herein as y(n) 203), and an example output signal 221 (which may be referred to herein as z(t) 221).

[0040] Mode selection signal 200 is a signal generated by controller circuitry 108 that indicates whether CFR circuitry 202 uses the PC-CFR technique or the W-CFR technique. In some examples, mode selection signal 200 is a predetermined value in response to the availability of frequency distribution information as described above.

[0041] The CFR circuit system 202 reduces and removes peaks in x(n) 201 to produce a modified signal y(n) 203 having a lower PAR than x(n) 201. By reducing and removing peaks, y(n) 203 may have fewer envelope excursions that violate a target peak limit than x(n) 201. Peak limit violations that remain in y(n) 203 may also have smaller magnitudes than those of x(n) 201. The example CFR circuit system 202 produces y(n) 203 by performing a PC-CFR operation or a W-CFR operation without an FIR filter, as taught herein. The CFR circuit system 202 determines which CFR technique to use in response to the mode selection signal 200. The CFR circuit system 202 may be configured to generate a CFR signal having a lower PAR than x(n) 201. Figure 3 CFR circuitry 202 is further described. In some examples, CFR circuitry 202 is instantiated by programmable circuitry that executes CFR instructions or is configured to perform operations (such as by Fig. 9 and Fig.10 (or operations represented by the flowchart(s)).

[0042] The DPD corrector circuitry 204 pre-distorts y(n) 203 to counteract distortion that occurs when the signal is transmitted over the transmission medium 106 using the PA circuitry 220. The DPD corrector circuitry 204 forms a pre-distorted version of y(n) 203 using various configuration parameters. The values ​​of the configuration parameters are updated by the DPD estimator circuitry 206 in response to the output of the capture subsystem circuitry 208. The capture subsystem circuitry 208 samples y(n) 203, the output of the DPD corrector circuitry, and z(t) 221 (e.g., the output of the PA circuitry 220) to help determine how y(n) 203 will be pre-distorted. One or more of the DPD corrector circuitry 204, the DPD estimator circuitry 206, or the capture subsystem circuitry 208 may be implemented by any type of programmable circuitry. In some examples, the DPD corrector circuitry 204 is instantiated by a programmable circuitry that executes DPD corrector instructions or is configured to perform operations (such as by Fig. 9 and Fig.10 (or operations represented by the flowchart(s)).

[0043] TX digital circuitry 210 interpolates the output of DPD corrector circuitry 204 to introduce additional data points. The additional data points increase the sampling rate of the modified signal relative to the sampling rate of the original input signal x(n) 201 for efficient digital-to-analog conversion using TX DAC circuitry 212.

[0044] The example TX DAC circuitry 212 converts the output of the TX digital circuitry 210 from a digital signal to an analog signal.Thus, the information transmitted across the transmission medium 106 is encoded continuously across a range of voltages rather than a discrete set of voltages.

[0045] The example TX DSA circuitry 218 attenuates the aforementioned analog signal in order to compensate for gain variations in the PA circuitry 220. The TX DSA circuitry 218 performs the attenuation in response to the gain of the PA circuitry 220 (which may vary in response to temperature). The PA circuitry 220 then amplifies the interpolated and attenuated signal to produce z(t) 221, which is transmitted across the transmission medium 106 via the antenna 224. The amplification of the PA circuitry 220 introduces nonlinearities that are offset by the predistortion of the DPD corrector circuitry 204. In some examples, the PA circuitry 220 is instantiated by programmable circuitry that executes PA instructions or is configured to perform operations (such as by Fig. 9 and Fig.10 (or operations represented by the flowchart(s)).

[0046] FB DSA circuitry 226 receives analog signal z(t) 221 from PA circuitry 220 and attenuates the signal. In some examples, FB DSA circuitry 226 attenuates z(t) 221 in response to operating parameters of FB ADC circuitry 228.

[0047] FB ADC circuitry 228 converts the attenuated version of z(t) 221 from an analog signal back to a digital signal. FB digital circuitry 230 then reduces the sampling rate of the digital signal. The resulting signal is obtained by capture subsystem circuitry 208 for interpretation by DPD estimator circuitry 206 and controller circuitry 108.

[0048] Figure 3 yes Figure 2 2 is a block diagram of an example implementation of a crest factor reduction (CFR) circuit system 202 for generating a modified signal y(n) 203 having a lower PAR than an original input signal x(n) 201. The CFR circuit system 202 includes an example delay circuit system 302, an example multiplier 304, an example adder 306, an example multiplexer 308 (which may be referred to as mux 308 hereinafter), an example interpolator circuit system 310, an example envelope computer circuit system 312, an example peak attribute extractor circuit system 314, and an example peak limited waveform generator (PLWG) circuit system 316. The PLWG circuit system 316 includes an example mode switcher circuit system 318, an example memory 320, and an example multiplier pool 324. The memory 320 includes example registers 321 and 322. The multiplier pool 324 includes an example multiplier 325 and an example multiplier 326. Figure 3 Also included is an example PLW signal 317 (which may be referred to herein as b w (n) 317) and an example cancellation signal 319 (which may be referred to herein as b pc (n) 319). In some examples, multiplier 304 or adder 306 may be individually or collectively referred to as arithmetic circuitry.

[0049] The example delay circuit system 302 outputs a delayed copy of the original input signal x(n) 201. For example, the delay circuit system 302 may receive sample n=0 from x(n) 201 (e.g., receive x(0)) at T0 and output the sample at T1. The amount of time between the output and input of the delay circuit system 302 (e.g., the difference between T0 and T1) is set so that the multiplier 304 and the adder 306 receive inputs with matching sample indices. For example, the multiplier 304 may receive x(0) and b(0) at T1. w (0), receiving x(1) and b at T2 w(1), or more generally, at any time we receive x(n) and b w (n) 317, where n is any integer. Similarly, adder 306 receives x(n) and b at any time. pc (n) 319, where n is an arbitrary integer. Thus, the magnitude of the delay produced by delay circuitry 302 is responsive to the amount of time required by interpolator circuitry 310, envelope computer circuitry 312, peak attribute extractor circuitry 314, and PLWG circuitry 316 to perform their operations.

[0050] Multiplier 304 combines the delayed version of the samples from x(n) 201 that correspond in time to each other with the samples from b w Similarly, adder 306 multiplies the samples from x(n) 201 that correspond in time to each other with the delayed version of samples from b(n) 317. pc (n)319 samples are added. w (n)317 and b pc (n) 319 are both generated by mode switcher circuitry 318 and are described further below.

[0051] The mux 308 obtains the signal formed by the product from the multiplier 304 and the signal formed by the sum from the adder 306. The mux 308 outputs one of the two input signals to form the modified signal y(n) 203. The mux 308 determines which input will form y(n) 203 in response to the mode selection signal 200. If the mode selection signal 200 indicates that the W-CFR technique is to be used, the mux 308 uses the output of the multiplier 304 to form y(n) 203. Alternatively, if the mode selection signal 200 indicates that the PC-CFR technique is to be used, the mux 308 uses the output of the adder 306 to form y(n) 203.

[0052] Mode selection signal 200 is a static configuration value based on a specific use case (e.g., whether frequency distribution information as described above is present). Thus, in some examples, a designer or manufacturer of network device 102 can configure a specific instance of CFR circuit system 202 to only perform required operations (e.g., use adder 306 when frequency distribution information is present, and use multiplier 304 when frequency distribution information is not present), thereby saving power.

[0053] The original input signal x(n) 201 is a digital signal formed of discrete samples. In some examples, the sampling frequency of the discrete samples in x(n) is low enough so that when the TX digital circuit system 210 interpolates the samples and / or the TX DAC circuit system 212 converts the signal to an analog signal, a peak is formed between two of the discrete samples. Therefore, the interpolator circuit system 310 adds new data points between the existing data points of x(n) 201 (e.g., interpolates x(n) 201) so that any peaks that may be achieved at an increased sampling rate or in the analog signal can be detected and mitigated. The interpolator circuit system 310 can use any suitable interpolation technique, including but not limited to linear interpolation, polynomial interpolation, nearest neighbor interpolation, etc. In some examples, the output of the interpolator circuit system 310 may have twice or four times more samples than x(n) 201. In other examples, the output generated by the interpolator circuit system 310 has a different number of data points. The output of the interpolator circuit system 310 may be referred to herein as x int (n).

[0054] Envelope computer circuitry 312 generates x int (n). In general, the CFR technique operates by identifying locations in the (possibly interpolated) input signal where envelope values ​​violate a pre-specified threshold (which may be referred to as a peak limit). The CFR technique also selects appropriate local maxima in the envelope signal as "peaks" that need to be addressed for crest factor reduction. The output of the envelope computer circuitry 312 may be referred to as |x int (n)|2.

[0055] The peak attribute extractor circuitry 314 identifies the peak location in the input envelope and determines the envelope signal at the identified peak location |x int (n)|2. The attributes determined by the peak attribute extractor circuit system 314 may include, but are not limited to: {ni, ci, ri2, ai}. Here, ni refers to the sample index n of the i-th peak in the envelope signal. ci refers to the composite sample of the i-th peak. The peak attribute extractor circuit system 314 outputs ci in response to the mode selector signal 200 indicating the use of the PC-CFR technique. Combined Figure 8 ci is further described. ri2 refers to the squared amplitude of the ith peak in the envelope signal. ai refers to the expected attenuation factor ai for the ith peak. The expected attenuation factor ai quantifies the reduction in amplitude of the signal output by the CFR circuit system 202. The value of ai is given by (λ / ri), where λ is a threshold value that describes the maximum expected amplitude of y(n) 203, and ri is the amplitude of the ith peak. In some examples, the peak attribute extractor circuit system 314 also generates other attributes in addition to or instead of {ni,ci,ri2,ai}.

[0056] Within PLWG circuitry 316, mode switcher circuitry 318 uses one or more of {ni, ci, ri2, ai} to calculate b pc (n) 319 or b w (n) 317. If the mode selection signal 200 indicates the use of PC-CFR technology, the mode switch circuit system 318 uses {ni, ci, ri2} and the PCW stored in the memory 320 to form b pc (n) 319. Alternatively, if the mode selection signal 200 indicates the use of the W-CFR technique, the mode switch circuitry 318 uses {ni, ai} and the windowing function samples from the memory 320 to form b w (n) 317. The mode switch circuitry 318 may be implemented by any type of programmable circuitry and may be combined with Figure 4 is further described.

[0057] Within memory 320, registers 321 and 322 refer to different sets of addresses. Memory 320 includes two terminals (e.g., communication interfaces, ports, pins, etc.) so that registers 321 and 322 can be accessed in parallel by mode switch circuitry 318. PLWG circuitry 316 stores different types of data in registers 321 and 322 in response to mode selection signal 200. Figure 8 As described above, if the mode selection signal 200 indicates that the PC-CFR technique is used, registers 321 and 322 will store the real and imaginary components of the composite valued PCW samples. In some examples, the real and imaginary components of the PCW are referred to as I samples and Q samples, respectively. Conversely, if the mode selection signal 200 indicates that the W-CFR technique is used, registers 321 and 322 store full and half copies of the normalized real-valued windowing function. The real and imaginary components of the PCW samples are referred to as I samples and Q samples, respectively. Figure 5A and Fig. 6A The aforementioned full replica and half replica are further described.

[0058] The multiplier pool 324 is a multiplier pool used by the mode switch circuit system 318 to generate b w (n) 317 or b pc (n) A collection of multiplier circuits of 319. Figure 8As further described, if the mode selection signal 200 indicates that the PC-CFR technique is to be used, some or all of the multiplier pool 324 is used to calculate a phasor (compound scaling factor) that is used to scale and rotate the PCW component to create the cancellation pulse. Conversely, if the mode selection signal 200 indicates that the W-CFR technique is to be used, the mode switcher circuit system 318 uses multipliers 325 (a first subset of the multiplier pool 324) to calculate the scaling factor for the i-th peak. The mode switcher circuit system 318 simultaneously uses multipliers 326 (a second subset of the multiplier pool 324) to calculate the scaling factor that together forms b w (n) 317 PLW samples. Combined Figure 5B , Figure 6B and Figure 8 Multipliers 325 and 326 are further described.

[0059] Memory 320 and multiplier pool 324 are both examples of computing resources that are shared across PC-CFR operations and W-CFR operations. Such resource sharing enables CFR circuit system 202 to perform PC-CFR operations and W-CFR operations in response to the availability of frequency distribution information as described above, and enables CFR circuit system 202 to be implemented in a small size and at a low cost compared to a hypothetical device that supports PC-CFR and W-CFR as two independent subsystems (e.g., as two separate entities within a transmitter device).

[0060] Figure 4 yes Figure 3 1. A block diagram of an example implementation of a mode switch circuit system 318 for generating a mode switch circuit system ... w (n) 317 PLW samples or form b pc (n) 319 of the elimination pulse sample. The mode switch circuit system 318 can be instantiated (e.g., an instance of it is created, caused to occur for an arbitrary period of time, embodied, implemented, etc.) by a programmable circuit system (such as a central processing unit (CPU)) executing a first instruction. In addition, Figure 3 The mode switch circuit system 318 may be instantiated (e.g., an instance of it is created, caused to occur for an arbitrary period of time, embodied, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) or (ii) a field programmable gate array (FPGA) that is constructed or configured to perform an operation corresponding to the first instruction in response to the execution of the second instruction. Thus, Figure 4 Some or all of the circuitry of may be instantiated at the same or different times. For example, Figure 4 Some or all of the circuitry of can be instantiated in one or more threads that execute concurrently on hardware or serially on hardware. In addition, in some examples, Figure 4 Some or all of the circuitry of may be implemented by a microprocessor circuitry that executes instructions or an FPGA circuitry that performs operations to implement one or more virtual machines or containers. Figure 4 The mode switch circuitry 318 is shown to include Figure 2 4 , example mode select signal 200, example inverter 404, example switch signal 406, switches 409, 411, and 413, example effective weight generator (EWG) circuitry 410, example composite waveform generator (CWG) circuitry 412, and example PC-CFR circuitry 414. In some examples, the EWG circuitry and the CWG circuitry 412 are collectively referred to as W-CFR circuitry.

[0061] exist Figure 4 In the example of FIG. 4 , the mode selection signal 200 is represented as a binary signal such that a logic “1” represents PC-CFR and a logic “0” represents W-CFR, and vice versa. In other examples, the mode selection signal 200 is implemented by a different technique of indicating a state (e.g., an interrupt, setting a bit flag in a register, etc.). The inverter 404 receives the mode selection signal 200 and generates a switch signal 406. Therefore, the switch signal 406 and the mode selection signal 200 are inverted binary signals (e.g., when one signal is a logic “1”, the other signal is a logic “0”, and vice versa).

[0062] Mode selection signal 200 is used to open or close switch 413, while switch signal 200 is used to open and close switches 409 and 411. Therefore, at any point in time: either a) switches 409 and 411 are closed, while switch 413 is open; or b) switches 409 and 411 are open, while switch 411 is closed.

[0063] When the mode selection signal 200 and the switch signal 406 indicate the use of the W-CFR technique, switches 409 and 411 are closed. In such an example, the EWG circuit system 410 obtains one or more parameters from the peak attribute extractor circuit system 314, obtains a value from a portion of the memory 320, and accesses the multiplier pool 324. The EWG circuit system 410 uses this resource to generate a scaling factor as described in the teachings herein. Given a scaling factor di, the following quantity is quantized: for |x int The i-th peak within (n)|2, the amount by which the window function is to be scaled up or down. Figure 5B The EWG circuitry 410 is further described.

[0064] When enabled by switch signal 406, CWG circuitry 412 uses the scaling factors generated by EWG circuitry 410, parameters from peak attribute extractor circuitry 314, and portions of memory 320 and multiplier pool 324 to generate b w (n) 317, as taught herein. Figure 5B The EWG circuitry 410 is further described.

[0065] When the mode selection signal 200 and the switch signal 406 indicate the use of the PC-CFR technique, the switch 413 is closed. In such an example, the PC-CFR circuit system 414 obtains one or more parameters from the peak attribute extractor circuit system 314, obtains the PCW sample from the memory 320, and accesses a portion of the multiplier pool 324 to generate b pc (n) 319. Will combine Figure 5B PC-CFR circuitry 414 is further described.

[0066] exist Figure 4 In the example of FIG. 1 , switches 409, 411, and 413 are used to configure the mode switcher circuit system 318 to implement the PC-CFR technique or the W-CFR technique in response to the mode selection signal 200 (which is a static value determined based on the use case of the network device 102). In other examples, different techniques (e.g., different configurations of switches, implementations without switches, etc.) are used to configure the mode switcher circuit system 318 to implement the PC-CFR technique or the W-CFR technique in response to the mode selection signal 200.

[0067] Figure 5A is the normalized window function (which may be referred to as w above and herein). h The window function w(n) is a normalized shape that, when appropriately scaled and combined by the EWG circuitry 410 and the CWG circuitry 412, will form b w (n) 317, and can be used to attenuate the peak of x(n) 201. In the examples described herein, w(n) is a windowing function. Examples of windowing functions include, but are not limited to, Hann window, Hamming window, Blackman-Harris window, etc. In other examples, w(n) is a different standardized shape.

[0068] PLWG circuitry 316 scales and combines the copies of the window function under the assumption that the width of a given copy of the window function is centered in time around a particular peak. h(n) 500, which represents only half of the normalized window shape, because the scaling factors di generated by the EWG circuitry 410 can only be determined in response to previous peaks, not future peaks. Figure 5A w is shown by indicating that there are L / 2+1 non-zero samples h (n)500 is half the normalized window shape, where L+1 is the number of non-zero samples in w(n). Figure 5B The EWG circuit system 410 is further described in h (n) Use of 500.

[0069] Figure 5B yes Figure 4 A block diagram of an example implementation of an effective waveform weight generation (EWG) circuit system. Figure 5B include Figure 3 321 and multiplier 325 in . Register 321 includes individual indexes 321-1, 321-2, ..., and 321-(R-1). Similarly, multiplier 325 includes individual multipliers 325-1, 325-2, ..., and 325-(R-1). Figure 5B Also included is an example tapped delay line 502 consisting of indexes 502 - 1 , 502 - 2 , . . . , 502 -(R− 1 ), and example adders 506 and 508 .

[0070] The EWG circuit system 410 generates a scaling factor di that represents the relative magnitude of a given (e.g., i-th) peak. In some examples, di is referred to as a weight. The EWG circuit system 410 does not operate continuously, but generates a weight value in response to the circuit being triggered. The circuit detects |x int (n)|2, the peak attribute extractor circuit system 314 indicates the peak by an appropriate change in the value of ni. For example, the value of ni may indicate that the first peak is at |x int The sample of (n)|2 is at n=0, the second peak is at n=50, and so on.

[0071] When the value of ni received at switch 409 indicates that the i-th peak has been detected, the most recently calculated weight d i-1 Stored at index 502-1, the second weight d i-2 Move to index 502-1, ...., second oldest weight d i-(R-1) Move to index 502-R, and the oldest value d i-R is removed. Thus, the tapped delay line 502 can be referred to as a first-in, first-out (FIFO) buffer that stores the weights of the previous R-1 peaks. The R-1 weights allow any given sample to be wThe value of (n) 317 cancels the effect of R-1 many previous peaks within x(n) 201. In some examples, the value of R is between approximately eight and twelve. In other examples, the value of R is a different number.

[0072] As mentioned above, register 321 stores w h (n) samples of 500. In addition to updating the tapped delay line 502, the detection of the peak also changes w h (n) Which samples of 500 (e.g., which specific indices of register 321) are used as input by multiplier 325. For example, when calculating the weight d of the i-th peak, multiplier 325-1 uses index 321-1 to obtain sample w h [n i -n i-1 ], which is a sample whose index is determined by the current peak index (n i ) and the previous first peak index (n i-1 ) is given by the difference between . Similarly, multiplier 325-2 uses index 321-2 to obtain w h [n i -n i-2 ], which is a sample whose index is determined by the index of the current peak value (n i ) and the second peak index before (n i-2 ) is given by the difference between the indices of h The samples of (n)500 represent the most recent R-1 peak indices relative to the current peak index.

[0073] When the EWG circuit system 410 is triggered, the multiplier 325-1 will correspond to the half-replica waveform sample w of the first previous peak. h [n i -n i-1 ] and the weight of the first peak before d i-1 The resulting product is a value that indicates how much the current peak (e.g., the i-th peak) will be attenuated due to its proximity to the first previous peak (e.g., the (i-1)-th peak) affecting the amplitude of the current peak. Similarly, the other multipliers 325 generate products that indicate how much the current peak will be attenuated due to its proximity to the most recent R-1 peaks.

[0074] Adder 506 adds the products produced by multiplier 325 to each other. The term (1-ai) represents the overshoot factor of the ith peak (e.g., the amount by which the ith peak has exceeded the expected maximum amplitude of y(n) 203) and is responsive to the attenuation factor (ai) produced by peak attribute extractor circuitry 314. Finally, adder 508 subtracts the sum of adder 506 from (1-ai) and replaces any negative values ​​with zero (in Figure 5BIn determining the weight of the current peak, the calculations of adders 506 and 508 effectively subtract the continued influence of the previous peak at the current peak position.

[0075] Other ways of calculating W-CFR are as follows: int (n)|2. The FIR filter that is always running is sampled at a specific time point corresponding to the peak value in |2. However, as described above, the continuous use of the FIR filter requires a lot of space and consumes a lot of power. In contrast, the EWG circuit system 410 only generates an output when a new peak value is detected by the peak attribute extractor circuit system 314. In addition, the EWG circuit system 410 uses a fixed number of computing resources: R-1 indexes of the memory in the tapped delay line 502, R-1 multipliers from the multiplier 325, and R-1 indexes of the memory from the register 321, where R can be any integer, but can generally be implemented between eight and twelve. In contrast, as described above, the FIR filter can use thousands of memory indexes and multipliers. Therefore, compared with other methods that rely on FIR filters, the EWG circuit system 410 uses fewer computing resources and consumes less power to generate peak scaling factors.

[0076] In the above example, the EWG circuitry 410 will generate w when triggered by the detection of a new peak. h The appropriate value of (n)500 is moved into the specific group index (325-1, 325-2, ..., 325-(R-1)). Figure 5B In the example, the multiplier 325 repeatedly selects inputs from the same group index. In other examples, the values ​​are not moved between indexes. Instead, when a peak is detected, the EWG circuit system 410 causes the multiplier to access different values ​​from different indexes.

[0077] Fig. 6A is an example graph 600 of a complete copy of a normalized window function (which may be referred to herein as w f (n) 600). Before any scaling occurs, Fig. 6A Show w f (n)600 evaluates to 0 when n=0, evaluates to 1 when n=L / 2, and evaluates to 0 when n=L. Therefore, w f (n) 600 is the combination of the above Figure 5A The normalized window function w f The CWG circuitry 412 uses w f (n)600, not w h (n)500, so that b w(n) 317 not only makes the specific sample index n corresponding to the peak i Attenuation also attenuates the neighboring indices before and after the peak that are affected by the peak neighborhood. Figure 6B Further description of the operation of CWG circuit system 412 f (n) Use of 600.

[0078] Figure 6B yes Figure 4 4 is a block diagram of an example implementation of a CWG circuit system 412. Figure 6B include Figure 3 322 and multiplier 326, example adders 606 and 608, and example signal 607. Multiplier 326 includes individual multipliers 326-1, 326-2, ..., 326R. Register 322 includes indexes 322-1, 322-2, ..., 322-R.

[0079] CWG circuitry 412 generates b using the scaling factors generated by EWG circuitry 410, portions of shared memory 320 and multiplier pool 324, and parameters determined by peak attribute extractor circuitry 314. w (n) 317. Unlike EWG circuitry 410, CWG circuitry 412 operates continuously so that b is generated for each sample n. w (n)317. When the value of ni indicates |x int When a new peak is detected in (n)|2, w The value used in the calculation of (n) 317 changes, triggering the CWG circuitry 412 to update.

[0080] CWG circuitry 412 contributes one index from register 322 and one multiplier from multiplier 326 to each peak that is attenuated in parallel. Thus, register 322 has a total of R indices, and there are a total of R multipliers in multiplier 326. As described above, R may be any positive integer, and in some examples may be implemented between eight and twelve.

[0081] When the value of ni received from switch 411 indicates that the i-th peak has been detected, multiplier 326 updates the set of weights used as input. For example, multiplier 326-1 stops using weight d i-1 As input, and instead uses weight di immediately after it is generated by EWG circuitry 410. Similarly, in response to detecting a new peak, multiplier 326-2 stops using weight d i-2 , and start using weight d i-1 As input, ..., and multiplier 326-R discards weight d i-R , and use weight d insteadi-(R-1) as input.

[0082] As above combined Fig. 6A As described above, register 322 stores w f (n) 600 samples. In addition to updating which weights are used as input, the detection of a peak also changes w f Which samples of (n) (e.g., which particular indices of register 322) are used as input by multiplier 326. For example, when b is updated in response to detecting the i-th peak w When the value of (n) 317 is equal to 1, multiplier 326-1 uses index 322-1 to obtain w f [n-ni], which is a sample of the full copy waveform, the index of which is the sum of the current index and the index of the ith peak (n i ) is given by the difference between . Similarly, multiplier 326-2 uses index 322-2 to obtain w as a sample f [nn i-1 ], the index of which is given by the difference between the current index and the index of the (i-1)th peak. In total, w obtained by multiplier 326 f A particular sample of (n) represents the R most recent peak indices relative to the current sample index.

[0083] When the CWG circuitry 412 is triggered, the multiplier 326-1 converts the full replica waveform sample w corresponding to the current peak value to f [n-ni] is multiplied by the weight di of the current peak. The resulting product is a value that represents the magnitude of the PLW at the current index if the PLW eliminates only the current peak. Similarly, the other multipliers 326 generate products that represent the magnitude of the PLW with the R most recent peaks eliminated. In some examples, such as Figure 6B As shown, the products of multiplier 326 may be referred to as partial results, which correspond to respective peaks in input signal x(n) 201 .

[0084] Adder 606 adds the values ​​of multiplier 326 into a single value. Adder 608 then subtracts signal 607 (which is the output of adder 606) from value 1. In some examples, signal 607 may be referred to as an output waveform. The resulting sum is b w The value of (n) 317 corresponds to sample n from x(n) 201.

[0085] Figure 7 Is Figure 4 Graphs of illustrative examples of operations performed by EWG circuitry and CWG circuitry. Figure 7The example graph 700 and the example graph 702 are included. The graph 700 includes an example |x(n)| signal 704, an example |y(n)| signal 706, and b w (n) 317. Graph 702 includes signal 607. The x-axis of both graphs 700 and 702 is aligned with sample index n. In the examples described herein, new samples are created by periodic measurements such that n=0 refers to the same point in time across all signals using digital sample index n.

[0086] exist Figure 7 In the example of , |x(n)| signal 704 represents the envelope of input signal x(n) 201. Similarly, |y(n)| signal 706 represents the envelope of input signal x(n) 203. The envelope of a signal refers to the boundary within which the signal is contained when viewed in the time domain. Therefore, |x(n)| signal 704 and |y(n)| signal 706 contain only non-negative values.

[0087] Graph 700 shows a segment of |x(n)| 704. The segment includes four local maxima, but only two of the local maxima have values ​​above λ (the desired maximum value of |y(n)| 706). Therefore, peak attribute extractor circuitry 314 treats the values ​​of r1 and r2 as peaks to be attenuated and does not classify the other two local maxima as peaks.

[0088] Graph 700 shows that b w (n) 317 has a value of 1 when there is no peak in |x(n)| 704, and has a local minimum value when there is a peak. Specifically, adder 608 performs the above combination Figure 6B The operation described above forms b in the form of a shifted and reflected version of signal 607. w (n)317.

[0089] For a given index n, multiplier 304 multiplies the value of x(n) 201 by b w The values ​​of x(n) 317 are multiplied to produce y(n) 203. The resulting modified signal: a) reduces the amplitude of the peak to λ, thereby reducing PAR, b) ensures that the amplitude reduction occurs in a smooth manner near the peak, thereby maintaining signal integrity, and c) mitigates the amount of distortion that occurs to neighboring samples of x(n) that have fallen below λ.

[0090] Graph 702 shows that signal 607 includes w f (n) multiple copies of 600 that are scaled and shifted in time. Specifically, w f A copy of (n) 600 is scaled by d1 and shifted to be centered on n1 (the index corresponding to the middle of the first peak). Similarly, w fThe second copy of (n) 600 is scaled by d2 and shifted to be centered on n2 (the index corresponding to the middle of the second peak). Figure 5B As described above, weights d1 and d2 are based in part on attenuation factors a1 and a2 provided by peak attribute extractor circuitry 314, and are also responsive to the weights of the R previous peaks. Thus, if two peaks of |x(n)| 704 are close enough that the tails of the peaks overlap in time, then b w The value of (n) 317 will be non-zero at this point in time to reflect the impact of the two peaks.

[0091] Figure 8 yes Figure 4 804 . The PC-CFR circuit system 414 includes an example phasor computer circuit system 802 , an example cancellation signal generator circuit system 804 , and an example PCW sample 806 .

[0092] When mode select signal 200 indicates the use of PC-CFR techniques, phasor computer circuitry 802 obtains the complex sample ci of the ith peak. Peak attribute extractor circuitry 314 stores the real and imaginary components of PCW in registers 321 and 322, which are accessed by PC-CFR circuitry 414 via switch 413 as described above. Phasor computer circuitry 802 uses ci to determine the value of aie jΦi The cancellation phasor is given by , where j is the square root of -1, and i is the index of the current peak, and Φi is related to the phase of the complex sample corresponding to the current peak.

[0093] The elimination phasor representation is generated by the pulse generator circuit system b pc 819. For example, the cancellation signal generator circuit system 804 uses the cancellation phasor to scale and rotate specific values ​​from the PCW samples 806. The PCW samples 806 refer to data points (e.g., composite samples) that together form the PCW. Unlike the windowing function in the W-CFR technique, the PCW in the PC-CFR technique is a composite waveform that responds to the frequency distribution information of the signal. The cancellation signal generator circuit system 804 combines up to R scaled and rotated PCW values ​​to form b pc (n) 319. In some examples, PCW samples 806 are stored in memory 320.

[0094] Each time a new peak is detected, the phasor computer circuitry 802 calculates aie jΦi The cancellation signal generator circuitry 804 uses up to 4R multipliers to form b pc(n) 319, where R can be any positive integer, and as described above, in some examples is between approximately eight and twelve. Because the 4R multipliers are part of the multiplier pool 324, they can also be used to form the weights d when the mode selection signal 200 indicates that the W-CFR technique is to be used. i or b w (n) 317. Similarly, the peak attribute extractor circuitry 314 uses registers 321 and 322 to store the real and imaginary components of PCW when PC-CFR is used, but stores w when W-CFR is used. h (n)500 and w f (n) Sample of 600. Therefore, the CFR circuitry 202 described herein may be implemented using fewer computing resources than other devices that implement the PC-CFR and W-CFR as two separate systems.

[0095] Fig. 9 is a flow diagram representative of example machine-readable instructions or example operations 900 that may be executed, instantiated, or performed by programmable circuitry to implement the transmitter circuitry 110 described herein. Fig. 9 The example machine readable instructions or example operations 900 begin with the CFR circuit system 202 obtaining an input signal x(n) 201. (Block 902). The input signal x(n) 201 is a digital signal generated by the controller circuit system 108. The input signal x(n) 201 may contain any type and format of information (e.g., text, audio, etc.).

[0096] Controller circuitry 108 determines whether frequency distribution information for the incoming signal is available. (Block 904). As described above, the frequency distribution information describes the frequency spectrum occupancy of the signal to be transmitted. In some examples, the frequency distribution information is referred to as system-level data because it is provided to CFR circuitry 202 from an external component (e.g., controller circuitry 108). The frequency distribution information is used to implement PC-CFR operations as described above. In some examples, the availability of the frequency distribution information depends on the availability of the frequency distribution information as described above. Figure 1 The type of network device 102 implemented in.

[0097] If frequency distribution information is available (block 904: YES), PC-CFR circuitry 414 generates a cancellation signal (eg, b) using the input signal, the frequency information, memory 320, and multiplier pool 324. pc (n) 319). (Block 906). The cancellation signal of block 906 is referred to above as b pc (n) 319. In order to generate b pcThe PC-CFR circuit system 414 generates a cancellation phasor based on the peak properties of the input signal x(n) 202 and generates PCW samples based on the frequency information. The PC-CFR circuit system 414 then uses the memory 320 and the multiplier pool 324 to scale and rotate the PCW samples based on the cancellation phasor to form Figure 8 The generation of b pc (n) 319. The controller circuitry 108 indicates that frequency distribution information is available by setting the mode select signal 200 to indicate that PC-CFR is to be used.

[0098] The adder 306 adds the cancellation signal to the input signal x(n) 201. (Block 908). pc The addition of y(n) 319 removes peaks present within the envelope of input signal x(n) 201. Thus, CFR circuitry 202 produces y(n) 203, a modified version of x(n) 201, which has a lower PAR than x(n) 201, as described above.

[0099] If the frequency distribution information is not available (block 904: No), the EWG circuitry 410 and the CWG circuitry 412 jointly form a PLW signal using the memory 320 and the multiplier pool (block 910). The PLW signal of block 910 is referred to above as b w (n) 317. Controller circuitry 108 indicates that frequency distribution information is available by setting mode selection signal 200 to indicate that PC-CFR is to be used. Note that EWG circuitry 410 and CWG circuitry 412 together form the PLW signal using fewer resources and less space than other devices using W-CFR technology. Fig.10 Block 910 is further described.

[0100] Multiplier 304 multiplies the PLW signal of block 910 with input signal x(n) 201. Multiplication of the PLW signal attenuates peaks present in input signal x(n) 201. Thus, CFR circuitry 202 generates y(n) 203, a modified version of x(n) 201, which has a lower PAR than x(n) 201, as described above.

[0101] Regardless of whether the PC-CFR technique or the W-CFR technique was previously used, the DPD corrector circuitry 204 digitally pre-distorts the modified version of the input signal. (Block 914). The DPD corrector circuitry 204 pre-distorts y(n) 203 to counteract the distortion that will occur when z(t) 221 travels across the transmission medium 106. In addition, because y(n) 203 has a lower PAR (and thus improves utilization of the circuit's dynamic range), using y(n) 203 allows components in the transmitter circuitry 110 to operate more efficiently than using x(n) 201.

[0102] PA circuitry 220 transmits the predistorted and modified version of the input signal. (Block 916). One or more components may perform operations between blocks 914 and 916, including, but not limited to, TX digital circuitry 210, TX DAC circuitry 212, and TX DSA circuitry 218. Example machine-readable instructions or operations 900 end after block 916.

[0103] Fig.10 It is meant to be performed, instantiated or implemented using an example programmable circuit system to use, for example, in combination with Fig. 9 A flowchart of example machine readable instructions or example operations for generating a peak limited waveform (PLW) signal using the memory and multiplier described above. Specifically, Fig.10 A flowchart is provided Fig. 9 An example implementation of block 910 of .

[0104] Execution of block 910 begins with the PLWG circuitry 316 storing a full copy and a half copy of the normalized windowed waveform in parallel access memory. (Block 1002). As described above, the full copy of the windowed waveform w f (n) 600 is stored in register 322, and a half copy of the windowed waveform w h (n)500 is stored in Figure 3 The normalized windowed waveform may have any standardized shape and may include any number of samples.

[0105] EWG circuitry 410 multiplies the samples of the half-replica waveform by the previous window weight to generate a partial weight. (Block 1004). For example, one of multipliers 325 (e.g., multiplier 325-1) obtains the window weight d, which represents the window weight d in |x int The relative importance of one of the most recent R previous peaks that appeared in (n)|2 (e.g., d i-1 ). The same multiplier also generates h (n) 500 obtains a sample, which represents the sample index n of the current peak value iThe sample index corresponding to the previous peak of the obtained weight (e.g., n i-1 ). Therefore, the partial weights of block 1004 refer to Figure 5B The output of one of the multipliers 325 described above.

[0106] The EWG circuitry 410 determines whether to use another peak limiting resource. (Block 1006). As used in the context of block 1006, a peak limiting resource may refer to: a) an index within the tapped delay line 502, and b) a multiplier from the multiplier 325, and c) an index from the register 321 accessible by the multiplier. In the examples described above and herein, the EWG circuitry 410 uses a total of R-1 peak limiting resources.

[0107] If another peak limiting resource is used (block 1006: yes), control returns to block 1004 where a different multiplier within multiplier 325 multiplies a different sample of the half-replica waveform with a different previous window weight to generate another partial weight. Fig. 9 In the example of FIG. 1004 , the multiplication of the EWG circuit system 410 is described serially in blocks 1004 and 1006 . In other examples, such as Figure 5B As shown, EWG circuitry 410 performs R-1 multiplication operations in parallel.

[0108] If another peak-limited resource is not used (block 1006: No), the EWG circuitry 410 adds the partial weights together to form a window weight d. (block 1008). Figure 5B In the example of FIG. 5 , adder 506 adds the products of multipliers 325 together. Then, adder 508 adds the products of multipliers 325 together from the overshoot factor (1-a i ) is subtracted from the sum of adder 506. Adder 508 then replaces any resulting negative values ​​with zero to prevent weights from having negative values. The non-negative number remaining after the operation of adder 508 is the window weight d i , which represents the relative importance of the i-th peak.

[0109] CWG circuitry 412 multiplies the window weights by samples of the full replica waveform to generate a partial result. (Block 910). For example, one of multipliers 326 (e.g., multiplier 326-1) obtains the window weight d, which represents the window weight d in |x int The relative importance of a peak among the R most recent peaks that appear in (n)|2 (e.g., d i ). The same multiplier also generates f (n), which represents the difference between the current sample index n and the sample index corresponding to the previous peak value of the obtained weight (such as n i ). Therefore, the partial result of block 1006 refers to Figure 6B The output of one of the multipliers 326 described in .

[0110] The CWG circuitry 412 determines whether to use another peak limiting resource. (Block 1012). In the context of block 1012, the peak limiting resource may refer to: a) a multiplier from the multiplier 326, and b) an index from the register 322 accessible by the multiplier. In the examples described above and herein, the CWG circuitry 412 uses a total of R peak limiting resources, where R used in the context of the EWG circuitry 410 and the CWG circuitry 412 refers to the same positive integer.

[0111] If another peak-limited resource is used (block 1012: YES), control returns to block 1010 where a different multiplier within multiplier 326 multiplies a different sample of the full replica waveform with a different window weight to generate another partial result. Fig. 9 In the example of FIG. 1010 , the multiplication of CWG circuit system 412 is described serially in blocks 1010 and 1012 . In other examples, such as Figure 6B As shown, CWG circuitry 412 performs R multiplication operations in parallel.

[0112] If the other peak limited resource is not used (block 1012: No), the CWG circuitry 412 adds the partial weights together to form the PLW signal. (block 1014). Figure 6B In the example of FIG. 5 , adder 606 adds together the products of multipliers 325. Adder 608 then subtracts the sum of adder 606 from the value “1” to form the value for b. w (n) The value of the nth discrete sample within 317. After block 1014, the example machine readable instructions or operations 900 return to block 912.

[0113] Fig.11 is constructed to execute or instantiate Fig. 9 and Fig.10 Example machine readable instructions or example operations to implement Figure 2 1 is a block diagram of an example programmable circuit system platform 1100 of the transmitter circuit system 110. The programmable circuit system platform 1100 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, an iPad, etc.). TM tablet computers), Internet appliances, headsets (such as augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices or any other type of computing or electronic device.

[0114] The programmable circuit system platform 1100 of the illustrated example includes a programmable circuit system 1112. The programmable circuit system 1112 of the illustrated example is hardware. For example, the programmable circuit system 1112 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired series or manufacturer. The programmable circuit system 1112 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1112 implements the EWG circuit system 410, the CWG circuit system 412, the PC-CFR circuit system 414, the mode switcher circuit system 318, the CFR circuit system 202, the DPD corrector circuit system 204, the DPD estimator circuit system 206, the example capture subsystem circuit system 208, or more generally, the transmitter circuit system 110.

[0115] The programmable circuit system 1112 of the illustrated example includes a local memory 1113 (e.g., cache, registers, etc.). The programmable circuit system 1112 of the illustrated example communicates with main memories 1114, 1116 including a volatile memory 1114 and a non-volatile memory 1116 via a bus 1118. The volatile memory 1114 may be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1116 may be implemented by flash memory or any other desired type of memory device. Access to the main memory 1114, 1116 of the illustrated example is controlled by a memory controller 1117. In some examples, the memory controller 1117 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data into and out of the main memory 1114, 1116. In this example, the main memory 1114, 1116 implements the memory 320.

[0116] The programmable circuit system platform 1100 of the illustrated example also includes an interface circuit system 1120. The interface circuit system 1120 may be configured according to any type of interface standard (such as an Ethernet interface, a universal serial bus (USB) interface, interface, near field communication (NFC) interface, peripheral component interconnect (PCI) interface, or peripheral component interconnect express (PCIe) interface) is implemented by hardware.

[0117] In the example shown, one or more input devices 1122 are connected to the interface circuitry 1120. The input device(s) 1122 allow a user (e.g., a human user, a machine user, etc.) to input data or commands into the programmable circuitry 1112. The input device(s) 1122 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, or a voice recognition system.

[0118] One or more output devices 1124 are also connected to the interface circuit system 1120 of the illustrated example. For example, the output device(s) 1124 may be implemented by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, or a speaker. Thus, the interface circuit system 1120 of the illustrated example typically includes a graphics driver card, a graphics driver chip, or a graphics processor circuit system (such as a GPU).

[0119] The interface circuitry 1120 of the illustrated example also includes a communication device, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface to facilitate the exchange of data with external devices (e.g., any type of computing device) over the network 1126. For example, communications may be via an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0120] The programmable circuit system platform 1100 of the illustrated example also includes one or more mass storage disks or devices 1128 for storing firmware, software, or data. Examples of such mass storage disks or devices 1128 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices (such as flash memory devices or SSDs).

[0121] Machine readable instructions 1132 (which may be Fig. 9 and Fig.10 The computer program product (implemented by machine-readable instructions) may be stored in mass storage device 1128, in volatile memory 1114, in non-volatile memory 1116, or on at least one non-transitory computer-readable storage medium (such as a removable CD or DVD).

[0122] Although Figure 3 - FIG. 6 shows an implementation Figure 2The CFR circuit system 202 is an example of Figure 3 -One or more of the elements, processes or devices shown in FIG6 may be combined, divided, rearranged, omitted, eliminated or implemented in any other manner. In addition, Figure 3 - Delay circuitry 302, multipliers 304, adders 306, mux 308, interpolator circuitry 310, envelope computer circuitry 312, peak attribute extractor circuitry 314, memory 320, multiplier pool 324, EWG circuitry 410, CWG circuitry 412, and PC-CFR circuitry 414 of FIG. 6, or more generally, PLWG circuitry 316 and CFR circuitry 202, may be implemented by hardware alone, or by hardware in combination with software or firmware. Thus, for example, Figure 3 - Any of the delay circuit system 302, multiplier 304, adder 306, mux 308, interpolator circuit system 310, envelope computer circuit system 312, peak attribute extractor circuit system 314, memory 320, multiplier pool 324, EWG circuit system 410, CWG circuit system 412, and PC-CFR circuit system 414 of FIG. 6, or more generally, PLWG circuit system 316 and CFR circuit system 202 may be implemented by the following items: programmable circuit system in combination with machine-readable instructions (such as firmware or software), processor circuit system, (one or more) analog circuits, (one or more) digital circuits, (one or more) logic circuits, (one or more) programmable processors, (one or more) programmable microcontrollers, (one or more) graphics processing units (GPUs), (one or more) digital signal processors (DSPs), (one or more) ASICs, (one or more) programmable logic devices (PLDs), or (one or more) field programmable logic devices (FPLDs) (such as FPGAs). In addition, Figure 2 The example CFR circuit system 202 may include one or more components, processes, or devices in addition to or in place of Figure 2 The elements, processes or devices shown in the figure may include more than one of any or all of the elements, processes and devices shown.

[0123] Fig. 9 and Fig.10 , which may be executed by a programmable circuit system to implement or instantiate Figure 2 Example machine-readable instructions of the transmitter circuit system 110, or representations that may be executed by the programmable circuit system to implement or instantiate Figure 2 The machine-readable instructions may be instructions for programmable circuitry (such as the following in conjunction with Fig.11The machine-readable instructions may be one or more executable programs or portions of one or more executable programs executed by the programmable circuit system 1112 shown in the example programmable circuit system platform 1100 described herein, or may be one or more functions or portions of functions to be performed by the example programmable circuit system (e.g., FPGA). In some examples, the machine-readable instructions cause an operation, task, etc. to be performed or executed in an automated manner in the real world. As used herein, "automation" means without human involvement.

[0124] The program may be embodied in instructions (e.g., software, firmware, or both) stored in one or more non-transitory computer-readable or machine-readable storage media (such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), or any other storage device or storage disk. The non-transitory computer-readable or machine-readable medium The instructions may be programmed into or executed by a programmable circuit system located in one or more hardware devices, but the entire program or portions thereof may alternatively be executed or instantiated by one or more hardware devices other than the programmable circuit system, or embodied in dedicated hardware. Machine-readable instructions may be distributed across multiple hardware devices, or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. In addition, although reference is made to Fig. 9 and Fig.10The flowchart(s) shown describe example procedures, but many other methods of implementing the example transmitter circuit system 110 may be used instead. For example, the order of execution of the blocks of the flowchart(s) may be changed, or some of the blocks described may be changed, eliminated, or combined. Any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete or integrated analog or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to perform corresponding operations without executing software or firmware. The programmable circuit system may be distributed in different network locations or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.). For example, the programmable circuit system may be a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, etc., or any combination thereof (one or more).

[0125] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as: data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure that can be used to create, manufacture, or generate machine-executable instructions (e.g., as (one or more) parts of instructions, codes, representations of codes, etc.). For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations of a network or a collection of networks (e.g., in a cloud, an edge device, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, update, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, etc., so that the machine-readable instructions can be directly read, interpreted, or executed by a computing device or other machine. For example, machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, or stored on separate computing devices so that the parts, when decrypted, decompressed, or combined, form a set of computer-executable or machine-executable instructions that implement one or more functions or operations that may collectively form a program (such as the programs described herein).

[0126] In another example, the machine-readable instructions may be stored in a state in which the machine-readable instructions can be read by a programmable circuit system, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., stored settings, input data, recorded network addresses, etc.) before the machine-readable instructions or (one or more) corresponding programs can be executed in whole or in part. Therefore, as used herein, a machine-readable, computer-readable, or machine-readable medium may include instructions or (one or more) programs, regardless of the specific format or state of the machine-readable instructions or (one or more) programs.

[0127] The machine-readable instructions described herein may be presented in any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be presented in any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0128] As described above, the present invention may be implemented using executable instructions (eg, computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. Fig. 9 and Fig.10As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device or storage disk and exclude propagation signals, and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or storage disk in which information is stored for any duration (e.g., for a long period of time, permanently, for a short period of time, for temporary buffering, or for caching of information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, or electrical) hardware for retaining information for a period of time, but exclude propagation signals, and exclude transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, magnetic drives, or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure such as mechanical or electrical equipment, hardware, or circuitry that may or may not be configured with computer-readable instructions, machine-readable instructions, etc., or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0129] The terms "include" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprising" (e.g., comprising, including, including, having, etc.) as a preamble or within any type of claim recitation, additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, just as the terms "include" and "comprising" are open-ended, "at least" is likewise open-ended. The term "or" when used, for example, in a form such as A, B, or C, refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein, in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein, in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0130] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, "a" or "an" object refers to one or more of the object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. In addition, although listed individually, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Although individual features may be included in different examples or claims, these features may also be combined together, and inclusion in different examples or claims does not mean that the combination of features is not feasible or disadvantageous.

[0131] As used herein, unless otherwise specified, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements to which the connection reference refers or relative movement between such elements. Thus, connection references do not necessarily infer that two elements are directly connected or in a fixed relationship to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0132] Unless otherwise specifically stated, descriptors such as "first", "second", "third", etc. are used herein without being considered or otherwise indicating any meaning of priority, physical order, arrangement in a list, or ordering in any manner, but are merely used as labels or arbitrary names to distinguish elements in order to understand the described examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while in the claims, a different descriptor (such as "second" or "third") may be used to refer to the same element. In such instances, such descriptors are used only to clearly identify those elements in the context of the discussion (e.g., in the claims) where the elements might otherwise share the same name.

[0133] As used herein, "approximately" and "about" modify the subject matter / values ​​thereof to recognize variations that may exist in real-world applications. For example, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances or other real-world imperfections. For example, unless otherwise specified herein, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / - 10%.

[0134] As used herein, the phrase "communication" (including variations thereof) encompasses direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or continuous communication, but also includes selective communication at regular intervals, scheduled intervals, non-regular intervals, or one-time events.

[0135] As used herein, "programmable circuitry" is defined to include: (i) one or more special-purpose circuits (e.g., an application-specific circuit (ASIC)) that are constructed to perform specific operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform specific function(s) or operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include: a programmable microprocessor, such as a central processor unit (CPU), which can execute a first instruction to perform one or more operations or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction to cause the configuration or structuring of the FPGA to instantiate one or more operations or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, the XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any (one or more) combinations thereof), and an orchestration technology (e.g., (one or more) application programming interfaces (APIs)) that can assign (one or more) computing tasks to the programmable circuit system (s) that are suitable and available for performing (one or more) computing tasks among the multiple types of programmable circuit systems.

[0136] In this description, the term "coupled" may cover connections, communications, or signal paths that achieve a functional relationship consistent with this description. For example, if device A generates a signal for controlling device B to perform an action: (a) in the first example, device A is coupled to device B through a direct connection; or (b) in the second example, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0137] A device that is "configured to" perform a task or function may be configured (e.g., programmed or hardwired) by the manufacturer at the time of manufacture to perform that function, or may be configurable (or reconfigurable) by a user after manufacture to perform that function or other additional or alternative functions. Configuration may be programmable through the device's firmware or software, through the construction or layout of the device's hardware components and interconnections, or a combination thereof.

[0138] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms generally refer to an interconnection between or a terminal of a device element, circuit element, integrated circuit, device or other electronic device or semiconductor component.

[0139] A circuit or device described herein as including certain components may be adapted to be coupled with those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (e.g., resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources or current sources) may include only semiconductor elements within a single physical device (e.g., a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements or sources to form the structure during or after manufacture, such as by an end user or a third party.

[0140] Although some elements in the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, more or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as outside the integrated circuit may be included in the integrated circuit, or some features shown as within the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; or (iv) are incorporated in / on the same printed circuit board.

[0141] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

[0142] From the foregoing, it will be appreciated that example systems, apparatus, articles, and methods have been described that switch between PC-CFR techniques and W-CFR techniques in response to the availability of frequency distribution information, and implement W-CFR using fewer computing resources than other W-CFR techniques. The described systems, apparatus, articles, and methods improve the efficiency of using computing devices in the following manner: the example transmitter circuit system includes a shared set of computing resources (e.g., multipliers and memory registers) and uses the shared resources to implement the PC-CFR technique or the W-CFR technique in response to the operating mode. When generating a PLW in the W-CFR mode, the example transmitter circuit system calculates a scaling factor for the current peak in response to the overshoot factor of the current peak, the sample value of the half-replica waveform from the previous peak, and the scaling factor of the previous peak. Then, the example transmitter circuit system uses the scaling factor of the current peak and the sample value of the full-replica waveform from the previous peak to calculate the overall PLW. The described systems, apparatus, articles, and methods accordingly relate to (one or more) improvements in the operation of machines such as computers, electromechanical devices, etc.

Claims

1. A device for reducing peaks in an input signal, the device comprising: a memory having a first terminal and a second terminal, the memory being configured to store a first copy and a second copy of a normalized windowed waveform in the memory; effective waveform weight generation circuitry (EWG circuitry) having a first terminal coupled to the first terminal of the memory and a second terminal, the EWG circuitry configured to use the first copy of the normalized windowed waveform to generate weights corresponding to peaks in the input signal; a composite waveform generating circuit system, i.e., a CWG circuit system, having a first terminal coupled to the second terminal of the EWG circuit system, a second terminal coupled to the second terminal of the memory, and a third terminal, the CWG circuit system being configured to: generating an output waveform using the weights and the second copy of the normalized windowed waveform; and generating a peak limiting waveform in response to the output waveform; as well as Arithmetic circuitry has a terminal coupled to the third terminal of the CWG circuitry, the arithmetic circuitry for combining the peak limited waveform with the input signal to reduce the magnitude of the peak.

2. The device according to claim 1, wherein: The memory includes two terminals for parallel access; and The EWG circuitry is configured to access the first copy of the normalized windowed waveform, and in parallel, the CWG circuitry is configured to access the second copy of the normalized windowed waveform.

3. The device according to claim 2, wherein: The peak is a first peak; and The CWG circuitry is further configured to generate the output waveform corresponding to a first peak value using the second copy of the normalized windowed waveform; and In parallel with the generation of the output waveform, the EWG circuitry is further configured to generate a weight for a second peak in the input signal using the first copy of the normalized windowed waveform.

4. The device according to claim 1, wherein: The peak value is a first peak value; The output waveform is responsive to a first portion of the result corresponding to the first peak; and The CWG circuitry is further configured to add together a plurality of partial results to form the output waveform, the partial results corresponding to respective peaks in the input signal.

5. The device according to claim 4, wherein: The CWG circuitry is further configured to form the plurality of partial results in parallel using the second copy of the normalized windowed waveform.

6. The device according to claim 1, wherein: To reduce the amplitude of the peak, the CWG circuitry is configured to generate the peak limiting waveform such that when the peak limiting waveform is combined with the input signal: The local maximum within the envelope of the input signal has a reduced amplitude; and A number of samples within the input signal adjacent to the local maximum have reduced amplitudes.

7. The device according to claim 1, wherein: The weight is a second weight; The peak is a second peak; and To generate the second weight, the EWG circuit system is further configured to multiply a first weight corresponding to a first peak by a sample from the normalized windowed waveform, the first peak occurring before the second peak, the sample being responsive to a time difference between the first peak and the second peak.

8. The device according to claim 1, wherein: The normalized windowed waveform has a shape; and The memory is configured as: storing a complete copy of the shape as the second copy of the windowed waveform; and A half copy of the shape is stored as the first copy of the windowed waveform.

9. The device according to claim 1, wherein: To reduce the magnitude of the peak, the arithmetic circuitry is further configured to multiply the peak limited waveform by a delayed copy of the input signal.

10. An apparatus comprising: a memory having a first terminal and a second terminal; a windowed crest factor reduction circuit system, or W-CFR circuit system, having a first terminal coupled to the first terminal of the memory, a second terminal coupled to the second terminal of the memory, and a third terminal, the W-CFR circuit system being configured to, in response to the apparatus being coupled to a first device providing a first input signal but not providing frequency distribution information corresponding to the first input signal, generate a peak limited waveform in response to a window function stored in the memory; first arithmetic circuitry having a terminal coupled to the third terminal of the W-CFR circuitry, the first arithmetic circuitry combining the peak limiting waveform with the first input signal to reduce the magnitude of peaks within the first input signal in response to the apparatus being coupled to the first device; peak-cancellation crest factor reduction circuitry, or PC-CFR circuitry, having a first terminal coupled to the first terminal of the memory, a second terminal coupled to a second terminal of the memory, the PC-CFR circuitry configured to generate a cancellation signal using the frequency information and the memory in response to the apparatus being coupled to a second device providing a second input signal and providing frequency information corresponding to the second input signal; second arithmetic circuitry having a terminal coupled to a third terminal of the PC-CFR circuitry, the second arithmetic circuitry being configured to combine the cancellation signal with the second input signal to reduce the magnitude of peaks in the second input signal in response to the apparatus being coupled to the second device; as well as a multiplexer having a first terminal coupled to the first arithmetic circuit system and a second terminal coupled to the second arithmetic circuit system, the multiplexer being configured to provide one of an output of the first arithmetic circuit system or an output of the second arithmetic circuit system to an external device, the providing being responsive to whether the apparatus is coupled to the first device or the second device.

11. The device according to claim 10, wherein: The W-CFR circuit system includes: effective waveform weight generation circuitry (EWG circuitry) having a first terminal coupled to the first terminal of the memory and a second terminal, the EWG circuitry being configured to, in response to the apparatus being coupled to the first device, generate weights corresponding to peaks in the first input signal using a first copy of a normalized windowed waveform; and a composite waveform generating circuitry, i.e., CWG circuitry, having a first terminal coupled to the second terminal of the EWG circuitry, a second terminal coupled to the second terminal of the memory, and a third terminal, the CWG circuitry being configured to: in response to the apparatus being coupled to the first device: generating an output waveform using the weights and a second copy of the normalized windowed waveform; and The peak limiting waveform is generated in response to the output waveform.

12. The device according to claim 11, wherein: The memory is configured to, in response to the apparatus being coupled to the first device, store the first copy and the second copy of the normalized windowed waveform; and The first terminal of the memory and the second terminal of the memory are configured for parallel access.

13. The device according to claim 10, wherein: In response to the apparatus being coupled to the second device, The memory is configured to store a real component and an imaginary component of a peak-canceled waveform, the pulse-canceled waveform being responsive to the frequency distribution information; and The PC-CFR circuitry is configured to access the real component and the imaginary component in parallel to generate the cancellation signal.

14. The device according to claim 13, wherein: In response to the apparatus being coupled to the first device, the W-CFR circuitry is configured to generate the peak limited waveform by providing samples of the window function as inputs to a plurality of multiplier circuits; and In response to the apparatus being coupled to the first device, the PC-CFR circuitry is configured to generate the cancellation signal by providing the real component and the imaginary component as inputs to the plurality of multiplier circuits.

15. The device according to claim 10, wherein: said output of said multiplexer being a modified input signal; and The device also includes: digital predistortion corrector circuitry, or DPD corrector circuitry, having a first terminal coupled to the third terminal of the multiplexer, the DPD circuitry configured to digitally predistort the modified input signal; a power amplifier circuitry having a first terminal coupled to a second terminal of the DPD circuitry, the power amplifier circuitry configured to amplify a predistorted version of the modified input signal, the amplification being operable to introduce nonlinearities that are offset by the predistortion; and An antenna having a terminal coupled to the second terminal of the power amplifier circuitry, the antenna being configured to transmit an amplified and predistorted version of the modified input signal.

16. A non-transitory machine-readable storage medium comprising instructions for causing a programmable circuit system to at least: storing a first copy and a second copy of the normalized windowed waveform in a memory; using the first copy of the normalized windowed waveform to generate weights corresponding to peaks in an input signal; generating an output waveform using the weights and the second copy of the normalized windowed waveform; generating a peak limiting waveform in response to the output waveform; and The peak limiting waveform is combined with the input signal to reduce the amplitude of the peak.

17. The non-transitory machine-readable storage medium of claim 16, wherein: The memory includes two terminals for parallel access by the programmable circuitry; and The programmable circuitry is also configured to access the first copy and the second copy of the normalized windowed waveform in parallel.

18. The non-transitory machine-readable storage medium of claim 17, wherein: The peak is a first peak; and The programmable circuit system is further configured to: using the second copy of the normalized windowed waveform to produce the output waveform corresponding to the first peak; and In parallel with generating the output waveform, a weight for a second peak in the input signal is generated using the first copy of the normalized windowed waveform.

19. The non-transitory machine-readable storage medium of claim 16, wherein: The peak value is a first peak value; The output waveform is responsive to a first portion of the result corresponding to the first peak; and The programmable circuitry is further configured to add together a plurality of partial results to form the output waveform, the partial results corresponding to respective peaks in the input signal.

20. The non-transitory machine-readable storage medium of claim 16, wherein: The normalized windowed waveform has a shape; and The non-transitory machine-readable storage medium is further configured to: A full copy of the shape is stored as the second copy of the windowed waveform; and a half copy of the shape is stored as the first copy of the windowed waveform.

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