PAM4 transmitting device and linearity adjusting method thereof

Abstract

The invention provides a PAM4 transmitting device and a linearity adjusting method thereof. The PAM4 generating apparatus according to the present disclosure comprises: a transmission unit configured to receive a transmission signal and a linearity configuration signal, and output a PAM4 output signal; a read-back unit configured to receive the PAM4 output signal and a threshold configuration signal, and output a read-back signal; a comparison unit configured to receive the transmission signal and the read-back signal, and compare the transmission signal and the read-back signal to output a comparison result; and a control unit configured to receive the comparison result and output a linearity configuration signal and a threshold configuration signal. According to the PAM4 sending device and the linearity adjusting method thereof, the linearity of the PAM4 output signal can be adjusted in real time while the PAM4 output signal is output no matter how the environment and the temperature change, so that the linearity requirement of the PAM4 output signal is met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular, to a PAM4 transmitting device and a linearity adjustment method thereof. Background Art

[0002] Wired high-speed data transmission systems usually include a transmitter and a receiver. With the increase in transmission bandwidth, four-level pulse amplitude modulation (PAM4: Pulse-Amplitude Modulation 4-Level) technology has been widely used and adopted by multiple transmission standards. PAM4 technology uses four different voltage levels to transmit data, and can transmit 2 bits of information in each symbol cycle. Compared with the traditional non-return-to-zero (NRZ: Non-Return-to-Zero) signal, PAM4 signal can achieve twice the bit rate at the same baud rate.

[0003] In PAM4 technology, the linearity of the output signal is an important indicator of the PAM4 transmitter. Unsatisfactory linearity usually increases the bit error rate of the receiving device and affects the entire transmission system. However, it is difficult for existing PAM4 transmitters to meet the linearity requirements of the PAM4 output signal. Therefore, a PAM4 transmitter is needed that can optimize the PAM4 output signal to meet the linearity requirements of the PAM4 output signal.

[0004] The above information disclosed in this Background section is only for understanding the background of the present disclosure concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel PAM4 transmitting device and a linearity adjustment method thereof.

[0006] According to one aspect of the present disclosure, a four-level pulse amplitude modulation (PAM4) transmitting device is provided, which includes: a transmitting unit, configured to receive a transmitting signal and a linearity configuration signal, and output a PAM4 output signal; a readback unit, configured to receive the PAM4 output signal and a threshold configuration signal, and output the readback signal; a comparing unit, configured to receive the transmitting signal and the readback signal, and compare the transmitting signal and the readback signal to output a comparison result; and a control unit, configured to receive the comparison result, and output a linearity configuration signal and a threshold configuration signal.

[0007] According to another aspect of the present disclosure, a linearity adjustment method for a PAM4 transmitting device is provided, comprising: a first step: a control unit outputs a linearity configuration signal, and the transmitting unit adjusts the linearity of a PAM4 output signal according to the linearity configuration signal; a second step: a control unit outputs a threshold configuration signal, a readback unit outputs a readback signal according to the threshold configuration signal, a comparison unit compares the transmitting signal and the readback signal and outputs the comparison result to the control unit, and the control unit records the current threshold configuration signal and the corresponding comparison result; a third step: the second step is repeated multiple times, and the control unit records a series of threshold configuration signals and a corresponding series of comparison results; a fourth step: the control unit calculates the linearity of the PAM4 output signal, and when the linearity does not meet the target value, the control unit adjusts the linearity configuration signal; and a fifth step: repeating the first step to the fourth step until the linearity of the PAM4 output signal meets the target value.

[0008] According to the PAM4 transmitting device disclosed in the present invention, during the transmission process, regardless of changes in the environment and temperature, the linearity of the PAM4 output signal can be adjusted in real time while outputting the PAM4 output signal to meet the linearity requirement of the PAM4 output signal.

[0009] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the concepts of the disclosure.

[0011] Figure 1 is a schematic block diagram illustrating a PAM4 wired data transmission system.

[0012] Figure 2 is a schematic eye diagram showing a PAM4 output signal.

[0013] Figure 3 is a schematic block diagram showing a PAM4 transmitting device according to an embodiment of the present disclosure.

[0014] Figure 4 is a schematic block diagram showing a sending unit according to an embodiment of the present disclosure.

[0015] Figure 5 is a schematic circuit diagram showing an output subunit according to an embodiment of the present disclosure.

[0016] Figure 6 is a schematic block diagram illustrating a readback unit according to an embodiment of the present disclosure.

[0017] Figure 7 is a schematic circuit diagram of an input subunit and an eye diagram of a PAM4 output signal according to an embodiment of the present disclosure.

[0018] Figure 8 Detailed description is a schematic flowchart illustrating a linearity adjustment method of a PAM4 transmitting device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the concept of the present disclosure, specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0020] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the disclosed concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, units, regions and / or aspects of each embodiment (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or reconfigured without departing from the disclosed concept.

[0021] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0023] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" mean the presence of stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0025] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be exhaustive and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals throughout the text represent the same components.

[0026] Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0027] Figure 1 A schematic block diagram of a four-level pulse amplitude modulation (PAM4) wired data transmission system 1 is shown.

[0028] like Figure 1 As shown, the PAM4 wired data transmission system 1 may generally include a PAM4 transmitting device 10, a PAM4 receiving device 50, and a transmission cable connected between the PAM4 transmitting device 10 and the PAM4 receiving device 50. The PAM4 transmitting device 10 may receive a transmission signal 11 and output a PAM4 output signal 21. The PAM4 output signal 21 may be received by the PAM4 receiving device 50 via the transmission cable, and the PAM4 receiving device 50 may perform amplification or equalization processing on the PAM4 output signal 21.

[0029] The PAM4 transmitting device 10 can be configured to transmit a PAM4 output signal 21 in the form of a differential signal. In this case, the transmission cable can be a differential signal cable, such as a differential twisted pair cable. The PAM4 transmitting device 10 can also be configured to transmit a PAM4 output signal 21 in the form of a single-ended signal. In this case, the transmission cable can also be a single-ended signal cable such as a shielded coaxial cable.

[0030] Figure 2 Figure 2 shows a schematic eye diagram of a PAM4 output signal. Figure 2 In the figure, the linearity of the PAM4 output signal shown in (a) is good, while the linearity of the PAM4 output signal shown in (b) is poor, which will be explained in more detail below.

[0031] PAM4 technology uses a predetermined rule to convert binary logic signals into four different level signals. Therefore, each cycle of the PAM4 output signal includes two bits of logic information. The two bits of data can be represented by the most significant bit (MSB) data and the least significant bit (LSB) data.

[0032] In this article, when the MSB data and the LSB data are both logic low level 0, the two-bit data of PAM4 can be marked as "00", when the MSB data and the LSB data are logic low level 0 and logic high level 1 respectively, the two-bit data of PAM4 can be marked as "01", when the MSB data and the LSB data are logic high level 1 and logic low level 0 respectively, the two-bit data of PAM4 can be marked as "10", and when the MSB data and the LSB data are both logic high level 1, the two-bit data of PAM4 can be marked as "11".

[0033] It should be noted that "logic high level" and "logic low level" are used to describe the logic level of a signal. A signal having a "logic high level" is different from a signal having a "logic low level". For example, when a signal having a first voltage corresponds to a signal having a "logic high level", a signal having a second voltage corresponds to a signal having a "logic low level". According to an embodiment, the voltage of the "logic high level" is higher than the "logic low level". According to an embodiment, the logic level of a signal may be at different logic levels or opposite logic levels. For example, in some embodiments, a signal having a logic high level may be at a logic low level, while in other embodiments, a signal having a logic low level may be at a logic high level.

[0034] like Figure 2 As shown, the voltage of the PAM4 output signal may include four level voltages. In this embodiment, the four level voltages of the PAM4 output signal may be represented as level 0, level 1, level 2, and level 3, respectively.

[0035] In this article, level 0 is the PAM4 output signal when the two-bit data of PAM4 is "00", level 1 is the PAM4 output signal when the two-bit data of PAM4 is "01", level 2 is the PAM4 output signal when the two-bit data of PAM4 is "10", and level 3 is the PAM4 output signal when the two-bit data of PAM4 is "11".

[0036] like Figure 2 As shown, the schematic eye diagram of the PAM4 output signal includes three eye heights, namely eye height A, eye height B and eye height C, where eye height A can be defined as the voltage amplitude difference between level 0 and level 1, eye height B can be defined as the voltage amplitude difference between level 1 and level 2, and eye height C can be defined as the voltage amplitude difference between level 2 and level 3.

[0037] The linearity (RLM) of the PAM4 output signal can be defined as: 3× min(A,B,C) / sum(A,B,C), where min(A,B,C) is the minimum value of eye height A, eye height B and eye height C, that is, the minimum value among the three eye heights, and sum(A,B,C) is the sum of eye height A, eye height B and eye height C, that is, the total voltage amplitude of the PAM4 output signal.

[0038] It can be seen from the above linearity calculation formula that the smaller the difference between the three eye heights, the larger the calculation result of the linearity RLM, and the better the linearity of the PAM4 output signal. On the contrary, the larger the difference between the three eye heights, the smaller the calculation result of the linearity RLM, and the worse the linearity of the PAM4 output signal.

[0039] Specifically, when the eye heights A, B, and C are the same, the calculated value of the linearity RLM is 1, which is the theoretical maximum value of RLM. When the eye heights A, B, and C are different from each other, RLM is less than 1. Therefore, in order to obtain a larger RLM value, that is, better linearity, the eye heights A, B, and C should be as identical as possible.

[0040] return Figure 2 ,exist Figure 2 In the schematic eye diagram shown in (a), eye height A, eye height B and eye height C are the same or close to each other, and the calculation result of linearity RLM is approximately 1, so its linearity is good. Figure 2 In the schematic eye diagram shown in (b), eye height A is the smallest, eye height B is the second, and eye height C is the largest. The three are different from each other, and the calculated value of linearity RLM is much less than 1, so its linearity is poor.

[0041] PAM4 technology has been adopted by multiple transmission standards. Generally, PAM4 technology defines relatively strict index requirements for the linearity of the output signal of the PAM4 transmitter (i.e., the PAM4 output signal). For example, the 56G optical communication protocol (OIFCEI-56G) stipulates that the minimum linearity RLM of the PAM4 output signal is 0.95. In addition, although the linearity RLM is not specified in the 10G automotive Ethernet protocol (10G BASE-T1), it can be seen from other calculation methods that it also has relatively strict requirements for the linearity of the PAM4 output signal.

[0042] However, it is difficult for existing PAM4 transmitting devices to meet the linearity requirements of PAM4 output signals. The linearity of PAM4 output signals is usually achieved by optimizing design parameters during the design process of the transmitting device. However, the linearity of the PAM4 output signal is inevitably affected by factors such as semiconductor process, power supply voltage, and temperature. For example, environmental and temperature changes will affect the characteristics of semiconductor devices in the PAM4 transmitting device, thereby changing the linearity of the PAM4 output signal. Therefore, a PAM4 transmitting device is needed that can continuously optimize the linearity of the PAM4 output signal during operation to meet the system's linearity requirements for the PAM4 output signal.

[0043] In order to solve the above problems, a PAM4 transmitting device according to the present disclosure is proposed.

[0044] Figure 3 A schematic block diagram of a PAM4 transmitting device 10 according to an embodiment of the present disclosure is shown.

[0045] like Figure 3 As shown, according to an embodiment of the present disclosure, the PAM4 transmitting device 10 may include a transmitting unit 100 , a readback unit 200 , a comparing unit 300 and a control unit 400 .

[0046] like Figure 3 As shown, according to an embodiment of the present disclosure, the transmitting unit 100 may receive a transmit signal 11 and output a PAM4 output signal 21. According to an embodiment of the present disclosure, the transmit signal 11 may be an analog signal. According to an embodiment of the present disclosure, the transmit signal 11 may be a digital signal of one or more bits. According to an embodiment of the present disclosure, the PAM4 output signal 21 may be a differential signal including a positive signal and a negative signal. According to an embodiment of the present disclosure, the PAM4 output signal 21 may be a single-ended signal including only one polarity.

[0047] According to an embodiment of the present disclosure, the transmitting unit 100 may also receive a linearity configuration signal 41 for adjusting the linearity of the PAM4 output signal 21. According to an embodiment of the present disclosure, the linearity configuration signal 41 may be a digital signal of one or more bits. According to an embodiment of the present disclosure, the linearity configuration signal 41 may be one or more analog signals.

[0048] like Figure 3As shown, according to an embodiment of the present disclosure, the readback unit 200 may receive the PAM4 output signal 21 and output the readback signal 31. According to an embodiment of the present disclosure, the readback unit 200 may receive the differential PAM4 output signal 21, which includes a positive signal and a negative signal. According to an embodiment of the present disclosure, the readback unit 200 may receive the single-ended PAM4 output signal 21, which includes only one polarity. According to an embodiment of the present disclosure, the readback signal 31 may be an analog signal. According to an embodiment of the present disclosure, the readback signal 31 may be a digital signal of one or more bits.

[0049] According to an embodiment of the present disclosure, the readback unit 200 may also receive a threshold configuration signal 42 for changing the readback signal 31 output by the readback unit 200. According to an embodiment of the present disclosure, the threshold configuration signal 42 may be a digital signal of one or more bits. According to an embodiment of the present disclosure, the threshold configuration signal 42 may also be one or more analog signals.

[0050] like Figure 3 As shown, according to an embodiment of the present disclosure, the comparison unit 300 may receive the transmission signal 11 and the readback signal 31 , and compare the transmission signal 11 and the readback signal 31 to output a comparison result 32 .

[0051] Specifically, according to an embodiment of the present disclosure, when the sending signal 11 and the readback signal 31 are exactly the same, the comparison result 32 output by the comparison unit 300 may be a logic high level 1, and when the sending signal 11 and the readback signal 31 are not exactly the same, the comparison result 32 output by the comparison unit 300 may be a logic low level 0.

[0052] According to an embodiment of the present disclosure, when both the transmission signal 11 and the readback signal 31 are multi-bit digital signals, the comparison result 32 may be a one-bit voltage signal. For example, when each corresponding bit of the transmission signal 11 and the readback signal 31 is exactly the same, the comparison result 32 may be a logic high level 1, otherwise it may be a logic low level 0.

[0053] According to an embodiment of the present disclosure, when the transmitted signal 11 and the readback signal 31 are both multi-bit digital signals, the comparison result 32 can be a multi-bit digital signal, wherein each bit of the comparison result 32 can represent the comparison result of each corresponding bit of the transmitted signal 11 and the readback signal 31.

[0054] like Figure 3 As shown, according to an embodiment of the present disclosure, the control unit 400 receives the comparison result 32 and outputs a linearity configuration signal 41 and a threshold configuration signal 42 .

[0055] Figure 4A schematic block diagram of a sending unit 100 according to an embodiment of the present disclosure is shown.

[0056] like Figure 4 As shown, according to an embodiment of the present disclosure, the sending unit 100 may include a serialization subunit 101 , an encoding subunit 102 and an output subunit 103 .

[0057] like Figure 4 As shown, according to an embodiment of the present disclosure, the serialization subunit 101 can receive the transmission signal 11 and output a two-bit digital signal, including a transmission MSB signal 13 and a transmission LSB signal 12. According to an embodiment of the present disclosure, when the transmission signal 11 is a multi-bit digital signal, the serialization subunit 101 can perform a serialization operation on the transmission signal 11. Specifically, according to an embodiment of the present disclosure, when the transmission signal 11 is, for example, a 20-bit digital signal, the serialization subunit 101 can perform a 10:1 serialization operation on the transmission signal 11 to output the transmission MSB signal 13 and the transmission LSB signal 12.

[0058] like Figure 4 As shown, according to an embodiment of the present disclosure, the encoding subunit 102 can receive the transmit MSB signal 13 and the transmit LSB signal 12 and perform encoding operations thereon, and output encoded transmit signals, including signal 16, signal 15 and signal 14.

[0059] Specifically, according to the embodiment of the present disclosure, the encoding subunit 102 can perform the following encoding operation on the sending MSB signal 13 and the sending LSB signal 12: when the sending MSB signal 13 and the sending LSB signal 12 are "00", the encoded sending signal can be "000", that is, the signal 16, the signal 15 and the signal 14 are all logic low level 0; when the sending MSB signal 13 and the sending LSB signal 12 are "01", the encoded sending signal can be "001", that is, the signal 16, the signal 15 and the signal 14 are all logic low level 0. Signal 16, signal 15 and signal 14 are respectively logic low level 0, logic low level 0 and logic high level 1. When the MSB signal 13 and the LSB signal 12 are "10", the encoded transmitted signal can be "011", that is, signal 16, signal 15 and signal 14 are respectively logic low level 0, logic high level 1, and logic high level 1. When the MSB signal 13 and the LSB signal 12 are "11", the encoded transmitted signal can be "111", that is, signal 16, signal 15 and signal 14 are all logic high level 1.

[0060] like Figure 4 As shown, according to an embodiment of the present disclosure, the output subunit 103 can receive the encoded transmit signal (including signal 16 , signal 15 , and signal 14 ) and the linearity configuration signal 41 , and output the PAM4 output signal 21 .

[0061] Herein, according to an embodiment of the present disclosure, the voltage level of the PAM4 output signal 21 may be level 0, level 1, level 2, or level 3.

[0062] According to an embodiment of the present disclosure, when the encoded transmitted signal is "000", the PAM4 output signal 21 can be level 0, when the encoded transmitted signal is "001", the PAM4 output signal 21 can be level 1, when the encoded transmitted signal is "011", the PAM4 output signal 21 can be level 2, and when the encoded transmitted signal is "111", the PAM4 output signal 21 can be level 3.

[0063] According to an embodiment of the present disclosure, the linearity configuration signal 41 can adjust the linearity of the PAM4 output signal 21 .

[0064] Specifically, according to an embodiment of the present disclosure, the linearity configuration signal 41 can adjust the linearity of the PAM4 output signal 21 by changing at least one of the eye height A, the eye height B, and the eye height C of the PAM4 output signal 21 .

[0065] Figure 5 Schematic circuit diagram of the output subunit 103 according to an embodiment of the present disclosure is shown.

[0066] According to an embodiment of the present disclosure, the output subunit 103 may include one or more current source subunits. Figure 5 As shown, according to an embodiment of the present disclosure, the output subunit 103 may include a first current source subunit 104 , a second current source subunit 105 and a third current source subunit 106 .

[0067] According to an embodiment of the present disclosure, the linearity configuration signal 41 can change the output current value of one or more current source subunits in the output subunit 103. Accordingly, Figure 5 As shown, according to an embodiment of the present disclosure, the linearity configuration signal 41 may include a first linearity configuration signal 41_1 , a second linearity configuration signal 41_2 , and a third linearity configuration signal 41_3 .

[0068] like Figure 5 As shown, according to an embodiment of the present disclosure, the first current source subunit 104 can receive a first linearity configuration signal 41_1 for adjusting its output current value, the second current source subunit 105 can receive a second linearity configuration signal 41_2 for adjusting its output current value, and the third current source subunit 106 can receive a third linearity configuration signal 41_3 for adjusting its output current value.

[0069] According to an embodiment of the present disclosure, the output subunit 103 includes one or more switch transistors for controlling whether the current of the corresponding current source subunit is merged into the PAM4 output signal 21. Figure 5 As shown, according to an embodiment of the present disclosure, the output subunit 103 may include a first switch transistor M14, a second switch transistor M15, and a third switch transistor M16.

[0070] like Figure 5 As shown, according to an embodiment of the present disclosure, the first switch transistor M14 is connected in series with the first current source sub-unit 104, and the gate of the first switch transistor M14 receives the encoded transmission signal 14, the source of the first switch transistor M14 is connected to the PAM4 output signal 21, and the drain of the first switch transistor M14 is connected to the first current source sub-unit 104.

[0071] According to an embodiment of the present disclosure, when the encoded transmission signal 14 is a logic high level 1, the first switch transistor M14 is turned on, so that the first current source subunit 104 is connected to the PAM4 output signal 21 and provides an output current for the PAM4 output signal 21, and when the encoded transmission signal 14 is a logic low level 0, the first switch transistor M14 is turned off, so that the first current source subunit 104 cannot provide an output current for the PAM4 output signal 21.

[0072] like Figure 5 As shown, according to an embodiment of the present disclosure, the second switch transistor M15 is connected in series with the second current source sub-unit 105, and the gate of the second switch transistor M15 receives the encoded transmission signal 15, the source of the second switch transistor M15 is connected to the PAM4 output signal 21, and the drain of the second switch transistor M15 is connected to the second current source sub-unit 105.

[0073] According to an embodiment of the present disclosure, when the encoded transmission signal 15 is a logic high level 1, the second switch transistor M15 is turned on, so that the second current source subunit 105 is connected to the PAM4 output signal 21 and provides an output current for the PAM4 output signal 21, and when the encoded transmission signal 15 is a logic low level 0, the second switch transistor M15 is turned off, so that the second current source subunit 105 cannot provide an output current for the PAM4 output signal 21.

[0074] like Figure 5 As shown, according to an embodiment of the present disclosure, the third switch transistor M16 is connected in series with the third current source sub-unit 106, and the gate of the third switch transistor M16 receives the encoded transmission signal 16, the source of the third switch transistor M16 is connected to the PAM4 output signal 21, and the drain of the third switch transistor M16 is connected to the third current source sub-unit 106.

[0075] According to an embodiment of the present disclosure, when the encoded transmission signal 16 is a logic high level 1, the third switch transistor M16 is turned on, so that the third current source subunit 106 is connected to the PAM4 output signal 21 and provides an output current for the PAM4 output signal 21, and when the encoded transmission signal 16 is a logic low level 0, the third switch transistor M16 is turned off, so that the third current source subunit 106 cannot provide an output current for the PAM4 output signal 21.

[0076] like Figure 5 As shown, according to an embodiment of the present disclosure, the first current source subunit 104 and the first switch transistor M14 connected in series, the second current source subunit 105 and the second switch transistor M15 connected in series, and the third current source subunit 106 and the third switch transistor M16 connected in series are connected in parallel between the power supply voltage VDD and the PAM4 output signal 21. Therefore, the first current source subunit 104, the second current source subunit 105, and the third current source subunit 106 jointly provide current for the PAM4 output signal 21.

[0077] like Figure 5 As shown, according to an embodiment of the present disclosure, the output subunit 103 further includes a terminal resistance unit 107 for providing a terminal resistance. According to an embodiment of the present disclosure, a typical resistance value of the terminal resistance unit 107 may be, for example, 50 ohms.

[0078] Therefore, according to an embodiment of the present disclosure, the output level of the PAM4 output signal 21 is the product of the sum of the current values ​​output by all the first to third current source sub-units 104 to 106 and the resistance value provided by the terminal resistance unit 107 .

[0079] Specifically, according to an embodiment of the present disclosure, when the MSB signal 13 and the LSB signal 12 are "00", the encoded transmitted signal is "000", that is, the signal 16, the signal 15 and the signal 14 are all logic low level 0, so the third switch transistor M16, the second switch transistor M15 and the first switch transistor M14 are all turned off, so that the third current source sub-unit 106, the second current source sub-unit 105 and the first current source sub-unit 104 do not provide current for the PAM4 output signal 21, so that the voltage value of the PAM4 output signal 21 is 0, that is, it is at level 0.

[0080] Similarly, according to an embodiment of the present disclosure, when the MSB signal 13 and the LSB signal 12 are "01", the encoded transmission signal is "001", that is, the signal 16, the signal 15 and the signal 14 are respectively a logic low level 0, a logic low level 0 and a logic high level 1, so the third switch transistor M16 and the second switch transistor M15 are turned off and the first switch transistor M14 is turned on, so that only the first current source subunit 104 provides current for the PAM4 output signal 21, so that the voltage value of the PAM4 output signal 21 can be calculated as the product of the current value of the first current source subunit 104 and the resistance value of the terminal resistance unit 107, that is, level 1. Therefore, by adjusting the current value of the first current source subunit 104, the voltage value of the PAM4 output signal 21 can be adjusted, that is, the size of the eye height A of the PAM4 output signal 21 can be adjusted.

[0081] Therefore, according to an embodiment of the present disclosure, adjusting the first linearity configuration signal 41_1 can adjust the size of the eye height A by adjusting the current value of the first current source subunit 104 , so that the linearity of the PAM4 output signal 21 can be adjusted.

[0082] Similarly, according to an embodiment of the present disclosure, when the MSB signal 13 and the LSB signal 12 are "10", the encoded transmission signal is "011", that is, the signal 16, the signal 15 and the signal 14 are respectively a logic low level 0, a logic high level 1 and a logic high level 1, so the third switch transistor M16 is turned off and the second switch transistor M15 and the first switch transistor M14 are turned on, so that the second current source subunit 105 and the first current source subunit 104 provide current for the PAM4 output signal 21, so that the voltage value of the PAM4 output signal 21 can be calculated as the sum of the current values ​​of the second current source subunit 105 and the first current source subunit 104 and the product of the resistance value of the terminal resistance unit 107, that is, level 2. Since the eye height B is the voltage amplitude difference between the level 2 of the PAM4 output signal 21 and the level 1 of the PAM4 output signal 21, the size of the eye height B can be adjusted by adjusting the current value of the second current source subunit 105.

[0083] Therefore, according to an embodiment of the present disclosure, adjusting the second linearity configuration signal 41_2 can adjust the size of the eye height B by adjusting the current value of the second current source subunit 105 , so that the linearity of the PAM4 output signal 21 can be adjusted.

[0084] Similarly, according to the embodiment of the present disclosure, when the two bits of the MSB signal and the LSB signal are "11", the encoded transmission signal is "111", that is, the signal 16, the signal 15 and the signal 14 are all logic high level 1, so the third switch transistor M16, the second switch transistor M15 and the first switch transistor M14 are all turned on, so that the third current source subunit 106, the second current source subunit 105 and the first current source subunit 104 all provide current for the PAM4 output signal 21, so that the voltage value of the PAM4 output signal 21 can be calculated as the sum of the current values ​​of the third current source subunit 106, the second current source subunit 105 and the first current source subunit 104 and the product of the resistance value of the terminal resistance unit 107, that is, level 3. Since the eye height C is the voltage difference between the level 3 of the PAM4 output signal and the level 2 of the PAM4 output signal, the size of the eye height C can be adjusted by adjusting the current value of the third current source subunit 106.

[0085] Therefore, according to an embodiment of the present disclosure, adjusting the third linearity configuration signal 41_3 can adjust the size of the eye height C by adjusting the current value of the third current source subunit 106 , so that the linearity of the PAM4 output signal 21 can be adjusted.

[0086] In summary, according to the embodiments of the present disclosure, the linearity of the PAM4 output signal 21 may be adjusted by adjusting at least one of the first linearity configuration signal 41_1 , the second linearity configuration signal 41_2 , and the third linearity configuration signal 41_3 .

[0087] although Figure 5 The PAM4 output signal 21 of the output subunit 105 is shown as a single-ended signal, but those skilled in the art should recognize that when the PAM4 output signal 21 is a differential signal, the working principle described above is also applicable, so for the sake of brevity, it will not be repeated here.

[0088] Figure 6 A schematic block diagram of a readback unit 200 according to an embodiment of the present disclosure is shown.

[0089] like Figure 6 As shown, according to an embodiment of the present disclosure, the read-back unit 200 may include a parallelization subunit 201 , a decoding subunit 202 and an input subunit 203 .

[0090] like Figure 6 As shown, according to an embodiment of the present disclosure, the input subunit 203 can receive the PAM4 output signal 21 and the threshold configuration signal 42 and output the encoded readback signal, including the signal 26 , the signal 25 and the signal 24 .

[0091] Specifically, according to an embodiment of the present disclosure, when the PAM4 input signal 21 is level 0, the input subunit 203 can output the encoded readback signal "000", that is, the signal 26, the signal 25 and the signal 24 are all logic low level 0, when the PAM4 input signal 21 is level 1, the input subunit 203 can output the encoded readback signal "001", that is, the signal 26, the signal 25 and the signal 24 are respectively logic low level 0, logic low level 0 and logic high level 1, when the PAM4 input signal 21 is level 2, the input subunit 203 can output the encoded readback signal "011", that is, the signal 26, the signal 25 and the signal 24 are respectively logic low level 0, logic high level 1 and logic high level 1, and when the PAM4 input signal 21 is level 3, the input subunit 203 can output the encoded readback signal "111", that is, the signal 26, the signal 25 and the signal 24 are all logic high level 1.

[0092] According to an embodiment of the present disclosure, the input subunit 203 receives the threshold configuration signal 42. According to an embodiment of the present disclosure, the encoded readback signal output by the input subunit 203 can be changed by adjusting the threshold configuration signal 42, including at least one of the signals 26, 25 and 24.

[0093] like Figure 6 As shown, the decoding subunit 202 receives the encoded readback signals, including signal 26 , signal 25 and signal 24 , performs decoding operations thereon, and outputs a readback MSB signal 23 and a readback LSB signal 22 .

[0094] According to an embodiment of the present disclosure, the decoding subunit 202 can perform the following decoding operations on the encoded readback signal, including signal 26, signal 25 and signal 24: when the decoding subunit 202 receives the encoded readback signal "000", that is, signal 26, signal 25 and signal 24 are all logic low level 0, the decoding subunit 202 can output the readback MSB signal 23 and the readback LSB signal 22, both of which are logic low level 0, that is, "00"; when the decoding subunit 202 receives the encoded readback signal "001", that is, signal 26, signal 25 and signal 24 are respectively logic low level 0, logic low level 0 and logic high level 1, the decoding subunit 202 can output the readback MSB signal 23 and the readback LSB signal 22, both of which are logic low level 0. 23 and the readback LSB signal 22 of logic high level 1, that is, "01". When the decoding subunit 202 receives the encoded readback signal "011", that is, signal 26, signal 25 and signal 24 are logic low level 0, logic high level 1 and logic high level 1 respectively, the decoding subunit 202 can output the readback MSB signal 23 of logic high level 1 and the readback LSB signal 22 of logic low level 0, that is, "10", and when the decoding subunit 202 receives the encoded readback signal "111", that is, signal 26, signal 25 and signal 24 are all logic high level 1, the decoding subunit 202 can output the readback MSB signal 23 and the readback LSB signal 22 both of which are logic high level 1, that is, "11".

[0095] like Figure 6 As shown, according to an embodiment of the present disclosure, the parallelization subunit 201 may receive the readback MSB signal 23 and the readback LSB signal 22 and perform a parallelization operation to output a readback signal 31 .

[0096] According to an embodiment of the present disclosure, the parallelization subunit 201 may perform, for example, a 1:10 parallelization operation on the readback MSB signal 23 and the readback LSB signal 22 to output a readback signal 31 as a 20-bit digital signal.

[0097] Figure 7 A schematic circuit diagram of the input subunit 203 and a schematic eye diagram of the PAM4 output signal 21 according to an embodiment of the present disclosure are shown.

[0098] According to an embodiment of the present disclosure, the input subunit 203 may include a plurality of comparator subunits. Figure 7 As shown in (a), according to an embodiment of the present disclosure, the input sub-unit 203 may include a first comparator sub-unit 204 , a second comparator sub-unit 205 and a third comparator sub-unit 206 .

[0099] like Figure 7As shown in (a), according to an embodiment of the present disclosure, the positive input terminal of the first comparator subunit 204 receives the PAM4 output signal 21, the negative input terminal of the first comparator subunit 204 receives the first threshold signal 27, and the output of the first comparator subunit 204 is connected to the encoded readback signal 24.

[0100] According to an embodiment of the present disclosure, when the voltage of the PAM4 output signal 21 is greater than or equal to the voltage of the first threshold signal 27, the encoded readback signal 24 output by the first comparator sub-unit 204 can be a logic high level 1, and when the voltage of the PAM4 output signal 21 is less than the voltage of the first threshold signal 27, the encoded readback signal 24 output by the first comparator sub-unit 204 can be a logic low level 0.

[0101] like Figure 7 As shown in (a), according to an embodiment of the present disclosure, the positive input terminal of the second comparator subunit 205 receives the PAM4 output signal 21, the negative input terminal of the second comparator subunit 205 receives the second threshold signal 28, and the output of the second comparator subunit 205 is connected to the encoded readback signal 25.

[0102] Similarly, according to an embodiment of the present disclosure, when the voltage of the PAM4 output signal 21 is greater than or equal to the voltage of the second threshold signal 28, the encoded readback signal 25 output by the second comparator sub-unit 205 can be a logic high level 1, and when the voltage of the PAM4 output signal 21 is less than the voltage of the second threshold signal 28, the encoded readback signal 25 output by the second comparator sub-unit 205 can be a logic low level 0.

[0103] like Figure 7 As shown in (a), according to an embodiment of the present disclosure, the positive input terminal of the third comparator subunit 206 receives the PAM4 output signal 21, the negative input terminal of the third comparator subunit 206 receives the third threshold signal 29, and the output of the third comparator subunit 204 is connected to the encoded readback signal 26.

[0104] Similarly, according to an embodiment of the present disclosure, when the voltage of the PAM4 output signal 21 is greater than or equal to the voltage of the third threshold signal 29, the encoded readback signal 26 output by the third comparator sub-unit 206 can be a logic high level 1, and when the voltage of the PAM4 output signal 21 is less than the voltage of the third threshold signal 29, the encoded readback signal 26 output by the third comparator sub-unit 206 can be a logic low level 0.

[0105] exist Figure 7In the schematic eye diagram of the PAM4 output signal 21 shown in (b), the voltage of the PAM4 output signal 21 can be level 0, level 1, level 2, or level 3. According to an embodiment of the present disclosure, the threshold voltage 1 can be set between level 0 and level 1, the threshold voltage 2 can be set between level 1 and level 2, and the threshold voltage 3 can be set between level 2 and level 3.

[0106] According to an embodiment of the present disclosure, threshold voltage 1, threshold voltage 2, and threshold voltage 3 may be used as voltage determination conditions for the PAM4 output signal 21.

[0107] Specifically, according to an embodiment of the present disclosure, when the PAM4 output signal 21 is less than the threshold voltage 1, the PAM4 output signal 21 may be level 0, when the PAM4 output signal 21 is less than the threshold voltage 2 and greater than or equal to the threshold voltage 1, the PAM4 output signal 21 may be level 1, when the PAM4 output signal 21 is less than the threshold voltage 3 and greater than or equal to the threshold voltage 2, the PAM4 output signal 21 may be level 2, and when the PAM4 output signal 21 is greater than or equal to the threshold voltage 3, the PAM4 output signal 21 may be level 3.

[0108] According to an embodiment of the present disclosure, the voltage of the first threshold signal 27 may be set to threshold voltage 1 , the voltage of the second threshold signal 28 may be set to threshold voltage 2 , and the voltage of the third threshold signal 29 may be set to threshold voltage 3 .

[0109] Accordingly, according to the embodiment of the present disclosure, when the PAM4 output signal 21 is less than the voltage of the first threshold signal 27, the PAM4 output signal 21 is level 0, so the encoded readback signal is "000", that is, the signal 26, the signal 25 and the signal 24 are all logic low level 0, when the PAM4 output signal 21 is less than the voltage of the second threshold signal 28 and greater than or equal to the voltage of the first threshold signal 27, the PAM4 output signal 21 is level 1, so the encoded readback signal is "001", that is, the signal 26, the signal 25 and the signal 24 are logic low level 0, logic low level 0 and logic high level 0, respectively. High level 1, when the PAM4 output signal 21 is less than the voltage of the third threshold signal 29 and greater than or equal to the voltage of the second threshold signal 28, the PAM4 output signal 21 is level 2, so the encoded readback signal is "011", that is, the signal 26, the signal 25 and the signal 24 are logic low level 0, logic high level 1 and logic high level 1 respectively, and when the PAM4 output signal 21 is greater than or equal to the voltage of the third threshold signal 29, the PAM4 output signal 21 is level 3, so the encoded readback signal is "111", that is, the signal 26, the signal 25 and the signal 24 are all logic high level 1.

[0110] It can be seen that according to the embodiments of the present disclosure, by changing at least one of the voltage value of the first threshold signal 27, the voltage value of the second threshold signal 28 and the voltage value of the third threshold signal 29, the result of the encoded readback signal of the PAM4 output signal 21 can be changed.

[0111] According to an embodiment of the present disclosure, the threshold configuration signal 42 output by the control unit 400 may be a plurality of analog signals, serving as the first threshold signal 27 , the second threshold signal 28 , and the third threshold signal 29 , respectively.

[0112] According to an embodiment of the present disclosure, the threshold configuration signal 42 output by the control unit 400 may be a digital signal, and generates the first threshold signal 27 , the second threshold signal 28 and the third threshold signal 29 respectively through digital-to-analog conversion.

[0113] like Figure 7 As shown in (a), according to an embodiment of the present disclosure, the first threshold configuration signal 42_1 output by the control unit 400 is a digital signal. Accordingly, the first digital-to-analog conversion unit 207 receives the first threshold configuration signal 42_1 and performs digital-to-analog conversion on it to output a first threshold signal 27 .

[0114] like Figure 7 As shown in (a), according to an embodiment of the present disclosure, the second threshold configuration signal 42_2 output by the control unit 400 is a digital signal. Accordingly, the second digital-to-analog conversion unit 208 receives the second threshold configuration signal 42_2 and performs digital-to-analog conversion on it to output a second threshold signal 28.

[0115] like Figure 7 As shown in (a), according to an embodiment of the present disclosure, the third threshold configuration signal 42_3 output by the control unit 400 is a digital signal. Accordingly, the third digital-to-analog conversion unit 209 receives the third threshold configuration signal 42_3 and performs digital-to-analog conversion on it to output a third threshold signal 29 .

[0116] Figure 8 FIG. 8 is a schematic flow chart of a linearity adjustment method 800 of a PAM4 transmitting device 10 according to an embodiment of the present disclosure. Figures 3 to 7 The PAM4 transmitting device 10 may include a transmitting unit 100, a readback unit 200, a comparing unit 300 and a controlling unit 400. According to an embodiment of the present disclosure, a linearity adjustment method 800 of the PAM4 transmitting device 10 may include the following steps.

[0117] Step S801 : the control unit 400 outputs the linearity configuration signal 41 , and the sending unit 100 adjusts the linearity of the PAM4 output signal 21 according to the linearity configuration signal 41 .

[0118] As mentioned above Figures 3 to 7 As described, according to an embodiment of the present disclosure, the control unit 400 outputs the linearity configuration signal 41 to the transmitting unit 100 , and the transmitting unit 100 receives the transmitting signal 11 and adjusts the linearity of the PAM4 output signal 21 according to the received linearity configuration signal 41 .

[0119] Specifically, as mentioned above Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 may output the first linearity configuration signal 41_1 to the first current source subunit 104, and the first current source subunit 104 may adjust its output current according to the received first linearity configuration signal 41_1 to adjust the linearity of the PAM4 output signal 21. Similarly, as described above with reference to Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the control unit 400 may output the second linearity configuration signal 41_2 to the second current source subunit 105, and the second current source subunit 105 may adjust its output current according to the received second linearity configuration signal 41_2 to adjust the linearity of the PAM4 output signal 21. Similarly, as described above with reference to Figures 3 to 7 As described, according to an embodiment of the present disclosure, the control unit 400 can output the third linearity configuration signal 41_3 to the third current source sub-unit 106, and the third current source sub-unit 106 can adjust its output current according to the received third linearity configuration signal 41_3 to adjust the linearity of the PAM4 output signal 21.

[0120] Step S802: The control unit 400 outputs the threshold configuration signal 42, the readback unit 200 outputs the readback signal 31 according to the received threshold configuration signal 42, the comparison unit 300 compares the transmitted signal 11 and the readback signal 31 and outputs the comparison result 32 to the control unit 400, and the control unit 400 records the current threshold configuration signal 42 and the corresponding comparison result.

[0121] As mentioned above Figures 3 to 7 As described above, according to the embodiment of the present disclosure, the control unit 400 may output the threshold configuration signal 42, and the readback unit 200 may receive the PAM4 output signal 21 and output the readback signal 31 according to the received threshold configuration signal 42. Figures 3 to 7 According to the embodiment of the present disclosure, the comparison unit 300 can compare the transmission signal 11 and the readback signal 31 and output the comparison result 32 to the control unit 400. According to the embodiment of the present disclosure, the control unit 400 can record the current threshold configuration signal 42 and the corresponding comparison result 32.

[0122] Specifically, as mentioned above Figures 3 to 7As described above, according to an embodiment of the present disclosure, the control unit 400 may output a first threshold configuration signal 42_1, a second threshold configuration signal 42_2, and a third threshold configuration signal 42_3 to generate a first threshold signal 27, a second threshold signal 28, and a third threshold signal 29, respectively. Figures 3 to 7 As described above, according to the embodiment of the present disclosure, the readback unit 200 may output the readback signal 31 according to the voltage values ​​of the first to third threshold signals 27 to 29 .

[0123] As mentioned above Figures 3 to 7 As described above, according to an embodiment of the present disclosure, the comparison unit 300 may receive the readback signal 31 to compare the transmission signal 11 with the readback signal 31, and output the comparison result 32 to the control unit 400. According to an embodiment of the present disclosure, the control unit 400 may record the current threshold configuration signal 42, including the first threshold configuration signal 42_1, the second threshold configuration signal 42_2 and the third threshold configuration signal 42_3, and the corresponding comparison result 32.

[0124] Step S803: Repeat step S802 multiple times, and the control unit 400 records a series of threshold configuration signals 42 and a corresponding series of comparison results 32.

[0125] According to an embodiment of the present disclosure, the control unit 400 can change the threshold configuration signal 42 input to the readback unit 200, the readback unit 200 can output the readback signal 31 according to the received threshold configuration signal 42, the comparison unit 300 can output the comparison result 32 of the transmitted signal 11 and the readback signal 31, and the control unit 400 can record the current threshold configuration signal 42 and the corresponding comparison result 32.

[0126] According to an embodiment of the present disclosure, each time the control unit 400 changes the threshold configuration signal 42, the current threshold configuration signal 42 and the corresponding comparison result 32 are recorded. According to an embodiment of the present disclosure, the control unit 400 may repeat the above steps multiple times, that is, a series of threshold configuration signals 42 and a corresponding series of comparison results 32 may be recorded.

[0127] According to an embodiment of the present disclosure, the threshold configuration signal 42 can be adjusted. Figure 7 The threshold voltages 1 to 3 in the eye diagram shown in (b) cause the readback signal 31 output by the readback unit 200 to change, so as to determine the eye height of the PAM4 output signal 21 .

[0128] Specifically, according to an embodiment of the present disclosure, the voltage value of the first threshold signal 27, that is, the threshold voltage 1, can be changed by adjusting the first threshold configuration signal 42_1. By repeatedly adjusting the first threshold configuration signal 42_1, the control unit 400 can determine the size of the eye height A of the PAM4 output signal 21 according to the corresponding comparison result 32.

[0129] Similarly, according to an embodiment of the present disclosure, the voltage value of the second threshold signal 28, i.e., the threshold voltage 2, can be changed by adjusting the second threshold configuration signal 42_2. By repeatedly adjusting the second threshold configuration signal 42_2, the control unit 400 can determine the size of the eye height B of the PAM4 output signal 21 according to the corresponding comparison result 32.

[0130] Similarly, according to an embodiment of the present disclosure, the voltage value of the third threshold signal 29, that is, the threshold voltage 3, can be changed by adjusting the third threshold configuration signal 42_3. By repeatedly adjusting the third threshold configuration signal 42_3, according to the corresponding comparison result 32, the control unit 400 can determine the size of the eye height C of the PAM4 output signal 21.

[0131] Step S804: the control unit 400 calculates the linearity of the PAM4 output signal 21. When the linearity does not meet the target value, the control unit 400 adjusts the linearity configuration signal 42 so that the linearity of the PAM4 output signal 21 is close to the target value.

[0132] Specifically, according to an embodiment of the present disclosure, the control unit 400 can determine the size of the eye height A, eye height B and eye height C of the PAM4 output signal 21 according to a series of threshold configuration signals 42 and a corresponding series of comparison results 32 recorded in step S803.

[0133] According to an embodiment of the present disclosure, the control unit 400 can use the sizes of eye height A, eye height B and eye height C to calculate the linearity of the PAM4 output signal 21 according to the linearity calculation formula RLM=3×min(A,B,C) / sum(A,B,C).

[0134] According to an embodiment of the present disclosure, a target value of linearity may be preset. If the currently calculated linearity does not reach the target value of linearity, the control unit 400 may adjust the linearity configuration signal 41 to adjust the linearity of the PAM4 output signal 21 output by the transmitting unit 100, so that the linearity of the PAM4 output signal 21 is closer to the target value.

[0135] Specifically, as mentioned above Figures 3 to 7As described, according to an embodiment of the present disclosure, when the eye height A is small, the control unit 400 can adjust the first linearity configuration signal 41_1 so that the output current of the first current source subunit 104 is larger, so that the eye height A of the PAM4 output signal 21 is larger, thereby improving the linearity of the PAM4 output signal 21.

[0136] Similarly, as mentioned above, Figures 3 to 7 As described, according to an embodiment of the present disclosure, when the eye height C is large, the control unit 400 can adjust the third linearity configuration signal 41_3 so that the output current of the third current source subunit 106 is smaller, so that the eye height C of the PAM4 output signal 21 is smaller, thereby improving the linearity of the PAM4 output signal 21.

[0137] Step S805: Repeat steps S801 to S804 until the linearity of the PAM4 output signal 21 meets the target value.

[0138] According to an embodiment of the present disclosure, the control unit 400 may repeat steps S801 to S804 until the linearity of the PAM4 output signal 21 reaches a preset linearity target value.

[0139] According to an embodiment of the present disclosure, the PAM4 transmitting device 10 may perform the linearity adjustment method 800 of the PAM4 transmitting device once after power-on or during operation. According to an embodiment of the present disclosure, after the linearity of the PAM4 output signal 21 reaches the linearity target value, the readback unit 200 and the comparison unit 300 may be turned off, thereby reducing the overall power consumption of the PAM4 transmitting device 10.

[0140] According to the embodiments of the present disclosure, a time period may be pre-set for the PAM4 transmitting device 10. According to the time period, the PAM4 transmitting device 10 may periodically start the readback unit 200 and the comparison unit 300 and execute the linearity adjustment method 800 of the PAM4 transmitting device 10. When the readback unit 200 and the comparison unit 300 are not working, the readback unit 200 and the comparison unit 300 are turned off to save power. Therefore, the PAM4 transmitting device 10 may continuously adjust the linearity of the PAM4 output signal 21 according to the pre-set time period to achieve the linearity target value, thereby reducing the influence of changes in the external environment and temperature on the linearity of the PAM4 output signal 21.

[0141] According to the PAM4 transmitting device and linearity adjustment method thereof disclosed in the present invention, regardless of changes in the environment and temperature, the linearity of the PAM4 output signal can be adjusted in real time while the PAM4 output signal is output, thereby meeting the linearity requirements of the PAM4 output signal.

[0142] For the purpose of illustration, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure disclosed in the appended claims.

[0143] Although this document contains many details, these details should not be interpreted as limitations on the scope of the present disclosure or what may be claimed, but rather should be interpreted as descriptions of features that may be specific to a particular embodiment. Certain features described herein in the context of discrete embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially stated as such, in some cases, one or more features in the combination may be deleted from the claimed combination, and the claimed combination may involve sub-combinations or variations of sub-combinations.

Claims

1. A PAM4 transmitting device, comprising: A transmitting unit configured to receive a transmit signal and a linearity configuration signal, and output a PAM4 output signal; a readback unit configured to receive the PAM4 output signal and a threshold configuration signal, and output a readback signal; a comparison unit configured to receive the transmission signal and the readback signal, and compare the transmission signal and the readback signal to output a comparison result; as well as The control unit is configured to receive the comparison result and output the linearity configuration signal and the threshold configuration signal according to the comparison result.

2. The PAM4 transmitting device according to claim 1, wherein: The sending unit is configured to adjust the linearity of the PAM4 output signal according to the linearity configuration signal.

3. The PAM4 transmitting device according to claim 2, wherein: The transmitting unit includes one or more current source subunits, and The linearity configuration signal adjusts the linearity of the PAM4 output signal by adjusting the current value of the current source subunit.

4. The PAM4 transmitting device according to claim 1, wherein: The readback unit is configured to change the readback signal according to the threshold configuration signal.

5. The PAM4 transmitting device according to claim 4, wherein: The readback unit includes one or more comparator subunits, and The threshold configuration signal changes the readback signal by adjusting the threshold voltage of the comparator subunit.

6. The PAM4 transmitting device according to claim 1, wherein: The sending unit comprises: A serialization subunit, configured to receive the transmission signal and perform a serialization operation thereon, and output a transmission MSB signal and a transmission LSB signal; an encoding subunit configured to receive the transmit MSB signal and the transmit LSB signal and perform encoding operations thereon, and output an encoded transmit signal; and The output subunit is configured to receive the encoded transmit signal and the linearity configuration signal, and output the PAM4 output signal.

7. The PAM4 transmitting device according to claim 1, wherein: The readback unit comprises: An input subunit, configured to receive the PAM4 transmit signal and the threshold configuration signal, and output a coded readback signal; A decoding subunit, configured to receive the encoded readback signal and perform a decoding operation thereon, and output a readback MSB signal and a readback LSB signal; The parallelization subunit is configured to receive the readback MSB signal and the readback LSB signal, perform a parallelization operation thereon, and output the readback signal.

8. The PAM4 transmitting device according to claim 1, wherein: The PAM4 output signal is a single-ended output signal or a differential output signal.

9. The PAM4 transmitting device according to claim 1, wherein: The comparison unit is configured to output the comparison result indicating whether the transmission signal and the readback signal are identical.

10. The PAM4 transmitting device according to claim 1, wherein: The control unit is configured to record a series of threshold configuration signals and corresponding comparison results.

11. A linearity adjustment method for a PAM4 transmitting device according to any one of claims 1 to 10, comprising: Step 1: the control unit outputs the linearity configuration signal, and the sending unit adjusts the linearity of the PAM4 output signal according to the linearity configuration signal; Step 2: the control unit outputs the threshold configuration signal, the readback unit outputs the readback signal according to the threshold configuration signal, the comparison unit compares the transmission signal with the readback signal and outputs the comparison result to the control unit, and the control unit records the current threshold configuration signal and the corresponding comparison result; Step 3: Repeat the second step multiple times, and the control unit records a series of threshold configuration signals and a corresponding series of comparison results; Step 4: the control unit calculates the linearity of the PAM4 output signal, and when the linearity does not meet the target value, the control unit adjusts the linearity configuration signal; as well as Step 5: Repeat the first step to the fourth step until the linearity of the PAM4 output signal meets the target value.

12. The linearity adjustment method according to claim 11, wherein: The PAM4 transmitting device executes the linearity adjustment method once, and then turns off the readback unit and the comparison unit.

13. The linearity adjustment method according to claim 11, wherein: The PAM4 transmitting device periodically starts the readback unit and the comparison unit according to a time period to execute the linearity adjustment method.

14. The linearity adjustment method according to claim 11, wherein: The PAM4 output signal is a single-ended output signal or a differential output signal.

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