Communication device

Abstract

A communication apparatus includes a communication line, a master node, and a slave node. At least one of the master node and the slave node is configured to switch to one of a first state in which a feedback input of a bus voltage of the communication line is received to control a slew rate of the bus voltage to a desired value and a second state in which a slew rate of the bus voltage is controlled to a desired value. An input of a predetermined control signal is received in the second state to control the slew rate of the bus voltage to a desired value.

Description

Technical Field

[0001] The present disclosure relates to a communication device. Background Art

[0002] Recently, in the field of in-vehicle communication, communication devices such as clock extension peripheral interface (CXPI) communication devices are being put into practical use. These communication devices use pulse width modulation signals as line codes between multiple nodes (master nodes and slave nodes) connected to a communication line. Summary of the invention

[0003] A communication device according to one aspect of the present disclosure includes a communication line, a master node connected to the communication line, and a slave node connected to the communication line, wherein the master node and the slave node communicate with each other by using a pulse width modulation signal as a line code. At least one of the master node and the slave node is configured to switch to one of a first state and a second state, in which a feedback input of a bus voltage of the communication line is received to control a conversion rate of the bus voltage to a desired value, and in which a predetermined control signal is received to control the conversion rate of the bus voltage to a desired value. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 : is a block diagram illustrating the overall structure of a communication device according to a comparative example.

[0005] Figure 2 is a block diagram illustrating the structure of a communication device.

[0006] Figure 3 is a timing diagram showing a first signal, a driving signal, and a bus voltage during data transmission at a master node.

[0007] Figure 4 is a timing diagram showing a first signal, a driving signal, a second signal, a driving signal, and a bus voltage during data transmission at a slave node.

[0008] Figure 5 is a graph comparing the amount of noise generated during data transmission at a master node and during data transmission at a slave node.

[0009] Figure 6 is a block diagram illustrating the structure of a communication device according to the present disclosure.

[0010] Figure 7 is a timing diagram showing a first signal, a driving signal, a current detection signal, a second signal, a driving signal, and a bus voltage during data transmission at a slave node.

[0011] Figure 8is a timing diagram showing a first signal, a driving signal, a second signal, a driving signal, and a bus voltage during data transmission at a slave node.

[0012] Fig. 9 is a block diagram illustrating a structure of a communication device according to a second embodiment of the present disclosure.

[0013] Fig.10 is a timing diagram showing a first signal, a detection signal, a second signal, a driving signal, and a bus voltage during data transmission at a slave node according to a second embodiment of the present disclosure.

[0014] Fig.11 is a block diagram illustrating an example of a waveform shaping circuit. DETAILED DESCRIPTION

[0015] <Communication Device of Comparative Example>

[0016] First, refer to Figure 1 A communication device Y as a comparative example for comparison with the communication device X of the present disclosure (ie, a structure to be compared with an embodiment of the present disclosure described below) is described. Figure 1 : is a block diagram illustrating the overall structure of a communication device Y of a comparative example.

[0017] The communication device Y is installed in the vehicle as a device for constructing an in-vehicle local area network (LAN). The communication device Y includes a master node 1y, a plurality of slave nodes (such as the slave nodes 2Ay and 2By described with reference to the drawings), and a communication line 3. Note that the communication device Y complies with the CXPI protocol and uses a pulse width modulation signal PWM as a line code between a plurality of nodes connected to the communication line 3.

[0018] For example, the master node 1 y is a body control module (BCM) (or an electronic control unit (ECU) mounted on the BCM) that comprehensively controls components such as wipers and interior lights. The master node 1 y includes a CXPI transceiver 4 , a microcontroller 5 , and an oscillator 6 .

[0019] The slave node 2Ay is, for example, a windshield wiper (or an ECU installed in the windshield wiper). The slave node 2Ay includes a CXPI transceiver 7A and a microcontroller 8 .

[0020] The slave node 2By is, for example, an interior lamp (or an ECU installed in the interior lamp). The slave node 2By includes a CXPI transceiver 7B without a microcontroller. The CXPI transceiver 7B without a microcontroller includes, for example, a CXPI physical layer, a sequencer, and an interface (driver, etc.).

[0021] The communication line 3 is a so-called harness (wire harness) that extends over various components of the vehicle. Note that in addition to the above-mentioned wipers and interior lights, various vehicle-mounted devices such as air conditioners and rearview mirrors can also be assumed to be slave nodes connected to the communication line 3.

[0022] The features of the CXPI protocol will now be briefly described. First, both microcontrollers 5 and 8 can communicate using a multifunctional universal asynchronous receiver / transmitter (UART) interface. Secondly, a pulse width modulation signal PWM obtained by superimposing data on the communication clock CLK is used to achieve bidirectional communication between the CXPI transceiver 4 and the CXPI transceivers 7A and 7B. Third, the slave nodes 2Ay and 2By can extract the communication clock CLK from the pulse width modulation signal PWM, and therefore they do not need to be equipped with a separate oscillator. Fourth, in the communication device Y, bidirectional communication between multiple nodes is achieved synchronously with the communication clock CLK generated by the oscillator 6 of the master node 1y.

[0023] Next, bidirectional communication using the pulse width modulation signal PWM will be described. The logic value of data superimposed on the pulse width modulation signal PWM is determined according to the length of the period (=pulse width WL) during which the pulse width modulation signal PWM is at a low level (dominant level).

[0024] Specifically, the logic value is determined as follows: When the pulse width WL is shorter than a predetermined logic judgment value, the logic value of the judgment data is [1]. On the other hand, when the pulse width WL is longer than the logic judgment value, the logic value of the judgment data is [0].

[0025] When data [1] is transmitted from the master node 1y, the CXPI transceiver 4 sets the low level period (= pulse width WL) of the pulse width modulation signal PWM to be shorter than the logic judgment value. On the other hand, when data [0] is transmitted from the master node 1y, the CXPI transceiver 4 sets the low level period (= pulse width WL) of the pulse width modulation signal PWM to be longer than the logic judgment value.

[0026] Note that during the data sending period of the slave node 2Ay or 2By (= the data receiving period of the master node 1y), the master node 1y is always in the state of sending data [1], that is, the master node 1y is always in the state of sending the communication clock CLK for synchronization to the slave nodes 2Ay and 2By.

[0027] At this time, the CXPI transceiver 7A or 7B decides whether to extend the low level period (=pulse width WL) of the pulse width modulation signal PWM according to the data to be transmitted from the slave node 2Ay or 2By.

[0028] More specifically, when data [0] is transmitted from the slave node 2Ay or 2By, the low level period of the pulse width modulation signal PWM is extended, and the pulse width WL becomes longer than the logic judgment value. On the other hand, when data [1] is transmitted from the slave node 2Ay or 2By, the low level period of the pulse width modulation signal PWM is not extended, and the pulse width WL remains shorter than the logic judgment value.

[0029] Note that the communication device Y conforming to the CXPI protocol is configured so that the low level (dominant level) of the pulse width modulation signal PWM is dominant relative to the high level (recessive level). Therefore, in the event of a conflict between the data (master-side transmission signal and slave-side transmission signal) transmitted from the master node 1y and each of the slave nodes 2Ay and 2By, whichever node sends the low level (dominant level) for a longer time will be dominant in arbitration. It should also be noted that the above-mentioned part of the structure of the communication device Y is the same structure in the communication device X described below.

[0030] Next, the master node 1y and the slave node 2Ay will be described in more detail. The slave node 2By and the slave node 2Ay have the same basic structure. For this reason, only the slave node 2Ay will be described here, and the description of the slave node 2By will be omitted.

[0031] Figure 2 is a block diagram illustrating the structure of the communication device Y. Figure 2 As shown, the master node 1y includes an external terminal N1 as a device for establishing an electrical connection with an external device. The slave node 2Ay includes an external terminal N2 as a device for establishing an electrical connection with an external device. A first end of the communication line 3 is connected to the external terminal N1. A second end of the communication line 3 is connected to the external terminal N2. The master node 1y will be described first. Then, the slave node 2Ay will be described.

[0032] The master node 1y is composed of a diode D1a, a diode D1b, a terminal resistor R1, a receiving circuit 9, a communication circuit 10, and a waveform shaping circuit 11y.

[0033] The anode of the diode D1a is connected to the power supply terminal P1. The cathode of the diode D1a is connected to the first end of the terminal resistor R1. The second end of the terminal resistor R1 is connected to the external terminal N1. The anode of the diode D1b is connected to the second end of the terminal resistor R1. The cathode of the diode D1b is connected to the drain of the main side transistor T1 which will be described below.

[0034] The receiving circuit 9 detects the pulse width WL (= pulse width modulation signal PWM) of the bus voltage VBUS appearing on the communication line 3 and outputs the detection result to the communication circuit 10. A comparator that compares the bus voltage VBUS with a predetermined logic determination value may be used as the receiving circuit 9 as appropriate.

[0035] The communication circuit 10 receives data (slave-side transmission signal) transmitted from the slave node 2Ay by receiving the output of the receiving circuit 9. The communication circuit 10 also outputs the first signal S1 as data superimposed on the communication clock to the waveform shaping circuit 11y (more precisely, the master-side drive control circuit 12y described below).

[0036] The waveform shaping circuit 11 y transmits data (master-side transmission signal) to the slave node 2Ay based on the first signal S1 and the bus voltage VBUS.

[0037] Specifically, the waveform shaping circuit 11y includes a master-side drive control circuit 12y and a master-side transistor T1. The master-side drive control circuit 12y generates a drive signal G1 based on the first signal S1 input from the communication circuit 10 and the bus voltage VBUS. The master-side drive control circuit 12y generates a drive signal G1 having the same period as the first signal S1.

[0038] The master-side drive control circuit 12y controls the slew rate of the drive signal G1 based on the first signal S1 and the bus voltage VBUS. Specifically, at the logic level switching timing of the first signal S1, a predetermined slew rate (slope) is added to the rising / falling edge of the drive signal G1.

[0039] The main side transistor T1 is an N-channel metal oxide semiconductor field effect transistor (NMOSFET). The source of the main side transistor T1 is connected to the ground terminal. The gate of the main side transistor T1 is connected to the application end of the drive signal G1 (= the output end of the main side drive control circuit 12y). The drain of the main side transistor T1 is connected to the communication line 3 (more precisely, the external terminal N1) via the diode D1b.

[0040] When the drive signal G1 is at a high level, the main side transistor T1 is turned on, and when the drive signal G1 is at a low level, the main side transistor T1 is turned off.

[0041] The slave node 2Ay is composed of a diode D2a, a diode D2b, a receiving circuit 13, a communication circuit 14, a waveform shaping circuit 15y, and a terminal resistor R2.

[0042] The anode of the diode D2a is connected to the power supply terminal P2. The cathode of the diode D2a is connected to the first end of the terminal resistor R2. The second end of the terminal resistor R2 is connected to the external terminal N2. The resistance value of the terminal resistor R2 is greater than the resistance value of the terminal resistor R1. For example, the resistance value of the terminal resistor R1 may be 1 kΩ, and the resistance value of the terminal resistor R2 may be 30 kΩ.

[0043] The anode of the diode D2b is connected to the second end of the terminal resistor R2. The cathode of the diode D2b is connected to the drain of the slave-side transistor T2 to be described below.

[0044] The receiving circuit 13 detects the pulse width WL (= pulse width modulation signal PWM) of the bus voltage VBUS appearing on the communication line 3, and outputs the detection result to the communication circuit 14. As the receiving circuit 13, a comparator that compares the bus voltage VBUS with a predetermined logic judgment value can be used appropriately. Note that the slave node 2Ay is configured to be able to record the length of the pulse width WL of the bus voltage VBUS.

[0045] The communication circuit 14 receives data (master-side transmission signal) transmitted from the master node 1y by receiving the output of the receiving circuit 13. The communication circuit 14 can detect the communication clock for generating the first signal S1, that is, the switching timing of the logic level of the first signal S1 (in other words, the switching timing of the logic level of the drive signal G1) from the output of the receiving circuit 13. The communication circuit 14 outputs the second signal S2 obtained by superimposing the data on the communication clock and detected from the output of the receiving circuit 13 to the waveform shaping circuit 15y (more precisely, the slave-side drive control circuit 16y to be described below).

[0046] The waveform shaping circuit 15 y transmits data (slave-side transmission signal) to the master node 1 y based on the second signal S2 and the bus voltage VBUS.

[0047] Specifically, the waveform shaping circuit 15y includes a slave-side drive control circuit 16y and a slave-side transistor T2. The slave-side drive control circuit 16y generates a drive signal G2 based on the second signal S2 input from the communication circuit 14 and the bus voltage VBUS. The slave-side drive control circuit 16y generates a drive signal G2 having the same period as the period of the second signal S2.

[0048] The slave-side drive control circuit 16y controls the slew rate of the drive signal G2 based on the second signal S2 and the bus voltage VBUS. Specifically, at the logic level switching timing of the second signal S2, a predetermined slew rate is added to the rising / falling edge of the drive signal G2.

[0049] The slave-side transistor T2 is an NMOSFET. The source of the slave-side transistor T2 is connected to the ground terminal. The gate of the slave-side transistor T2 is connected to the application end of the drive signal G2 (= the output end of the slave-side drive control circuit 16y). The drain of the slave-side transistor T2 is connected to the communication line 3 (more precisely, the external terminal N2) via the diode D2b.

[0050] When the drive signal G2 is at a high level, the slave side transistor T2 is turned on, and when the drive signal G2 is at a low level, the slave side transistor T2 is turned off. Thereafter, the bus voltage VBUS in a state where both the master side transistor T1 and the slave side transistor T2 are turned off is referred to as a first voltage V1. The first voltage V1 is approximately 12V.

[0051] In the state where the master-side transistor T1 is turned on and the slave-side transistor T2 is turned off, a micro-current flows in the communication line 3 in the direction from the slave node 2Ay to the master node 1y. More precisely, the current flows from the power supply terminal P2 through the communication line 3 via the diode D1b and the master-side transistor T1 to the ground terminal. Since the current flows through the terminal resistor R2 having a high resistance value, the current value of the current is tiny. And in this case, the current flows from the power supply terminal P1 via the diode D1b and the master-side transistor T1 to the ground terminal. The current does not flow to the communication line 3.

[0052] The bus voltage VBUS in this state (=master transistor T1 is on and slave transistor T2 is off) is a second voltage V2. The voltage value of the second voltage V2 corresponds to the value of the forward voltage drop of the diode D1b, which is about 0.7 to 0.8V.

[0053] In a state where both the master-side transistor T1 and the slave-side transistor T2 are turned on, current flows in a direction from the master node 1y to the slave node 2Ay in the communication line 3. This current is approximately equal to a current value obtained by subtracting a current flowing from the power supply terminal P1 via the terminal resistor R1 having a low resistance value (e.g., 1 kΩ) from a current flowing toward the ground terminal via the master-side transistor T1.

[0054] The bus voltage VBUS in this state (=both the master-side transistor T1 and the slave-side transistor T2 are turned on) is the third voltage V3. The voltage value of the third voltage V3 is the forward drop voltage of each of the diodes D1b and D2b, and is approximately 0.6V.

[0055] In the state where both the master-side transistor T1 and the slave-side transistor T2 are turned on, the current flowing from the power supply terminal P1 is divided into a current flowing to the ground terminal via the diode D1b and a current flowing to the ground terminal via the communication line 3 and the diode D2b. Therefore, the current value flowing through the diode D1b is smaller than the current value in the state where the master-side transistor T1 is turned on and the slave-side transistor T2 is turned off, and the forward drop voltage of the diode D1b decreases. Therefore, the third voltage V3 becomes smaller than the second voltage V2. The forward drop voltage of the diode D2b is similarly reduced.

[0056] In a state where the master-side transistor T1 is turned off and the slave-side transistor T2 is turned on, a current flows in the communication line 3 in a direction from the master node 1y to the slave node 2Ay. This current corresponds to almost all of the large current flowing through the terminal resistor R1 having a low resistance value. Therefore, compared with the case where both the master-side transistor T1 and the slave-side transistor T2 are turned on, the current value increases. Therefore, the bus voltage VBUS in this state (= the master-side transistor T1 is turned off and the slave-side transistor T2 is turned on) is greater than the bus voltage VBUS in a state where both the master-side transistor T1 and the slave-side transistor T2 are turned on. The bus voltage VBUS in this state is approximately equal to the second voltage V2.

[0057] <Data transmission between nodes>

[0058] Next, the data transmission between the master node 1y and the slave node 2Ay will be described in detail with reference to the timing diagram. As described above, the communication between the master node 1y and the slave node 2Ay in the communication device Y is realized by a communication method that distinguishes the logic value (=data [0] or data [1]) according to whether the pulse width WL (=length of the low level period) of the pulse width modulation signal PWM exceeds a predetermined logic judgment value. Specifically, the following method is used.

[0059] First, a case where the master node 1y transmits data to the slave node 2Ay will be described. Figure 3 is a timing diagram showing the first signal S1 , the drive signal G1 , and the bus voltage VBUS during data transmission of the master node 1 y .

[0060] During the data transmission period of the master node 1y, the master node 1y is basically in a state of outputting data [1] to the communication line 3. This state is a state during the period from time t11 to time t13, as will be referred to in Figure 3 At this time, the drive signal G1 is pulse driven with an "on" duty ratio (=Ton / T, where T is the switching period and Ton is the on period) such that the pulse width WL (=length of the low level period) of the pulse width modulation signal PWM is lower than the logic judgment value.

[0061] In the data transmission period of the master node 1y, in the case where the master node 1y outputs data [0] to the communication line 3, the drive signal G1 is pulse-driven at an "on" duty ratio such that the pulse width WL (=length of the low level period) of the pulse width modulation signal PWM exceeds the logic judgment value. This state is the state during the period from time t13 to time t15, which will be referred to as Figure 3 Give a description.

[0062] As described above, the master-side drive control circuit 12y adds a slew rate to the rising / falling edge of the drive signal G1 at the logic level switching timing of the first signal S1. Figure 3 , a predetermined conversion rate (slope) is added to the drive signal G1 at times t11, t13, and t15 and at times t12, t14, and t16.

[0063] By adding a slew rate to the rising / falling edge of the driving signal G1 , the bus voltage VBUS changes at a predetermined slew rate when changing between the first voltage V1 and the second voltage V2 .

[0064] Next, a case where data is transmitted from the slave node 2Ay to the master node 1y will be described. Figure 4 is a timing diagram showing the first signal S1 , the drive signal G1 , the second signal S2 , the drive signal G2 , and the bus voltage VBUS during data transmission from the node 2Ay.

[0065] During the data transmission period of the slave node 2Ay, the master node 1y is still basically in a state of outputting data [1] to the communication line 3.

[0066] During the period of sending data [1] from the slave node 2Ay (refer to Figure 4 During the time t21 to t23), the drive signal G2 is kept at a low level, and the slave side transistor T2 is kept off. Therefore, the low level period of the pulse width modulation signal PWM is not extended, and the pulse width WL is kept shorter than the logic judgment value.

[0067] On the other hand, during the period when the slave node 2Ay transmits data [0] to the master node 1y (refer to Figure 4 From time t23 to time t27), the pulse width WL is extended to exceed the logic judgment value.

[0068] Specifically, after the node 2Ay receives the falling timing of the first signal S1 (= the falling timing of the bus voltage VBUS) via the communication line 3, the second signal S2 is lowered to a low level. At this time, a conflict occurs between the data output from the master node 1y (master-side transmission signal) and the data output from the slave node 2Ay (slave-side transmission signal). Therefore, the data output from the slave node 2Ay becomes dominant, and the pulse width WL is extended until the timing when the second signal S2 switches from the low level to the high level.

[0069] More specifically, referring to Figure 4 , at time t23, the drive signal G1 rises to the high level, and the bus voltage VBUS drops, causing the slave node 2Ay to detect the falling timing of the first signal S1. Then, at time t24, after a predetermined period, the slave node 2Ay raises the drive signal G2 to the high level.

[0070] At time t25, the drive signal G1 drops to the low level. At time t26, when the low level is longer than the pulse width WL recorded during the interval from time t21 to time t23, the slave node 2Ay drops the drive signal G2 to the low level. Therefore, by adjusting the timing at which the slave node 2Ay drops the drive signal G2 to the low level, the pulse width WL is longer than the logical judgment value, and the data [1] is sent from the slave node 2Ay to the master node 1y.

[0071] <EMI Noise Consideration>

[0072] Incidentally, a sharp change in the bus voltage VBUS may cause the generation of EMI noise. The generation of EMI noise is explained below.

[0073] In the communication device Y, as described above, the master-side drive control circuit 12y adds a slew rate to the drive signal G1 at the logical level switching timing of the first signal S1 (refer to Figure 4 times t21, t22, t23, t27, and t28). The slave-side drive control circuit 16y also adds a slew rate to the drive signal G2 at the logical level switching timing of the second signal S2 (refer to Figure 4 time t26).

[0074] The transition speed between the on / off states of the master-side transistor T1 changes according to the slew rate of the drive signal G1. In addition, the transition speed between the on / off states of the slave-side transistor T2 changes according to the slew rate of the drive signal G2. When the bus voltage VBUS changes between the above first voltage V1 and second voltage V2, a slew rate is added to the bus voltage VBUS according to the slew rates of the drive signal G1 and the drive signal G2.

[0075] Therefore, at the logic level switching timing of the first signal S1 and the logic level switching timing of the second signal S2 , the bus voltage VBUS changes relatively slowly with the increased slew rate, and the generation of EMI noise is suppressed.

[0076] As described above, the slew rates of the driving signals G1 and G2 are controlled based on the bus voltage VBUS. In other words, by receiving a feedback input of the bus voltage VBUS, the slew rate of the bus voltage VBUS is feedback-controlled to a desired value.

[0077] Incidentally, in a state where the slave-side transistor T2 is in the on state and the master-side transistor T1 is turned on, EMI noise may be generated even at the logic level switching timing of the second signal S2. This is due to the following reasons.

[0078] As described above, in the state where the master side transistor T1 is turned on and the slave side transistor T2 is turned off (refer to Figure 4 In the state immediately before time t24), the voltage value of the bus voltage VBUS is the second voltage V2. When the slave-side transistor T2 is turned on in this state, the bus voltage VBUS drops from the second voltage V2 to the third voltage V3. The potential difference (= about 0.1V) between the second voltage V2 and the third voltage V3 is much smaller than the potential difference (= about 11V) between the first voltage V1 and the second voltage V2.

[0079] Here, the slew rate added to the bus voltage VBUS is feedback-controlled to a desired value, which is set to a value added when the bus voltage VBUS shifts between the first voltage V1 and the second voltage V2 (when the voltage value of the bus voltage VBUS shifts between about 12V and about 0.7V). In contrast, in the case where the bus voltage VBUS shifts between the second voltage V2 (=about 0.7V) and the third voltage V3 (about 0.6V), the potential difference (=about 0.1V) is relatively small, as described above. When the bus voltage VBUS drops from the second voltage V2 to the third voltage V3, it is difficult to make the slew rate of the bus voltage VBUS reach the desired value by the feedback control as described above. Therefore, when the bus voltage VBUS drops from the second voltage V2 to the third voltage V3 (when the slave side transistor T2 is turned on while the master side transistor T1 is in the on state), the bus voltage VBUS shifts sharply and generates EMI noise.

[0080] Similarly, even at the logic level switching timing of the first signal S1, if the master side transistor T1 is turned off while the slave side transistor T2 is in the on state, EMI noise may be generated. This is due to the following reasons.

[0081] As described above, in the state where both the master-side transistor T1 and the slave-side transistor T2 are turned on (see reference Figure 4In the state during the period from time t24 to time t25 described above, the voltage value of the bus voltage VBUS is the third voltage V3. When the master-side transistor T1 is turned off in this state, the bus voltage VBUS rises from the third voltage V3 to the second voltage V2. The potential difference (=about 0.1V) between the second voltage V2 and the third voltage V3 is much smaller than the potential difference (about 11V) between the first voltage V1 and the second voltage V2. When the master-side transistor T1 is turned off when the slave-side transistor T2 is in the on state, it is difficult to make the conversion rate of the bus voltage VBUS reach the desired value through the feedback control as described above. Therefore, when the bus voltage VBUS rises from the third voltage V3 to the second voltage V2 (when the master-side transistor T1 is turned off when the slave-side transistor T2 is in the on state), the bus voltage VBUS shifts sharply and generates EMI noise.

[0082] Figure 5 is a graph comparing the amount of noise generated during data transmission at the master node 1y and during data transmission at the slave node 2Ay. Figure 5 In FIG. 1 , data transmission at the master node 1 y is represented by a dotted line, and data transmission at the slave node 2Ay is represented by a solid line.

[0083] Generally, EMI noise has a relatively high frequency bandwidth among various types of noise. Figure 5 As shown, in a frequency band lower than a given frequency a [Hz], the amount of noise between the data transmission at the slave node 2Ay and the data transmission at the master node 1y is equal. However, in a relatively high frequency band higher than the frequency a [Hz], the amount of noise during the data transmission at the slave node 2Ay is higher than the amount of noise during the data transmission at the master node 1y. This is because during the period when the slave node 2Ay transmits data [0] (as shown in reference Figure 4 EMI noise is generated during the described period from time t23 to time t26), as described above.

[0084] The changes in the bus voltage VBUS and EMI noise have been explained focusing on the diodes D1a to D2b. However, even when focusing on the current (bus current) flowing in the communication line 3, the same problem as described above can be explained, that is, a sharp change in the bus voltage VBUS causes a sharp change in the bus current, which generates EMI noise.

[0085] In response to the above problems, the communication device X according to the embodiment of the present disclosure can suppress the generation of EMI noise. The communication device X according to the first embodiment of the present disclosure will be described in detail below. The communication device X according to the embodiment of the present disclosure has a common structure with the above-mentioned communication device Y. For this reason, the common structure is represented by the same figure mark and omitted from the description.

[0086] <Communication device of the present disclosure>

[0087] Similar to the above-mentioned communication device Y, the communication device X of the first embodiment of the present disclosure is installed in a vehicle as a device for constructing an in-vehicle local area network (LAN). The communication device X complies with the CXPI protocol and uses a pulse width modulation signal PWM as a line code between multiple nodes.

[0088] Figure 6 is a block diagram illustrating the structure of the communication device X of the present disclosure. Figure 6 As shown, the communication device X includes a master node 1x, a slave node 2Ax, and a communication line 3. The master node 1x includes an external terminal N1 as a means for establishing an electrical connection with an external device. The slave node 2Ax includes an external terminal N2 as a means for establishing an electrical connection with an external device.

[0089] At least one of the master node 1x and the slave node 2Ax is configured to be switchable between a first state and a second state. The first state is a state in which at least one of the master node 1x and the slave node 2Ax feedback controls the conversion rate of the bus voltage VBUS to a desired value by receiving a feedback input of the bus voltage VBUS. The second state is a state in which at least one of the master node 1x and the slave node 2Ax controls the conversion rate of the bus voltage VBUS to a desired value by receiving a predetermined internal signal input. The specific structures of the master node 1x and the slave node 2Ax will be described below.

[0090] The master node 1 x is composed of a diode D1 a , a diode D1 b , a terminal resistor R1 , a receiving circuit 9 , a communication circuit 10 , a control circuit 17 , a selector 18 , a waveform shaping circuit 11 x , and a detection circuit 19 .

[0091] The communication circuit 10 receives the data transmitted from the slave node 2Ax by receiving the output of the reception circuit 9 .

[0092] The detection circuit 19 is connected to the current path through the main side transistor T1 (at Figure 6 The detection circuit 19 detects a change in current (= a decrease in the sink current flowing in the main side transistor T1) during the on period Ton of the main side transistor T1, and inputs the result of the detection to the selector 18 as a current detection signal S3.

[0093] The control circuit 17 outputs a predetermined control signal. The selector 18 receives the output of the control circuit 17 and the bus voltage VBUS, selects the output of the control circuit 17 or the bus voltage VBUS according to the current detection signal S3, and inputs the selection to the waveform shaping circuit 11x (more specifically, the main side drive control circuit 12x).

[0094] The waveform shaping circuit 11x receives the first signal S1 and the output of the selector 18, and transmits data to the slave node 2Ax while controlling the slew rate of the bus voltage VBUS.

[0095] In the case where the output of the selector 18 is the bus voltage VBUS, the waveform shaping circuit 11x receives the bus voltage VBUS as a feedback input and feedback-controls the slew rate of the bus voltage VBUS to a desired value. This state is the first state described above. In the case where the output of the selector 18 is the output of the control circuit 17, the waveform shaping circuit 11x receives the control signal (internal signal) output by the control circuit 17 as an input and controls the slew rate of the bus voltage VBUS to a desired value. This state is the second state described above.

[0096] Specifically, the waveform shaping circuit 11x includes a main-side drive control circuit 12x and a main-side transistor T1. The main-side drive control circuit 12x generates a drive signal G1 in response to the first signal S1 and the output of the selector 18. More specifically, the main-side drive control circuit 12x generates a drive signal G1 having the same period as the first signal S1.

[0097] The master-side drive control circuit 12x controls the slew rate of the drive signal G1 based on the first signal S1 and the output of the selector 18. Specifically, the master-side drive control circuit 12x adds a slew rate based on the bus voltage VBUS or a slew rate based on the output of the control circuit 17 to the drive signal G1 at the logic level switching timing of the first signal S1.

[0098] The slave node 2Ax is composed of a diode D2a, a diode D2b, a receiving circuit 13, a communication circuit 14, a waveform shaping circuit 15x, and a terminal resistor R2.

[0099] The communication circuit 14 receives data transmitted from the master node 1x by receiving the output of the receiving circuit 13. The communication circuit 14 also transmits data to the master node 1x by outputting a second signal S2 obtained by superimposing data on a communication clock extracted from the output of the receiving circuit 13 to a waveform shaping circuit 15x (more precisely, to a slave-side drive control circuit 16x to be described below).

[0100] The control circuit 20 outputs a predetermined control signal. The selector 21 receives the output of the control circuit 20 and the bus voltage VBUS, and inputs the output of the control circuit 20 or the bus voltage VBUS to the waveform shaping circuit 15x (more precisely, the slave side driving control circuit 16x) under a predetermined condition. In other words, the communication circuit 14 switches the output of the selector 21 to the output of the control circuit 20 or the bus voltage VBUS in synchronization with the logic level switching timing of the second signal S2.

[0101] The waveform shaping circuit 15x receives the second signal S2 and the output of the selector 21, and transmits data to the master node 1x while controlling the slew rate of the bus voltage VBUS.

[0102] In the case where the output of the selector 21 is the bus voltage VBUS, the waveform shaping circuit 15x receives the bus voltage VBUS as a feedback input and feedback-controls the slew rate of the bus voltage VBUS to a desired value. This state is the first state described above. In the case where the output of the selector 21 is the output of the control circuit 20, the waveform shaping circuit 15x receives the control signal (internal signal) output by the control circuit 20 as an input and controls the slew rate of the bus voltage VBUS to a desired value. This state is the second state described above.

[0103] Specifically, the waveform shaping circuit 15x includes a slave-side drive control circuit 16x and a slave-side transistor T2. The slave-side drive control circuit 16x generates a drive signal G1 in response to the second signal S2 and the output of the selector 21. More precisely, the slave-side drive control circuit 16x generates a drive signal G2 having the same period as that of the second signal S2.

[0104] The slave-side drive control circuit 16x controls the slew rate of the drive signal G2 based on the second signal S2 and the output of the selector 21. Specifically, the slave-side drive control circuit 16x adds a slew rate based on the bus voltage VBUS or a slew rate based on the output of the control circuit 20 to the drive signal G2 at the logic level switching timing of the second signal S2.

[0105] The following describes in more detail the slew rate control of the bus voltage VBUS by the communication device X according to the present embodiment.

[0106] Figure 7 is a timing diagram illustrating the first signal S1 , the drive signal G1 , the current detection signal S3 , the second signal S2 , the drive signal G2 , and the bus voltage VBUS during data transmission at the slave node 2Ax.

[0107] The slave node 2Ax switches to the second state at the first timing. The first timing is the timing at which the logic level of the second signal S2 switches from a high level (= recessive level) to a low level (= dominant level). Figure 7 , the first timing is time t34.

[0108] On the other hand, the master node 1x switches to the second state at the second timing. The second timing is the timing at which the logic level of the first signal S1 switches when the second signal S2 is set to a low level (= dominant level) by the slave node 2Ax. Figure 7 , the second timing is time t35.

[0109] The master node 1x switches to the first state at the third timing. The third timing is the timing at which the logic level of the first signal S1 switches when the second signal S2 is set to a high level (= recessive level) by the slave node 2A1. Figure 7 , the third timing is time t31, time t32, time t33, time t37 and time t38.

[0110] The master node 1 x determines whether the logic level switching timing of the first signal S1 is the second timing or the third timing based on the current detection signal S3 output by the detection circuit 19 .

[0111] The slave node 2Ax switches to the first state at the fourth timing. The fourth timing is the timing at which the logic level of the second signal S2 switches from a low level (= dominant level) to a high level (= recessive level). Figure 7 , the fourth timing is t36.

[0112] The following are references Figure 7 . At time t31, time t33, and time t37 (= third timing), the first signal S1 drops to a low level, while the drive signal G1 rises to a high level. Therefore, the slave-side transistor T2 remains off, while the master-side transistor T1 is turned on. Therefore, the bus voltage VBUS drops from the first voltage V1 to the second voltage V2.

[0113] At time t31 and time t33, the detection circuit 19 outputs a current detection signal S3 of a low level. At time t37, the detection circuit 19 detects that the bus voltage VBUS is the first voltage V1, and reduces the current detection signal S3 to a low level. The selector 18 receives the low-level current detection signal S3, selects the bus voltage VBUS, and inputs the bus voltage VBUS to the main-side drive control circuit 12x. Then, the conversion rate is added to the drive signal G1 based on the bus voltage VBUS, and rises from a low level to a high level. Therefore, at time t31, time t33, and time t37 (= third timing), the conversion rate (specifically, the conversion rate that is feedback-controlled to a desired value by receiving a feedback input of the bus voltage VBUS) is added to the bus voltage VBUS.

[0114] At time t32 and time t38 (= third timing), the first signal S1 rises from low level to high level, the drive signal G1 falls to low level, and both the master side transistor T1 and the slave side transistor T2 are turned off. Therefore, the bus voltage VBUS rises from the second voltage V2 to the first voltage V1.

[0115] At this time, the detection circuit 19 outputs a low-level current detection signal S3. Therefore, the selector 18 receives the low-level current detection signal S3, selects the bus voltage VBUS, and inputs the bus voltage VBUS to the main-side drive control circuit 12x. Therefore, the second slew rate is added to the drive signal G1, and the drive signal G1 drops from a high level to a low level. Therefore, at time t32 and time t38 (= third timing), the slew rate (specifically, the slew rate that is feedback-controlled to a desired value by receiving a feedback input of the bus voltage VBUS) is added to the bus voltage VBUS.

[0116] At time t34 (= first timing), the second signal S2 rises to a high level while the first signal S1 is at a low level. At this time, the slave transistor T2 is turned on while the master transistor T1 is on, and the bus voltage VBUS drops from the second voltage V2 to the third voltage V3.

[0117] At this time, the selector 21 selects the output of the control circuit 20 and outputs this to the slave-side drive control circuit 16x. Therefore, the drive signal G2 rises from a low level to a high level in a state where a slew rate based on the output of the control circuit 20 is added. Therefore, at time t34, a slew rate (specifically, a slew rate controlled to a desired value by receiving an internal signal (= output signal of the control circuit 20)) is added to the bus voltage VBUS.

[0118] After reaching time t34 and before reaching time t35, the detection circuit 19 detects the current change in the on period Ton of the primary side transistor T1 and raises the logic level of the current detection signal S3 from the low level to the high level. Then, the selector 18 selects the output of the control circuit 17 based on the current detection signal S3 and outputs it to the primary side drive control circuit 12x.

[0119] At time t35 (second timing), the first signal S1 rises from a state where both the first signal S1 and the second signal S2 are at a low level to a high level. At this time, only the master-side transistor T1 is turned off from a state where both the master-side transistor T1 and the slave-side transistor T2 are turned on. Then, the bus voltage VBUS rises from the third voltage V3 to the second voltage V2.

[0120] At this time, as described above, the logic level of the current detection signal S3 is high, and the selector 18 receives the high-level current detection signal S3, selects the output of the control circuit 17, and outputs this to the main-side drive control circuit 12x. Therefore, the second slew rate is added to the drive signal G1, and the drive signal G1 drops from a high level to a low level. Therefore, at time t35, the slew rate (specifically, the slew rate controlled to a desired value by receiving an internal signal (= the output signal of the control circuit 17)) is added to the bus voltage VBUS.

[0121] At time t36 (= fourth timing), the second signal S2 rises from low level to high level, the drive signal G2 falls from high level to low level, and both the master side transistor T1 and the slave side transistor T2 are turned off. Therefore, the bus voltage VBUS rises from the second voltage V2 to the first voltage V1.

[0122] At this time, the selector 21 selects the bus voltage VBUS and outputs the bus voltage VBUS to the slave-side drive control circuit 16x. Therefore, the slew rate based on the bus voltage VBUS is added to the drive signal G2, and the drive signal G2 drops from a high level to a low level. Therefore, at time t36 (= fourth timing), the slew rate (the slew rate that is feedback-controlled to a desired value by receiving a feedback input of the bus voltage VBUS) is added to the bus voltage VBUS.

[0123] As described above, by switching to the first state or the second state, when the slave-side transistor T2 is turned on in the state where the master-side transistor T1 is turned on, and when the master-side transistor T1 is turned off in the state where the slave-side transistor T2 is turned on, a desired slew rate can be added to the bus voltage VBUS. Therefore, EMI noise can be suppressed.

[0124] <Considerations on burrs>

[0125] Incidentally, in the case where the pulse width of the low level of the first signal S1 is relatively small (for example, the minimum value within the range that complies with the communication standard), even if the pulse width is a value that can be adopted under the communication standard (=CXPI protocol), a so-called glitch may occur due to the above-mentioned conversion rate control. When a glitch that is not allowed by the communication standard occurs, the bidirectional communication between the master node 1x and the slave node 2Ax may become unstable (or fail). Figure 8 Explain the occurrence of glitches in detail.

[0126] Figure 8 is a timing diagram showing the first signal S1 , the drive signal G1 , the second signal S2 , the drive signal G2 , and the bus voltage VBUS during data transmission at the slave node 2Ax.

[0127] Here, as described above, when the drive signal G2 rises from a low level to a high level, the conversion rate is added to the drive signal G2. Assume that the pulse width of the low level of the first signal S1 is the minimum width that satisfies the communication standard. Then, at time t41, when the drive signal G2 rises to a high level, the drive signal G1 falls to a low level, and this may cause a so-called glitch (see Figure 8 The bus voltage VBUS rises instantaneously at this glitch.

[0128] In order to deal with such a problem, the communication device X according to the second embodiment of the present disclosure can suppress the occurrence of glitches. The second embodiment of the communication device X will now be described. In the following description, the differences from the first embodiment will be described, and the same structures as those in the first embodiment will be represented by the same reference numerals and omitted from the description.

[0129] Fig. 9 : is a block diagram illustrating the structure of a communication device X according to a second embodiment of the present disclosure. Fig. 9 As shown, the waveform shaping circuit 15 x of the second embodiment of the communication device X includes a slave-side drive control circuit 16 x , a selector 21 , a pulse width detection circuit 22 , a selector 23 , and control circuits 24 and 25 .

[0130] The pulse width detection circuit 22 detects the pulse width WL of the bus voltage VBUS (=pulse width modulation signal PWM), and outputs a detection signal S4 corresponding to the pulse width WL to the selector 23. More specifically, the pulse width detection circuit 22 detects whether the pulse width WL of the bus voltage VBUS is greater than or equal to a predetermined threshold value TH, and outputs a detection signal S4 reflecting the detection result.

[0131] The selector 23 receives the output of the control circuit 24 and the output of the control circuit 25 , selects the output of the control circuit 24 or the output of the control circuit 25 according to the detection signal S4 , and outputs the selected signal to the selector 21 .

[0132] The selector 21 receives the output of the selector 23 and the bus voltage VBUS, selects the output of the selector 23 or the bus voltage VBUS under a predetermined criterion, and inputs the selection to the waveform shaping circuit 15x (more specifically, the slave-side drive control circuit 16x).

[0133] Specifically, when the relationship of pulse width WL≥threshold value TH is established, the selector 23 selects the output of the control circuit 24 according to the detection signal S4, and inputs the output to the selector 21. When the output of the control circuit 24 is input to the slave-side drive control circuit 16x by the selector 21, a relatively gentle slew rate is added to the rising / falling edge of the drive signal G2. The slew rate added to the bus voltage VBUS at this time is called the first slew rate.

[0134] On the other hand, in the case where the relationship of pulse width WL<threshold value TH holds, the selector 23 selects the output of the control circuit 25 according to the detection signal S4, and inputs the output to the selector 21. When the output of the control circuit 25 is input to the slave-side drive control circuit 16x by the selector 21, a relatively steep slew rate (steeper than when the output of the control circuit 24 is input to the slave-side drive control circuit 16x) is added to the rising / falling edge of the drive signal G2. The slew rate added to the bus voltage VBUS at this time is the second slew rate.

[0135] Fig.10 is a timing diagram showing a first signal S1, a detection signal S4, a second signal S2, a drive signal G2, and a bus voltage VBUS during data transmission at a slave node 2Ax according to a second embodiment of the present disclosure. Fig.10 At time t51, the first signal S1 drops to a low level. When time t52 arrives, the first signal S1 rises to a high level. At this time, the pulse width detection circuit 22 detects whether the pulse width WL is greater than or equal to a predetermined threshold TH.

[0136] like Fig.10 As shown, when the pulse width WL is less than the threshold value TH, at time t53, the pulse width detection circuit 22 raises the detection signal S4 from a low level to a high level. After the first signal S1 drops to a low level at time t54, when the second signal S2 drops to a low level at time t55, the slave side drive control circuit 16x sharply raises the drive signal G2. Specifically, upon receiving the detection signal S4, the selector 23 selects the output of the control circuit 25 and inputs the output to the selector 21. The selector 21 selects the output of the control circuit 25 so input, and inputs this to the slave side drive control circuit 16x. In response, the slave side drive control circuit 16x sharply raises the drive signal G2. Therefore, when the first signal S1 drops to a low level at time t55, the slave side transistor T2 transitions to an on state before the above-mentioned burr occurs. This suppresses the occurrence of burrs.

[0137] Here, the pulse width detection circuit 22 always detects the pulse width WL immediately before and outputs a detection signal S4 corresponding to the detection result. In the case where the pulse width WL changes from less than the threshold value TH to greater than or equal to the threshold value TH, the pulse width detection circuit 22 detects the pulse width WL and reduces the detection signal S4 to a low level immediately before the falling timing of the first signal S1 after the change. With this structure, a relatively gentle conversion rate is added to the drive signal G2, and the drive signal G2 rises to a high level. Therefore, the conversion rate of the drive signal G2 always changes according to the pulse width WL at the falling timing of the first signal S1 immediately before.

[0138] <Waveform Shaper>

[0139] The structure of the waveform shaping circuit 15x will now be described in more detail. Fig.11 2 is a block diagram illustrating an example of a waveform shaping circuit 15x. The waveform shaping circuit 15x is configured by current sources CS1 to CS4.

[0140] The current sources CS1 to CS3 are connected in parallel between the power supply terminal and the gate of the slave-side transistor T2 (= the application terminal of the drive signal G2). Each current source CS1 to CS3 generates a turn-on current IH1 to IH3 that switches the drive signal G2 to a high level (= the logic level when turned on). The turn-on currents IH1 to IH3 may be the same current value or different current values.

[0141] The current source CS4 is connected between the gate (=application terminal of the drive signal G2 ) of the slave-side transistor T2 and the ground terminal, and generates an off current IL that switches the drive signal G2 to a low level (=logic level when turned off).

[0142] When the drive signal G2 is set to a high level, the communication circuit 14 turns on at least one of the current sources CS1 to CS3 and turns off the current source CS4. On the other hand, when the drive signal G2 is set to a low level, the communication circuit 14 turns off all the current sources CS1 to CS3 and turns on the current source CS4.

[0143] The communication circuit 14 also has a function of individually turning on / off the current sources CS1 to CS3 (and thus the on-currents IH1 to IH3) according to the output of the pulse width detection circuit 22 when the drive signal G2 rises from a low level to a high level. In other words, the communication circuit 14 has a function of controlling the magnitude of the on-current IH flowing into the gate capacitance of the slave-side transistor T2.

[0144] For example, in the case where current source CS1 is turned on and current sources CS2 and CS3 are turned off, IH=IH1. For example, if current sources CS1 and CS2 are turned on and current source CS3 is turned off, IH=IH1+IH2. Also, for example, if all current sources CS1 to CS3 are turned on, IH=IH1+IH2+IH3.

[0145] The smaller the on-current IH is, the more gradually the drive signal G2 rises. Therefore, the current flowing during the on-transition of the slave-side transistor T2 is limited, and the bus voltage VBUS drops gently. On the contrary, the larger the on-current IH is, the more rapidly the drive signal G2 rises. Therefore, the bus voltage VBUS rises sharply.

[0146] Therefore, for example, when the pulse width WL of the pulse width modulation signal PWM is greater than the threshold value TH, EMI noise can be suppressed by not turning on all the current sources CS1 to CS3 and by reducing the turned-on current IH to a small value.

[0147] On the other hand, when the pulse width WL of the pulse width modulation signal PWM is smaller than the threshold value TH, all the current sources CS1 to CS3 are turned on so that more on-current IH flows, which enables improvement in communication stability.

[0148] <Other variations>

[0149] In addition to the above-mentioned embodiments, various technical features disclosed in this article can also be modified within the scope of the main idea of ​​the technical concept of this article. In other words, the above-mentioned embodiments should be considered as exemplary rather than limiting in all aspects, and it should be understood that the technical scope of the present disclosure is not limited to the above-mentioned embodiments, and includes all modifications that fall within the scope and equivalent meaning of the claims.

[0150] For example, in the above embodiment, a vehicle communication system conforming to the CXPI protocol is used as an example, but the application of the present disclosure is not limited thereto. A communication system with a similar working principle to the above working principle may be used, that is, a pulse width modulation signal may be used as a line code between multiple nodes, and in the event of a conflict between transmission signals at a node, the node that has transmitted a dominant level for a longer period of time will be dominant in arbitration.

[0151] The master-side transistor T1 and the slave-side transistor T2 are described as NMOSFETs, but the master-side transistor T1 and the slave-side transistor T2 may also be npn-type bipolar transistors or N-channel insulated gate bipolar transistors (IGBTs).

[0152] <Notes>

[0153] The communication device (X) disclosed in this article includes: a communication line (3); a master node (1x), the master node (1x) being connected to the communication line (3); and a slave node (1Ax), the slave node (1Ax) being connected to the communication line (3), wherein the master node (1x) and the slave node (1Ax) communicate with each other by using a pulse width modulation signal (PWM) as a line code, and at least one of the master node (1x) and the slave node (1Ax) is configured to switch to one of a first state and a second state, in which a feedback input of a bus voltage (VBUS) of the communication line (3) is received to control the conversion rate of the bus voltage (VBUS) to a desired value, and in which a predetermined control signal is received to control the conversion rate of the bus voltage (VBUS) to a desired value (first structure).

[0154] Note that in the communication device (X) according to the first structure, the master node (1x) can be configured to generate a master-side transmission signal (S1) that changes the logic level between a dominant level and a recessive level, and send the master-side transmission signal (S1) to the slave node (1Ax) via the communication line (3), and the slave node (1Ax) can be configured to generate a slave-side transmission signal (S2) that changes the logic level between a dominant level and a recessive level, and send the slave-side transmission signal (S2) to the master node (1x) via the communication line (3), and the master-side transmission signal (S1) and the slave-side transmission signal (S2) are transmitted to the master node (1x) via the communication line (3). In the event of a conflict in the communication line (3), the one of the master-side transmission signal (S1) and the slave-side transmission signal (S2) that maintains the dominant level for a longer time can be sent preferentially, the slave node (1Ax) can switch to the second state at a first timing when the logic level of the slave-side transmission signal (S2) switches from the recessive level to the dominant level, and the master node (1x) can switch to the second state (second structure) at a second timing when the logic level of the master-side transmission signal (S1) switches when the slave node (1Ax) sets the slave-side transmission signal (S2) to the dominant level.

[0155] In a communication device (X) according to the second structure, the master node (1x) can switch to the first state at a third timing when the logic level of the master side transmission signal (S1) switches when the slave node (1Ax) sets the slave side transmission signal (S2) to the recessive level, and the slave node (1Ax) can switch to the first state at a fourth timing when the logic level of the slave side transmission signal (S2) switches from the dominant level to the recessive level (third structure).

[0156] In a communication device (X) according to the second or third structure, the master node (1x) may include a master-side transistor (T1), which is connected to the communication line (3); and a master-side drive control circuit (12x), which is configured to control a first drive signal (G1) of the master-side transistor (T1), and the slave node (1Ax) may include a slave-side transistor (T2), which is connected to the communication line (3); and a slave-side drive control circuit (16x), which is configured to control a second drive signal (G2) of the slave-side transistor (T2), and the master node (1x) and the slave node (1Ax) may be configured to change the bus voltage (VBUS) by controlling the on / off state of the first transistor and the second transistor (fourth structure).

[0157] In a communication device (X) according to any one of the second to fourth structures, the master node (1x) may include a detection circuit (19), which is configured to detect whether the timing of arrival of the logic level of the master-side sending signal (S1) is the second timing or the third timing based on the bus voltage (VBUS), and the master-side drive control circuit (12x) can control the first drive signal (G1) according to the detection result of the detection circuit (19) (fifth structure).

[0158] In a communication device (X) according to any one of the second to fifth structures, in the second state, as the expected value, the conversion rate of the bus voltage (VBUS) can be controlled to a predetermined first conversion rate or a second conversion rate steeper than the first conversion rate, and the slave node (1Ax) can include a pulse width detection circuit (19), the pulse width detection circuit (19) being configured to detect a pulse width between a timing at which the logic level of the master-side transmission signal (S1) switches from the recessive level to the dominant level and a timing at which the logic level of the master-side transmission signal (S1) switches next, and at the second timing, when the pulse width is less than or equal to an interval between the second timing and an immediately preceding third timing, the slave node (1Ax) can switch the conversion rate of the bus voltage (VBUS) to the second conversion rate (sixth structure).

[0159] The communication device (X) according to any one of the first to sixth structures complies with the CXPI protocol (seventh structure).

[0160] With the communication device (X) according to the first structure, even if it is difficult to control the conversion rate of the bus voltage (VBUS) to a desired value in the first state, the conversion rate of the bus voltage (VBUS) can be controlled by switching to the second state. Therefore, a sharp change in the bus voltage (VBUS) can be suppressed, and the generation of EMI noise can be suppressed.

[0161] With the communication device (X) according to the second structure, even if it is difficult to control the conversion rate of the bus voltage (VBUS) to a desired value at the first timing and the second timing in the first state, the conversion rate of the bus voltage (VBUS) can be controlled by switching to the second state. Therefore, the rapid change of the bus voltage (VBUS) can be more appropriately suppressed, and the generation of EMI noise can be suppressed.

[0162] With the communication device (X) according to the third structure, by switching to the first state at the third timing and the fourth timing, the conversion rate of the bus voltage (VBUS) can be appropriately controlled by the feedback control.

[0163] With the communication device (X) according to the fourth structure, the bus voltage (VBUS) can be controlled more appropriately.

[0164] With the communication device (X) according to the fifth structure, the timing for controlling the slew rate of the bus voltage (VBUS) can be more appropriately selected.

[0165] With the communication device (X) according to the sixth structure, even if the pulse width is less than or equal to the interval between the second timing and the third timing immediately before the second timing, since the bus voltage (VBUS) rises at the second slew rate, the rise of the bus voltage (VBUS) can be suppressed until before the timing at which the logic level of the master-side transmission signal (S1) is switched. This can suppress the occurrence of glitches.

[0166] With the communication device (X) according to the seventh structure, in the communication device (X) conforming to the CXPI protocol, the occurrence of EMI noise can be suppressed more appropriately.

Claims

1. A communication device, comprising: Communication lines; a master node, the master node being connected to the communication line; as well as A slave node connected to the communication line, wherein The master node and the slave node communicate with each other by using a pulse width modulation signal as a line code, and At least one of the master node and the slave node is configured to switch to one of a first state and a second state, in which the feedback input of the bus voltage of the communication line is received to control the conversion rate of the bus voltage to a desired value, and in the second state, the input of a predetermined control signal is received to control the conversion rate of the bus voltage to a desired value.

2. The communication device according to claim 1, wherein The master node is configured to generate a master-side transmission signal whose logic level changes between a dominant level and a recessive level, and transmit the master-side transmission signal to the slave node via the communication line, the slave node is configured to generate a slave-side transmission signal that changes a logic level between a dominant level and a recessive level, and transmit the slave-side transmission signal to the master node via the communication line, In the case where the master-side transmission signal and the slave-side transmission signal collide in the communication line, the one of the master-side transmission signal and the slave-side transmission signal that maintains the dominant level is preferentially transmitted, The slave node switches to the second state at a first timing when the logic level of the slave-side transmission signal switches from the recessive level to the dominant level, and The master node switches to the second state at a second timing at which the logic level of the master-side transmission signal switches when the slave node sets the slave-side transmission signal to the dominant level.

3. The communication device according to claim 2, wherein The master node switches to the first state at a third timing when the logic level of the master-side transmission signal switches when the slave node sets the slave-side transmission signal to the recessive level, and The slave node switches to the first state at a fourth timing at which the logic level of the slave-side transmission signal switches from the dominant level to the recessive level.

4. The communication device according to claim 3, wherein The master node includes: a primary-side transistor connected to the communication line; as well as a primary-side drive control circuit configured to control a first drive signal of the primary-side transistor, The slave node comprises: a slave-side transistor connected to the communication line; as well as a slave-side drive control circuit configured to control a second drive signal of the slave-side transistor, and The master node and the slave node are configured to change the bus voltage by controlling the on / off states of the first transistor and the second transistor.

5. The communication device according to claim 4, wherein The master node includes a detection circuit configured to detect whether the timing at which the logic level of the master-side transmission signal reaches the second timing or the third timing based on the bus voltage, and The primary-side driving control circuit controls the first driving signal according to a detection result of the detection circuit.

6. The communication device according to any one of claims 2 to 5, wherein In the second state, as the desired value, the slew rate of the bus voltage is controlled to be a predetermined first slew rate or a second slew rate steeper than the first slew rate, The slave node comprises: a pulse width detection circuit configured to detect a pulse width between a timing at which the logic level of the master-side transmission signal switches from the recessive level to the dominant level and a timing at which the logic level of the master-side transmission signal switches next, and At the second timing, when the pulse width is less than or equal to an interval between the second timing and an immediately preceding third timing, the slave node switches the conversion rate of the bus voltage to the second conversion rate. The communication device according to claim 1 , wherein the communication device complies with the CXPI protocol.

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