Chip aging test fixture control method, device and storage medium

Abstract

The present invention relates to the technical field of chip aging test, and discloses a chip aging test fixture control method, device and storage medium. The method comprises: collecting parameters of a test fixture to obtain original test data; performing control signal analysis and signal fusion, inputting fused temperature control instructions into a temperature control unit of the test fixture to obtain steady-state test data; performing multi-dimensional analysis and data screening to obtain effective test data; performing performance feature extraction to obtain performance feature data; performing grouping, and calculating a weight coefficient of each test channel, performing weighted processing in combination with a failure mode standard to obtain aging characteristic data; and inputting the aging characteristic data into a life prediction model to calculate a performance prediction value and a life prediction value to obtain a chip aging test result. The present invention can accurately capture chip performance degradation characteristics, and output a performance prediction value and a life prediction value at the same time, thereby providing a comprehensive aging evaluation result.

Description

Technical Field

[0001] The present invention relates to the technical field of chip aging test, and in particular to a chip aging test fixture control method, device and storage medium. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, chip integration and performance requirements are constantly increasing. Chip aging test is becoming more and more important as a key means to evaluate chip reliability. Traditional chip aging test methods mainly use single-channel serial test methods, which have low test efficiency and are difficult to meet the needs of large-scale chip batch testing. At the same time, due to the complexity of the chip working environment, factors such as temperature fluctuations and voltage fluctuations will cause test data instability, affecting the accuracy of the test results.

[0003] Existing chip aging test systems generally have the problem of insufficient temperature control accuracy, making it difficult to accurately simulate the temperature stress conditions of the chip in the actual working environment. In addition, the large amount of data generated during the test lacks effective screening and analysis methods, making it impossible to accurately identify and eliminate abnormal data, resulting in low reliability of the test results. At the same time, traditional data processing methods are difficult to fully explore the deep characteristics of chip performance degradation and cannot accurately predict the remaining service life of the chip. Summary of the invention

[0004] The present invention provides a chip aging test fixture control method, device and storage medium, which can accurately capture chip performance degradation characteristics, output performance prediction values ​​and life prediction values ​​at the same time, and provide comprehensive aging evaluation results.

[0005] In a first aspect, the present invention provides a chip burn-in test fixture control method, the chip burn-in test fixture control method comprising:

[0006] Collecting parameters of a test fixture to obtain original test data, wherein the test fixture includes a plurality of parallel test channels;

[0007] The original test data is respectively input into the temperature stress compensator and the dynamic parameter controller for control signal analysis and signal fusion, a fusion temperature control instruction is generated, and the fusion temperature control instruction is input into the temperature control unit of the test fixture to obtain steady-state test data;

[0008] Performing multi-dimensional analysis and data screening on the steady-state test data to obtain effective test data;

[0009] Inputting the effective test data into a feature enhancement network to extract performance features to obtain performance feature data;

[0010] The performance characteristic data are grouped according to the multiple test channels, and a weight coefficient of each test channel is calculated, and the performance characteristic data of each test channel is weighted in combination with a failure mode standard to obtain aging characteristic data;

[0011] The aging characteristic data is input into the life prediction model to calculate the performance prediction value and the life prediction value to obtain the chip aging test result.

[0012] In a second aspect, the present invention provides a chip aging test fixture control device, the chip aging test fixture control device comprising:

[0013] An acquisition module, used to acquire parameters of a test fixture to obtain original test data, wherein the test fixture includes a plurality of parallel test channels;

[0014] A temperature control module, used for inputting the original test data into the temperature stress compensator and the dynamic parameter controller respectively to perform control signal analysis and signal fusion, generate fusion temperature control instructions, and input the fusion temperature control instructions into the temperature control unit of the test fixture to obtain steady-state test data;

[0015] A data screening module, used for performing multi-dimensional analysis and data screening on the steady-state test data to obtain valid test data;

[0016] A feature extraction module, used for inputting the effective test data into a feature enhancement network to extract performance features and obtain performance feature data;

[0017] A weighted processing module, used to group the performance characteristic data according to the multiple test channels, calculate the weight coefficient of each test channel, and perform weighted processing on the performance characteristic data of each test channel in combination with the failure mode standard to obtain aging characteristic data;

[0018] The calculation module is used to input the aging characteristic data into the life prediction model to calculate the performance prediction value and the life prediction value to obtain the chip aging test result.

[0019] The third aspect of the present invention provides a computer device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the computer device executes the above-mentioned chip aging test fixture control method.

[0020] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the above-mentioned chip aging test fixture control method.

[0021] In the technical solution provided by the present invention, the design of multiple parallel test channels is adopted, combined with a multi-layer PCB wiring structure, which significantly improves the test throughput; through the dual control strategy of temperature stress compensation and dynamic parameter control, the temperature control accuracy reaches ±0.5°C, which accelerates the achievement of test steady state. Multi-dimensional analysis and data screening mechanisms are introduced, and abnormal data are effectively identified and eliminated through means such as statistical feature calculation, correlation analysis and normality test; a feature enhancement network including a group normalization layer, a SiLU activation layer, a convolutional block attention module and a multi-head self-attention layer is designed to achieve a deep fusion of voltage, current and temperature features; through position encoding and residual connection mechanisms, the temporal expression ability of features is enhanced. A life prediction model based on a bidirectional long short-term memory network and a self-attention mechanism is constructed, and the chip performance degradation characteristics are accurately captured through multi-scale feature extraction and residual connection; a dual-branch prediction structure is adopted to simultaneously output performance prediction values ​​and life prediction values, providing comprehensive aging evaluation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the steps of a jig control method for chip aging test in an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of the structure of a jig control device for chip aging test in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention provide a jig control method, device and storage medium for chip aging test. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of a chip aging test fixture control method in an embodiment of the present invention includes:

[0027] Step S1, collecting parameters of a test fixture to obtain original test data, where the test fixture includes multiple parallel test channels;

[0028] It is understandable that the execution subject of the present invention may be a fixture control device for chip aging test, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0029] Specifically, a plurality of first pins and test points are arranged on the first surface of the test fixture, and a plurality of second pins are arranged on the second surface opposite to the first surface, and the first pins are connected to the second pins through the upper layer routing, the via routing and the lower layer routing, so as to construct a signal acquisition circuit and realize the effective conduction of electrical signals between different layers. The plurality of first pins, the plurality of second pins and the test points are numbered and grouped, and the first pins, the second pins and the test points with adjacent numbers are divided into a test channel to obtain a plurality of parallel test channels. The initial temperature control parameter is input into the temperature control unit of the test fixture, and the overall temperature of the test fixture is adjusted to a preset value to obtain the initial temperature of the test, wherein the preset value is -40°C. By setting a low temperature environment, the working state of the chip under extreme temperature conditions is simulated, and its aging characteristics and performance in a low temperature environment are examined. The voltage of each test channel in the plurality of parallel test channels is sampled, and the voltage value between the first pin and the second pin in each channel is recorded to obtain channel voltage data, reflecting the voltage distribution of each channel under the initial temperature conditions. Current sampling is performed on each test channel in multiple parallel test channels, and the current value between the first pin and the second pin in each channel is recorded to obtain channel current data. The channel current data is combined with the voltage data to calculate the resistance value or conduction characteristic of each channel. Temperature sampling is performed on the temperature sensors of multiple parallel test channels, and the temperature value of each test channel is recorded to obtain channel temperature data. By sampling the temperature, the temperature change of each channel during the test process is understood, so as to analyze the impact of temperature on chip performance, especially the working stability and reliability of the chip under extreme temperature conditions. Channel voltage data, channel current data and channel temperature data are timestamped, and a mapping relationship between test data and sampling time is established to obtain original test data. Through timestamp marking, the electrical performance and temperature status of each test channel at different time points can be accurately tracked.

[0030] Step S2, inputting the original test data into the temperature stress compensator and the dynamic parameter controller respectively for control signal analysis and signal fusion, generating a fusion temperature control instruction, and inputting the fusion temperature control instruction into the temperature control unit of the test fixture to obtain steady-state test data;

[0031] Specifically, the channel temperature data in the original test data is input into the temperature stress compensator, and the mapping relationship between temperature and stress is calculated according to the pre-established temperature-stress inverse model to obtain the stress compensation parameters for adjusting the temperature. The mapping relationship can accurately reflect the changing law between temperature and stress during chip aging, and in this way, it can better adapt to the stress change characteristics of the chip under different temperature conditions. The stress compensation parameters are nonlinearly transformed, and the transfer function of temperature fluctuation and stress change is established to ensure accurate compensation of the stress on the chip. In order to obtain the best compensation effect, the transfer function is optimized and calculated by the least squares method to solve the optimal compensation coefficient, obtain the temperature compensation signal, and effectively eliminate the impact of temperature fluctuation on chip performance. At the same time, the original test data is input into the dynamic parameter controller, and the PID control model is constructed based on the proportional coefficient, integral time and differential time to obtain the initial control parameters for temperature regulation. Through the PID control model, the output of the temperature control system is effectively adjusted, so that the system can respond quickly to temperature changes and remain stable. In order to improve the adaptability of the temperature control system, the initial control parameters are adaptively adjusted, and the PID parameter values ​​are dynamically updated according to the rate of change of the temperature error to obtain a more adaptable dynamic control signal. The introduction of the PID controller enables the system to respond and adjust quickly according to temperature changes, thereby maintaining a stable temperature state. This dynamic control signal is combined with the aforementioned temperature compensation signal, so that the temperature control unit can achieve a balance between stress compensation and dynamic regulation. The temperature compensation signal and the dynamic control signal are linearly combined to generate a fused temperature control instruction, and the fused temperature control instruction is converted into an analog control voltage through a digital-to-analog conversion circuit, which is input into the heater and refrigerator in the temperature control unit of the test fixture to obtain a control signal for temperature regulation. Through the cooperation of the heater and the refrigerator, the temperature control unit accurately adjusts the temperature of the test fixture according to the fused temperature control instruction to ensure that the system can maintain the required temperature state under different test conditions. In order to ensure the regulation effect of the temperature control system, the temperature regulation signal is closed-loop controlled, and the control signal is adjusted by real-time monitoring of temperature changes so that the temperature can be kept within the set target range. When it is detected that the temperature fluctuation is less than 0.5°C within 100 consecutive sampling cycles, it means that the system has reached a steady-state condition. At this time, the voltage, current and temperature values ​​of multiple test channels in parallel are collected to obtain steady-state test data.

[0032] Step S3, performing multi-dimensional analysis and data screening on the steady-state test data to obtain effective test data;

[0033] Specifically, the voltage value, current value and temperature value in the steady-state test data are respectively calculated for statistical characteristics to obtain parameter statistical characteristic values. The calculation process of statistical characteristics includes the calculation of key statistical quantities such as the mean value, variance, standard deviation and so on of each parameter, and the overall change trend of each parameter and the discreteness of the data are reflected through statistical characteristics. Based on the parameter statistical characteristic values, a parameter correlation matrix is ​​constructed, and the correlation coefficients between the voltage value, current value and temperature value are calculated to obtain the correlation coefficients between the parameters. By calculating the parameter correlation coefficients, it is clear whether there is a significant linear relationship between the parameters. According to the parameter correlation coefficient, a data continuity index is established, and the continuity of the data is judged by calculating the parameter change rate of adjacent sampling points, and the continuity score is obtained accordingly. Data continuity is an important criterion for measuring whether the test data changes smoothly. The score can be used to identify abnormal data points in the test process. At the same time, a sliding window analysis is performed on the steady-state test data, and the window length is set to 50 sampling points. The consistency deviation of the parameters in the window is calculated to obtain a consistency score. Through the sliding window analysis, the fluctuation of the data in a short period of time can be effectively detected, and the consistency of each parameter in the time series can be judged to evaluate the stability of the test data. Combine the continuity score and consistency score to generate a comprehensive score for data quality, and set a certain score threshold to obtain the standard for data screening. According to the data screening criteria, screen the steady-state test data, remove the data points with a comprehensive score lower than the threshold, and obtain preliminary screening data. Perform a normality test on the data after preliminary screening. Calculate the skewness coefficient and kurtosis coefficient to determine whether the data distribution conforms to the characteristics of a normal distribution. The skewness coefficient is used to measure the symmetry of the data distribution, while the kurtosis coefficient is used to measure the kurtosis of the data distribution. By calculating the skewness and kurtosis, the rationality of the data distribution can be judged and the abnormal data points can be identified. Based on the distribution test results, the preliminary screening data is screened for a second time, and only the test data with a reasonable data distribution is retained to obtain the final valid test data.

[0034] Step S4, inputting the effective test data into the feature enhancement network to extract performance features and obtain performance feature data;

[0035] Specifically, the valid test data is input into the group normalization layer in the feature enhancement network, and the valid test data is standardized by calculating the mean and variance of each feature group to obtain standardized feature data. Through the group normalization operation, each feature group has the same mean and variance, so that the data distribution is more standardized, which helps to eliminate the dimensional differences between different features and improve the stability and effectiveness of the feature extraction process. The standardized feature data is input into the SiLU activation layer, and the SiLU activation layer uses the sigmoid function and the linear unit to perform nonlinear transformation to obtain preliminary activation features. The introduction of the SiLU activation function can effectively increase the nonlinear expression ability of the feature, so that the network can better fit complex nonlinear relationships. The preliminary activation features are input into the convolutional block attention module for processing. The convolutional block attention module includes a channel attention unit and a spatial attention unit. The feature weights are extracted through maximum pooling and average pooling operations to obtain attention features. The channel attention unit enables the network to focus on more important feature channels, while the spatial attention unit enables the network to focus on the spatial distribution of features, enhancing the network's feature extraction ability. The attention features are input into the multi-head self-attention layer for processing. The multi-head self-attention layer contains 8 attention heads. Each attention head obtains an attention score by calculating the dot product between the query vector, the key vector, and the value vector, realizes the extraction of feature association, and obtains the time series association feature. The multi-head self-attention mechanism enables the network to understand the relationship between features from different perspectives and better capture the correlation of features in the time dimension. It is suitable for the extraction of dynamic features that change over time in chip aging testing. The time series association features are input into the feedforward neural network for processing. The feedforward neural network contains two fully connected layers, where the number of neurons in the first fully connected layer is 512 and the number of neurons in the second fully connected layer is 256. This structure further extracts high-order features and obtains fully connected features. The fully connected features are input into the position encoding layer, and the position encoding vectors of different frequencies are calculated by sine and cosine functions, and are added to the features to obtain position enhancement features. Through position encoding, the network perceives the temporal order of the input data, thereby improving the model's ability to capture time series features. The position enhancement features are processed by residual connection, and the input features are added to the output features to retain the original feature information. At the same time, the data distribution is adjusted through layer normalization to obtain residual features. Residual connection effectively prevents the layer-by-layer degradation of features in multi-layer networks and improves the training efficiency and stability of the network. Layer normalization ensures that the distribution of residual features is consistent between layers, which helps the network to better learn useful features. The residual features are input into the output layer, and the features are reduced in dimension through 1×1 convolution to reduce the feature dimension and improve the computational efficiency. The Softmax function is then used to map the features to obtain the final performance feature data.The role of 1×1 convolution is to retain important features while compressing redundant information, and the use of Softmax function is to normalize the output features so that the values ​​of each feature are within a certain range, which is convenient for subsequent performance evaluation and life prediction. Through the above steps, the performance characteristic data is finally obtained, which can accurately reflect the performance of the chip during the aging test.

[0036] Step S5, grouping the performance characteristic data according to multiple test channels, calculating the weight coefficient of each test channel, and weighting the performance characteristic data of each test channel in combination with the failure mode standard to obtain aging characteristic data;

[0037] Specifically, the performance characteristic data is grouped according to multiple test channels, and the voltage characteristics, current characteristics and temperature characteristics of each test channel are combined to obtain the corresponding channel characteristic group. The variance and mean of each group of characteristic data in the channel characteristic group are calculated respectively, and the similarity of each group of characteristic data is calculated by the local sensitive hashing algorithm to obtain the characteristic similarity matrix. Each element in the characteristic similarity matrix represents the similarity degree of the characteristic data between the corresponding two test channels. Based on the characteristic similarity matrix, a graph neural network is constructed, each test channel is regarded as a node in the graph, and the characteristic similarity is used as the weight of the edge between the nodes. The relationship between the channels is extracted by graph convolution operation to obtain the channel association feature. The graph neural network effectively captures the complex association between channels by performing convolution operations on the graph structure, which helps to understand the mutual influence and overall performance of each channel of the chip during the aging process. The obtained channel association feature can reflect the intrinsic connection between each test channel during the aging process. The channel association feature is input into the adaptive weight calculation unit, and the importance score of each test channel is calculated by the attention mechanism, and the importance score is normalized by the Softmax function to obtain the weight coefficient of each channel. The attention mechanism enables the model to dynamically assign weights to each channel according to the importance of the features, so as to more flexibly handle the contribution of different channels in the aging process. Through Softmax normalization, the sum of the weight coefficients of all channels is ensured to be 1, which is convenient for subsequent weighted calculations. According to the preset chip failure mode standard, a fault feature library is constructed, and the feature vectors in the fault feature library are calculated with the cosine similarity of each channel feature group to obtain the failure mode matching degree. Cosine similarity can effectively measure the directional similarity between feature vectors and is used to judge the similarity between each channel feature and the known failure mode. The failure mode matching degree is multiplied by the channel weight coefficient to generate a comprehensive weight coefficient, and the comprehensive weight coefficient is normalized to obtain the target weight coefficient. According to the target weight coefficient, a weighted sum operation is performed on each channel feature group, and the feature data of multiple test channels are fused into a unified feature vector to obtain fused feature data. The fused feature data is subjected to feature standardization to ensure that the numerical range of features of different dimensions is the same, improve the effect of subsequent analysis and processing, and obtain aging characteristic data.

[0038] Step S6: Input the aging characteristic data into the life prediction model to calculate the performance prediction value and the life prediction value to obtain the chip aging test result.

[0039] Specifically, the aging characteristic data is input into the bidirectional long short-term memory network (Bi-LSTM) layer in the life prediction model. Through the forward and reverse time series feature extraction, the state values ​​of the forget gate, input gate and output gate are calculated to obtain the time series coding features. The bidirectional LSTM can capture the forward and backward dependencies of the features at the same time, so that the model can extract the association between various features in the chip aging process from the complete time series information and model the dynamic changes of the chip in the aging process. The time series coding features are processed by self-attention, and the multi-head self-attention mechanism is used to calculate the correlation weights between features. In the self-attention layer, each attention head contains a 64-dimensional query vector, a key vector and a value vector. By calculating the dot product between the query vector and the key vector, the correlation score of each feature is obtained, and the value vector is weighted summed using these scores to obtain the attention enhancement feature. The multi-head self-attention mechanism enables the network to capture the relationship between features from multiple perspectives and improve the model's ability to understand the dependency between features. The attention-enhanced features are input into the encoding and decoding module, which contains 3 encoding blocks and 3 decoding blocks. Each encoding block contains a convolution layer and a maximum pooling layer, while each decoding block contains a deconvolution layer and an upsampling layer. The encoding block performs convolution and pooling operations on the features to extract the information of different scales of the features, compress the spatial dimensions of the features, and enhance the abstractness of the features. The decoding block restores the spatial dimensions of the features through deconvolution and upsampling operations to ensure that the model can effectively capture the feature information at different scales. The resulting multi-scale features contain spatial and temporal information, allowing the model to understand the multi-scale feature changes of the chip during the aging process. The multi-scale features are processed by residual connection, the features of different scales are skipped, and 1×1 convolution is used for feature fusion to retain the feature information of the encoding stage and the decoding stage, and effectively fuse these features. The batch normalization layer is used to adjust the data distribution of the fused features to ensure that the features maintain numerical stability when input into the subsequent network layers, thereby improving the training efficiency and convergence of the model. By combining residual connection with batch normalization, the network's ability to learn features is enhanced, and the gradient vanishing problem in deep network training is effectively alleviated. The fused features are input into a fully connected neural network for processing. The fully connected neural network contains three hidden layers with 512, 256 and 128 neurons, respectively. Each layer uses the ReLU activation function. Through a multi-layer fully connected neural network, the features are extracted and abstracted layer by layer to obtain a deep feature representation. The introduction of the ReLU activation function enables the model to effectively handle nonlinear relationships and accelerate the network training process. The performance prediction branch and the life prediction branch are processed separately. For the performance prediction branch, the trend of the key performance parameters of the chip is calculated through two fully connected layers, and the Sigmoid function is used for output mapping to obtain the performance prediction value of the chip.The output range of the Sigmoid function is between 0 and 1, which is suitable for predicting the changing trend of performance parameters, so that the output results have clear upper and lower bounds. In the life prediction branch, the remaining service life of the chip is also calculated through two fully connected layers, and the TanH function is used for output mapping to obtain the life prediction value. The output range of the TanH function is between -1 and 1, which is suitable for normalizing the life prediction value, making the output result more interpretable and convenient for subsequent analysis. The performance prediction value and the life prediction value are combined to output the aging test results of the chip. This result can intuitively reflect the performance change trend and remaining service life of the chip during the aging process.

[0040] In the embodiment of the present invention, the design of multiple parallel test channels is adopted, combined with the multi-layer PCB wiring structure, which significantly improves the test throughput; through the dual control strategy of temperature stress compensation and dynamic parameter control, the temperature control accuracy reaches ±0.5°C, which accelerates the achievement of test steady state. Multi-dimensional analysis and data screening mechanism are introduced, and abnormal data are effectively identified and eliminated by means of statistical feature calculation, correlation analysis and normality test; a feature enhancement network including group normalization layer, SiLU activation layer, convolutional block attention module and multi-head self-attention layer is designed to achieve deep fusion of voltage, current and temperature features; through position encoding and residual connection mechanism, the temporal expression ability of features is enhanced. A life prediction model based on bidirectional long short-term memory network and self-attention mechanism is constructed, and the chip performance degradation characteristics are accurately captured through multi-scale feature extraction and residual connection; a dual-branch prediction structure is adopted to simultaneously output performance prediction values ​​and life prediction values, providing comprehensive aging evaluation results.

[0041] In a specific embodiment, the process of executing step S1 may specifically include the following steps:

[0042] A plurality of first pins and test points are arranged on a first surface of the test fixture, a plurality of second pins are arranged on a second surface opposite to the first surface, and the first pins are connected to the second pins through upper layer wiring, via wiring and lower layer wiring to obtain a signal acquisition circuit;

[0043] The plurality of first pins, the plurality of second pins and the test points are numbered and grouped, and the first pins, the second pins and the test points with adjacent numbers are divided into a test channel to obtain a plurality of parallel test channels;

[0044] Inputting an initial temperature control parameter into a temperature control unit of the test fixture, adjusting the temperature of the test fixture to a preset value, obtaining an initial test temperature, and performing voltage sampling on each of a plurality of parallel test channels, recording a voltage value between a first pin and a second pin, and obtaining channel voltage data;

[0045] Performing current sampling on each of the multiple parallel test channels, recording the current value between the first pin and the second pin, and obtaining channel current data, and performing temperature sampling on the temperature sensors of the multiple parallel test channels, recording the temperature value of each test channel, and obtaining channel temperature data;

[0046] The channel voltage data, channel current data and channel temperature data are time-stamped, a mapping relationship between the test data and the sampling time is established, and the original test data is obtained.

[0047] Specifically, a plurality of first pins and test points are arranged on the first surface of the test fixture, and a plurality of second pins are arranged on the second surface opposite to the first surface to construct a signal acquisition circuit. The first pin is connected to the second pin through the upper layer routing, the via routing and the lower layer routing to form a complete signal acquisition path. Through this design, signal transmission between different layers is effectively realized, signal attenuation and interference are reduced, and the measurement accuracy during the test process is improved. In the combination of the upper layer routing, the via routing and the lower layer routing, the upper layer and the lower layer routing are used to provide planar transmission between the pins, while the via routing realizes electrical connection in the vertical direction to ensure the conductivity and reliability of the entire circuit. The plurality of first pins, the plurality of second pins and the test points are numbered and grouped. In order to achieve effective test control, the first pins, the second pins and the test points with adjacent numbers are divided into a test channel to obtain multiple parallel test channels. Each test channel consists of a first pin, a second pin and a test point. By grouping, it is ensured that each channel is independent and there is no mutual interference between different channels. For example, if there are 12 first pins and 12 second pins, the first pin numbered 1, the second pin numbered 1 and the corresponding test points are grouped into one channel, and the first pin numbered 2, the second pin numbered 2 and the corresponding test points are grouped into another channel to form 12 parallel test channels. The initial temperature control parameters are input into the temperature control unit of the test fixture, and the temperature of the test fixture is adjusted to a preset value, where the preset value is -40°C, to obtain the initial test temperature. Simulate the working state of the chip in an extremely low temperature environment to examine its performance and reliability. Under this temperature condition, perform voltage sampling on each test channel, record the voltage value between the first pin and the second pin, obtain the channel voltage data, and measure the voltage response of each channel under extreme conditions. Assume that the voltage between the first pin and the second pin is ,in Indicates the channel number, represents the sampling time, and the channel voltage data obtained by sampling is expressed as:

[0048] ;

[0049] in, Indicates the maximum voltage amplitude, represents the angular frequency of the voltage signal, For time, is the initial phase angle. Current sampling is performed on each of the multiple parallel test channels, and the current value between the first pin and the second pin is recorded to obtain channel current data. The current characteristics of the chip under extreme temperature conditions are measured, and the measured current value reflects the relationship between voltage and resistance. Assume that the current between the first pin and the second pin is ,in Indicates the channel number, represents the sampling moment, then according to Ohm’s law, the current is expressed as:

[0050] ;

[0051] in, is the voltage value, is the equivalent resistance of the channel. Through the relationship between voltage and current, the resistance change of each channel is calculated to determine the change in electrical characteristics during chip aging. The temperature sensors of multiple test channels in parallel are sampled, and the temperature value of each test channel is recorded to obtain channel temperature data. The channel voltage data, channel current data, and channel temperature data are timestamped, and a mapping relationship between test data and sampling time is established to obtain the original test data. Let the timestamp be , then the voltage, current and temperature data of each channel at different sampling time points are represented as a triplet , and associate the triple with the corresponding timestamp Establish a mapping relationship.

[0052] In a specific embodiment, the process of executing step S2 may specifically include the following steps:

[0053] The channel temperature data in the original test data is input into the temperature stress compensator, and the mapping relationship between temperature and stress is calculated according to the temperature-stress inverse model to obtain the stress compensation parameters. The stress compensation parameters are transformed nonlinearly to establish the transfer function of temperature fluctuation and stress change. The compensation coefficient is calculated by the least square method to obtain the temperature compensation signal.

[0054] The original test data is input into the dynamic parameter controller, and a PID control model is constructed based on the proportional coefficient, integral time and differential time to obtain the initial control parameters, and the initial control parameters are adaptively adjusted. The PID parameter value is dynamically updated according to the change rate of the temperature error to obtain a dynamic control signal;

[0055] The temperature compensation signal and the dynamic control signal are linearly combined to generate a fused temperature control instruction, and the fused temperature control instruction is converted into an analog control voltage through a digital-to-analog conversion circuit, and input into the heater and refrigerator of the temperature control unit to obtain a temperature adjustment signal;

[0056] The temperature regulation signal is closed-loop controlled. When it is detected that the temperature fluctuation is less than 0.5°C within 100 consecutive sampling cycles, the voltage, current and temperature values ​​of multiple test channels in parallel are collected to obtain steady-state test data.

[0057] Specifically, the channel temperature data in the original test data is input into the temperature stress compensator to analyze the relationship between temperature and stress. According to the temperature-stress inverse model, the temperature With stress The mapping relationship between them is used to obtain the stress compensation parameters. The mapping relationship is described by a mathematical model, for example:

[0058] ;

[0059] in, , , is a constant parameter in the model, is the temperature measured during the test, is the stress value. The temperature data is converted into the corresponding stress value through the model, so as to understand the stress situation of the chip under different temperature conditions. The stress compensation parameters are transformed nonlinearly, and the transfer function of temperature fluctuation and stress change is established to describe how temperature change affects the magnitude of stress, in the form of:

[0060] ;

[0061] in, represents the transfer function, is the system gain, is the time constant, is the complex frequency domain variable in Laplace transform. The transfer function reflects the dynamic process of temperature fluctuation response to stress. In order to determine the most suitable transfer function parameters, the least squares method is used to fit the experimental data and calculate the compensation coefficient. The least squares method finds the best by minimizing the error between the model output and the experimental data. and The original test data is input into the dynamic parameter controller, and the proportional coefficient is used to calculate the temperature compensation signal. , Integration time and derivative time Construct a PID (proportional-integral-differential) control model and obtain the initial control parameters. The PID control model adjusts the output of the system to reduce the error. The expression is:

[0062] ;

[0063] in, is the temperature error of the system, that is, the difference between the set temperature and the actual temperature; is the proportional gain, which is used to adjust the sensitivity of the error response; is the integration time, used to eliminate static errors; is the differential time, which is used to predict the trend of the error and make preventive adjustments. The initial control parameters are adaptively adjusted, and the PID parameter values ​​are dynamically updated according to the rate of change of the temperature error to obtain a dynamic control signal, so that the system can adapt to temperature changes and maintain a stable control effect. The temperature compensation signal and the dynamic control signal are linearly combined to generate a fused temperature control command. The fused control command is expressed in the following form:

[0064] ;

[0065] in, Indicates the temperature control instruction after fusion, is the temperature compensation signal, is the PID control signal, and is the weight coefficient of the linear combination, which is set according to the specific control requirements. The fused temperature control command is converted into an analog control voltage through a digital-to-analog conversion circuit, and the voltage is input into the heater and refrigerator of the temperature control unit to obtain a temperature control signal. By adjusting the heating and cooling devices, the temperature in the fixture can be maintained within the target range. In the process of achieving temperature control, the temperature control signal is closed-loop controlled. By real-time monitoring of the system's temperature feedback, the input signal is adjusted to ensure temperature stability. When the system detects that the temperature fluctuation is less than 100 consecutive sampling cycles, the temperature is adjusted to ensure temperature stability. When the temperature reaches a steady state, the data of multiple parallel test channels are collected, including voltage, current and temperature values, and the steady-state test data is finally obtained. For example, suppose that in a certain sampling period, the temperature is set to the preset value of -40°C and the actual temperature is , then the temperature error The adjustment signal is calculated by the PID controller, and the temperature is adjusted by the heater or refrigerator so that the actual temperature gradually approaches the set temperature.

[0066] In a specific embodiment, the process of executing step S3 may specifically include the following steps:

[0067] Calculate statistical characteristics of voltage values, current values ​​and temperature values ​​in steady-state test data respectively to obtain parameter statistical characteristic values, and construct a parameter correlation matrix based on the parameter statistical characteristic values, calculate the correlation coefficients among the voltage values, current values ​​and temperature values, and obtain the parameter correlation coefficients;

[0068] The data continuity index is established according to the parameter correlation coefficient. The data continuity is judged by calculating the parameter change rate of adjacent sampling points to obtain the continuity score. The steady-state test data is subjected to sliding window analysis. The window length is set to 50 sampling points. The consistency deviation of the parameters in the window is calculated to obtain the consistency score.

[0069] The continuity score and consistency score are combined to generate a comprehensive data quality score, and a score threshold is set to obtain a data screening standard. The steady-state test data is screened according to the data screening standard, and data points with a comprehensive quality score lower than the threshold are eliminated to obtain preliminary screening data;

[0070] Perform a normality test on the data distribution of the preliminary screening data, calculate the skewness coefficient and kurtosis coefficient, judge the rationality of the data distribution, obtain the distribution test results, and perform a secondary screening on the preliminary screening data based on the distribution test results to retain the test data with reasonable data distribution and obtain valid test data.

[0071] Specifically, the statistical characteristics of the voltage value, current value and temperature value in the steady-state test data are calculated respectively to obtain the statistical characteristic values ​​of each parameter. The calculation of statistical characteristics includes mean value, variance, standard deviation, etc., which reflect the overall distribution of parameters and the degree of discreteness of data. Based on the statistical characteristic values, a parameter correlation matrix is ​​constructed to measure the linear correlation between voltage value, current value and temperature value. The elements in the correlation matrix represent the correlation coefficients between different parameters, which are expressed using the Pearson correlation coefficient, and the formula is:

[0072] ;

[0073] in, and Represent different parameters, such as voltage and current, and is the corresponding mean, Representation parameters and By calculating the correlation matrix, the relationship between voltage, current and temperature is obtained, which helps to identify whether there is a significant linear relationship between the parameters, such as whether the temperature has a significant effect on the voltage. According to the parameter correlation coefficient, the data continuity index is established, and the continuity of the data is judged by calculating the parameter change rate of adjacent sampling points to obtain the continuity score. For every two adjacent sampling points and , calculate the parameter change rate for:

[0074] ;

[0075] in, represents the rate of change of the parameter, and is the value of two adjacent sampling points, is the sampling time interval. By calculating the rate of change of all sampling points and combining the correlation coefficient, the continuity score of the parameter is obtained, which reflects the stability of the data in time. The continuity of data is an important indicator of the quality of test data. High continuity usually indicates that the data is less disturbed or fluctuated during the acquisition process. Perform sliding window analysis on the steady-state test data, set the window length to 50 sampling points, calculate the consistency deviation of the parameters in the window, and obtain the consistency score. The sliding window analysis performs statistical analysis on the data in a window of fixed length to determine the stability of the data in a local range. For each window, the mean and standard deviation of the parameter are calculated. The smaller the standard deviation, the better the consistency of the data in the window. The consistency score is used to measure the volatility of the data in a local range. If the parameter changes greatly in the window, the consistency score will decrease, which helps identify unstable data segments. The continuity score and the consistency score are combined to generate a comprehensive score of data quality. The comprehensive score is calculated by weighted average, for example:

[0076] ;

[0077] in, Provide a comprehensive score for data quality. To score continuity, Score consistency. and The weight coefficient is usually set according to the specific application requirements. Set the scoring threshold , the data is screened according to the threshold, and the data points with comprehensive scores below the threshold are eliminated to obtain the preliminary screening data. The data after preliminary screening is tested for normality of data distribution to ensure the rationality of the data. The normality test is implemented by calculating the skewness coefficient and the kurtosis coefficient. The skewness coefficient is used to measure the symmetry of data distribution and is defined as:

[0078] ;

[0079] in, is the mean of the data, is the standard deviation of the data. The closer the skewness coefficient is to 0, the more symmetrical the data distribution is. The kurtosis coefficient is used to measure the steepness of the data distribution and is defined as:

[0080] ;

[0081] A kurtosis coefficient of 0 indicates a standard normal distribution, a value greater than 0 indicates a steeper distribution than a normal distribution, and a value less than 0 indicates a flatter distribution than a normal distribution. By calculating the skewness and kurtosis, we can determine whether the data conforms to the normal distribution and determine its rationality. Based on the distribution test results, we conduct a secondary screening of the preliminary screening data, retain the test data with a reasonable data distribution, and obtain the final valid test data. For example, if the data skewness and kurtosis of a test channel are close to 0, it is considered that the data conforms to the normal distribution, and the data of the channel is retained as valid data; on the contrary, if the data distribution skewness and kurtosis deviate greatly, there is an anomaly and it should be eliminated.

[0082] In a specific embodiment, the process of executing step S4 may specifically include the following steps:

[0083] Input the valid test data into the group normalization layer of the feature enhancement network, and standardize the valid test data by calculating the mean and variance of each feature group to obtain standardized feature data;

[0084] The standardized feature data is input into the SiLU activation layer, and nonlinear transformation is performed by multiplying the sigmoid function with the linear unit to obtain the preliminary activation features;

[0085] The initial activation features are processed by the convolutional block attention module, which includes a channel attention unit and a spatial attention unit. The feature weights are extracted through maximum pooling and average pooling to obtain the attention features.

[0086] The attention features are input into the multi-head self-attention layer. The multi-head self-attention layer contains 8 attention heads. Each attention head obtains an attention score by calculating the dot product of the query vector, key vector, and value vector, performs feature association extraction, and obtains time series association features.

[0087] The time series correlation features are processed by a feedforward neural network. The feedforward neural network contains two fully connected layers. The number of neurons in the first fully connected layer is 512, and the number of neurons in the second fully connected layer is 256, so as to obtain fully connected features.

[0088] The fully connected features are input into the position encoding layer, and the position encoding vectors of different frequencies are calculated by sine and cosine functions, and then added to the features to obtain the position enhancement features;

[0089] The position enhanced features are processed by residual connection, the input features are added to the output features, and the data distribution is adjusted through layer normalization to obtain the residual features. The residual features are input into the output layer, and the feature dimension is reduced through 1×1 convolution. The Softmax function is used for feature mapping to obtain the performance characteristic data.

[0090] Specifically, the valid test data is input into the group normalization layer of the feature enhancement network to calculate the mean and variance of each feature group, and the valid test data is standardized by these statistics to obtain standardized feature data. The standardized feature data is input into the SiLU activation layer, and nonlinear transformation is performed by multiplying the sigmoid function with the linear unit to obtain the preliminary activation feature. The formula of the SiLU activation function is expressed as:

[0091] ;

[0092] in, is the input feature, is the sigmoid function, defined as . Through nonlinear transformation, the SiLU activation function can combine the value of the input feature with its corresponding activation degree, so that the network has stronger nonlinear expression ability and improves the network's ability to fit complex feature patterns. The preliminary activated features are processed by the convolutional block attention module. The convolutional block attention module consists of a channel attention unit and a spatial attention unit. The feature weights are extracted through maximum pooling and average pooling operations to obtain attention features. The channel attention unit is used to pay attention to the weight relationship between different feature channels. It obtains the global information of the feature and calculates the weight of each channel by performing maximum pooling and average pooling operations on each channel. The spatial attention unit obtains the importance weight in the spatial dimension by performing maximum pooling and average pooling operations on the features in the spatial dimension, thereby highlighting the contribution of the features at different positions. The combination of channel and spatial attention enables the network to adaptively allocate attention between different features and positions and extract key information from the features. The attention feature is input into the multi-head self-attention layer. The multi-head self-attention layer contains 8 attention heads. Each attention head obtains the attention score by calculating the dot product of the query vector, key vector and value vector to perform feature association extraction. For the first The calculation formula of attention head is expressed as:

[0093] ;

[0094] in, , and are query, key and value vectors respectively, represents the dimension of the key vector, and the dot product result is obtained by dividing by The vector is scaled and the attention weight is obtained through the softmax function, so as to perform weighted summation on the value vector. The multi-head self-attention mechanism enables the network to capture the correlation between features from multiple angles and extract richer temporal correlation features. The temporal correlation features are input into the feedforward neural network for processing. The feedforward neural network contains two fully connected layers, where the number of neurons in the first fully connected layer is 512 and the number of neurons in the second fully connected layer is 256. Through these two layers of the network, the features are gradually compressed and abstracted to obtain fully connected features. The output of the fully connected layer is expressed by the following formula:

[0095] ;

[0096] in, is the output feature, is the weight matrix, is the input feature, is the bias term. Through full connection, the network performs linear transformation on the input features and gradually extracts higher-order features. The fully connected features are input into the position encoding layer, and the position encoding vectors of different frequencies are calculated through sine and cosine functions, and added to the features to obtain position enhancement features, so that the model can perceive the position of the feature in the sequence. The calculation formula of the position encoding vector is:

[0097] ;

[0098] Among them, pos represents the position of the feature, is the dimension of the position encoding, is the total dimension of the feature. By adding the position encoding vector to the original feature, the network can take its position into consideration when processing the feature, thus enhancing the temporal information of the feature. The position enhanced feature is processed by residual connection, the input feature is added to the output feature, and the distribution of the data is adjusted by layer normalization to obtain the residual feature. The residual connection avoids the gradient vanishing problem in the deep network by directly adding the input feature to the output feature, making the network easier to train. Layer normalization adjusts the mean and variance of the features of each layer to keep the distribution of the features stable, thereby improving the training efficiency of the network and the generalization ability of the model. The residual feature is input to the output layer, and the feature dimension is reduced by 1×1 convolution, and the Softmax function is used to map the features to obtain the final performance feature data. The role of 1×1 convolution is to compress the dimension of the feature without affecting the spatial information of the feature, so that the network compresses the high-dimensional feature into a low-dimensional feature while maintaining the original spatial structure. The output of the Softmax function is used to map the feature probability, and its formula is:

[0099] ;

[0100] in, The first The output of the Softmax function represents the probability distribution of the feature belonging to a certain category, ensuring that the value of the output feature is between 0 and 1 and the sum of all outputs is 1.

[0101] In a specific embodiment, the process of executing step S5 may specifically include the following steps:

[0102] Grouping the performance characteristic data according to multiple test channels, combining the voltage characteristic, the current characteristic and the temperature characteristic of each test channel to obtain a channel characteristic group;

[0103] Calculate the variance and mean of each set of feature data in the channel feature group, calculate the similarity of each set of feature data using the local sensitive hashing algorithm, and obtain the feature similarity matrix;

[0104] A graph neural network is constructed based on the feature similarity matrix. Each test channel is used as a node in the graph and the similarity is used as the weight of the edge. The relationship between channels is extracted through graph convolution operations to obtain channel association features.

[0105] The channel-related features are input into the adaptive weight calculation unit, and the importance score of each test channel is calculated using the attention mechanism. The channel weight coefficient is obtained by normalization through the Softmax function.

[0106] A fault feature library is constructed according to the preset chip failure mode standard, and the feature vector in the fault feature library is calculated with the channel feature group for cosine similarity to obtain the failure mode matching degree, and the failure mode matching degree and the channel weight coefficient are multiplied to generate a comprehensive weight coefficient, and the comprehensive weight coefficient is normalized to obtain the target weight coefficient;

[0107] A weighted sum operation is performed on the channel feature group according to the target weight coefficient, the feature data of multiple test channels are fused into a unified feature vector to obtain fused feature data, and the fused feature data is subjected to feature standardization processing to obtain aging characteristic data.

[0108] Specifically, the performance characteristic data is grouped according to multiple test channels, and the voltage characteristics, current characteristics, and temperature characteristics of each test channel are combined to obtain a channel characteristic group. Each channel characteristic group contains the characteristic data of the voltage, current, and temperature of the channel during the test process, which can fully reflect the state of the channel. For example, for channel , whose channel feature group is expressed as ,in , and Represent the voltage characteristics, current characteristics and temperature characteristics of the channel respectively. The mean and variance are calculated for each set of feature data in the channel feature group to describe the distribution characteristics of the data. The mean is used to measure the central position of the data, while the variance is used to describe the degree of discreteness of the data. For the current and temperature characteristics, their means and variances are similarly calculated to obtain the overall statistical characteristics of each channel feature group. Based on the calculated mean and variance, the similarity of each set of feature data is calculated using the local sensitive hashing algorithm to obtain a feature similarity matrix. Local sensitive hashing is an efficient similarity calculation method suitable for similarity retrieval of high-dimensional data. The feature data is hashed using local sensitive hashing, and similar data is mapped to the same hash bucket, so that similar feature pairs can be quickly found. Each element in the feature similarity matrix Indicates channel and Channel The similarity between them is measured by cosine similarity, and the calculation formula is:

[0109] ;

[0110] in, and Channel and Channel The eigenvector of , · represents the dot product of the vectors, and Respectively represent the norm of the vector. The similarity matrix can reflect the similarity of features between channels. Based on the feature similarity matrix, a graph neural network is constructed. Each test channel is regarded as a node in the graph, and the similarity between channels is used as the weight of the edge in the graph. The relationship between channels is extracted through graph convolution operations to obtain the associated features of the channels. The graph neural network performs convolution operations on the graph structure, aggregates the information of adjacent nodes to the current node, and captures the mutual dependence between channels. For a channel node , and its graph convolution operation is expressed as:

[0111] ;

[0112] in, Indicates channel In the The feature representation of the layer, Indicates channel The set of neighbor nodes of For Channel and Channel The similarity between and Respectively The weight matrix and bias term of the layer, Represents an activation function (such as a ReLU function). Through graph convolution operations, the channel association features obtained can reflect the complex relationship between different channels, and thus characterize the behavioral characteristics of the chip during aging. The channel association features are input into the adaptive weight calculation unit, and the attention mechanism is used to calculate the importance score of each test channel. The attention mechanism performs weighted calculations on each channel feature to highlight channels that are more important to the overall behavior. The importance score of the channel is obtained by calculating the attention weight and normalized by the Softmax function to ensure that the sum of the weights of all channels is 1. The calculation formula is:

[0113] ;

[0114] in, For Channel The attention weight, For Channel The importance score of the channel is obtained by the Softmax function, which makes the sum of the weight coefficients of all channels equal to 1, thereby ensuring the normalization of the weights. A fault feature library is constructed according to the preset chip failure mode standard, and the feature vectors in the fault feature library are calculated by cosine similarity with the channel feature group to obtain the failure mode matching degree. Cosine similarity measures the similarity between channel features and fault features to determine whether the channel conforms to a certain failure mode. By multiplying the failure mode matching degree with the channel weight coefficient, a comprehensive weight coefficient is generated to reflect the importance of the channel in the aging process and the matching of the failure mode. The comprehensive weight coefficient is normalized to obtain the target weight coefficient. The channel feature group is weighted and summed according to the target weight coefficient, and the feature data of multiple test channels are fused into a unified feature vector to obtain fused feature data. The fused feature data is calculated using the following formula:

[0115] ;

[0116] in, is the fused feature vector, For Channel The target weight coefficient is For Channel The feature vector of . Through the weighted sum operation, the features of multiple channels are effectively integrated to obtain the fusion feature containing all channel information. The fusion feature data is subjected to feature standardization to ensure that the features of different dimensions have the same scale and obtain the aging characteristic data.

[0117] In a specific embodiment, the process of executing step S6 may specifically include the following steps:

[0118] The aging characteristic data is input into the bidirectional long short-term memory network layer of the life prediction model, and the state values ​​of the forget gate, input gate and output gate are calculated through the time series feature extraction in the forward and reverse directions to obtain the time series coding features;

[0119] The temporal coding features are processed by self-attention, and the correlation weights between features are calculated using a multi-head self-attention mechanism. Each attention head contains a 64-dimensional query vector, a key vector, and a value vector to obtain attention-enhanced features.

[0120] The attention-enhanced features are input into the encoding-decoding module, which contains 3 encoding blocks and 3 decoding blocks. Each encoding block contains a convolution layer and a maximum pooling layer, and each decoding block contains a deconvolution layer and an upsampling layer to obtain multi-scale features.

[0121] Perform residual connection processing on multi-scale features, perform jump connection on features of different scales, use 1×1 convolution to fuse features, and adjust data distribution through batch normalization layer to obtain fused features;

[0122] The fused features are input into a fully connected neural network, which contains three hidden layers with 512, 256 and 128 neurons respectively. Each layer uses the ReLU activation function to obtain deep feature representation;

[0123] The deep feature representation is processed by the performance prediction branch. The key performance parameter change trend of the chip is calculated through two fully connected layers, and the Sigmoid function is used for output mapping to obtain the performance prediction value. The deep feature representation is processed by the life prediction branch. The remaining service life of the chip is calculated through two fully connected layers, and the TanH function is used for output mapping to obtain the life prediction value.

[0124] The performance prediction value and the life prediction value are combined to output the chip aging test results.

[0125] Specifically, the aging characteristic data is input into the bidirectional long short-term memory network (Bi-LSTM) layer of the life prediction model. Bidirectional LSTM captures the bidirectional dependency of data in the time series by extracting time series features in both forward and reverse directions, thus obtaining more comprehensive time series information. The core of LSTM lies in its unique gating mechanism, including forget gate, input gate and output gate. The state values ​​of these gates are calculated by the following formula to obtain the time series encoding features. time steps, forget gate , Input Gate and output gate The states are represented as:

[0126] ;

[0127] ;

[0128] ;

[0129] in, , , Represent the activation states of the forget gate, input gate, and output gate respectively; , , is the corresponding weight matrix, , , is the corresponding bias term; is the hidden state of the previous time step, is the input feature of the current time step, is the sigmoid activation function. Through these gating mechanisms, LSTM selectively remembers or forgets past information, improves the modeling ability of time series data, and obtains time series coding features. The time series coding features are self-attention processed, and the multi-head self-attention mechanism is used to calculate the correlation weights between features. The multi-head self-attention mechanism contains multiple attention heads, and each attention head obtains the correlation between features by calculating the dot product of the query vector, key vector, and value vector. In this process, the time series coding features are mapped to the query vector , key vector Sum value vector , each vector has a dimension of 64. Then the dot product between the query and the key is calculated and normalized by the softmax function to obtain the attention weights, which are then used to perform a weighted summation of the value vectors. The calculation formula is as follows:

[0130] ;

[0131] in, , , Respectively represent The query, key, and value vectors of the attention heads, represents the dimension of the key vector, normalized by the factor To reduce the magnitude of the dot product result and prevent the gradient of the softmax output from being too small. Through the multi-head self-attention mechanism, the network can capture the association between features from multiple angles and obtain attention-enhanced features. The attention-enhanced features are input into the encoding and decoding module. The encoding and decoding module contains 3 encoding blocks and 3 decoding blocks. Each encoding block contains a convolution layer and a maximum pooling layer, while each decoding block contains a deconvolution layer and an upsampling layer. The encoding block extracts multi-scale representations of features through convolution and pooling operations, and gradually reduces the spatial dimensions of the features to obtain a more abstract representation. The convolution operation is used to capture local spatial features, while the maximum pooling operation reduces the spatial dimensions of the features while retaining the most important information. In the decoding block, the spatial dimensions of the features are restored through the deconvolution operation, and the resolution of the features is increased through the upsampling operation to obtain a multi-scale feature representation of the same size as the input. The multi-scale features are processed with residual connections, and features of different scales are jump-connected, and through Convolution is used for feature fusion. Residual connection enables the network to directly transfer input features in the deep structure, prevents the occurrence of gradient vanishing problem, and improves the training efficiency of the network. 1×1 convolution is used to fuse multi-scale features, compress different channel information, and obtain a unified feature representation. In order to stabilize the distribution of data, the data distribution of the fused features is adjusted through the batch normalization layer so that the features have a more stable numerical range when input to the subsequent network, and the fused features are obtained. The fused features are input into the fully connected neural network. The fully connected network contains three hidden layers with 512, 256 and 128 neurons respectively. Each layer uses the ReLU activation function. The formula of the ReLU activation function is:

[0132] ;

[0133] ReLU can effectively solve the problem of gradient disappearance, so that the network maintains a high computational efficiency during both forward and backward propagation. Through a multi-layer fully connected network, the features are gradually compressed and abstracted to obtain a deep feature representation, which contains important information in the aging process and is helpful for subsequent performance and life prediction. After obtaining the deep feature representation, the network is divided into two branches: the performance prediction branch and the life prediction branch. In the performance prediction branch, two fully connected layers are used to calculate the change trend of the key performance parameters of the chip, and the output is mapped through the Sigmoid function to obtain the performance prediction value. The output range of the Sigmoid function is between 0 and 1, which maps the features to a limited range and is suitable for representing the performance change trend. The formula is:

[0134] ;

[0135] In the life prediction branch, the remaining service life of the chip is calculated through two fully connected layers, and the output is mapped through the TanH function to obtain the life prediction value. The output range of the TanH function is between -1 and 1, which is suitable for normalization processing, so that the life prediction value varies within a certain range. The formula is:

[0136] ;

[0137] The performance prediction value and the life prediction value are combined to obtain the chip aging test result.

[0138] The above describes the jig control method for chip aging test in the embodiment of the present invention. The following describes the jig control device for chip aging test in the embodiment of the present invention. Figure 2 , an embodiment of a chip aging test fixture control device in an embodiment of the present invention includes:

[0139] The acquisition module is used to collect parameters of the test fixture to obtain original test data. The test fixture includes multiple parallel test channels.

[0140] The temperature control module is used to input the original test data into the temperature stress compensator and the dynamic parameter controller for control signal analysis and signal fusion, generate fused temperature control instructions, and input the fused temperature control instructions into the temperature control unit of the test fixture to obtain steady-state test data;

[0141] Data screening module, used to perform multi-dimensional analysis and data screening on steady-state test data to obtain effective test data;

[0142] A feature extraction module, used to input effective test data into a feature enhancement network to extract performance features and obtain performance feature data;

[0143] A weighted processing module is used to group the performance characteristic data according to multiple test channels, calculate the weight coefficient of each test channel, and perform weighted processing on the performance characteristic data of each test channel in combination with the failure mode standard to obtain aging characteristic data;

[0144] The calculation module is used to input the aging characteristic data into the life prediction model to calculate the performance prediction value and the life prediction value to obtain the chip aging test result.

[0145] Through the collaboration of the above components, the design of multiple parallel test channels and the combination of multi-layer PCB wiring structure significantly improve the test throughput; through the dual control strategy of temperature stress compensation and dynamic parameter control, the temperature control accuracy reaches ±0.5°C, which accelerates the achievement of test steady state. Multi-dimensional analysis and data screening mechanism are introduced to effectively identify and eliminate abnormal data through statistical feature calculation, correlation analysis and normality test; a feature enhancement network including group normalization layer, SiLU activation layer, convolutional block attention module and multi-head self-attention layer is designed to achieve deep fusion of voltage, current and temperature features; through position encoding and residual connection mechanism, the temporal expression ability of features is enhanced. A life prediction model based on bidirectional long short-term memory network and self-attention mechanism is constructed, which accurately captures the chip performance degradation characteristics through multi-scale feature extraction and residual connection; a dual-branch prediction structure is adopted to output performance prediction value and life prediction value at the same time, providing comprehensive aging evaluation results.

[0146] The present invention also provides a computer device, which includes a memory and a processor. The memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes the steps of the chip aging test fixture control method in the above-mentioned embodiments.

[0147] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the steps of the chip aging test fixture control method.

[0148] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0149] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0150] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip aging test fixture control method, characterized in that: The method comprises: Collecting parameters of a test fixture to obtain original test data, wherein the test fixture includes a plurality of parallel test channels; The original test data is respectively input into the temperature stress compensator and the dynamic parameter controller for control signal analysis and signal fusion, a fusion temperature control instruction is generated, and the fusion temperature control instruction is input into the temperature control unit of the test fixture to obtain steady-state test data; Performing multi-dimensional analysis and data screening on the steady-state test data to obtain effective test data; Inputting the effective test data into a feature enhancement network to extract performance features to obtain performance feature data; The performance characteristic data are grouped according to the multiple test channels, and the weight coefficient of each test channel is calculated, and the performance characteristic data of each test channel is weighted in combination with the failure mode standard to obtain aging characteristic data; specifically including: grouping the performance characteristic data according to the multiple test channels, combining the voltage characteristics, current characteristics and temperature characteristics of each test channel to obtain a channel characteristic group; calculating the variance and mean of each group of characteristic data in the channel characteristic group, and calculating the similarity of each group of characteristic data through a local sensitive hashing algorithm to obtain a characteristic similarity matrix; constructing a graph neural network based on the characteristic similarity matrix, taking each test channel as a node in the graph, and the similarity as the weight of the edge, extracting the relationship between channels through a graph convolution operation to obtain channel association features; and converting the channel association features into Input an adaptive weight calculation unit, use an attention mechanism to calculate the importance score of each test channel, and perform normalization processing through a Softmax function to obtain a channel weight coefficient; construct a fault feature library according to a preset chip failure mode standard, perform cosine similarity calculation on the feature vector in the fault feature library and the channel feature group to obtain a failure mode matching degree, perform a product operation on the failure mode matching degree and the channel weight coefficient to generate a comprehensive weight coefficient, and perform normalization processing on the comprehensive weight coefficient to obtain a target weight coefficient; perform a weighted sum operation on the channel feature group according to the target weight coefficient, fuse the feature data of the multiple test channels into a unified feature vector to obtain fused feature data, and perform feature normalization processing on the fused feature data to obtain the aging characteristic data; The aging characteristic data is input into the life prediction model to calculate the performance prediction value and the life prediction value to obtain the chip aging test result.

2. The chip aging test fixture control method according to claim 1, characterized in that: The test fixture is subjected to parameter collection to obtain original test data, wherein the test fixture includes a plurality of parallel test channels, including: A plurality of first pins and test points are arranged on a first surface of the test fixture, a plurality of second pins are arranged on a second surface opposite to the first surface, and the first pins are connected to the second pins through upper layer wiring, via wiring and lower layer wiring to obtain a signal acquisition circuit; The plurality of first pins, the plurality of second pins and the test points are numbered and grouped, and the first pins, the second pins and the test points with adjacent numbers are divided into a test channel to obtain a plurality of parallel test channels; Inputting an initial temperature control parameter into the temperature control unit of the test fixture, adjusting the temperature of the test fixture to a preset value, obtaining a test initial temperature, performing voltage sampling on each of the plurality of parallel test channels, recording a voltage value between the first pin and the second pin, and obtaining channel voltage data; Performing current sampling on each of the multiple parallel test channels, recording the current value between the first pin and the second pin to obtain channel current data, and performing temperature sampling on the temperature sensors of the multiple parallel test channels, recording the temperature value of each test channel to obtain channel temperature data; The channel voltage data, the channel current data and the channel temperature data are time-stamped, a mapping relationship between the test data and the sampling time is established, and original test data is obtained.

3. The chip aging test fixture control method according to claim 2, characterized in that: The raw test data is respectively input into the temperature stress compensator and the dynamic parameter controller for control signal analysis and signal fusion, a fusion temperature control instruction is generated, and the fusion temperature control instruction is input into the temperature control unit of the test fixture to obtain steady-state test data, including: Inputting the channel temperature data in the original test data into the temperature stress compensator, calculating the mapping relationship between temperature and stress according to the temperature-stress inverse model, obtaining stress compensation parameters, performing nonlinear transformation on the stress compensation parameters, establishing a transfer function between temperature fluctuation and stress change, calculating the compensation coefficient by the least square method, and obtaining a temperature compensation signal; The original test data is input into a dynamic parameter controller, a PID control model is constructed based on a proportional coefficient, an integral time, and a differential time to obtain initial control parameters, and the initial control parameters are adaptively adjusted, and the PID parameter values ​​are dynamically updated according to the rate of change of the temperature error to obtain a dynamic control signal; Linearly combining the temperature compensation signal and the dynamic control signal to generate the fused temperature control instruction, and converting the fused temperature control instruction into an analog control voltage through a digital-to-analog conversion circuit, and inputting the analog control voltage into the heater and the refrigerator of the temperature control unit to obtain a temperature adjustment signal; The temperature adjustment signal is closed-loop controlled, and when it is detected that the temperature fluctuation is less than 0.5°C within 100 consecutive sampling cycles, the voltage value, current value and temperature value of the parallel multiple test channels are collected to obtain the steady-state test data.

4. The chip aging test fixture control method according to claim 3, characterized in that: The multi-dimensional analysis and data screening of the steady-state test data to obtain effective test data includes: Calculating statistical characteristics of the voltage value, current value and temperature value in the steady-state test data respectively to obtain parameter statistical characteristic values, constructing a parameter correlation matrix based on the parameter statistical characteristic values, calculating the correlation coefficients among the voltage value, current value and temperature value to obtain the parameter correlation coefficient; A data continuity index is established according to the parameter correlation coefficient, and the data continuity is judged by calculating the parameter change rate of adjacent sampling points to obtain a continuity score. A sliding window analysis is performed on the steady-state test data, and the window length is set to 50 sampling points. The consistency deviation of the parameters in the window is calculated to obtain a consistency score; The continuity score and the consistency score are combined to generate a comprehensive data quality score, and a score threshold is set to obtain a data screening standard, and the steady-state test data is screened according to the data screening standard to remove data points with a comprehensive quality score lower than the threshold to obtain preliminary screening data; A normality test is performed on the data distribution of the preliminary screening data, the skewness coefficient and the kurtosis coefficient are calculated, the rationality of the data distribution is judged, and a distribution test result is obtained. Based on the distribution test result, a secondary screening is performed on the preliminary screening data, and test data with reasonable data distribution is retained to obtain the valid test data.

5. The chip aging test fixture control method according to claim 4, characterized in that: The step of inputting the effective test data into a feature enhancement network to extract performance features and obtain performance feature data comprises: Input the valid test data into the group normalization layer of the feature enhancement network, and perform standardization processing on the valid test data by calculating the mean and variance of each feature group to obtain standardized feature data; The standardized feature data is input into the SiLU activation layer, and nonlinearly transformed by multiplying the sigmoid function with the linear unit to obtain preliminary activation features; The preliminary activated features are processed by a convolutional block attention module, wherein the convolutional block attention module includes a channel attention unit and a spatial attention unit, and feature weights are extracted by maximum pooling and average pooling to obtain attention features; Input the attention feature into a multi-head self-attention layer, where the multi-head self-attention layer includes 8 attention heads. Each attention head obtains an attention score by calculating the dot product of the query vector, the key vector, and the value vector, performs feature association extraction, and obtains a time series association feature. Perform feedforward neural network processing on the time series correlation features, the feedforward neural network includes two fully connected layers, the number of neurons in the first fully connected layer is 512, and the number of neurons in the second fully connected layer is 256, to obtain fully connected features; The fully connected features are input into the position encoding layer, position encoding vectors of different frequencies are calculated by sine and cosine functions, and summed with the features to obtain position enhancement features; The position enhancement feature is subjected to residual connection processing, the input feature and the output feature are added, and the data distribution is adjusted through layer normalization to obtain the residual feature, and the residual feature is input into the output layer, and the feature dimension is reduced through 1×1 convolution, and the Softmax function is used for feature mapping to obtain the performance feature data.

6. The chip aging test fixture control method according to claim 1, characterized in that: The step of inputting the aging characteristic data into a life prediction model to calculate a performance prediction value and a life prediction value to obtain a chip aging test result includes: Inputting the aging characteristic data into the bidirectional long short-term memory network layer of the life prediction model, extracting the time series features in the forward and reverse directions, calculating the state values ​​of the forget gate, the input gate and the output gate, and obtaining the time series coding features; Performing self-attention processing on the temporal coding features, using a multi-head self-attention mechanism to calculate the correlation weights between features, each attention head contains a 64-dimensional query vector, a key vector and a value vector, to obtain an attention-enhanced feature; Inputting the attention enhancement feature into a coding and decoding module, the coding and decoding module comprises 3 coding blocks and 3 decoding blocks, each coding block comprises a convolution layer and a maximum pooling layer, and each decoding block comprises a deconvolution layer and an upsampling layer, to obtain multi-scale features; Performing residual connection processing on the multi-scale features, performing jump connection on features of different scales, using 1×1 convolution to fuse features, and adjusting data distribution through a batch normalization layer to obtain fused features; Input the fused features into a fully connected neural network, wherein the fully connected neural network comprises three hidden layers, the number of neurons is 512, 256 and 128 respectively, and each layer uses a ReLU activation function to obtain a deep feature representation; The deep feature representation is subjected to performance prediction branch processing, the key performance parameter change trend of the chip is calculated through two fully connected layers, and the Sigmoid function is used for output mapping to obtain a performance prediction value, and the deep feature representation is subjected to life prediction branch processing, the remaining service life of the chip is calculated through two fully connected layers, and the TanH function is used for output mapping to obtain a life prediction value; The performance prediction value and the life prediction value are combined to output the chip aging test result.

7. A chip aging test fixture control device, characterized in that: A jig control method for performing a chip aging test according to any one of claims 1 to 6, wherein the jig control device for the chip aging test comprises: An acquisition module, used to acquire parameters of a test fixture to obtain original test data, wherein the test fixture includes a plurality of parallel test channels; A temperature control module, used for inputting the original test data into the temperature stress compensator and the dynamic parameter controller respectively to perform control signal analysis and signal fusion, generate fusion temperature control instructions, and input the fusion temperature control instructions into the temperature control unit of the test fixture to obtain steady-state test data; A data screening module, used for performing multi-dimensional analysis and data screening on the steady-state test data to obtain valid test data; A feature extraction module, used for inputting the effective test data into a feature enhancement network to extract performance features and obtain performance feature data; A weighted processing module, used to group the performance characteristic data according to the multiple test channels, calculate the weight coefficient of each test channel, and perform weighted processing on the performance characteristic data of each test channel in combination with the failure mode standard to obtain aging characteristic data; The calculation module is used to input the aging characteristic data into the life prediction model to calculate the performance prediction value and the life prediction value to obtain the chip aging test result.

8. A computer device, characterized in that: The invention comprises a memory and a processor, wherein the memory stores a computer program executable on the processor, and is characterized in that when the processor executes the computer program, the jig control method for chip aging test described in any one of claims 1 to 6 is implemented. 9 . A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor executes the chip aging test fixture control method according to any one of claims 1 to 6 .

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