Method for controlling flash memory module and related flash memory controller and memory device
By judging and processing super block data after abnormal power outage in the flash memory controller, the problem of low data judgment and processing efficiency after power outage is solved, and the rapid and accurate data processing and efficient memory use are achieved.
Patent Information
- Application Number
- CN202410114871.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-09
- Filing Date
- 2024-01-26
- Publication Date
- 2025-02-18
AI Technical Summary
After an abnormal power outage and power-up occurs in the flash memory controller, how to efficiently and accurately determine which data in the super block can be used, and then perform appropriate processing to continue writing the data.
By determining whether the flash memory module has encountered abnormal power outage before powering on, we decide the last super block written before powering on, and use binary search methods and other methods to determine for each block in the super block. The last page of data that can be read successfully, thus determining the data weak zone and moving it to another zone or super block.
It realizes the rapid and accurate judgment and processing of valid data in the super block after abnormal power outage, ensuring the reliability of data and efficient use of memory.
Smart Images
Figure CN119473123A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to flash memory. Background Art
[0002] During the process of writing data to a super block of the flash memory module by the flash memory controller, if an abnormal power failure occurs, such as power off recovery (POR) or sudden power off recovery (SPOR), after the flash memory controller is powered on again, the flash memory controller will determine whether an abnormal power failure has occurred, and if it is determined that an abnormal power failure has occurred, determine which data in the super block is still valid, and perform a garbage collection operation on the super block to move the valid data therein to another block. However, since the super block includes multiple blocks, and the data writing progress of each block is different, how to efficiently determine the valid data in the super block is an important issue. Summary of the invention
[0003] Therefore, one of the purposes of the present invention is to provide a control method for a memory device, which can efficiently and accurately determine which data in a super block can continue to be used after the memory device is abnormally powered off and powered on again, and process the super block for continued data writing, so as to solve the problems described in the prior art.
[0004] In one embodiment of the present invention, a method for controlling a flash memory module is disclosed, wherein the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the method includes: after the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before powering on; if the flash memory module encounters an abnormal power failure before powering on, determining a super block that is last written to the flash memory module before powering on, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining the last data page that can be successfully read from each first block in the super block; determining a data weak area of the super block according to the last data page that can be successfully read from each first block in the super block; and moving data in the data weak area to other areas of the super block or to another super block.
[0005] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of the dies includes a plurality of blocks, each of the blocks includes a plurality of data pages, and the flash memory controller includes a read-only memory and a microprocessor, and the microprocessor is used to perform the following operations: after the flash memory module is powered on, determine whether the flash memory module encounters an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters an abnormal power failure before the flash memory module is powered on, determine a super block that is last written to the flash memory module before the power is on, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determine the last data page that can be successfully read from each first block in the super block; determine a data weak area of the super block according to the last data page that can be successfully read from each first block in the super block; and move data in the data weak area to other areas of the super block or to another super block.
[0006] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of dies, each of which includes a plurality of blocks, and each of which includes a plurality of data pages. The flash memory controller is used to access the flash memory module, and the flash memory controller performs the following operations: after the flash memory module is powered on, determine whether the flash memory module encounters an abnormal power failure before powering on; if the flash memory module encounters an abnormal power failure before powering on, determine a super block that is last written to the flash memory module before powering on, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determine the last data page that can be successfully read in each first block in the super block; determine a data weak area of the super block according to the last data page that can be successfully read in each first block in the super block; and move the data in the data weak area to other areas of the super block or another super block. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.
[0008] Figure 2 FIG. 4 is a schematic diagram of a super block according to an embodiment of the present invention.
[0009] Figure 3 A schematic diagram of multiple data pages contained in a block.
[0010] Figure 4A schematic diagram showing that the writing speed of each block in a super block is different.
[0011] Figure 5 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present invention.
[0012] Figure 6 A flowchart of searching the last data page with data written in each block using a binary search method.
[0013] Figure 7 A schematic diagram for determining the last successfully readable data page of each block in a super block.
[0014] Figure 8 A schematic diagram for determining weak data areas and invalid areas of a super block.
[0015]
Explanation of symbols
[0016] 100: Memory device
[0017] 110: Flash memory controller
[0018] 112: Microprocessor
[0019] 112M: Read-only memory
[0020] 112C: Program code
[0021] 114: Control Logic
[0022] 116: Buffer memory
[0023] 118: Interface Logic
[0024] 120: Flash memory module
[0025] 130: Main device
[0026] 132: Encoder
[0027] 134:Decoder
[0028] 136: Randomizer
[0029] 138:De-Randomizer
[0030] 140: DRAM
[0031] 202,204:Super Block
[0032] 300: Block
[0033] 500~516: Steps
[0034] 600~620: Steps
[0035] B1~BK: Block
[0036] P1~P448: Data page DETAILED DESCRIPTION
[0037] Figure 1 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), the decoder 134 is used to decode the data read from the flash memory module 120, the randomizer 136 is used to perform a randomization operation on the data written into the flash memory module 120, and the de-randomizer 138 is used to perform a de-randomization operation on the data read from the flash memory module 120.
[0038] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.
[0039] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform many control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 and / or a dynamic random access memory (DRAM) 140 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.
[0040] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.
[0041] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, it will not be described in detail in the specification.
[0042] Figure 2 FIG. 1 is a schematic diagram of a super block according to an embodiment of the present invention. Figure 2 As shown, it is assumed that the flash memory module 120 includes four dies (die 1 to die 4), and each die includes a plurality of blocks B1 to BK. At this time, the microprocessor 112 can configure the blocks belonging to different data planes or different dies in the flash memory module 120 as a super block to facilitate the management of data access. In this embodiment, it is illustrated that a die has only one data plane, but the present invention is not limited to this. Figure 2As shown, die 1 to die 4 include blocks B1 to BK respectively, and the microprocessor 112 can configure the block B1 of each die as a super block 202, and the block B2 of each die as a super block 204, and so on, and the flash memory controller 110 is similar to a general block when accessing the super blocks 202 and 204. For example, the super block 202 itself is an erase unit, that is, although the four blocks B1 included in the super block 202 can be erased separately, the flash memory controller 110 will definitely erase the four blocks B1 together.
[0043] In addition, reference Figure 3 Schematic diagram of block 300 shown, where block 300 may be Figure 2 Any of the blocks B1 to BK shown, and the block 300 includes multiple data pages, such as 448 data pages shown. When writing data to the super block 202, the data can be written sequentially from the first data page P1 of the block B1 of the die 1, the first data page P1 of the block B1 of the die 2, the first data page P1 of the block B1 of the die 3, and the first data page P1 of the block B1 of the die 4, and then the data is sequentially written to the second data page P2 of the block B1 of the die 1, the second data page P2 of the block B1 of the die 2, ..., and so on. In other words, the flash memory controller 110 will arrange to write data to the first data page P1 of each block B1 in the super block 202, and then arrange to write data to the second data page P2 of each block B1 in the super block 202. The super block is a logically set block, not a physical set block, by the flash memory controller 110 for convenient management of the flash memory module 120. In addition, when performing garbage collection, calculating block valid pages, and calculating the length of block write time, calculations can also be performed using super blocks as units.
[0044] In one embodiment, the flash memory controller 110 may have a plurality of buffers for temporarily storing data to be written to a plurality of dies (eg, Figure 2 The buffers do not need to be used in sequence, and each die in the flash memory module 120 has its own backend hardware so that the flash memory module 120 can process the data written to multiple dies in parallel. However, in this embodiment, the slight difference in the writing speed of each die will continue to accumulate, resulting in a large difference in the data writing of each die. For example, referring to Figure 4, the flash memory controller 110 sequentially writes data to the first data page P1 of die 1 to die 4, the second data page P2 of die 1 to die 4, ... the third data page P1 of die 1 to die 4, ... and so on. Since each die has a difference in process, the speed of data writing in die 3 will be slower than that of other die. For example, when both die 1 and die 2 have been written to data page P18, die 3 only writes to data page P11. It should be noted that at this time, the microprocessor 112 has generated data to be written to data pages P12 to P18 of die 3, and these data are temporarily stored in a buffer of the control logic 114 or the flash memory module 120.
[0045] However, if in Figure 4 When the data shown is written to the super block 202, an abnormal power failure occurs, such as a sudden power failure recovery (SPOR) situation. After the memory device 100 is powered on again, the flash memory controller 110 will re-read the content of the super block 202 to determine the status of the super block 202, so as to determine an appropriate processing method. This embodiment proposes a control method after the memory device 100 is powered on again, which can efficiently and accurately determine which data in the super block 202 can continue to be used, and process the super block 202 for continued writing of data, so as to optimize the use of the super block 202.
[0046] Figure 5 1 is a flow chart of a control method of a memory device 100 according to an embodiment of the present invention. At step 500, the process starts, and the memory device 100 is just powered on and performs an initialization operation. At step 502, the flash memory controller 110 determines whether the memory device 100 has experienced an abnormal power failure before powering on. If so, the process proceeds to step 506; if not, the process proceeds to step 504. In one embodiment, when the memory device 100 is normally shut down / powered off, the flash memory controller 110 stores a plurality of temporary tables and data stored in the buffer memory 116 in the flash memory module 120, and includes a flag for indicating whether the memory device 100 is normally shut down. Therefore, after powering on, the flash memory controller 110 can determine whether the memory device 100 has previously experienced an abnormal power failure by reading the flag stored at a specific address in the flash memory module 120. For example, when the flag is not correctly set, it is determined that an abnormal power failure has previously occurred.
[0047] In step 504, since the memory device 100 does not encounter an abnormal power failure before powering on, the flash memory controller 110 starts to operate normally, such as writing data from the host device 130 to the flash memory module 120, or performing a garbage collection operation on the flash memory module 120, etc., that is, the flash memory controller 110 does not perform Figure 4 Steps 506 to 516.
[0048] In step 506, the flash memory controller 110 determines the last super block written to the flash memory module 120 before power-on. For example, the flash memory controller 110 may search for a super block in an active state recorded in the flash memory module 120 as the last super block written to the super block before power-on. Figure 4 Superblock 202 is shown for illustration purposes only.
[0049] In step 508, for each block in the super block, such as block B1 of die 1 to die 4 in super block 202, the flash memory controller 110 uses a binary search method or any other suitable search method to search for the last data page with data written in each block. Figure 4 For example, the flash memory controller 110 searches for data page P18 of block B1 of die 1 , data page P18 of block B1 of die 2 , data page P11 of block B1 of die 3 , and data page P17 of block B1 of die 4 .
[0050] For example, refer to Figure 6 The flowchart shown is a process of searching the last data page with data written in each block B1 using a binary search method. The process is described as follows.
[0051] Step 600: The process starts.
[0052] Step 602: Determine the search range (R) and the first data page number to be searched (P=(N / 2)) according to the total number of data pages (N) in block B1, and the search direction is forward (D=2, i.e., the direction of increasing data page numbers).
[0053] Step 604: Read the spare region of the data page (P).
[0054] Step 606: Determine whether the data page (P) is a blank data page based on the content in the spare area. For example, the data page (P) can be determined based on whether the spare area records relevant metadata. If the data page (P) is determined to be a blank data page, the process proceeds to step 608; if the data page (P) is determined to be not a blank data page, the process proceeds to step 610.
[0055] Step 608: Set the data page number to be searched next time to (P=P-(R / 2)), and the search direction at this time is backward (D=1, ie, the direction of decreasing data page numbers).
[0056] Step 610: Set the data page number to be searched next time to (P=P+(R / 2)), and the search direction is forward (D=2).
[0057] Step 612: Determine whether the search range (R) is 1. If not, the process proceeds to step 614; if so, the process proceeds to step 616.
[0058] Step 614: Reduce the search range by half (R=(R / 2)), and the process returns to step 604.
[0059] Step 616 : Determine whether the search direction is backward (D=1?), if not, the process proceeds to step 618 ; if so, the process proceeds to step 620 .
[0060] Step 618: Determine whether the data page (P) is the last data page in block B1 to which data is written.
[0061] Step 620: Determine whether the data page (P-1) is the last data page in block B1 to which data is written.
[0062] It should be noted that Figure 6 The detailed steps shown are only for illustrative purposes and are not intended to be limiting of the present invention.
[0063] In one embodiment, since each block in the super block 202 can be operated in parallel, the flash memory controller 110 can use interleave or multi-channel operation to read data from multiple blocks simultaneously to accelerate the execution speed of the above-mentioned binary search method or other search methods.
[0064] In step 510, for each block, the flash memory controller 110 reads data from the last data page with data written therein in sequence until the read data can be successfully decoded by the decoder 134, that is, the decoder 134 can successfully use the error correction code of the read data to complete the decoding operation, so as to determine the last data page that can be successfully read (that is, successfully decoded) in each block in the super block 202. Figure 7 For example, the decoder 134 cannot successfully decode the data of the data page P18 of the block B1 of the die 1, but can successfully decode the data of the data page P17 of the block B1 of the die 1, so the flash memory controller 110 determines that the last data page that can be successfully read in the block B1 of the die 1 is P17. Similarly, the flash memory controller 110 determines that the last data page that can be successfully read in the block B1 of the die 2 is P17, the last data page that can be successfully read in the block B1 of the die 3 is P10, and the last data page that can be successfully read in the block B1 of the die 4 is P16.
[0065] In step 512, based on the last successfully readable data page in each super block 202, the flash memory controller 110 determines the data page with the smallest data page number and a corresponding specific block or a specific die. Figure 7 For example, the specific block is block B1 of die 3, the specific die is die 3, and the data page with the smallest data page number is P10.
[0066] In step 514, the flash memory controller 110 determines the last validly written block and data page in the super block 202 according to the specific block and the data page with the smallest data page number determined in step 512. In one embodiment, if the number of the specific block or the number of the die to which the specific block belongs is N, where N is greater than 1, and the number of the data page with the smallest data page number is M, then the number of the die to which the last validly written block belongs is "N-1", and the data page of the last validly written block is "M+1". Figure 7 For example, if the specific die determined in step 512 is die 3, and the data page with the smallest data page number is P10, then the last validly written data page in super block 202 is data page P11 of block B1 of die 2. In addition, if the specific block belongs to die 1, then the die to which the last validly written block belongs is the die with the largest number (e.g. Figure 7 The last validly written data page of the block is “M”.
[0067] In step 516, the flash memory controller 110 determines a weak region and an invalid area of the super block 202 according to the last validly written block and data page in the super block 202 determined in step 514, and moves the data in the weak region to other areas in the super block 202 or to other super blocks. Figure 8 , the flash memory controller 110 may push back the last validly written block and data page in the super block 202 by several data pages (for example, the number of data pages corresponding to one or two word lines) to determine the data weak area. For example, the data weak area may include data pages P5-P10 of block B1 of die 1 to die 4, and data page P11 of the block of die 1 to die 2. In addition, the flash memory controller 110 may push back several data pages (for example, the number of data pages corresponding to one or two word lines) based on the last data page with data written in each block of the super block 202 determined in step 508 to determine the invalid area. For example, the invalid area may include data page P11 of block B1 of die 3 to die 4, data pages P5-P10 of block B1 of die 1 to die 4, and data pages P12-P20 of the block of die 1 to die 2.
[0068] In one embodiment, since the data weak area of the super block 202 can be regarded as an area where data is unstable, if the space after the invalid area in the super block 202 is sufficient, the flash memory controller 110 copies the data in the data weak area to the space after the invalid area in the super block 202, such as the data page P21 and the subsequent data pages of the block B1 of the die 3 to the die 4; and if the space after the invalid area in the super block 202 is insufficient, the flash memory controller 110 copies the data in the data weak area to other super blocks.
[0069] In one embodiment, the flash memory controller 110 may perform double programming on the invalid area of the super block 202 , that is, write invalid data or redundant data into the invalid area to stabilize the super block.
[0070] As described in the above embodiments, this embodiment can efficiently and accurately determine which data in the super block 202 can continue to be used, and migrate data in the weak data area of the super block 202 to ensure data reliability.
[0071] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.
Claims
1. A method for controlling a flash memory module, wherein the flash memory module comprises a plurality of dies, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages, and the method comprises: After the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before being powered on; If the flash memory module encounters an abnormal power failure before powering on, determining a super block to be written last before powering on the flash memory module, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; For each first block in the super block, determining the last successfully readable data page of each first block in the super block; Determine a data weak area of the super block according to the last successfully readable data page of each first block in the super block; and The data in the data weak area is moved to other areas of the super block or to another super block.
2. The method according to claim 1, characterized in that The step of determining the data weak area of the super block according to the last successfully readable data page of each first block in the super block comprises: According to the last successfully readable data page of each first block in the super block, a data page with a minimum data page number and a corresponding specific first block are determined; Determine the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block; as well as The data weak area is determined according to the first block and the data page that are last effectively written in the super block.
3. The method according to claim 2, characterized in that The step of determining the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block comprises: If the number of the specific first block or the number of the die to which the specific first block belongs is N, where N is greater than 1, and the number of the data page with the smallest data page number is M, then the number of the die to which the last validly written first block belongs is determined to be "N-1", and the data page of the last validly written first block is "M+1"; as well as The specific first block belongs to the first die, and the data page with the smallest data page number is numbered M. The die to which the last validly written first block belongs is the die with the largest number, and the data page of the last validly written first block is "M".
4. The method according to claim 1, characterized in that Contains: For each first block in the super block, determine the last data page with data written in each first block; as well as For each first block in the super block, the step of determining the last successfully readable data page of each first block in the super block comprises: The last data page with data written in each first block is read forward to determine the last successfully readable data page in each first block in the super block.
5. The method according to claim 4, characterized in that For each first block in the super block, the step of determining the last data page with data written in each first block includes: A binary search method is used to simultaneously read data from a plurality of first blocks of the super block through interleave or multi-channel operation to determine the last data page with data written in each first block.
6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of dies, each of which includes a plurality of blocks, each of which includes a plurality of data pages, and the flash memory controller includes: A read-only memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: After the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before being powered on; If the flash memory module encounters an abnormal power failure before powering on, determining a super block to be written last before powering on the flash memory module, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; For each first block in the super block, determining the last successfully readable data page of each first block in the super block; Determine a data weak area of the super block according to the last successfully readable data page of each first block in the super block; and The data in the data weak area is moved to other areas of the super block or to another super block.
7. The flash memory controller according to claim 6, wherein: The step of determining the data weak area of the super block according to the last successfully readable data page of each first block in the super block comprises: According to the last successfully readable data page of each first block in the super block, a data page with a minimum data page number and a corresponding specific first block are determined; Determine the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block; as well as The data weak area is determined according to the first block and the data page that are last effectively written in the super block.
8. The flash memory controller according to claim 7, wherein: The step of determining the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block comprises: If the number of the specific first block or the number of the die to which the specific first block belongs is N, where N is greater than 1, and the number of the data page with the smallest data page number is M, then the number of the die to which the last validly written first block belongs is determined to be "N-1", and the data page of the last validly written first block is "M+1"; as well as The specific first block belongs to the first die, and the data page with the smallest data page number is numbered M. The die to which the last validly written first block belongs is the die with the largest number, and the data page of the last validly written first block is "M".
9. The flash memory controller according to claim 6, wherein Contains: For each first block in the super block, determine the last data page with data written in each first block; as well as For each first block in the super block, the step of determining the last successfully readable data page of each first block in the super block comprises: The last data page with data written in each first block is read forward to determine the last successfully readable data page in each first block in the super block.
10. The flash memory controller according to claim 9, wherein: For each first block in the super block, the step of determining the last data page with data written in each first block includes: A binary search method is used to simultaneously read data from a plurality of first blocks of the super block through interleave or multi-channel operation to determine the last data page with data written in each first block.
11. A memory device comprising: A flash memory module comprising a plurality of dies, each of which comprises a plurality of blocks, each of which comprises a plurality of data pages; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: After the flash memory module is powered on, determining whether the flash memory module encounters an abnormal power failure before being powered on; If the flash memory module encounters an abnormal power failure before powering on, determining a super block to be written last before powering on the flash memory module, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; For each first block in the super block, determining the last successfully readable data page of each first block in the super block; Determine a data weak area of the super block according to the last successfully readable data page of each first block in the super block; and The data in the data weak area is moved to other areas of the super block or to another super block.
12. The memory device according to claim 11, characterized in that The step of determining the data weak area of the super block according to the last successfully readable data page of each first block in the super block comprises: According to the last successfully readable data page of each first block in the super block, a data page with a minimum data page number and a corresponding specific first block are determined; Determine the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block; as well as The data weak area is determined according to the first block and the data page that are last effectively written in the super block.
13. The memory device according to claim 12, characterized in that The step of determining the last validly written first block and data page in the super block according to the data page with the smallest data page number and the corresponding specific first block comprises: If the number of the specific first block or the number of the die to which the specific first block belongs is N, where N is greater than 1, and the number of the data page with the smallest data page number is M, then the number of the die to which the last validly written first block belongs is determined to be "N-1", and the data page of the last validly written first block is "M+1"; as well as The specific first block belongs to the first die, and the data page with the smallest data page number is numbered M. The die to which the last validly written first block belongs is the die with the largest number, and the data page of the last validly written first block is "M".
14. The memory device according to claim 11, wherein: Also included: For each first block in the super block, determine the last data page with data written in each first block; as well as For each first block in the super block, the step of determining the last successfully readable data page of each first block in the super block comprises: The last data page with data written in each first block is read forward to determine the last successfully readable data page in each first block in the super block.
15. The memory device according to claim 14, characterized in that For each first block in the super block, the step of determining the last data page with data written in each first block includes: A binary search method is used to simultaneously read data from a plurality of first blocks of the super block through interleave or multi-channel operation to determine the last data page with data written in each first block.