Reconfigurable processor compiling method based on fusion register allocation and DFG mapping technology

Abstract

The invention relates to a reconfigurable processor compiling method based on fusion register allocation and a DFG mapping technology. The method comprises the steps of generating an initial data flow diagram according to a to-be-compiled task, and determining a scheduling period corresponding to each subtask node according to each execution sequence, namely inserting routing nodes among the subtask nodes in the initial data flow diagram by utilizing each scheduling period to obtain a target data flow diagram, the initial data flow diagram comprises a plurality of sub-task nodes and an execution sequence corresponding to each sub-task node, each sub-task node corresponds to each sub-task split from the to-be-compiled task, the target data flow diagram is used for performing task compiling, and the routing node is used for mapping to the register node and / or the computing node in the task compiling process. By adopting the method, the compiling efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology. Background Art

[0002] Reconfigurable processors, such as CGRA (Coarse-Grained Reconfigurable Arrays) processors, usually compile tasks when processing tasks, and then process the tasks based on the compiled results.

[0003] Traditional task compilation methods usually decompose the task first and map the decomposed subtasks to computing resources. The reconfigurable processor then allocates registers for storing intermediate data to the task based on the mapping results. Task compilation ends after successful allocation.

[0004] However, the above task compilation method has the problem of low compilation efficiency. Summary of the invention

[0005] Based on this, it is necessary to provide a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology that can improve compilation efficiency in response to the above technical problems.

[0006] In a first aspect, the present application provides a reconfigurable processor compilation method based on fusion register allocation and DFG (Data Flow Diagram) mapping technology, comprising:

[0007] Generate an initial data flow graph according to the task to be compiled, the initial data flow graph includes multiple subtask nodes and the execution order corresponding to each subtask node, and each subtask node corresponds to each subtask split from the task to be compiled;

[0008] According to each execution order, determine the scheduling period corresponding to each subtask node;

[0009] Using each scheduling cycle, routing nodes are inserted between each subtask node in the initial data flow graph to obtain a target data flow graph. The target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0010] In one embodiment, routing nodes are inserted between subtask nodes in the initial data flow graph using each scheduling cycle to obtain a target data flow graph, including:

[0011] According to each scheduling period, obtain the scheduling period difference between adjacent subtask nodes in the initial data flow graph;

[0012] If the scheduling period difference is greater than a first preset threshold, a routing node is inserted between adjacent subtask nodes to obtain a target data flow graph.

[0013] In one embodiment, inserting a routing node between adjacent subtask nodes includes:

[0014] According to the scheduling cycle difference, the number of routing nodes inserted between adjacent subtask nodes is determined;

[0015] According to the number of nodes, routing nodes are inserted between adjacent subtask nodes.

[0016] In one embodiment, the method further comprises:

[0017] According to each scheduling period, determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph;

[0018] Iterative mapping is performed according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, and the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

[0019] In one embodiment, iterative mapping is performed according to the maximum scheduling period difference, the target data flow graph, and the current schedulable resource data to obtain a compilation result, including:

[0020] For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling cycle difference, then based on the current iteration number, sub-graph isomorphic mapping is performed on the target data flow graph and the schedulable resource data;

[0021] If the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

[0022] In one embodiment, the method further comprises:

[0023] If the subgraph isomorphic mapping result is not successfully obtained, and the current iteration number is less than the maximum scheduling cycle difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result;

[0024] If the subgraph isomorphic mapping result is not successfully obtained and the current number of iterations is equal to the maximum scheduling period difference, the compilation is determined to have failed.

[0025] In a second aspect, the present application also provides a reconfigurable processor compilation device based on fusion register allocation and DFG mapping technology, including:

[0026] An acquisition module is used to generate an initial data flow graph according to the task to be compiled, wherein the initial data flow graph includes a plurality of subtask nodes and an execution order corresponding to each subtask node, and each subtask node corresponds to each subtask split from the task to be compiled;

[0027] A cycle determination module is used to determine the scheduling cycle corresponding to each subtask node according to each execution order;

[0028] The compilation module is used to use each scheduling cycle to insert routing nodes between each subtask node in the initial data flow graph to obtain a target data flow graph. The target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0029] In a third aspect, an embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method of the first aspect when executing the computer program.

[0030] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method of the first aspect described above.

[0031] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method in the first aspect are implemented.

[0032] The above-mentioned reconfigurable processor compilation method based on the fusion register allocation and DFG mapping technology generates an initial data flow graph according to the task to be compiled, and determines the scheduling period corresponding to each subtask node according to each execution order, that is, each scheduling period can be used to insert a routing node between each subtask node in the initial data flow graph to obtain a target data flow graph, wherein the initial data flow graph includes a plurality of subtask nodes and the execution order corresponding to each subtask node, each subtask node corresponds to each subtask split from the task to be compiled, the target data flow graph is used to perform task compilation, and the routing node is used to map to the register node and / or the computing node during the task compilation process. In this way, after the initial data flow graph is generated according to the task to be compiled, the scheduling period is determined according to the execution order corresponding to each subtask node in the initial data flow graph, and then the scheduling period corresponding to each subtask node is used to insert a routing node for transmitting data in the initial data flow graph, so that the action of using registers to store intermediate data in the processing process of the subsequent compiled task can be retained in the routing node as a subtask node, and the processor does not need to allocate registers separately for the intermediate data, and the subsequent register allocation process can be completed simultaneously with the subtask mapping process, thereby improving the compilation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology in traditional technology;

[0035] Figure 2 It is an application environment diagram of a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology in one embodiment;

[0036] Figure 3 It is a flowchart of a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology in one embodiment;

[0037] Figure 4 It is a data flow diagram of an initial task in another embodiment;

[0038] Figure 5 is a flow chart of step 303 in another embodiment;

[0039] Figure 6 A target task data flow diagram in another embodiment;

[0040] Figure 7 A schematic diagram of a process of performing task compilation according to a target data flow graph in another embodiment;

[0041] Figure 8 is a schematic diagram of a mapping result in another embodiment;

[0042] Fig. 9 It is a structural block diagram of a reconfigurable processor compilation device based on fusion register allocation and DFG mapping technology in one embodiment;

[0043] Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] Reconfigurable processors, such as CGRA (Coarse-Grained Reconfigurable Arrays) processors, are coarse-grained processors designed to handle highly parallel computing tasks. Its background stems from the focus on the needs of computationally intensive tasks in applications, and by allowing parallel configuration of hardware resources, the overall performance is improved. The advantages of this architecture include high parallelism, flexibility, and power efficiency.

[0046] The design concept of the CGRA processor enables it to perform well in handling highly parallel computing tasks. In related technologies, when the CGRA processor processes a task, it usually compiles the task and then processes the task based on the compiled result. Therefore, the role of the compiler is crucial. The compiler plays a key role in resource mapping, performance optimization, and support for specific programming models, which directly affects system performance and developer experience.

[0047] Traditional task compilation methods usually decompose the task first and map the decomposed subtasks to computing resources. The reconfigurable processor then allocates registers for storing intermediate data to the task based on the mapping results. Task compilation ends after successful allocation.

[0048] For example, refer to Figure 1 , is the traditional task compilation process. The reconfigurable processor will first decompose the task to obtain a data flow graph consisting of multiple subtask nodes (see Figure 1 1a in ), and then the reconfigurable processor maps these subtasks to schedulable computing resources (PE) (see Figure 1 1b in the above), Figure 1 1c in the figure is the mapping result. Then, registers (GR) are allocated according to the mapping result. When allocating, the processor will allocate registers based on the cycle difference of task parallel startup (that is, the time interval between different processing generations when the same task is processed multiple times). It can be understood that the smaller the cycle difference of task parallel startup, the higher the task parallelism. Therefore, the processor will first try to allocate registers based on a smaller cycle difference of task parallel startup, such as 1. However, Figure 1 For example, when the period difference between the parallel start of tasks is 1, Figure 1 At least 4 registers are required during task processing (see Figure 1 1e in the figure), and the current processor has only two schedulable registers. At this time, the allocation fails (refer to Figure 1 In 1d in FIG. 1 , the processor needs to increase the cycle difference of the parallel startup of the tasks and reallocate registers to the tasks based on the increased cycle difference of the parallel startup of the tasks.

[0049] Therefore, the process of continuously allocating registers causes the task compilation method to have the problem of low compilation efficiency.

[0050] In view of this, the present application provides a reconfigurable processor compilation method based on the fusion register allocation and DFG mapping technology, generates an initial data flow graph according to the task to be compiled, and determines the scheduling period corresponding to each subtask node according to each execution order, that is, each scheduling period can be used to insert a routing node between each subtask node in the initial data flow graph to obtain a target data flow graph, wherein the initial data flow graph includes multiple subtask nodes and the execution order corresponding to each subtask node, each subtask node corresponds to each subtask split from the task to be compiled, the target data flow graph is used to compile the task, and the routing node is used to map to the register node and / or the computing node during the task compilation process. In this way, after the initial data flow graph is generated according to the task to be compiled, the scheduling period is determined according to the execution order corresponding to each subtask node in the initial data flow graph, and then the scheduling period corresponding to each subtask node is used to insert a routing node for transmitting data in the initial data flow graph, so that the action of using registers to store intermediate data in the processing process of the subsequent compiled task can be retained in the routing node as a subtask node, and the processor does not need to allocate registers separately for the intermediate data, and the subsequent register allocation process can be completed simultaneously with the subtask mapping process, thereby improving the compilation efficiency.

[0051] The embodiment of the present application provides a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology, which can be applied to Figure 2 In the application environment shown. Among them, the data storage system can store the data that the server 201 needs to process. The data storage system can be integrated on the server 201, or it can be placed on the cloud or other network servers. The server 201 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. The server 201 is deployed with a processor 202 for task compilation, and the processor 202 can be a reconfigurable processor.

[0052] In an exemplary embodiment, Figure 3 As shown, a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology is provided, and the method is applied to Figure 2 The processor 202 in the example is used as an example to illustrate, including the following steps 301 to 303. Among them:

[0053] Step 301, generating an initial data flow graph according to the task to be compiled.

[0054] The initial data flow graph includes a plurality of subtask nodes and an execution order corresponding to each subtask node, and each subtask node corresponds to each subtask split from the task to be compiled.

[0055] The task to be compiled is a task to be compiled. In the embodiment of the present application, the task to be compiled may be a task to be processed in parallel, such as a loop program, an iterative calculation task, etc.

[0056] In the embodiment of the present application, the processor may decompose the task to be compiled to obtain multiple subtasks and the execution order of each subtask. For example, the task to be compiled is the following code:

[0057] for (int i = 0; i < 100; i++) {

[0058] int a = src[i];

[0059] int b = a * a;

[0060] int c = b + b;

[0061] int d = -c;

[0062] int e = c + 1000;

[0063] *(int *)src[i] = e;}

[0064] Decompose the code into 6 subtasks. Subtask a is "int a = src [i]", with an execution order of 1. Subtask b is "int b = a * a", with an execution order of 2. Subtask c is "int c = b + b", with an execution order of 3. Subtask d is "int d = - c", with an execution order of 4. Subtask e is "inte = c + 1000", with an execution order of 5. Subtask f is "* (int *) src [i] = e", with an execution order of 6.

[0065] After obtaining multiple subtasks and the execution order of each subtask, the processor can generate a corresponding initial data flow graph according to each subtask and its corresponding execution order. Taking the above task as an example, the initial data flow graph can refer to Figure 4 , the processor can use the execution order corresponding to each subtask as the execution order of its corresponding subtask node.

[0066] Step 302: Determine the scheduling period corresponding to each subtask node according to each execution order.

[0067] In an embodiment of the present application, the processor can determine the scheduling period corresponding to each subtask node based on the execution order, and the scheduling period can reflect the execution order of each subtask node. Optionally, the processor can directly use the execution order corresponding to each subtask node as its corresponding scheduling period, for example, the scheduling period corresponding to node a is 1, and the scheduling period corresponding to node b is 2; optionally, the processor can process each execution order according to preset data processing conditions to obtain the scheduling period corresponding to each subtask node.

[0068] Step 303, using each scheduling cycle, inserting routing nodes between each subtask node in the initial data flow graph to obtain the target data flow graph.

[0069] It can be understood that the larger the difference in scheduling periods corresponding to adjacent subtask nodes is, the more intermediate data needs to be stored during the processing. Figure 4 Taking the initial task data flow diagram in as an example, it can be seen that the execution of subtask node f requires the output of subtask nodes a and e. The data output after the execution of subtask node e can be sent directly to subtask node f, and the data generated in the process does not need to be stored. However, if the data generated after the execution of subtask node a needs to be transmitted to subtask node f, it needs to go through 5 scheduling cycles. During this process, the intermediate data generated by subtask node a needs at least four transmissions before it can be passed to subtask node f.

[0070] In an embodiment of the present application, in order to reduce and improve the utilization rate of schedulable resources, the processor can add the storage action of intermediate data as a special executable subtask to the task to be compiled. Therefore, in a possible implementation manner, the processor can add the storage action of intermediate data as a special executable subtask to update the initial data flow graph accordingly, that is, the subtask corresponding to the storage action of intermediate data is mapped to a routing node that can perform data flow, and the routing node is inserted into the initial data flow graph to obtain the target data flow graph finally used for compilation, wherein the target data flow graph is used for task compilation, and the routing node is used to map to register nodes and / or computing nodes during the task compilation process.

[0071] Optionally, the processor can use the difference in scheduling periods corresponding to each adjacent subtask node to determine the scheduling period required for the intermediate data transmission. Based on this, the processor can determine the number of routing nodes to be inserted between the adjacent subtask nodes, and insert routing nodes between the adjacent subtask nodes according to the number; optionally, the processor calculates whether the difference in scheduling periods corresponding to each adjacent subtask node is greater than 1. If it is greater than 1, it means that the intermediate data between the adjacent subtask nodes needs to be transmitted at least once. The processor can iteratively update the initial data flow graph based on this, that is, continuously insert routing nodes between adjacent subtask nodes whose scheduling period difference is greater than 1, until the difference in scheduling periods between each subtask node is no greater than 1.

[0072] In the above embodiment, after the initial data flow graph is generated according to the task to be compiled, the scheduling cycle is determined according to the execution order corresponding to each subtask node in the initial data flow graph, and then the routing node for transmitting data is inserted into the initial data flow graph using the scheduling cycle corresponding to each subtask node, so that the action of using registers to store intermediate data in the processing process of subsequent compiled tasks can be retained in the routing node as a subtask node, and the processor no longer needs to allocate registers separately for the intermediate data. The subsequent register allocation process can be completed simultaneously with the subtask mapping process, thereby improving the compilation efficiency.

[0073] In one embodiment, based on the above Figure 3 The embodiment shown, see Figure 5 This embodiment involves the process of inserting routing nodes between each subtask node in the initial data flow graph using each scheduling cycle to obtain the target data flow graph. Figure 5 As shown, step 303 may include step 501 and step 502 .

[0074] Step 501, according to each scheduling period, obtain the scheduling period difference between adjacent subtask nodes in the initial data flow graph.

[0075] Step 502: If the scheduling period difference is greater than a first preset threshold, a routing node is inserted between adjacent subtask nodes to obtain a target data flow graph.

[0076] In an embodiment of the present application, the processor can determine adjacent sub-task nodes based on the initial data flow graph and obtain their corresponding scheduling periods. Then, the processor can calculate the scheduling period difference between adjacent sub-task nodes to determine the number of routing nodes that the intermediate data between adjacent sub-task nodes needs to pass through.

[0077] In a possible implementation, when the processor detects that the scheduling period differences are all less than or equal to a first preset threshold, such as 1, the processor can directly use the initial data flow graph as the target data flow graph.

[0078] In another possible implementation, when the processor detects that the scheduling cycle difference is greater than a first preset threshold, such as 1, the processor may insert routing nodes between adjacent subtask nodes according to the scheduling cycle difference to obtain a target data flow graph.

[0079] Optionally, the processor may iteratively insert routing nodes between adjacent subtask nodes based on the scheduling cycle difference; optionally, the processor may determine the number of routing nodes to be inserted between adjacent subtask nodes based on the scheduling cycle difference, and then insert routing nodes between adjacent subtask nodes based on the number of nodes.

[0080] For example, refer to Figure 6 , the scheduling period difference between adjacent subtask nodes a and f is 5, then the processor can determine that the number of routing nodes is 4, and the processor can insert 4 routing nodes r1, r2, r3 and r4 between adjacent subtask nodes a and f.

[0081] In one embodiment, based on the above Figure 3 The embodiment shown, see Figure 7 , this embodiment relates to the process of compiling tasks according to the target data flow graph. Figure 3 As shown, the process may include step 701 and step 702 .

[0082] Step 701, according to each scheduling period, determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph.

[0083] Step 702, iterative mapping is performed according to the maximum scheduling period difference, the target data flow graph and the current schedulable resource data to obtain a compilation result.

[0084] After determining the target data flow graph, the processor can compile the task to be compiled according to the target data flow graph.

[0085] It can be understood that the task to be compiled can be a task that is processed in parallel in multiple rounds of tasks. The smaller the cycle difference between the parallel start of each round of tasks, the higher the task parallelism. Therefore, in an embodiment of the present application, the processor can first start mapping each subtask node in the target data flow graph to the current schedulable resources based on a smaller cycle difference between the parallel start of tasks. The current schedulable resources include computing resources for running subtasks and register resources that can store data, and can also include some other special resources, such as row, column, and area registers.

[0086] In an embodiment of the present application, the cycle difference of parallel task startup is less than or equal to the maximum scheduling cycle difference between adjacent subtask nodes. When the cycle difference of parallel task startup is greater than the maximum scheduling cycle difference between adjacent subtask nodes, the task to be compiled cannot be processed in multiple rounds in parallel, which reduces the task processing efficiency.

[0087] Based on this, in a possible implementation, the processor can perform iterative mapping according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data. The number of iterative mappings corresponding to each generation can be used to characterize the cycle difference of parallel task startup. For example, if the number of iterative mappings is 1, it means that the cycle difference of parallel task startup corresponding to the current generation is 1. Therefore, the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

[0088] Regarding the iterative mapping process, in one possible implementation, for each iterative mapping process, if the current number of iterations corresponding to the current iterative mapping process is less than or equal to the maximum scheduling cycle difference, the processor can perform sub-graph isomorphic mapping on the target data flow graph and the schedulable resource data based on the current number of iterations. If the sub-graph isomorphic mapping result is successfully obtained, the sub-graph isomorphic mapping result is determined as the compilation result.

[0089] For example, Figure 6 As an example, the target data flow diagram in the figure can be used to refer to the current schedulable resource data corresponding to the current schedulable resources. Figure 8 8a in the figure, the processor performs subgraph isomorphic mapping based on the case where the cycle difference of task parallel startup is 1 during the first iterative mapping process, and successfully obtains Figure 8 The subgraph isomorphic mapping result in 8b in , at this time, the processor can use the result as the compilation result.

[0090] In another possible implementation, if the subgraph isomorphic mapping result is not successfully obtained and the current number of iterations is less than the maximum scheduling cycle difference, the processor may perform the next subgraph isomorphic mapping process according to the target data flow graph and the schedulable resource data to obtain the compilation result. If the subgraph isomorphic mapping result is not successfully obtained and the current number of iterations is equal to the maximum scheduling cycle difference, the compilation is determined to have failed.

[0091] In an embodiment of the present application, if the number of iterations is less than the maximum scheduling cycle difference, and the current generation processor has not successfully obtained the subgraph isomorphic mapping result, the processor can perform subgraph isomorphic mapping in the next round based on a larger task parallel startup cycle difference until the subgraph isomorphic mapping result is not successfully obtained during the current iteration, and the current number of iterations is equal to the maximum scheduling cycle difference, then the processor can determine that the compilation has failed.

[0092] Optionally, in the event of a compilation failure, the processor may output compilation failure information to indicate that the compilation of the task to be compiled has failed; optionally, in the event of a compilation failure, the processor may regenerate the target data flow graph and remap it according to the newly generated target data flow graph.

[0093] In one embodiment, an exemplary link direction acquisition method is provided, which can be applied to Figure 1 In the implementation environment shown.

[0094] Step a: Generate an initial data flow graph based on the task to be compiled.

[0095] The initial data flow graph includes a plurality of subtask nodes and an execution order corresponding to each subtask node, and each subtask node corresponds to each subtask split from the task to be compiled.

[0096] Step b: Determine the scheduling period corresponding to each subtask node according to each execution order.

[0097] Step c: according to each scheduling period, obtain the scheduling period difference between adjacent subtask nodes in the initial data flow graph.

[0098] Step d: if the scheduling cycle difference is greater than a first preset threshold, the number of routing nodes to be inserted between adjacent subtask nodes is determined according to the scheduling cycle difference.

[0099] Step e: insert routing nodes between adjacent subtask nodes according to the number of nodes to obtain the target data flow graph.

[0100] The target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0101] Step f, determining the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph according to each scheduling period.

[0102] Step g: For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling cycle difference, then based on the current iteration number, sub-graph isomorphic mapping is performed on the target data flow graph and the schedulable resource data.

[0103] Step h: if the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

[0104] The number of iterative mappings is less than or equal to the maximum scheduling period difference.

[0105] In step i, if the subgraph isomorphic mapping result is not successfully obtained and the current number of iterations is less than the maximum scheduling cycle difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result.

[0106] In step j, if the subgraph isomorphic mapping result is not successfully obtained and the current number of iterations is equal to the maximum scheduling period difference, it is determined that the compilation has failed.

[0107] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0108] Based on the same inventive concept, the embodiment of the present application also provides a reconfigurable processor compilation device based on fused register allocation and DFG mapping technology for implementing the reconfigurable processor compilation method based on fused register allocation and DFG mapping technology involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more embodiments of the reconfigurable processor compilation device based on fused register allocation and DFG mapping technology provided below can refer to the limitations of the reconfigurable processor compilation method based on fused register allocation and DFG mapping technology above, and will not be repeated here.

[0109] In an exemplary embodiment, Fig. 9 As shown, a reconfigurable processor compilation device based on fusion register allocation and DFG mapping technology is provided, including: an acquisition module 901, a cycle determination module 902 and a compilation module 903, wherein:

[0110] An acquisition module 901 is used to generate an initial data flow graph according to the task to be compiled, wherein the initial data flow graph includes a plurality of subtask nodes and an execution order corresponding to each of the subtask nodes, and each of the subtask nodes corresponds to each subtask split from the task to be compiled;

[0111] A period determination module 902 is used to determine the scheduling period corresponding to each of the subtask nodes according to the execution order;

[0112] The compilation module 903 is used to utilize each of the scheduling cycles to insert routing nodes between each of the subtask nodes in the initial data flow graph to obtain a target data flow graph, wherein the target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0113] In one embodiment, the compiling module 903 includes:

[0114] A difference acquisition unit, used for acquiring the scheduling period difference between adjacent subtask nodes in the initial data flow graph according to each scheduling period;

[0115] A node insertion unit is used to insert the routing node between the adjacent subtask nodes to obtain the target data flow graph if the scheduling period difference is greater than a first preset threshold.

[0116] In one embodiment, the node insertion unit is specifically used to perform:

[0117] Determining the number of routing nodes to be inserted between adjacent subtask nodes according to the scheduling period difference;

[0118] The routing nodes are inserted between the adjacent subtask nodes according to the number of nodes.

[0119] In one embodiment, the apparatus further comprises:

[0120] A maximum difference determination unit, used to determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph according to each of the scheduling periods;

[0121] A mapping unit is used to perform iterative mapping according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, wherein the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

[0122] In one embodiment, the mapping unit is specifically configured to perform:

[0123] For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling period difference, then based on the current iteration number, subgraph isomorphic mapping is performed on the target data flow graph and the schedulable resource data;

[0124] If the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

[0125] In one embodiment, the mapping unit is further configured to perform:

[0126] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is less than the maximum scheduling period difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result;

[0127] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is equal to the maximum scheduling period difference, it is determined that the compilation has failed.

[0128] Each module in the reconfigurable processor compilation device based on the fusion register allocation and DFG mapping technology can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each module above.

[0129] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig.10 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store task compilation data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology is implemented.

[0130] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0131] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0132] Generate an initial data flow graph according to the task to be compiled, the initial data flow graph comprising a plurality of subtask nodes and an execution order corresponding to each of the subtask nodes, each of the subtask nodes corresponding to each of the subtasks split from the task to be compiled;

[0133] Determine the scheduling period corresponding to each of the subtask nodes according to the execution order;

[0134] Using each of the scheduling cycles, routing nodes are inserted between each of the subtask nodes in the initial data flow graph to obtain a target data flow graph, wherein the target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0135] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0136] According to each of the scheduling cycles, obtaining the scheduling cycle difference between adjacent subtask nodes in the initial data flow graph;

[0137] If the scheduling period difference is greater than a first preset threshold, the routing node is inserted between the adjacent subtask nodes to obtain the target data flow graph.

[0138] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0139] Determining the number of routing nodes to be inserted between adjacent subtask nodes according to the scheduling period difference;

[0140] The routing nodes are inserted between the adjacent subtask nodes according to the number of nodes.

[0141] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0142] Determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph according to each of the scheduling periods;

[0143] Iterative mapping is performed according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, and the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

[0144] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0145] For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling period difference, then based on the current iteration number, subgraph isomorphic mapping is performed on the target data flow graph and the schedulable resource data;

[0146] If the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

[0147] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0148] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is less than the maximum scheduling period difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result;

[0149] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is equal to the maximum scheduling period difference, it is determined that the compilation has failed.

[0150] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0151] Generate an initial data flow graph according to the task to be compiled, the initial data flow graph comprising a plurality of subtask nodes and an execution order corresponding to each of the subtask nodes, each of the subtask nodes corresponding to each of the subtasks split from the task to be compiled;

[0152] Determine the scheduling period corresponding to each of the subtask nodes according to the execution order;

[0153] Using each of the scheduling cycles, routing nodes are inserted between each of the subtask nodes in the initial data flow graph to obtain a target data flow graph, wherein the target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0154] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0155] According to each of the scheduling cycles, obtaining the scheduling cycle difference between adjacent subtask nodes in the initial data flow graph;

[0156] If the scheduling period difference is greater than a first preset threshold, the routing node is inserted between the adjacent subtask nodes to obtain the target data flow graph.

[0157] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0158] Determining the number of routing nodes to be inserted between adjacent subtask nodes according to the scheduling period difference;

[0159] The routing nodes are inserted between the adjacent subtask nodes according to the number of nodes.

[0160] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0161] Determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph according to each of the scheduling periods;

[0162] Iterative mapping is performed according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, and the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

[0163] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0164] For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling period difference, then based on the current iteration number, subgraph isomorphic mapping is performed on the target data flow graph and the schedulable resource data;

[0165] If the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

[0166] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0167] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is less than the maximum scheduling period difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result;

[0168] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is equal to the maximum scheduling period difference, it is determined that the compilation has failed.

[0169] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0170] Generate an initial data flow graph according to the task to be compiled, the initial data flow graph comprising a plurality of subtask nodes and an execution order corresponding to each of the subtask nodes, each of the subtask nodes corresponding to each of the subtasks split from the task to be compiled;

[0171] Determine the scheduling period corresponding to each of the subtask nodes according to the execution order;

[0172] Using each of the scheduling cycles, routing nodes are inserted between each of the subtask nodes in the initial data flow graph to obtain a target data flow graph, wherein the target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

[0173] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0174] According to each of the scheduling cycles, obtaining the scheduling cycle difference between adjacent subtask nodes in the initial data flow graph;

[0175] If the scheduling period difference is greater than a first preset threshold, the routing node is inserted between the adjacent subtask nodes to obtain the target data flow graph.

[0176] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0177] Determining the number of routing nodes to be inserted between adjacent subtask nodes according to the scheduling period difference;

[0178] The routing nodes are inserted between the adjacent subtask nodes according to the number of nodes.

[0179] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0180] Determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph according to each of the scheduling periods;

[0181] Iterative mapping is performed according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, and the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

[0182] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0183] For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling period difference, then based on the current iteration number, subgraph isomorphic mapping is performed on the target data flow graph and the schedulable resource data;

[0184] If the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

[0185] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0186] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is less than the maximum scheduling period difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result;

[0187] If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is equal to the maximum scheduling period difference, it is determined that the compilation has failed.

[0188] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0189] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0190] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0191] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A reconfigurable processor compilation method based on fusion register allocation and DFG mapping technology, characterized in that: The method comprises: Generate an initial data flow graph according to the task to be compiled, the initial data flow graph comprising a plurality of subtask nodes and an execution order corresponding to each of the subtask nodes, each of the subtask nodes corresponding to each of the subtasks split from the task to be compiled; Determine the scheduling period corresponding to each of the subtask nodes according to the execution order; Using each of the scheduling cycles, routing nodes are inserted between each of the subtask nodes in the initial data flow graph to obtain a target data flow graph, wherein the target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

2. The method according to claim 1, characterized in that The method of inserting routing nodes between the subtask nodes in the initial data flow graph using the scheduling cycles to obtain a target data flow graph includes: According to each of the scheduling cycles, obtaining the scheduling cycle difference between adjacent subtask nodes in the initial data flow graph; If the scheduling period difference is greater than a first preset threshold, the routing node is inserted between the adjacent subtask nodes to obtain the target data flow graph.

3. The method according to claim 2, characterized in that The inserting the routing node between the adjacent subtask nodes includes: Determining the number of routing nodes to be inserted between the adjacent subtask nodes according to the scheduling period difference; The routing nodes are inserted between the adjacent subtask nodes according to the number of nodes.

4. The method according to claim 1, characterized in that The method further comprises: Determine the maximum scheduling period difference between adjacent subtask nodes in the target data flow graph according to each of the scheduling periods; Iterative mapping is performed according to the maximum scheduling cycle difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, and the number of iterative mappings is less than or equal to the maximum scheduling cycle difference.

5. The method according to claim 4, characterized in that The iterative mapping is performed according to the maximum scheduling period difference, the target data flow graph and the current schedulable resource data to obtain a compilation result, including: For each iterative mapping process, if the current iteration number corresponding to the current iterative mapping process is less than or equal to the maximum scheduling period difference, then based on the current iteration number, subgraph isomorphic mapping is performed on the target data flow graph and the schedulable resource data; If the subgraph isomorphic mapping result is successfully obtained, the subgraph isomorphic mapping result is determined as the compilation result.

6. The method according to claim 5, characterized in that The method further comprises: If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is less than the maximum scheduling period difference, the next subgraph isomorphic mapping process is performed according to the target data flow graph and the schedulable resource data to obtain the compilation result; If the subgraph isomorphic mapping result is not successfully obtained, and the current number of iterations is equal to the maximum scheduling period difference, it is determined that the compilation has failed.

7. A reconfigurable processor compilation device based on fusion register allocation and DFG mapping technology, characterized in that: The device comprises: An acquisition module is used to generate an initial data flow graph according to the task to be compiled, wherein the initial data flow graph includes a plurality of subtask nodes and an execution order corresponding to each of the subtask nodes, and each of the subtask nodes corresponds to each subtask split from the task to be compiled; A cycle determination module, used to determine the scheduling cycle corresponding to each of the subtask nodes according to the execution order; A compilation module is used to utilize each of the scheduling cycles to insert routing nodes between each of the subtask nodes in the initial data flow graph to obtain a target data flow graph, wherein the target data flow graph is used for task compilation, and the routing nodes are used to map to register nodes and / or computing nodes during the task compilation process.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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