Shifting register and driving method thereof, gate driving circuit and display device

Abstract

The invention provides a shift register and a driving method thereof, a gate driving circuit and a display device, and relates to the technical field of display, the shift register comprises an input module, a first driving module and an output module; the first driving module is electrically connected with a driving signal line, an input signal line and a first node, and is configured to write a driving signal into the first node under the control of an input signal of the input signal line and a driving signal of the driving signal line in a touch control stage; the input module is electrically connected with an input signal line and a first node, and is configured to write an input signal into the first node under the control of the input signal; the output module is electrically connected with the clock signal line, the first node and the output signal line, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node. The difference of output waveforms of different shift registers can be reduced, so that the poor cross grain of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] Currently, display panels with touch functions include embedded touch panels. For example, the Incell Touch display panel embeds the touch sensor network inside the display panel, and can drive the touch panel to realize screen display and touch functions through a touch and display integrated control chip. The touch and display control chip can divide a frame of picture time into multiple display stages and touch stages, and the touch stage is set between two adjacent display stages to achieve a higher touch frequency.

[0003] The shift register in the gate drive circuit can provide a gate drive signal to the pixel row of the display panel. In the touch control stage, the first node in the shift register used to control the output signal needs to maintain a constant level state, but the level state of the first node may fluctuate due to transistor leakage in the shift register, which can easily cause the shift register output signal to be abnormal, resulting in insufficient charging of the pixel row and causing poor horizontal stripes on the display panel. Summary of the invention

[0004] The present application provides a shift register and a driving method thereof, a gate driving circuit, and a display device, which can solve the problem of bad horizontal stripes on a display panel caused by abnormal output signals of the shift register.

[0005] In a first aspect, the present application provides a shift register, the shift register comprising: an input module, a first driving module, and an output module;

[0006] The first driving module is electrically connected to the driving signal line, the input signal line, and the first node respectively, and is configured to write the driving signal into the first node under the control of the input signal of the input signal line and the driving signal of the driving signal line in the touch control stage;

[0007] The input module is electrically connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal;

[0008] The output module is electrically connected to the clock signal line, the first node and the output signal line respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.

[0009] Optionally, the first driving module includes a driving control unit and a pull-up driving unit;

[0010] The driving control unit is electrically connected to the driving signal line, the input signal line, and the control end of the pull-up driving unit, respectively, and is configured to write the driving signal into the control end of the pull-up driving unit under the control of the input signal;

[0011] The pull-up driving unit is also electrically connected to the driving signal line and the first node respectively, and is configured to write the driving signal into the first node under the control of the driving signal.

[0012] Optionally, the driving control unit includes a first transistor; the pull-up driving unit includes a second transistor;

[0013] The control electrode of the first transistor is electrically connected to the input signal line, the first electrode is electrically connected to the drive signal line, and the second electrode is electrically connected to the control electrode of the second transistor;

[0014] A first electrode of the second transistor is electrically connected to the driving signal line, and a second electrode of the second transistor is electrically connected to the first node.

[0015] Optionally, the shift register further includes a second driving module;

[0016] The second driving module is electrically connected to the control end, the second node, and the first power signal line of the pull-up driving unit respectively, and is configured to write the second power signal of the first power signal line into the control end of the pull-up driving unit under the control of the voltage of the second node;

[0017] The pull-up driving unit is further configured to disconnect the driving signal line from the first node under the control of the second power signal.

[0018] Optionally, the second driving module includes a third transistor;

[0019] The control electrode of the third transistor is electrically connected to the second node, the first electrode is electrically connected to the control end of the pull-up driving unit, and the second electrode is electrically connected to the first power signal line.

[0020] In a second aspect, the present application provides a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded shift registers as described in the first aspect.

[0021] In a third aspect, the present application provides a display device, comprising the gate driving circuit as described in the second aspect.

[0022] In a fourth aspect, the present application provides a driving method for controlling the shift register as described in the first aspect, the method comprising:

[0023] In the touch control stage, an input signal is written to the input signal line, and a driving signal with a first level is written to the driving signal line, so that the first driving module writes the driving signal with the first level into the first node under the control of the input signal and the driving signal with the first level.

[0024] Optionally, the first driving module includes a driving control unit and a pull-up driving unit, and the driving method further includes:

[0025] In the display stage, the input signal is written to the input signal line, and the drive signal with the second level is written to the drive signal line, and before the touch stage, the drive signal with the first level is written to the drive signal line, and the clock signal is written to the clock signal line, so that the drive control unit writes the drive signal to the control end of the pull-up drive unit under the control of the input signal, so that the pull-up drive unit disconnects the drive signal line and the first node under the control of the drive signal with the second level, so that the pull-up drive unit writes the drive signal with the first level to the first node under the control of the drive signal with the first level.

[0026] Optionally, the step of switching to write the driving signal having the first level to the driving signal line before the touch control stage includes:

[0027] The drive signal having the first level is switched to be written to the drive signal line in advance by a first time duration; wherein the first time duration is greater than or equal to a cycle duration of the clock signal and less than a total duration of the display phase.

[0028] Optionally, a level value of the first level is 1.3 to 1.4 times a high level value of the clock signal.

[0029] Optionally, the first driving module includes a driving control unit and a pull-up driving unit, and the driving method further includes:

[0030] In the display stage, the input signal is written to the input signal line, the drive signal with the first level is written to the drive signal line, and the clock signal is written to the clock signal line, so that the drive control unit writes the drive signal with the first level to the control end of the pull-up drive unit under the control of the input signal, so that the pull-up drive unit writes the drive signal with the first level to the first node under the control of the drive signal with the first level.

[0031] Optionally, a level value of the first level is equal to a high level value of the clock signal.

[0032] A shift register and a driving method thereof, a gate driving circuit, and a display device provided by the present application have at least the following advantages:

[0033] The input module is electrically connected to the input signal line and the first node respectively, and is configured to write the input signal to the first node under the control of the input signal, so that the voltage level state of the first node can be consistent with the voltage level state of the input signal. Since the first driving module is electrically connected to the driving signal line, the input signal line and the first node respectively, and is configured to write the driving signal to the first node under the control of the input signal of the input signal line and the driving signal of the driving signal line in the touch stage, the driving signal can keep the voltage of the first node at the level state after the input signal is written in the touch stage, and the problem of the transistor leakage in the shift register causing the level state of the first node to decrease can be avoided. The output module is electrically connected to the clock signal line, the first node and the output signal line respectively, and is configured to write the clock signal of the clock signal line to the output signal line under the control of the voltage of the first node. Since the first driving module can keep the level state of the first node unchanged in the touch stage, the clock signal of the output module is written to the output signal line with a stable waveform under the control of the voltage of the first node, avoiding the problem of abnormal output signal of the shift register, and reducing the difference in output waveforms of different shift registers, thereby improving the horizontal stripes of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0035] Figure 1 It is a schematic diagram of the level state of the pull-up node in the shift register corresponding to the pixel rows at different positions in the related art;

[0036] Figure 2 is a schematic diagram of output signals of a shift register corresponding to pixel rows at different positions in the related art;

[0037] Figure 3 This is one of the structural schematic diagrams of a shift register provided in an embodiment of the present application;

[0038] Figure 4 This is a second structural diagram of a shift register provided in an embodiment of the present application;

[0039] Figure 5 This is a third structural diagram of a shift register provided in an embodiment of the present application;

[0040] Figure 6 This is a fourth structural diagram of a shift register provided in an embodiment of the present application;

[0041] Figure 7 It is a schematic diagram of the steps of a driving method provided in an embodiment of the present application;

[0042] Figure 8 This is a schematic diagram of the level state of a pull-up node in a shift register provided by an embodiment of the present application;

[0043] Fig. 9 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0044] Fig.10 It is one of the timing diagrams of a display device provided in an embodiment of the present application;

[0045] Fig.11 This is the second timing diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in some embodiments to clearly and completely describe the technical solutions in some embodiments. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] At present, Incell Touch display panels generally use a touch and display integrated control chip (Touch and display Driver Integration, TDDI). In order to obtain better touch performance, Incell Touch TDDI display devices usually adopt an intra-frame drive (LHB) mode that alternates between the display phase (Display Period, DP) and the touch phase (Touch Period, TP) within a frame time. During touch scanning, the output signal of the shift register in the gate drive circuit pauses the corresponding row scan to maintain the current state. The time interval of the touch phase in the LHB mode is also called the "TP pit". Since the touch phase lasts for a long time, the level state of the pull-up node (PU) in the shift register will become lower due to the presence of thin film transistor (TFT) leakage current. The gradual decrease in the level state of the pull-up node (PU) will affect the output signal of the shift register. For example, at the end of the touch phase, the output signal attenuation or disturbance may cause horizontal stripes on the touch display, affecting the display effect of the display panel.

[0048] Figure 1is a schematic diagram of the level state of the pull-up node in the shift register corresponding to the pixel rows at different positions in the related art, such as Figure 1 (a) shows the state of the PU node of a normal row in the display phase, while Figure 1 (b) and Figure 1 (c) shows the PU node states of the entry and exit rows in the touch phase. The entry row is the pixel row that has just entered the touch phase, and the exit row is the pixel row that is about to exit the touch phase. Figure 1 (a) is a normal line, Figure 1 (b) and Figure 1 In (c), the level state of the pull-up node (PU) cannot be maintained during the touch control phase due to the leakage current effect. Different levels of the pull-up nodes in different shift registers will lead to different output waveforms of the shift registers, such as Figure 2 As shown, the horizontal stripes are visible on the display. The horizontal stripes are more serious in silicon (Si) and low temperature polysilicon (LTPS) display devices with large leakage current.

[0049] In some embodiments, the signal has a first level and a second level. The first level and the second level only represent that the level of the signal has two states, and do not represent that the first level or the second level has a specific value. The transistor used in the shift register in some embodiments may be a thin film transistor TFT or a metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor, for example, it may be an N-type TFT or a P-type TFT, and the embodiments of the present application are not limited to this.

[0050] Figure 3 is one of the structural diagrams of a shift register 10 provided in an embodiment of the present application, such as Figure 3 As shown, the shift register 10 comprises: an input module 101, a first driving module 102, and an output module 103;

[0051] The first driving module 102 is electrically connected to the driving signal line VH, the input signal line INPUT, and the first node PU, respectively, and is configured to write the driving signal into the first node PU under the control of the input signal of the input signal line INPUT and the driving signal of the driving signal line VH in the touch control stage;

[0052] The input module 101 is electrically connected to the input signal line INPUT and the first node PU respectively, and is configured to write the input signal into the first node PU under the control of the input signal;

[0053] The output module 103 is electrically connected to the clock signal line CLK, the first node PU and the output signal line OUTPUT respectively, and is configured to write the clock signal of the clock signal line CLK into the output signal line OUTPUT under the control of the voltage of the first node PU.

[0054] The shift register 10 provided in the embodiment of the present application can be applied to an embedded touch panel. For example, an IncellTouch display panel, an Incell Touch display panel reuses the V-com electrode in a liquid crystal display panel (LCD) as the transmitter (Tx) and receiver (Rx) of a touch sensor (Sensor), embeds the touch sensor network inside the LCD display panel, and the touch and display functions share a TDDI chip driver.

[0055] In some embodiments, the input module 101 is used to control the connection between the input signal line INPUT and the first node PU. When the input module 101 turns on the connection between the input signal line INPUT and the first node PU under the control of the input signal transmitted by the input signal line INPUT, the input signal is written to the first node PU, so that the first node PU has the same level state as the input signal. The output module 103 is used to control the connection between the clock signal line CLK and the output signal line OUTPUT. When the output module 103 turns on the connection between the clock signal line CLK and the output signal line OUTPUT under the control of the voltage of the first node PU, the clock signal transmitted by the clock signal line CLK is written to the output signal line OUTPUT, that is, the clock signal is used as the output signal of the shift register 10. Among them, the driving signal of the driving signal line VH can come from an external circuit, for example, the driving signal can come from the same IC chip as the clock signal.

[0056] In some embodiments, the shift register 10 can be used as a gate drive circuit corresponding to a pixel row on a display panel, and the output signal of the shift register 10 can be a gate drive signal of the pixel row. For example, the shift register 10 can be a gate driver integrated on array substrate (Gate Driver On Array, GOA) circuit, also known as a GOA circuit. Among them, the output signal of the shift register 10 in the touch stage is used to control the corresponding pixel row to stop scanning, and the clock signal can be changed to a low level signal in the touch stage, so that the corresponding pixel row maintains the current state.

[0057] The shift register 10 provided in the embodiment of the present application also includes a first driving module 102, and the first driving module 102 is jointly controlled by the input signal of the input signal line INPUT and the driving signal of the driving signal line VH. The first driving module 102 is configured to write the driving signal to the first node PU under the control of the input signal of the input signal line INPUT and the driving signal of the driving signal line VH during the touch stage, so that the first node PU can be charged by the driving signal, so that the first node PU can maintain a constant level state. In this way, by keeping the level state of the first node PU in the shift register 10 unchanged, the abnormal output signal of the shift register 10 due to the fluctuation of the level state of the first node PU can be avoided, and the output signal difference between different shift registers 10 can be reduced, so that the touch display horizontal stripes can be improved. The shift register 10 can be suitable for LCD products with large leakage current such as Si and LTPS.

[0058] Figure 4 FIG. 2 is a second structural diagram of a shift register 10 provided in an embodiment of the present application. Figure 4 As shown, the input module 101 includes a transistor T1, and the output module 103 includes a transistor T3 and a capacitor C1. Among them, the transistors T1 and T3 are N-type TFTs. The gate and drain of the transistor T1 are electrically connected to the input signal line INPUT, respectively, and the source of the transistor T1 is electrically connected to the first node PU. The first driving module 102 is electrically connected to the input signal line INPUT, the driving signal line VH and the first node PU, respectively. Among them, Figure 4 The first node PU in the shift register 10 shown is a pull-up node (PU), and the first node PU is also electrically connected to the gate of the transistor T3 and one end of the capacitor C1, respectively. The drain of the transistor T3 is electrically connected to the clock signal line CLK, and the source of the transistor T3 is electrically connected to the output signal line OUTPUT and the other end of the capacitor C1, respectively.

[0059] like Figure 4 As shown, in the touch stage, when the input signal of the output signal line OUTPUT is a high-level signal, the transistor T1 is turned on, the high-level signal is written into the first node PU, and the driving signal charges the first node PU under the control of the first driving module 102, so that the level state of the first node PU remains unchanged, that is, the voltage of the first node PU remains at a high level. The transistor T3 is turned on under the control of the high-level voltage of the first node PU, and then the clock signal can be output to the pixel circuit of the corresponding pixel row through the output signal line OUTPUT.

[0060] In the embodiment of the present application, the input module 101 is electrically connected to the input signal line INPUT and the first node PU respectively, and is configured to write the input signal to the first node PU under the control of the input signal, so that the voltage level state of the first node PU can be consistent with the voltage level state of the input signal. Since the first driving module 102 is electrically connected to the driving signal line VH, the input signal line INPUT and the first node PU respectively, it is configured to write the driving signal to the first node PU under the control of the input signal of the input signal line INPUT and the driving signal of the driving signal line VH in the touch stage, so that the driving signal can keep the voltage of the first node PU at the level state after the input signal is written in the touch stage, and the problem of the transistor leakage in the shift register 10 causing the level state of the first node PU to decrease can be avoided. The output module 103 is electrically connected to the clock signal line CLK, the first node PU and the output signal line OUTPUT respectively, and is configured to write the clock signal of the clock signal line CLK to the output signal line OUTPUT under the control of the voltage of the first node PU. Since the first driving module 102 can keep the level state of the first node PU unchanged during the touch stage, the clock signal of the output module 103 is written into the output signal line OUTPUT with a stable waveform under the control of the voltage of the first node PU, thereby avoiding the problem of abnormal output signal of the shift register 10 and reducing the difference in output waveforms of different shift registers 10, thereby improving the poor horizontal stripes of the display panel.

[0061] Optionally, the first driving module 102 includes a driving control unit 1021 and a pull-up driving unit 1022;

[0062] The driving control unit 1021 is electrically connected to the driving signal line VH, the input signal line INPUT, and the control end of the pull-up driving unit 1022, respectively, and is configured to write the driving signal into the control end of the pull-up driving unit 1022 under the control of the input signal;

[0063] The pull-up driving unit 1022 is also electrically connected to the driving signal line VH and the first node PU, and is configured to write the driving signal into the first node PU under the control of the driving signal.

[0064] In some embodiments, the control end of the driving control unit 1021 may be electrically connected to the input signal line INPUT, and the driving control unit 1021 is used to control the connection between the driving signal line VH and the control end of the pull-up driving unit 1022 in response to the input signal of the input signal line INPUT.

[0065] Specifically, in the display stage and the touch stage, for the non-output shift register 10, the input module 101 will respond to the input signal and control the input signal line INPUT to disconnect from the first node PU. And the driving control unit 1021 is configured to disconnect the driving signal line VH from the control end of the pull-up driving unit 1022 under the control of the input signal, so that the input signal and the driving signal cannot be written into the first node PU.

[0066] Specifically, in the display stage and the touch stage, for the shift register 10 with normal output, the input module 101 will respond to the input signal and conduct the connection between the input signal line INPUT and the first node PU, so that the input signal is written into the first node PU. And the driving control unit 1021 is configured to conduct the connection between the driving signal line VH and the control end of the pull-up driving unit 1022 under the control of the input signal, so as to write the driving signal into the control end of the pull-up driving unit 1022.

[0067] The level state of the input signal transmitted by the input signal line INPUT to the shift register 10 that does not output is different from the level state of the input signal transmitted by the input signal line INPUT to the shift register 10 that normally outputs. Figure 4 As shown, for the shift register 10 without output, the input signal can be a low-level signal, then the transistor T1 is turned off, and the input signal cannot be written into the first node PU. For the shift register 10 with normal output, the input signal can be a high-level signal, then the transistor T1 is turned on, and the high-level signal is written into the first node PU, so that the voltage of the first node PU is in a high-level state consistent with the input signal. This is only an example, and the embodiments of the present application are not limited to this.

[0068] In some embodiments, the input end of the pull-up driving unit 1022 is electrically connected to the driving signal line VH, the output end of the pull-up driving unit 1022 is electrically connected to the first node PU, and the pull-up driving unit 1022 is used to control the connection between the driving signal line VH and the first node PU in response to the driving signal. Specifically, in the display stage and the touch stage, for the shift register 10 with normal output, the driving control unit 1021 will conduct the connection between the driving signal line VH and the control end of the pull-up driving unit 1022 under the control of the input signal, so that the driving signal can be transmitted to the control end of the pull-up driving unit 1022.

[0069] Among them, in the display stage and the touch stage, if the driving signal controls the pull-up driving unit 1022 to conduct the connection between the driving signal line VH and the first node PU, the driving signal is written into the first node PU, and if the driving signal controls the pull-up driving unit 1022 to disconnect the connection between the driving signal line VH and the first node PU, the driving signal cannot be written into the first node PU. Therefore, if the level state of the first node PU is to be maintained by the driving signal in the touch stage, the driving signal needs to control the pull-up driving unit 1022 to conduct the connection between the driving signal line VH and the first node PU, and the level state of the driving signal is consistent with the level state of the input signal written into the first node PU by the input module 101, so that the driving signal can play a role in keeping the level state of the first node PU unchanged.

[0070] In the embodiment of the present application, the first driving module 102 includes a driving control unit 1021 and a pull-up driving unit 1022. The driving control unit 1021 receives an input signal of an input signal line INPUT to control whether the driving signal of the driving signal line VH is written into the control end of the pull-up driving unit 1022. The pull-up driving unit 1022 controls whether the driving signal is written into the first node PU under the control of the driving signal of the driving signal line VH. In this way, when the input signal controls the driving control unit 1021 to conduct the connection between the driving signal line VH and the control end of the pull-up driving unit 1022, and then the pull-up driving unit 1022 conducts the connection between the driving signal line VH and the first node PU, the driving signal can be written into the first node PU to keep the level state of the first node PU unchanged, so that the first driving module 102 keeps the level state of the first node PU unchanged under the control of the input signal and the driving signal, and the problem of the level state of the first node PU being reduced due to transistor leakage can be avoided.

[0071] Optionally, the shift register 10 further includes a second driving module 104;

[0072] The second driving module 104 is electrically connected to the control end of the pull-up driving unit 1022, the second node PD, and the first power signal line LVGL / VGL, respectively, and is configured to write the second power signal of the first power signal line LVGL / VGL into the control end of the pull-up driving unit 1022 under the control of the voltage of the second node PD;

[0073] The pull-up driving unit 1022 is further configured to disconnect the driving signal line VH from the first node PU under the control of the second power signal.

[0074] In some embodiments, the control end of the second driving module 104 can be electrically connected to the second node PD, and the second driving module 104 is used to control the connection between the first power signal line LVGL / VGL and the control end of the pull-up driving unit 1022 in response to the voltage of the second node PD.

[0075] Specifically, in the display stage and the touch stage, for the shift register 10 that does not output, the voltage of the second node PD controls the second driving module 104, and turns on the connection between the first power signal line LVGL / VGL and the control end of the pull-up driving unit 1022, so that the second power signal is written into the control end of the pull-up driving unit 1022, and then the pull-up driving unit 1022 disconnects the connection between the driving signal line VH and the first node PU under the control of the second power signal. In the display stage and the touch stage, for the shift register 10 that outputs normally, the voltage of the second node PD controls the second driving module 104, disconnects the connection between the first power signal line LVGL / VGL and the control end of the pull-up driving unit 1022, so that the second power signal does not affect the state of the pull-up driving unit 1022.

[0076] In the embodiment of the present application, the shift register 10 further includes a second driving module 104, the control end of the pull-up driving unit 1022 is electrically connected to the second driving module 104, and the second driving module 104 is also electrically connected to the second node PD and the first power signal line LVGL / VGL. Since the second driving module 104 is configured to write the second power signal of the first power signal line LVGL / VGL into the control end of the pull-up driving unit 1022 under the control of the voltage of the second node PD, the pull-up driving unit 1022 is controlled by the second power signal. Since the pull-up driving unit 1022 is also configured to disconnect the connection between the drive signal line VH and the first node PU under the control of the second power signal, the drive signal cannot be written into the first node PU, and the drive signal does not affect the level state of the first node PU at this time.

[0077] Optionally, the driving control unit 1021 includes a first transistor Tt1; the pull-up driving unit 1022 includes a second transistor Tt2;

[0078] The control electrode of the first transistor Tt1 is electrically connected to the input signal line INPUT, the first electrode is electrically connected to the drive signal line VH, and the second electrode is electrically connected to the control electrode of the second transistor Tt2;

[0079] A first electrode of the second transistor Tt2 is electrically connected to the driving signal line VH, and a second electrode is electrically connected to the first node PU.

[0080] In some embodiments, the first driving module 102 is composed of a first transistor Tt1 and a second transistor Tt2. Specifically, the control electrode of the first transistor Tt1 is electrically connected to the input signal line INPUT, and can receive the input signal. The first electrode of the first transistor Tt1 is electrically connected to the drive signal line VH, and can receive the drive signal. The second electrode of the first transistor Tt1 is electrically connected to the control electrode of the second transistor Tt2. When the first transistor Tt1 is turned on under the control of the input signal, the drive signal is written into the control electrode of the second transistor Tt2. Among them, the control electrode of the second transistor Tt2 can be used as the control terminal of the pull-up driving unit 1022.

[0081] Specifically, the first electrode of the second transistor Tt2 is electrically connected to the driving signal line VH to receive the driving signal, and the second electrode of the second transistor Tt2 is electrically connected to the first node PU. When the second transistor Tt2 is turned on under the control of the driving signal, the driving signal is written into the first node PU.

[0082] Optionally, the second driving module 104 includes a third transistor Tt3;

[0083] The control electrode of the third transistor Tt3 is electrically connected to the second node PD, the first electrode is electrically connected to the control end of the pull-up driving unit 1022, and the second electrode is electrically connected to the first power signal line LVGL / VGL.

[0084] In some embodiments, the control electrode of the third transistor Tt3 is electrically connected to the second node PD, and can be turned on or off under the control of the voltage of the second node PD. The first electrode of the third transistor Tt3 is electrically connected to the control end of the pull-up driving unit 1022, and the second electrode is electrically connected to the first power signal line LVGL / VGL. Therefore, when the third transistor Tt3 is turned on under the control of the voltage of the second node PD, the second power signal of the first power signal line LVGL / VGL is written into the control end of the pull-up driving unit 1022Tt2.

[0085] In some embodiments, the first electrode of the third transistor Tt3 can be electrically connected to the control electrode of the second transistor Tt2 in the pull-up driving unit 1022, so that the third transistor Tt3 is used to control when the second transistor Tt2 is turned off. When the third transistor Tt3 is turned on under the control of the voltage of the second node PD, the second power signal is written into the control electrode of the second transistor Tt2, and the second transistor Tt2 can be turned off under the control of the second power signal, thereby disconnecting the connection between the drive signal line VH and the first node PU, so that the drive signal does not affect the level state of the first node PU.

[0086] Figure 5 3 is a structural diagram of a shift register 10 provided in an embodiment of the present application, such as Figure 5As shown, the input module 101 includes a transistor T1, the driving control unit 1021 includes a first transistor Tt1, the pull-up driving unit 1022 includes a second transistor Tt2, the second driving module 104104 includes a third transistor Tt3, and the output module 103 includes a transistor T3 and a capacitor C1. Transistors T1, T3, Tt1, Tt2 and Tt3 are N-type TFTs. Figure 5 In the shift register 10 shown, the first node PU is a pull-up node (PU), and the second node PD is a pull-down node (PD).

[0087] like Figure 5 As shown, the gate of the first transistor Tt1 is electrically connected to the input signal line INPUT and the drain of the transistor T1, the drain of the first transistor Tt1 is electrically connected to the drive signal line VH and the drain of the second transistor Tt2, and the source of the first transistor Tt1 is electrically connected to the gate of the second transistor Tt2 and the drain of the third transistor Tt3. The drain of the second transistor Tt2 is also electrically connected to the drive signal line VH, and the source of the second transistor Tt2 is electrically connected to the first node PU. The gate of the third transistor Tt3 is electrically connected to the second node PD, and the source of the third transistor Tt3 is electrically connected to the first power signal line LVGL / VGL.

[0088] like Figure 5 As shown, in the display stage and the touch stage, for the shift register 10 that does not output, the input signal controls the transistor T1 to turn off, and controls the first transistor Tt1 to turn off, so that the input signal and the drive signal cannot be written into the first node PU. In the display stage and the touch stage, for the shift register 10 that outputs normally, the input signal controls the transistor T1 to turn on, and controls the first transistor Tt1 to turn on, so that the input signal is written into the first node PU, and the drive signal is written into the control electrode of the second transistor Tt2.

[0089] Among them, when the driving signal is a high-level signal, the second transistor Tt2 is turned on, and when the driving signal is a low-level signal, the second transistor Tt2 is turned off. In this embodiment, in the touch stage, a driving signal with a high level is input to the driving signal line VH, and the high-level signal can control the second transistor Tt2 to turn on, and write a high-level signal to the first node PU, so that the level state of the first node PU remains unchanged, and the voltage of the first node PU can be maintained at a high level state.

[0090] like Figure 5As shown, in the display stage and the touch stage, for the shift register 10 that does not output, the voltage of the second node PD can be in a high level state, so that the third transistor Tt3 is turned on under the control of the high level voltage of the second node PD, and the first power signal line LVGL / VGL is connected to the gate of the second transistor Tt2, and the second power signal with a low level is written into the gate of the second transistor Tt2, so that the second transistor Tt2 is turned off. In this way, the drive signal line VH is disconnected from the first node PU, and the drive signal VH does not affect the level state of the first node PU. Among them, for example, Figure 5 As shown in the transistor T3, when the voltage of the first node PU is in a low level state, the transistor T3 is turned off, and the shift register 10 does not output a signal.

[0091] like Figure 5 As shown, when the voltage of the second node PD is in a low level state, the third transistor Tt3 is turned off, and the connection between the first power signal line LVGL / VGL and the gate of the second transistor Tt2 is disconnected, so that the second power signal does not affect the opening or closing of the second transistor Tt2. At this time, the second transistor Tt2 can be opened or closed under the control of the driving signal input by the driving signal line VH.

[0092] Figure 6 FIG. 4 is a structural diagram of a shift register 10 provided in an embodiment of the present application. Figure 5 The shift register 10 shown, Figure 6 The middle shift register 10 may further include a pull-up control module composed of transistors T9 and T5, a pull-down control module composed of transistors T8 and T6, a pull-down module composed of transistors T10 and T11, and a reset module composed of transistors T2, T7, T4 and T12. Figure 6 The transistors in are all N-type TFTs.

[0093] like Figure 6 As shown, the gate and drain of transistor T9 are respectively connected to the second power signal line VDD, and the source of transistor T9 is respectively connected to the drain of transistor T8 and the gate of transistor T5. The drain of transistor T5 is electrically connected to the second power signal line VDD, and the source of transistor T5 is electrically connected to the second node PD. Wherein, the second power signal of the second power signal line VDD is a high level signal, and transistor T9 is turned on, then transistor T5 is also turned on under the control of the second power signal, so that the second power signal is written into the second node PD.

[0094] like Figure 6As shown, the gate of transistor T8 and the gate of transistor T6 are both electrically connected to the first node PU, the source of transistor T8 and the source of transistor T6 are both electrically connected to the first power signal line LVGL / VGL, and the drain of transistor T6 is connected to the second node PD. When the voltage of the first node PU is in a high level state, transistors T8 and T6 are turned on, so that the first power signal, i.e., the low level signal, is written into the second node PD, so that the voltage of the second node PD becomes a low level state.

[0095] like Figure 6 As shown, for the shift register 10 with normal output, when the input signal turns on the transistor T1 and the first transistor Tt1, the input signal is written into the first node PU, and the drive signal is transmitted to the gate of the second transistor Tt2. If the drive signal is at a high level, the second transistor Tt2 is turned on, so that the drive signal is also written into the first node PU. At the same time, the high level voltage of the first node PU can turn on the transistor T8 and the transistor T6, thereby lowering the level state of the second node PD, so that the low level voltage of the second node PD can turn off the third transistor Tt3.

[0096] As for the shift register 10 without output, since the voltage of the first node PU is in a stable low level state, the voltage of the second node PD will be in a high level state under the control of the second power signal of the second power signal line VDD, so that the third transistor Tt3 is turned on, and the first power signal of the first power signal line LVGL / VGL is written into the second transistor Tt2, so that the second transistor Tt2 is turned off, so that the driving signal does not affect the level state of the first node PU.

[0097] like Figure 6 As shown, when the voltage of the second node PD is in a high level state, the transistor T10 is turned on so that the first power signal of the first power signal line LVGL / VGL pulls down the level state of the first node PU, and the transistor T11 is turned on so that the first power signal pulls down the source of the transistor T3. In addition, when the reset signal of the reset signal line TRST / RST is a high level signal, the transistor T7, the transistor T2, the transistor T4 and the transistor T12 are turned on so that the first power signal resets the first node PU and the source of the transistor T3.

[0098] The present application embodiment provides a driving method, such as Figure 7 As shown, the driving method for controlling the shift register 10 as in the above embodiment includes the following steps:

[0099] Step S1, in the touch control stage, an input signal is written to the input signal line INPUT, and a driving signal with a first level is written to the driving signal line VH, so that the first driving module 102 writes the driving signal with a first level into the first node PU under the control of the input signal and the driving signal with a first level.

[0100] In some embodiments, during the touch control phase of a frame time, for the shift register 10 with normal output, an input signal can be written to the input signal line INPUT, so that the input module 101 writes the input signal to the first node PU. In addition, a driving signal with a first level is written to the driving signal line VH, and the driving signal with the first level together with the input signal controls the first driving module 102 to write the driving signal with the first level to the first node PU.

[0101] For example, Figure 6 The shift register 10 shown can write a high-level signal to the input signal line INPUT, so that the transistor T1 and the first transistor Tt1 are turned on. A driving signal with a first level is written to the driving signal line VH, where the first level is a high level, so that the second transistor Tt2 is turned on, and the high-level driving signal is written to the first node PU. In this way, the first transistor Tt1 and the second transistor Tt2 can write a high-level signal to the first node PU under the control of the high-level input signal and the high-level driving signal, which can reduce Figure 6 The influence of the leakage current effect of the transistors T2, T7 and T10 in the shift register 10 shown on the level state of the first node PU can keep the level state of the first node PU unchanged, that is, the voltage of the first node PU remains at a high level.

[0102] In the touch control stage, for the shift register 10 that does not output, the driving signal line VH is disconnected from the first node PU, and the driving signal does not affect the level state of the first node PU. Figure 6 In the shift register 10 shown, the transistor T1 and the first transistor Tt1 in the non-output shift register 10 are both in a stable off state, and the second transistor Tt2 cannot be turned on, so the driving signal does not affect the level state of the first node PU. The voltage of the first node PU is in a stable low level state due to being reset.

[0103] In some embodiments, in the display stage and the touch stage, for the shift register 10 with normal output, the input signal is written into the first node PU so that the first node PU has a first initial level, and the first initial level is consistent with the level state of the input signal. In this embodiment, by writing a driving signal with a first level to the driving signal line VH in the touch stage, and then writing the driving signal with a first level to the first node PU through the first driving module 102, wherein the driving signal has the same phase as the input signal, so that the first level has the same phase as the first initial level, so that the first node PU is charged by the driving signal with the first level, so that the first node PU can maintain the level state unchanged. Among them, the first level is not less than the first initial level.

[0104] In some embodiments, in the display stage and the touch stage, for the non-output shift register 10, the first node PU is at a second initial level due to being reset, and the second initial level is opposite in phase to the first initial level. Figure 6 In the shift register 10 shown, the first node PU is in a stable low level state. This is only an example, and the embodiment of the present application does not limit this.

[0105] In the embodiment of the present application, during the touch stage, an input signal is written to the input signal line INPUT, and a driving signal with a first level is written to the driving signal line VH, so that the first driving module 102 writes the driving signal with a first level to the first node PU under the control of the input signal and the driving signal with a first level. In this way, the level state of the voltage of the first node PU can be consistent with the level state of the input signal, and the driving signal can keep the voltage of the first node PU at the level state after the input signal is written during the touch stage, which can avoid the problem of the transistor leakage in the shift register 10 causing the level state of the first node PU to decrease. Since the level state of the first node PU remains unchanged during the touch stage, the output module 103 is controlled by the voltage of the first node PU, and the clock signal is written to the output signal line OUTPUT with a stable waveform, avoiding the problem of abnormal output signal of the shift register 10, and reducing the difference in output waveforms of different shift registers 10, thereby improving the poor horizontal stripes of the display panel.

[0106] Optionally, the first driving module 102 includes a driving control unit 1021 and a pull-up driving unit 1022. Before step S1, the driving method further includes:

[0107] Step S2, in the display stage, an input signal is written to the input signal line INPUT, and a driving signal with a second level is written to the driving signal line VH, and before the touch stage, the driving signal with a first level is written to the driving signal line VH, and the clock signal is written to the clock signal line CLK, so that the driving control unit 1021 writes the driving signal to the control end of the pull-up driving unit 1022 under the control of the input signal, so that the pull-up driving unit 1022 disconnects the driving signal line VH and the first node PU under the control of the driving signal with the second level, so that the pull-up driving unit 1022 writes the driving signal with the first level to the first node PU under the control of the driving signal with the first level.

[0108] The driving method provided in the embodiment of the present application can be used to control the shift register 10 in the LHB mode that alternates between the display phase and the touch phase. In the display phase of one frame of picture time, for the shift register 10 with normal output, an input signal can be written to the input signal line INPUT, so that the input module 101 writes the input signal to the first node PU, and the driving control unit 1021 writes the driving signal to the control end of the pull-up driving unit 1022. For example, Figure 6 The shift register 10 shown can write a high level signal to the input signal line INPUT, so that the transistor T1 and the first transistor Tt1 are turned on, so that the first transistor Tt1 can connect the drive signal line VH with the second transistor Tt2, and then the drive signal is written into the gate of the second transistor Tt2.

[0109] In some embodiments, in the display stage, writing a driving signal with a second level to the driving signal line VH can cause the pull-up driving unit 1022 to disconnect the driving signal line VH from the first node PU, and writing a driving signal with a first level to the driving signal line VH can cause the pull-up driving unit 1022 to write the driving signal with the first level to the first node PU. Figure 6 The shift register 10 shown in the figure writes a driving signal having a first level to the driving signal line VH, wherein the first level is a high level, and the second transistor Tt2 can be turned on, so that the high-level driving signal is written into the first node PU. And writing a driving signal having a second level to the driving signal line VH, wherein the second level is a low level, the second transistor Tt2 can be turned off, so that the low-level driving signal cannot be written into the first node PU, and the level state of the first node PU is not affected.

[0110] In some embodiments, the display stage and the touch stage are performed alternately. In the display stage, a driving signal with a second level can be written to the driving signal line VH first, so that the driving signal with the second level will not affect the level state of the first node PU. Then, before the touch stage that takes over the current display stage, it can be switched to writing a driving signal with a first level to the driving signal line, so that it can be ensured that the driving signal with the first level is written to the first node PU at the beginning of the touch stage, thereby keeping the level state of the first node PU unchanged faster and better.

[0111] At the same time, writing a clock signal to the clock signal line CLK allows the output module 103 to write the clock signal to the output signal line OUTPUT under the control of the stable voltage of the first node PU, thereby avoiding abnormal output signals of the shift register 10 and improving the horizontal stripes of the display panel.

[0112] Optionally, before the touch control stage, switching to write a driving signal with a first level to the driving signal line VH includes:

[0113] The drive signal having the first level is switched to be written to the drive signal line VH in advance by a first time duration; wherein the first time duration is greater than or equal to the cycle duration of the clock signal and less than the total duration of the display phase.

[0114] In some embodiments, the display phase can be advanced by at least one clock cycle to switch to writing a drive signal having a first level to the drive signal line VH. The first duration represents the time of switching the signal in advance before the touch phase. The first duration can be at least one cycle duration of the clock cycle, that is, the first duration is greater than or equal to the cycle duration of the clock signal.

[0115] In addition, since the signal switching is performed during the display phase, the first duration can be less than the total duration of the display phase. Since one frame of picture time can be divided into multiple display phases and touch phases, and the touch phase is set between two adjacent display phases, and the display phase and the touch phase are performed alternately, the total duration of the display phase can be determined according to one frame of picture time and the division method of the display phase and the touch phase in actual applications, and the embodiments of the present application do not limit this.

[0116] Optionally, the level value of the first level is 1.3 to 1.4 times the high level value of the clock signal.

[0117] In some embodiments, Figure 6The shift register 10 shown, in the display stage, first writes a driving signal with a second level to the driving signal line VH, and the second level is a low level, which can turn off the second transistor Tt2, so that the low-level driving signal cannot be written into the first node PU, and does not affect the level state of the first node PU. Among them, the level value of the low-level driving signal can be equal to the level value of the first power signal of the first power signal line LVGL / VGL, or equal to the low-level value of the clock signal. For example, if the low level of the clock signal is -14V, then the low-level driving signal is -14V.

[0118] like Figure 6 The shift register 10 shown can switch to write a driving signal with a first level to the driving signal line VH in the display stage about 8H in advance of the touch stage. The first level is a high level, and the second transistor Tt2 can be turned on so that the high-level driving signal is written to the first node PU. The level value of the high-level driving signal can be 1.3 to 1.4 times the high-level value of the clock signal. For example, if the high level of the clock signal is 18V, the high-level driving signal is 23.4 to 25.2V.

[0119] In the embodiment of the present application, the drive signal having the first level is written to the drive signal line VH by switching in advance for a first time duration, wherein the first time duration is greater than or equal to the cycle duration of the clock signal and less than the total duration of the display phase. In this way, it can be ensured that the drive signal having the first level is written to the first node PU when the touch control phase that replaces the current display phase begins, thereby keeping the level state of the first node unchanged faster and better.

[0120] Optionally, the first driving module 102 includes a driving control unit 1021 and a pull-up driving unit 1022. Before step S1, the driving method further includes:

[0121] Step S3, display stage, writes an input signal to the input signal line INPUT, writes a driving signal with a first level to the driving signal line VH, and writes a clock signal to the clock signal line CLK, so that the driving control unit 1021 writes the driving signal with the first level to the control end of the pull-up driving unit 1022 under the control of the input signal, so that the pull-up driving unit 1022 writes the driving signal with the first level to the first node PU under the control of the driving signal with the first level.

[0122] In some embodiments, in the display stage, for the shift register 10 with normal output, a driving signal with a first level is directly written to the driving signal line VH, so that the pull-up driving unit 1022 can write the driving signal with a first level to the first node PU. Figure 6The shift register 10 shown writes a driving signal having a first level to the driving signal line VH, wherein the first level is a high level, and the second transistor Tt2 can be turned on, so that the high-level driving signal is written to the first node PU. At the same time, a clock signal is written to the clock signal line CLK, so that the output module 103 can write the clock signal to the output signal line OUTPUT under the control of the stable voltage of the first node PU.

[0123] Optionally, a level value of the first level is equal to a high level value of the clock signal.

[0124] In some embodiments, Figure 6 The shift register 10 shown can directly write a driving signal with a first level to the driving signal line VH in the display stage, and the first level is a high level, that is, the driving signal maintains a high level state. The high-level driving signal can turn on the second transistor Tt2, so that the high-level driving signal is written to the first node PU. Among them, the level value of the high-level driving signal can be equal to the level value of the second power signal of the second power signal line VDD (VGH), or equal to the high-level value of the clock signal. For example, if the high level of the clock signal is 18V, the high-level driving signal is 18V.

[0125] Thus, the shift register 10 normally outputs signals, for example, Figure 6 In the shift register 10 shown, after the row output is completed, the voltage of the first node PU is reset to a low level state, and the voltage of the second node PD is in a high level state under the control of the second power signal of the second power signal line VDD, so that the third transistor Tt3 is turned on, and the first power signal of the first power signal line LVGL / VGL is written into the second transistor Tt2, so that the second transistor Tt2 is turned off.

[0126] Figure 8 is a schematic diagram of the level state of a pull-up node in a shift register 10 provided in an embodiment of the present application, such as Figure 8 As shown, L1 represents the level state of the first node PU, i.e., the pull-up node, in the shift register 10 of this embodiment during the touch control stage, and L2 represents the level state of the pull-up node in the shift register in the related art. By comparing L1 with L2, it can be clearly seen that the first node PU in the shift register 10 of this embodiment can maintain the level state unchanged during the touch control stage, thereby avoiding the problem of level reduction due to transistor leakage. Since the first node PU can maintain a stable level state, the waveform abnormality of the output signal of the shift register 10 can be reduced, and the difference in output signals between different shift registers 10 can be reduced, thereby improving the horizontal stripe defect of the display panel.

[0127] An embodiment of the present application provides a gate driving circuit, which includes a plurality of cascaded shift registers 10 .

[0128] In some embodiments, the shift register 10 may be a GOA circuit. The gate drive circuit of this embodiment includes a plurality of GOA circuits, and the plurality of GOA circuits are cascaded with each other. Each GOA circuit corresponds to a pixel row on the display panel, and the output signal of each GOA circuit may be sent as a gate drive signal to the pixel circuit of the corresponding row through the output signal line OUTPUT.

[0129] Fig. 9 is a schematic diagram of a gate drive circuit provided in an embodiment of the present application, such as Fig. 9 The gate drive circuit shown includes cascaded GOA1 to GOA8, each GOA circuit is electrically connected to the input signal line INPUT, the output signal line OUTPUT, the reset signal line RST / TRST, the first power signal line VSS, the second power signal line VDDe / VDDo and the clock signal line CLK. Each GOA circuit can also be electrically connected to the drive signal line VH to receive the drive signal. In addition, each of the 8 GOAs can also receive a set of clock signals, such as Fig. 9 As shown, GOA1-GOA8 are connected to clock signal lines CLK1-CLK8 respectively.

[0130] like Fig. 9 As shown, in the gate drive circuit, GOA1 and GOA2 can receive the frame start signal STV1, and GOA3 and GOA4 can receive the frame start signal STV2, indicating that the current frame scan is turned on. GOA1-GOA4 can be regarded as a group of shift registers 10, and GOA5-GOA8 can be regarded as another group of shift registers 10. The output signals G1-G4 of GOA1-GOA4 are respectively used as input signals of GOA5-GOA8, and the output signals G5-G8 of GOA5-GOA8 can be used as reset signals of GOA1-GOA4 and sent to the reset terminals Reset of GOA1-GOA4.

[0131] The gate drive circuit can also cascade more groups of shift registers 10, and each group of shift registers 10 can include 4 GOA circuits. Fig. 9As shown, the output signals G5-G8 of GOA5-GOA8 can also be used as input signals of the next group GOA9-GOA12, and GOA5-GOA8 can send the output signals G5-G8 to the input signal lines INPUT9-INPUT12 respectively, and the output signals of the next group GOA9-GOA12 can also be used as reset signals of GOA5-GOA8, that is, GOA9-GOA12 can send the output signals G9-G12 to the reset terminals Reset of GOA5-GOA8 through the output signal lines OUTPUT9-OUTPUT12 respectively. When the gate drive circuit includes more cascaded shift registers 10, the same can be applied, which will not be described here.

[0132] An embodiment of the present application provides a display device, and the display device includes the above-mentioned gate driving circuit.

[0133] In some embodiments, the display device includes a display panel, a gate drive circuit, and a touch and display integrated control chip. Among them, the display panel can be an embedded touch panel, such as an Incell Touch display panel. The gate drive circuit can include a plurality of cascaded shift registers 10. The touch and display integrated control chip can be a TDDI chip. This is only an example, and the embodiments of the present application are not limited to this.

[0134] Fig.10 is one of the timing diagrams of a display device provided in an embodiment of the present application, such as Fig.10 As shown, the first stage is as follows Fig.10 The display stage shown. The driving signal of the driving signal line VH is first low level, and this low level can be equal to the low level of the VGL voltage, or can be equal to the low level of the clock signal of the clock signal line CLK. Before the next touch control stage, the driving signal can be converted to a high level state about 8H in advance. For the shift register 10 that does not output, the second node PD is in a high level state, and the gate of the third transistor Tt3 is turned on under the voltage control of the second node PD, so that the gate of the second transistor Tt2 is connected to the first power signal line LVGL / VGL. Since the gate of the second transistor Tt2 receives the low-level second power signal, the second transistor Tt2 is turned off, and the driving signal of the driving signal line VH does not affect the level state of the first node PU. For the shift register 10 with normal output, although the input signal of the input signal line INPUT turns on the first transistor Tt1, the introduced driving signal is low level, so that the gate of the second transistor Tt2 receives a low level and remains turned off, which does not affect the level state of the first node PU.

[0135] The second stage is Fig.10Touch stage shown. For the shift register 10 without output, such as the first stage, the second transistor Tt2 remains off, the driving signal does not affect the level at the PU point, and the first node PU point is not affected by the driving signal and is in a stable low level state. For the shift register 10 with normal output, since the second node PD is pulled down to a low level state by the first power supply signal when transistors T8 and T6 are turned on, at this time, the gate of the third transistor Tt3 is turned off under the voltage control of the second node PD, and the input signal turns on the first transistor Tt1, and introduces a high level driving signal to the gate of the second transistor Tt2, so that the second transistor Tt2 is turned on. Under the action of the high level driving signal, the first node PU can remain in a stable high level state for a long time. Figure 8 The level state of the pull-up node is shown, so that the waveform of the output signal of the shift register 10 is stable, and the difference in the output signals of different shift registers 10 can be reduced, thereby improving the horizontal stripe defects of the display panel. Next, the first stage and the second stage can be repeated, that is, the LHB mode is adopted, and the display stage and the touch stage are alternately performed within one frame time.

[0136] Fig.11 This is the second timing diagram of a display device provided in an embodiment of the present application. Fig.11 As shown, the first stage is as follows Fig.11 The display phase shown. The driving signal of the driving signal line VH maintains a high level, which can be equal to the high level of the VGH voltage, or can be equal to the high level of the clock signal of the clock signal line CLK. For the shift register 10 without output, the second node PD is in a high level state, and the gate of the third transistor Tt3 is turned on under the voltage control of the second node PD, so that the gate of the second transistor Tt2 is connected to the first power signal line LVGL / VGL. Since the gate of the second transistor Tt2 receives the low-level second power signal, the second transistor Tt2 is turned off, and the driving signal of the driving signal line VH does not affect the level state of the first node PU. For the shift register 10 with normal output, the input signal of the input signal line INPUT turns on the first transistor Tt1, and introduces a high-level driving signal, so that the gate of the second transistor Tt2 receives a low-high level and turns on, and the high-level driving signal is written to the first node PU. The shift register 10 outputs signals normally. After the output of this row is completed, the voltage of the first node PU is reset to a low-level state, and the voltage of the second node PD will be in a high-level state under the control of the second power signal of the second power signal line VDD, so that the third transistor Tt3 is turned on, and the first power signal of the first power signal line LVGL / VGL is written into the second transistor Tt2, so that the second transistor Tt2 is turned off.

[0137] The second stage is Fig.11In the touch stage shown, the drive signal maintains a high level state. For the shift register 10 without output, such as in the first stage, the second transistor Tt2 remains off, the drive signal does not affect the level at the PU point, and the first node PU point is not affected by the drive signal and is in a stable low level state. For the shift register 10 with normal output, since the second node PD is pulled down to a low level state by the first power signal when transistors T8 and T6 are turned on, at this time, the gate of the third transistor Tt3 is turned off under the voltage control of the second node PD, and the input signal turns on the first transistor Tt1, and introduces a high level drive signal to the gate of the second transistor Tt2, so that the second transistor Tt2 is turned on. Under the action of the high level drive signal, the first node PU can remain in a stable high level state for a long time. Figure 8 The level state of the pull-up node in the middle is shown, so that the waveform of the output signal of the shift register 10 is stable, and the difference in the output signals of different shift registers 10 can be reduced, thereby improving the horizontal stripe defects of the display panel. Next, the first stage and the second stage can be repeated, that is, the LHB mode is adopted, and the display stage and the touch stage are alternately performed within one frame time. Among them, Fig.10 and Fig.11 L0 in the figure represents a data signal of a black screen. The Data signal and the V-com signal are only used in the pixel area of ​​the display panel and are not used in the shift register 10 in the gate driving circuit.

[0138] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0139] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0140] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0141] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0142] The above is a detailed introduction to a shift register and its driving method, a gate driving circuit, and a display device provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A shift register, characterized in that: The shift register comprises: an input module, a first driving module, and an output module; The first driving module is electrically connected to the driving signal line, the input signal line, and the first node respectively, and is configured to write the driving signal into the first node under the control of the input signal of the input signal line and the driving signal of the driving signal line in the touch control stage; The input module is electrically connected to the input signal line and the first node respectively, and is configured to write the input signal into the first node under the control of the input signal; The output module is electrically connected to the clock signal line, the first node and the output signal line respectively, and is configured to write the clock signal of the clock signal line into the output signal line under the control of the voltage of the first node.

2. The shift register according to claim 1, characterized in that: The first driving module includes a driving control unit and a pull-up driving unit; The driving control unit is electrically connected to the driving signal line, the input signal line, and the control end of the pull-up driving unit, respectively, and is configured to write the driving signal into the control end of the pull-up driving unit under the control of the input signal; The pull-up driving unit is also electrically connected to the driving signal line and the first node, respectively, and is configured to write the driving signal into the first node under the control of the driving signal.

3. The shift register according to claim 2, characterized in that: The driving control unit includes a first transistor; the pull-up driving unit includes a second transistor; The control electrode of the first transistor is electrically connected to the input signal line, the first electrode is electrically connected to the drive signal line, and the second electrode is electrically connected to the control electrode of the second transistor; A first electrode of the second transistor is electrically connected to the driving signal line, and a second electrode of the second transistor is electrically connected to the first node.

4. The shift register according to claim 2 or 3, characterized in that: The shift register further includes a second driving module; The second driving module is electrically connected to the control end, the second node, and the first power signal line of the pull-up driving unit respectively, and is configured to write the second power signal of the first power signal line into the control end of the pull-up driving unit under the control of the voltage of the second node; The pull-up driving unit is further configured to disconnect the driving signal line from the first node under the control of the second power signal.

5. The shift register according to claim 4, characterized in that: The second driving module includes a third transistor; The control electrode of the third transistor is electrically connected to the second node, the first electrode is electrically connected to the control end of the pull-up driving unit, and the second electrode is electrically connected to the first power signal line.

6. A gate drive circuit, characterized in that: The gate driving circuit comprises a plurality of cascaded shift registers as claimed in any one of claims 1 to 5.

7. A display device, characterized in that: The display device comprises the gate driving circuit as claimed in claim 6.

8. A driving method, characterized in that: Used to control the shift register as claimed in any one of claims 1 to 5, the driving method comprising: In the touch control stage, an input signal is written to the input signal line, and a driving signal with a first level is written to the driving signal line, so that the first driving module writes the driving signal with the first level into the first node under the control of the input signal and the driving signal with the first level.

9. The driving method according to claim 8, characterized in that: The first driving module includes a driving control unit and a pull-up driving unit, and the driving method further includes: In the display stage, the input signal is written to the input signal line, and the drive signal with the second level is written to the drive signal line, and before the touch stage, the drive signal with the first level is written to the drive signal line, and the clock signal is written to the clock signal line, so that the drive control unit writes the drive signal to the control end of the pull-up drive unit under the control of the input signal, so that the pull-up drive unit disconnects the drive signal line and the first node under the control of the drive signal with the second level, so that the pull-up drive unit writes the drive signal with the first level to the first node under the control of the drive signal with the first level.

10. The driving method according to claim 9, characterized in that: The step of switching to write the driving signal having the first level to the driving signal line before the touch control stage includes: The drive signal having the first level is switched to be written to the drive signal line in advance by a first time duration; wherein the first time duration is greater than or equal to a cycle duration of the clock signal and less than a total duration of the display phase.

11. The driving method according to claim 9, characterized in that: The level value of the first level is 1.3 to 1.4 times the high level value of the clock signal.

12. The driving method according to claim 8, characterized in that: The first driving module includes a driving control unit and a pull-up driving unit, and the driving method further includes: In the display stage, the input signal is written to the input signal line, the drive signal with the first level is written to the drive signal line, and the clock signal is written to the clock signal line, so that the drive control unit writes the drive signal with the first level to the control end of the pull-up drive unit under the control of the input signal, so that the pull-up drive unit writes the drive signal with the first level to the first node under the control of the drive signal with the first level.

13. The driving method according to claim 12, characterized in that: The level value of the first level is equal to the high level value of the clock signal.

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