Display device

Abstract

The application provides a display device, comprising a display panel and a driving circuit. The driving circuit comprises a current value calculation circuit, electrically connected with a signal input end; a gain calculation circuit, electrically connected with the current value calculation circuit; a difference calculation circuit, electrically connected with the gain calculation circuit; a gain delay circuit, electrically connected with the difference calculation circuit; a gain limit calculation circuit, electrically connected with the current value calculation circuit; a judgment circuit, electrically connected with the gain delay circuit and the gain limit calculation circuit; and a multiplication operation circuit, used for multiplying the input first gray scale data and the first gain value output by the judgment circuit, and outputting second gray scale data. The application calculates the difference value of the gain value through the difference calculation circuit, performs delay calculation processing on the difference value through the gain delay circuit, limits the change range of the gain value through the gain limit calculation circuit, and adopts the feedback signal control mode, thereby effectively improving the flicker phenomenon of the display picture.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] In order to reduce the power consumption of the display panel, a brightness adjustment circuit is usually used to dynamically adjust the brightness of the display panel according to the content of the display picture.

[0003] like Figure 1 As shown, a conventional brightness adjustment circuit typically includes a current calculation module, a gain calculation module, and an arithmetic module. The current calculation module receives an input signal (grayscale data) and calculates the in-plane current value. The gain calculation module calculates the gain value based on the in-plane current value. The arithmetic module multiplies the input signal by the gain value to produce an output signal. In this technical solution, due to the large fluctuations in the gain value, the current signal output by the arithmetic module also fluctuates greatly, causing flicker on the display panel.

[0004] like Figures 2 to 4 As shown, the gain value varies significantly between different display frames. Since the output signal is the product of the input signal and the gain value, drastic changes in the gain value will lead to drastic changes in the output signal, causing significant fluctuations in the brightness of the display panel between different frames. This brightness fluctuation manifests as flickering on the display screen, seriously affecting the display quality of the display panel.

[0005] In addition, the simple correspondence between the gain value and the in-plane current value in the traditional solution may lead to excessive output current in certain display scenarios, which is not conducive to ensuring the stable operation and service life of the display panel.

[0006] Therefore, there is an urgent need to provide a new display panel driving solution to improve the display effect. Summary of the Invention

[0007] The purpose of this application is to provide a display device to solve the technical problem of display screen flickering in traditional display devices.

[0008] Embodiments of the present application provide a display device, comprising a display panel and a driving circuit, wherein the driving circuit comprises: a current value calculation circuit electrically connected with a signal input end of the driving circuit; a gain calculation circuit electrically connected with the current value calculation circuit; a difference calculation circuit electrically connected with the gain calculation circuit; a gain delay circuit electrically connected with the difference calculation circuit; a gain limit calculation circuit electrically connected with the current value calculation circuit; a judging circuit electrically connected with the gain delay circuit and the gain limit calculation circuit; and a multiplication operation circuit for performing multiplication operation on first gray scale data input by the signal input end and first gain value output by the judging circuit, and outputting second gray scale data.

[0009] In the display device, the current value calculation circuit is configured to receive the first gray scale data and calculate a current value.

[0010] In the display device, the gain calculation circuit is configured to calculate a second gain value according to the current value.

[0011] In the display device, the difference calculation circuit is configured to receive the second gain value and the first gain value output by the judging circuit, and calculate a difference value between the second gain value and the first gain value.

[0012] In the display device, the gain delay circuit is configured to multiply the difference value output by the difference calculation circuit by a preset coefficient to obtain a multiplication operation result, add the multiplication operation result and the first gain value to obtain an addition operation result, and output the addition operation result to the judging circuit.

[0013] In the display device, the preset coefficient ranges from 0.01 to 1.

[0014] In the display device, the gain limit calculation circuit is configured to calculate a third gain value according to the current value.

[0015] In the display device, when the current value is less than or equal to a first preset current value, the third gain value is a first preset gain value; and when the current value is greater than the first preset current value, the third gain value is nonlinearly reduced from the first preset gain value to a second preset gain value.

[0016] In the display device, the first preset gain value ranges from 0.9 to 1, and the second preset gain value ranges from 0.2 to 0.6.

[0017] In the display device, the judging circuit is configured to receive a fourth gain value output by the gain delay circuit and a third gain value output by the gain limit calculation circuit, and select the smaller one of the fourth gain value and the third gain value as the first gain value.

[0018] The display device provided in the present application can effectively improve the flicker phenomenon of the display image by setting the difference calculation circuit, the gain delay circuit, the gain limit calculation circuit and the judging circuit in the driving circuit, and using the feedback signal control mode. Specifically, the difference calculation circuit receives the second gain value output by the gain calculation circuit and the first gain value output by the judging circuit, and calculates the difference between the two values. The gain delay circuit multiplies the difference value by a preset coefficient and adds the first gain value. In this way, the change of the gain value is more gentle. At the same time, the gain limit calculation circuit calculates the third gain value according to the current value, limits the change range of the gain value, and the judging circuit selects the smaller one of the fourth gain value output by the gain delay circuit and the third gain value output by the gain limit calculation circuit as the first gain value output. This selection mode ensures that the output gain value will not exceed the reasonable range.

[0019] In the above technical solution, the difference calculation circuit calculates the difference value of the gain value, and the gain delay circuit performs delay calculation processing on the difference value, so as to slow down the change speed of the gain value. The gain limit calculation circuit calculates the third gain value, and the judging circuit selects the smaller gain value output, so as to prevent the gain value from exceeding the reasonable range. The first gain value output by the judging circuit is fed back to the difference calculation circuit, so as to realize the dynamic adjustment of the gain value. The above technical solution not only ensures the smooth transition of the display image brightness and avoids the flicker phenomenon of the display image, but also avoids the adverse effects of the too large output current on the display panel, thereby effectively improving the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic diagram of a brightness adjustment circuit in a conventional display device.

[0021] Figure 2 is Figure 1 is a waveform diagram of the signals of the brightness adjustment circuit shown in FIG. 4.

[0022] Figure 3 is a schematic diagram of a display device including the brightness adjustment circuit shown in FIG. 4. Figure 1 is a schematic diagram of the flicker phenomenon of the display device including the brightness adjustment circuit shown in FIG. 4.

[0023] Figure 4 is a schematic diagram of a display device including the brightness adjustment circuit shown in FIG. 5. Figure 1 is a schematic diagram of the flicker phenomenon of the display device including the brightness adjustment circuit shown in FIG. 5.

[0024] Figure 5 Schematic diagram of an embodiment of a display device provided in the present application.

[0025] Figure 6 is a schematic diagram of a driving circuit in an embodiment of a display device provided in this application.

[0026] Figure 7 yes Figure 6 The waveform diagram of the signal of the driving circuit is shown.

[0027] Figure 8 yes Figure 6 Schematic diagram of the differential calculation circuit and gain delay circuit in the driving circuit shown.

[0028] Figure 9 yes Figure 6 Schematic diagram of a curve of the second gain value and a curve of the third gain value of the driving circuit shown.

[0029] Figure 10 Schematic diagram of the driving circuit in comparative example 1 of the display device provided in this application.

[0030] Figure 11 yes Figure 10 The waveform diagram of the signal of the display device is shown.

[0031] Figure 12 yes Figure 11 Schematic diagram of the overcurrent phenomenon shown.

[0032] Figure 13 Schematic diagram of the driving circuit in comparative example 2 of the display device provided in this application.

[0033] Figure 14 yes Figure 13 The waveform diagram of the signal of the display device is shown. DETAILED DESCRIPTION

[0034] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0035] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0036] The embodiments of the present application may be combined with each other.

[0037] like Figure 5As shown, the display device provided in the embodiments of the present application includes a display panel, a timing controller, a source driver circuit, and a power management chip (the power management chip and the timing controller can be integrated into the same chip). The display panel can be, for example, an OLED display panel, a Mini-LED display panel, or a Micro-LED display panel. The embodiments of the present application are described using an OLED display panel as an example.

[0038] The display panel includes a display area and a non-display area. The display area is provided with m×n pixel units PX arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of scan lines SCAN, a plurality of data lines DATA and a gate drive circuit. The plurality of scan lines SCAN extend along a first direction and are arranged along a second direction, and the plurality of data lines DATA extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit is provided in the non-display area and is electrically connected to the plurality of scan lines SCAN. The source drive circuit is electrically connected to the plurality of data lines DATA through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit, respectively.

[0039] The display panel includes an organic light-emitting diode array substrate and an encapsulation layer. The organic light-emitting diode array substrate includes a base substrate, a buffer layer disposed on the base substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines SCAN, a gate electrode, etc. The second metal layer includes data lines DATA, a source electrode, a drain electrode, etc. The encapsulation layer is sealed and connected to the organic light-emitting diode array substrate to prevent moisture and oxygen from invading the organic light-emitting layer.

[0040] Each pixel unit PX includes a pixel driving circuit and an organic light emitting diode OLED (light emitting device). The pixel driving circuit includes at least two thin film transistors and a storage capacitor. One of the thin film transistors serves as a switching transistor, with its gate electrode electrically connected to a corresponding scan line and its source electrode electrically connected to a corresponding data line. The other thin film transistor serves as a driving transistor, with its gate electrode electrically connected to the drain electrode of the switching transistor, its source electrode electrically connected to a first power voltage line, and its drain electrode electrically connected to the anode electrode of the organic light emitting diode OLED. One end of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and the other end is electrically connected to the source electrode or the drain electrode of the driving transistor. The cathode electrode of the organic light emitting diode OLED is electrically connected to a second power voltage line.

[0041] The gate driving circuit includes n-stage gate driving units connected in cascade, each stage of the gate driving units being electrically connected to a scan line. The gate driving units sequentially output scan signals under the control of the timing controller, to scan the pixel units PX of each row of the display area in turn. The source driving circuit generates and outputs data signals according to image data under the control of the timing controller. The timing controller is configured to receive and process externally input image data and timing signals, to generate control signals, and to transmit the image data to the source driving circuit. The power management chip PMIC is configured to provide operating voltages for various parts of the display device, including providing the second power voltage VSS for the cathode electrode of the organic light emitting diode OLED, providing the first power voltage VDD for the first power voltage line, and providing the gate driving voltage VGH / VGL for the gate driving circuit, etc.

[0042] Referring to Figure 6 The driving circuit of the display device provided by the embodiments of the present application includes a current conversion circuit 501, a current value calculation circuit 502, a gain calculation circuit 503, a difference calculation circuit 504, a gain delay circuit 505, a gain limit calculation circuit 507, a judgment circuit 506, and a multiplication operation circuit 508. The current conversion circuit 501 is electrically connected to a signal input end, the current value calculation circuit 502 is electrically connected to the current conversion circuit 501, the gain calculation circuit 503 is electrically connected to the current value calculation circuit 502, the difference calculation circuit 504 is electrically connected to the gain calculation circuit 503, the gain delay circuit 505 is electrically connected to the difference calculation circuit 504, the gain limit calculation circuit 507 is electrically connected to the current value calculation circuit 502, the judgment circuit 506 is electrically connected to the gain delay circuit 505 and the gain limit calculation circuit 507.

[0043] In the embodiment of the present application, the current value calculation circuit 502 is configured to receive the first gray scale data (first current signal) and calculate a current value. The gain calculation circuit 503 is configured to calculate a second gain value according to the current value. The difference calculation circuit 504 is configured to receive the second gain value and the first gain value output by the judgment circuit 506, and calculate a difference value between the second gain value and the first gain value. The gain delay circuit 505 is configured to multiply the difference value output by the difference calculation circuit 504 by a preset coefficient to obtain a multiplication result, add the multiplication result to the first gain value to obtain an addition result, and then output the addition result as a fourth gain value to the judgment circuit 506. The preset coefficient has a value range of 0.01 to 1. The gain limit calculation circuit 507 is configured to calculate a third gain value according to the current value. Specifically, when the current value is less than or equal to a first preset current value C1, the third gain value is a first preset gain value; when the current value is greater than the first preset current value C1, the third gain value is nonlinearly reduced from the first preset gain value to a second preset gain value. The first preset gain value is 1, and the second preset gain value is 0.4. The judgment circuit 506 is configured to receive the fourth gain value output by the gain delay circuit 505 and the third gain value output by the gain limit calculation circuit 507, and select the smaller one of the fourth gain value and the third gain value as the first gain value. The multiplication operation circuit 508 is configured to multiply the first gray scale data and the first gain value output by the judgment circuit 506, and output second gray scale data (second current signal).

[0044] Referring to Figure 8 , the gain delay circuit 505 includes a multiplier 5051 and an adder 5052. The first input end of the multiplier 5051 receives a difference value signal from the difference calculation circuit 504, and the second input end receives a preset coefficient. The preset coefficient is used to control the change rate of the gain value. The multiplier 5051 multiplies the difference value signal by the preset coefficient to obtain a multiplication result. This multiplication process realizes the scaling of the difference value signal, and the change amplitude of the gain value can be controlled by adjusting the size of the preset coefficient. The first input end of the adder 5052 receives an output signal of the multiplier 5051, and the second input end receives the first gain value. The adder 5052 adds the two input signals to obtain an addition result, which is output as the fourth gain value. The combination of the multiplier 5051 and the adder 5052 realizes the adjustment of the gain value, so that the change of the gain value is more gentle. The value range of the preset coefficient is 0.01 to 1. A smaller preset coefficient will make the change of the gain value more slowly, and a larger preset coefficient will speed up the change rate of the gain value.

[0045] Referring to Figure 9 , Figure 9 The size relationship between the second gain value output by the gain calculation circuit 503 and the third gain value output by the gain limit calculation circuit 507 is shown.Figure 9 The abscissa represents the current value, and the ordinate represents the gain value. When the current value is less than or equal to the first preset current value C1, the second gain value and the third gain value remain the first preset gain value 1; when the current value is greater than the first preset current value C1 and less than the second preset current value C2, the second gain value is non-linearly reduced with the increase of the current value, and the change curve presents a smooth transition characteristic, and the third gain value remains the first preset gain value 1; when the current value is greater than or equal to the second preset current value C2 and less than the third preset current value C3, the second gain value and the third gain value are non-linearly reduced with the increase of the current value, and the change curve presents a smooth transition characteristic, and when the current value is equal to the third preset current value C3, the second gain value and the third gain value are reduced to the second preset gain value 0.4. When the current value is greater than the first preset current value C1, the curve of the third gain value is above the curve of the second gain value, and the change range of the third gain value is smaller than the change range of the second gain value.

[0046] The technical scheme of the present application realizes different gain control effects in different current value intervals: a higher gain value is maintained in a low current interval to ensure display brightness, and the gain value is non-linearly reduced in a high current interval to prevent excessive current. The technical scheme of the present application not only ensures the stability of the display picture and avoids serious flickering, but also effectively reduces the power consumption of the display panel.

[0047]

[0048] Table 1

[0049] Referring to Table 1, Table 1 shows the output value change of each circuit module of the display device provided by the embodiment of the present application during 11 consecutive frames. The first row in the table is the frame number, from 0 to 10, a total of 11 frames; the second row is the second gain value output by the gain calculation circuit 503; the third row is the third gain value output by the gain limiting calculation circuit 507; the fourth row is the fourth gain value output by the gain delay circuit 505; and the fifth row is the first gain value output by the judgment circuit 506.

[0050] Combined with Figure 9 analysis, in the first frame, the corresponding current value is the fourth preset current value C4, which is between the first preset current value C1 and the second preset current value C2. At this time, the second gain value output by the gain calculation circuit 503 is 0.8, the third gain value output by the gain limiting calculation circuit 507 remains 1, the fourth gain value 0.9 is output by the gain delay circuit 505 by calculating the gain values of the previous frame and the current frame, and the judgment circuit 506 selects the smaller value 0.9 as the first gain value output by comparing the third gain value and the fourth gain value.

[0051] In the fifth frame, the corresponding current value is the fifth preset current value C5, which is between the second preset current value C2 and the third preset current value C3. At this time, the second gain value output by the gain calculation circuit 503 is reduced to 0.5, the third gain value output by the gain limit calculation circuit 507 is reduced to 0.6, the fourth gain value output by the gain delay circuit 505 is 0.65625, and the judgment circuit 506 selects the smaller value 0.6 as the first gain value output.

[0052] In the ninth frame, the corresponding current value is the third preset current value C3. At this time, the second gain value output by the gain calculation circuit 503 and the third gain value output by the gain limit calculation circuit 507 are both reduced to the second preset gain value 0.4, the fourth gain value output by the gain delay circuit 505 is 0.45625, and the judgment circuit 506 selects the smaller value 0.4 as the first gain value output.

[0053] As can be seen from the data changes in Table 1, the gain limit calculation circuit 507 plays a limiting role in the gain value output by the gain calculation circuit 503, preventing the gain value from decreasing too quickly. At the same time, the gain delay circuit 505 smoothes the gain value, making the change of the gain value more gradual. The judgment circuit 506 selects the smaller gain value, which not only ensures smooth transition of display brightness but also avoids the occurrence of overcurrent phenomenon. This multiple control technical solution effectively improves the flicker phenomenon of the display picture and improves the display quality.

[0054] Referring to Figure 10 , Figure 10 The inventor first invented a technical solution of gain delay in the process of invention and creation, which is Example 1 of the present application.

[0055] As Figure 10 shown, in Example 1, the drive circuit only includes the current conversion circuit 501, the current value calculation circuit 502, the gain calculation circuit 503, the difference calculation circuit 504, the gain delay circuit 505, and the multiplication operation circuit 508.

[0056] Although the gain signal change can be made smooth through the gain delay circuit 505, due to the lack of current limiting mechanism, when the input signal suddenly increases, the output signal will be too large (overcurrent phenomenon), as Figure 11 shown. This overcurrent phenomenon can cause damage to the display panel and reduce the service life of the display panel.

[0057] Referring to Figure 12 , Figure 12 The reasons for the overcurrent phenomenon of the display device during a plurality of consecutive display frames are shown. Figure 12The horizontal axis of the graph represents display frames, including the Nth frame, the N+1th frame, the N+2th frame, and the N+3th frame. The vertical axis represents the numerical value of each signal.

[0058] During the Nth to N+3th frames, the input signal has a large value, and the gain signal also has a large value. In this case, the output signal is too large.

[0059] When the input gray-scale signal and the gain signal are both large, their product exceeds the safe range, resulting in an overcurrent phenomenon.

[0060] Referring to Figure 13 , Figure 13 The inventor invented a technical solution for the above-mentioned Example 1 during the invention process. The technical solution is a gain delay and current limit technical solution, which is Example 2 of the present application.

[0061] As shown in Figure 13 , in Example 2, the driving circuit includes the current conversion circuit 501, the current value calculation circuit 502, the gain calculation circuit 503, the difference calculation circuit 504, the gain delay circuit 505, the gain limit calculation circuit 507, the judgment circuit 506, and the multiplication operation circuit 508.

[0062] By adding the gain limit calculation circuit 507 and using the judgment circuit 506 to select the smaller one between the third gain value output by the gain limit calculation circuit 507 and the fourth gain value output by the gain delay circuit 505, the occurrence of the overcurrent phenomenon can be effectively prevented. However, due to the sudden limitation of the gain value, the output signal has a large fluctuation, and a significant flicker phenomenon occurs, as shown in Figure 14 This flicker phenomenon affects the viewing effect of the display picture and reduces the user experience.

[0063] In Example 2, to avoid the occurrence of the overcurrent phenomenon, the driving circuit limits the gain value through the gain limit calculation circuit 507 during each frame. When the current value exceeds the preset threshold, the gain limit calculation circuit 507 immediately adjusts the third gain value to a smaller value, and the judgment circuit 506 selects the smaller third gain value as the first gain value output. Although this direct limitation of the gain value can effectively prevent the occurrence of the overcurrent phenomenon, the sudden decrease in the gain value leads to a large difference in display brightness between adjacent frames. Specifically, when the current value of a frame exceeds the preset threshold, the gain limit calculation circuit 507 immediately reduces the third gain value of the frame to within the safe range. This sudden change in brightness causes flicker in the display picture. This flicker phenomenon is particularly obvious in high-brightness display scenarios, which seriously affects the display quality.

[0064] To solve the flicker problem, the technical scheme of the embodiment of the present application is invented on the basis of the above-mentioned Comparative Example 2, which is a technical scheme of gain delay and current limitation and feedback.

[0065] In the embodiment of the present application, the first gain value output by the judgment circuit 506 is fed back to the difference calculation circuit 504, so as to realize dynamic adjustment of the gain value. When the gain value is limited, the feedback control mode composed of the difference calculation circuit 504, the gain delay circuit 505, the gain limitation calculation circuit 507 and the judgment circuit 506 can make the change of the gain value more gentle, which not only avoids the overcurrent phenomenon, but also reduces the flicker phenomenon. From Figure 7 As can be seen from the waveforms shown in the figure, the current signal waveform under this scheme is the most stable, and there is no flicker phenomenon, and the display effect is the best.

[0066] Through the technical scheme of the embodiment of the present application, the gain value can be dynamically adjusted, so as to ensure that the output signal always remains within a reasonable range, thereby effectively protecting the display panel and improving the display quality.

[0067] The comparison of the three technical schemes clearly shows that the technical scheme (delay + current limitation + feedback control) of the embodiment of the present application has obvious effect in solving the overcurrent and flicker problems in the display panel driving process, and effectively improves the display quality.

[0068] As Figure 6 As shown in the figure, the embodiment of the present application provides a display device, which comprises a display panel and a driving circuit, wherein the driving circuit comprises a current value calculation circuit 502, a gain calculation circuit 503, a difference calculation circuit 504, a gain delay circuit 505, a gain limitation calculation circuit 507, a judgment circuit 506 and a multiplication operation circuit 508.

[0069] The current value calculation circuit 502 is electrically connected with a signal input end of the driving circuit;

[0070] The gain calculation circuit 503 is electrically connected with the current value calculation circuit 502;

[0071] The difference calculation circuit 504 is electrically connected with the gain calculation circuit 503;

[0072] The gain delay circuit 505 is electrically connected with the difference calculation circuit 504;

[0073] The gain limitation calculation circuit 507 is electrically connected with the current value calculation circuit 502;

[0074] The judgment circuit 506 is electrically connected with the gain delay circuit 505 and the gain limitation calculation circuit 507;

[0075] The multiplication operation circuit 508 is configured to multiply the first gray scale data (first current signal) input from the signal input end and the first gain value output from the judgment circuit 506, and output second gray scale data (second current signal).

[0076] The driving circuit further comprises a current conversion circuit 501 electrically connected with the signal input end, and a current value calculation circuit 502 electrically connected with the current conversion circuit 501. The current conversion circuit 501 is configured to convert the first gray scale data into corresponding current data.

[0077] The current value calculation circuit 502 is configured to receive the first gray scale data and calculate the current value. Specifically, the current value calculation circuit 502 is configured to cumulatively calculate all current data in a frame, and normalize the calculation result to obtain a standardized current value.

[0078] The timing controller is configured to generate a plurality of control signals, and control the current value calculation circuit 502 to start calculating the current value at the beginning of each frame.

[0079] The gain calculation circuit 503 is configured to calculate the second gain value according to the current value.

[0080] In this embodiment, as an improvement, the gain calculation circuit 503 is configured to look up the corresponding gain value in a preset current value-gain value corresponding table according to the current value, and configured to perform interpolation calculation according to the gain values corresponding to the two adjacent current values in the corresponding table to obtain the second gain value when the current value is not in the corresponding table.

[0081] In this embodiment, as an improvement, the variation range of the current value is divided into a plurality of intervals in advance, and different gain calculation parameters are configured for each interval. The gain calculation parameters are used to determine the calculation method of the second gain value, for example: the reference gain value is used to set the reference value of the second gain value in the interval; the gain adjustment step is used to control the adjustment amplitude of the second gain value relative to the reference gain value; and the gain variation rate is used to control the fast or slow degree of the second gain value changing with the current value.

[0082] As an improvement, the gain calculation circuit 503 is further configured to dynamically adjust the gain calculation parameters based on the current value change trend of multiple consecutive frames. For example, the gain calculation circuit 503 is further configured to sample the current values ​​of multiple consecutive frames and calculate their change trend, specifically by calculating the current value difference between adjacent frames and statistically analyzing the change direction and magnitude of the current value to determine the change trend; and is further configured to update the gain calculation parameters of the current interval based on the change trend. When it is detected that the current value shows a continuous upward trend, the baseline gain value is correspondingly reduced and the gain adjustment step size is increased; when it is detected that the current value shows a continuous downward trend, the baseline gain value is correspondingly increased and the gain adjustment step size is reduced; the gain calculation circuit 503 is also configured to ensure a smooth transition of the gain value through gradual adjustment when the current value crosses different intervals, thereby avoiding sudden changes in the gain value.

[0083] The difference calculation circuit 504 is configured to receive the second gain value and the first gain value output by the determination circuit 506 , and calculate a difference between the second gain value and the first gain value.

[0084] In this embodiment, as an improvement, the difference calculation circuit 504 may include a cache unit and an operation unit, the cache unit is used to store the second gain value and the first gain value, and the operation unit is used to calculate the difference between the second gain value and the first gain value.

[0085] In this embodiment, as an improvement, the difference calculation circuit 504 is further configured to control the second gain value and the first gain value to be calculated at the same time. The difference calculation circuit 504 is further configured to detect whether the difference calculation result exceeds a preset range and, if the difference calculation result is detected to exceed the preset range, select a preset default difference value as output.

[0086] The preset range includes a preset upper threshold value and a preset lower threshold value. The difference calculation circuit 504 is further configured to generate a preset default difference value based on the current operating state, and to calculate a transition difference value based on the historical difference value and the current difference value when the difference value exceeds the preset range, and to select whether to use the default difference value or the transition difference value based on the degree of the difference exceeding the range.

[0087] like Figure 8 As shown, the gain delay circuit 505 is used to multiply the difference output by the difference calculation circuit 504 by a preset coefficient to obtain a multiplication result, add the multiplication result to the first gain value to obtain an addition result, and output the addition result to the judgment circuit 506.

[0088] The preset coefficient ranges from 0.01 to 1.

[0089] In the embodiment, the gain delay circuit 505 can include a multiplier 5051 and an adder 5052, the multiplier 5051 is configured to multiply the difference value output by the difference calculation circuit 504 by a preset coefficient to obtain a multiplication result, and the adder 5052 is configured to add the multiplication result and the first gain value output by the judgment circuit 506 to obtain an addition result.

[0090] As an improvement, the gain delay circuit 505 can further include a coefficient selection unit configured to dynamically adjust the value of the preset coefficient according to the size of the difference value. The gain delay circuit 505 can further include a smoothing processing unit configured to perform smoothing processing on the addition result. The gain delay circuit 505 can further include a storage unit configured to store the addition result of the historical frame, and the gain delay circuit 505 can further include an average value calculation unit configured to calculate a weighted average value of the addition result of the current frame and the addition result of the historical frame as the fourth gain value.

[0091] In the embodiment, the gain delay circuit 505 is further configured to perform addition operation on the multiplication result and the first gain value at the same time.

[0092] As an improvement, the gain delay circuit 505 is further configured to correct the addition result according to a preset compensation algorithm when an abnormal fluctuation of the addition result is detected. The gain delay circuit 505 is further configured to perform trend analysis on the addition results of a plurality of continuous frames, and adjust the calculation parameters of the weighted average value according to the analysis result.

[0093] The gain limit calculation circuit 507 is configured to calculate the third gain value according to the current value.

[0094] When the current value is less than or equal to a first preset current value C1, the third gain value is a first preset gain value; when the current value is greater than the first preset current value C1, the third gain value is nonlinearly reduced from the first preset gain value to a second preset gain value.

[0095] The first preset gain value is in the range of 0.9 to 1, and the second preset gain value is in the range of 0.2 to 0.6. Preferably, the first preset gain value is 1, and the second preset gain value is 0.4.

[0096] In this embodiment, as an improvement, the gain limit calculation circuit 507 can include a first comparison unit for comparing the current value with a first preset current value C1, a second preset current value C2 and a third preset current value C3 respectively, and a calculation unit for calculating the third gain value according to the comparison result: when the current value is less than or equal to the first preset current value C1, the calculation unit sets the third gain value as the first preset gain value; when the current value is greater than the first preset current value C1 and less than the second preset current value C2, the calculation unit keeps the third gain value as the first preset gain value; when the current value is greater than or equal to the second preset current value C2 and less than the third preset current value C3, the calculation unit calculates the third gain value according to a preset nonlinear function, so that it is nonlinearly reduced from the first preset gain value; when the current value is greater than or equal to the third preset current value C3, the calculation unit sets the third gain value as the second preset gain value. The gain limit calculation circuit 507 can further include a function operation unit for calculating the third gain value according to the preset nonlinear function.

[0097] As an improvement, the gain limit calculation circuit 507 is further configured to dynamically adjust the parameters of the preset nonlinear function according to the content characteristics of the display picture.

[0098] The parameters of the preset nonlinear function include: a curve slope parameter for controlling the speed of change of the third gain value with the current value; a turning point parameter for determining the position where the third gain value starts to change nonlinearly; and a curvature parameter for controlling the bending degree of the third gain value change curve. Specifically, when calculating the third gain value, the gain limit calculation circuit 507 first determines whether the current current value exceeds the threshold set by the turning point parameter, and when it exceeds, calculates the nonlinear reduction amount of the third gain value according to the curve slope parameter and the curvature parameter.

[0099] The determination circuit 506 is configured to receive the fourth gain value output by the gain delay circuit 505 and the third gain value output by the gain limit calculation circuit 507, and to select the smaller one of the fourth gain value and the third gain value as the first gain value output.

[0100] In this embodiment, the determination circuit 506 can include a second comparison unit for comparing the fourth gain value and the third gain value, and a selection unit for selecting the smaller one of the fourth gain value and the third gain value as the first gain value output according to the comparison result.

[0101] The display device provided in the application can effectively improve the flicker phenomenon of the display image by setting the difference calculation circuit 504, the gain delay circuit 505, the gain limit calculation circuit 507 and the judgment circuit 506 in the driving circuit and adopting the feedback signal control mode. Specifically, the difference calculation circuit 504 receives the second gain value output by the gain calculation circuit 503 and the first gain value output by the judgment circuit 506, and calculates the difference between the two, the gain delay circuit 505 multiplies the difference with a preset coefficient and adds the first gain value, so that the change of the gain value is more gentle through this calculation mode. At the same time, the gain limit calculation circuit 507 calculates the third gain value according to the current value, limits the change range of the gain value, and the judgment circuit 506 selects the smaller one of the fourth gain value output by the gain delay circuit 505 and the third gain value output by the gain limit calculation circuit 507 as the first gain value output, which ensures that the output gain value will not exceed the reasonable range.

[0102] In the above technical solution, the difference calculation circuit 504 calculates the difference of the gain value, and the gain delay circuit 505 performs delay calculation processing on the difference, which slows down the change speed of the gain value; the gain limit calculation circuit 507 calculates the third gain value, and the judgment circuit 506 selects the smaller gain value output, which prevents the gain value from exceeding the reasonable range; the first gain value output by the judgment circuit 506 is fed back to the difference calculation circuit 504, which realizes the dynamic adjustment of the gain value. Figure 7 As shown in the above technical solution, it not only ensures the smooth transition of the display image brightness and avoids the flicker phenomenon of the display image, but also avoids the adverse effects of the too large output current on the display panel, thereby effectively improving the display effect.

[0103] The above detailed the embodiments of the application, and the content of the specification should not be understood as limiting the protection scope of the application.

Claims

1. A display device, characterized in that: The device comprises a display panel and a driving circuit, wherein the driving circuit comprises: a current value calculation circuit, the current value calculation circuit being electrically connected to the signal input terminal of the drive circuit; a gain calculation circuit, the gain calculation circuit being electrically connected to the current value calculation circuit; a differential calculation circuit, the differential calculation circuit being electrically connected to the gain calculation circuit; a gain delay circuit, the gain delay circuit being electrically connected to the differential calculation circuit; a gain limiting calculation circuit, the gain limiting calculation circuit being electrically connected to the current value calculation circuit; a judgment circuit electrically connected to the gain delay circuit and the gain limit calculation circuit; and a multiplication circuit, configured to perform a multiplication operation on the first grayscale data inputted from the signal input terminal and the first gain value outputted from the judgment circuit, and output second grayscale data; The differential calculation circuit is configured to receive the first gain value output by the judgment circuit and the second gain value output by the gain calculation circuit, and calculate the difference between the first gain value and the second gain value; The gain delay circuit is configured to multiply the difference value output by the difference calculation circuit by a preset coefficient to obtain a multiplication result, add the multiplication result to the first gain value to obtain an addition result, and output the addition result to the judgment circuit; The gain limit calculation circuit is used to calculate a third gain value according to the current value; The judgment circuit is used to receive the third gain value output by the gain limit calculation circuit and the fourth gain value output by the gain delay circuit, and to select the smaller one between the third gain value and the fourth gain value as the first gain value to be output.

2. The display device according to claim 1, wherein The current value calculation circuit is used for receiving the first grayscale data and calculating the current value.

3. The display device according to claim 2, wherein: The gain calculation circuit is used to calculate a second gain value according to the current value.

4. The display device according to claim 1, wherein The value range of the preset coefficient is 0.01 to 1.

5. The display device according to claim 1, wherein When the current value is less than or equal to the first preset current value, the third gain value is the first preset gain value; When the current value is greater than the first preset current value, the third gain value decreases nonlinearly from the first preset gain value to a second preset gain value.

6. The display device according to claim 5, wherein: The first preset gain value is in the range of 0.9 to 1, and the second preset gain value is in the range of 0.2 to 0.6.

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