Pixel circuit, driving method thereof, array substrate and display panel

Abstract

The application discloses a pixel circuit, a driving method thereof, an array substrate and a display panel. The pixel circuit comprises a driving module, a first end of the driving module being connected with a first power line; wherein, in each driving period, a first power signal on the first power line has different voltages in at least two driving stages; a threshold compensation module, the threshold compensation module being connected between a second end of the driving module and a control end of the driving module, and the threshold compensation module being used for resetting and threshold compensating the driving module in time; the first power signal comprises a second reset voltage and a first power voltage; and the first power line is used for transmitting the second reset voltage and the first power voltage to the first end of the driving module in time. The technical scheme of the application improves the use performance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, an array substrate, and a display panel. Background Technology

[0002] With the rapid development of display technology, organic light-emitting display (OLED) products are being used more and more widely.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] This invention provides a pixel circuit and its driving method, an array substrate, and a display panel to improve the performance of the display panel.

[0005] According to one aspect of the present invention, a pixel circuit is provided, the pixel circuit comprising:

[0006] A driving module, wherein a first end of the driving module is connected to a first power line; wherein, in each driving cycle, the voltage of a first power signal on the first power line is different in at least two driving phases;

[0007] A threshold compensation module is connected between the second end of the drive module and the control end of the drive module. The threshold compensation module is used to perform time-division multiplexing of the drive module for resetting and threshold compensation. The first power signal includes a second reset voltage and a first power supply voltage. The first power line is used to transmit the second reset voltage and the first power supply voltage to the first end of the drive module in a time-division multiplexing manner.

[0008] Optionally, during the reset phase of one of the drive cycles, the first power supply signal is the second reset voltage, and during the remaining phases of the drive cycle, the first power supply signal is the first power supply voltage.

[0009] Optionally, the voltage of the first power supply signal changes from the first power supply voltage to the second reset voltage in the first sub-stage of the reset phase;

[0010] Preferably, the threshold compensation module is used to transmit the second reset voltage to the control terminal of the drive module in the second sub-stage of the reset phase, so as to reset the control terminal of the drive module;

[0011] Preferably, the second sub-stage is located after the first sub-stage;

[0012] Preferably, the threshold compensation module is further configured to perform threshold compensation on the drive module during the threshold compensation stage, wherein the voltage of the first power supply signal changes from the second reset voltage to the first power supply voltage during the threshold compensation stage.

[0013] Preferably, the pixel circuit further includes a data writing module and a coupling module; the first terminal of the data writing module is connected to a data voltage or a first reset voltage, and the coupling module is connected between the second terminal of the data writing module and the control terminal of the driving module; the data writing module is used to transmit the data voltage and the first reset voltage to the coupling module in a time-division multiplexing manner.

[0014] Preferably, the data writing module is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset phase, so as to reset the control terminal of the drive module through the coupling module;

[0015] Preferably, the third sub-stage is located after the second sub-stage;

[0016] Preferably, in one of the reset phases, the duration of the second sub-phase is greater than the duration of the third sub-phase;

[0017] Preferably, in one of the reset phases, the duration of the second sub-phase is greater than the duration of the first sub-phase.

[0018] Optionally, the data writing module includes a data writing transistor, the first terminal of which is connected to the data voltage and / or the first reset voltage, and the second terminal of which is connected to the coupling module; the control terminal of the data writing transistor is connected to the first scan line; the data writing transistor is used to transmit the data voltage and the first reset voltage to the coupling module in a time-division multiplexing manner.

[0019] Preferably, the data writing transistor is used to transmit the data voltage to the coupling module during the data writing phase, and to transmit the first reset voltage to the coupling module during at least a portion of the reset phase;

[0020] Preferably, the data writing transistor is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset phase.

[0021] Optionally, the data writing module includes a data writing transistor and a reset transistor;

[0022] The control electrode of the data writing transistor is connected to the first scan line, the first electrode of the data writing transistor is connected to the data voltage, and the second electrode of the data writing transistor is connected to the coupling module; the data writing transistor is used to transmit the data voltage to the coupling module during the data writing stage, and the coupling module is used to couple the data voltage to the control terminal of the driving module;

[0023] The first terminal of the reset transistor is connected to the first reset voltage, and the second terminal of the reset transistor is connected to the coupling module; the reset transistor is used to transmit the first reset voltage to the coupling module during at least a portion of the reset phase.

[0024] Preferably, the reset transistor is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset phase.

[0025] Optionally, the control electrode of the reset transistor is connected to the second scan line;

[0026] Preferably, the threshold compensation module includes a threshold compensation transistor, the control electrode of which is connected to the third scan line; the threshold compensation transistor is connected between the second terminal of the driving module and the control terminal of the driving module.

[0027] Preferably, the threshold compensation transistor is of the same type as the reset transistor;

[0028] Preferably, both the threshold compensation transistor and the reset transistor are of type N or P.

[0029] Preferably, the start time of the effective level of the second scan signal on the second scan line is delayed by one line time relative to the start time of the effective level of the third scan signal on the third scan line; the second scan signal and the third scan signal have the same period and the same waveform;

[0030] Preferably, the second scan line and the third scan line extend along a first direction, and in two adjacent pixel circuits in a second direction, the third scan line corresponding to one pixel circuit is connected to the second scan line corresponding to the other pixel circuit; wherein, the first direction intersects the second direction.

[0031] Optionally, the second reset voltage is less than the first reset voltage.

[0032] Optionally, the driving module includes a driving transistor, the control electrode of the driving transistor is connected to the coupling module, the first electrode of the driving transistor is connected to the first power supply signal, and the second electrode of the driving transistor is connected to the threshold compensation module;

[0033] Preferably, the coupling module includes a coupling capacitor, the first terminal of which is connected to the control terminal of the driving transistor, and the second terminal of which is connected to the data writing module;

[0034] Preferably, the pixel circuit further includes a storage module;

[0035] The first end of the storage module is connected to the first power signal, and the second end of the storage module is connected to the second end of the coupling module or the control end of the drive module.

[0036] The first end of the coupling module is connected to the control end of the drive module;

[0037] Preferably, the pixel circuit further includes a light-emitting control module, the control terminal of which is connected to the light-emitting control line, and the light-emitting control module is connected between the second terminal of the driving module and the light-emitting element;

[0038] Preferably, the storage module includes a storage capacitor, the first terminal of the storage capacitor is connected to the first power signal, and the second terminal of the storage capacitor is connected to the second end of the coupling module;

[0039] Preferably, the light-emitting control module includes a light-emitting control transistor, the control electrode of which is connected to the light-emitting control line, and the light-emitting control transistor is connected between the second terminal of the driving module and the light-emitting element.

[0040] Optionally, the driving module includes a driving transistor, the driving transistor having an active layer material different from that of the data writing transistor;

[0041] Preferably, the active layer of the driving transistor comprises a polycrystalline silicon semiconductor material, and the active layer of the data writing transistor comprises an oxide semiconductor material.

[0042] According to another aspect of the present invention, an array substrate is provided, the array substrate comprising:

[0043] Substrate;

[0044] The first active layer is located on one side of the substrate. The first active layer includes a first active region, which has a channel region for driving transistors and a channel region for threshold compensation transistors.

[0045] A first conductive layer is located on the side of the first active layer opposite to the substrate. The first conductive layer includes a first metal block forming the control electrode of the driving transistor and a third scan line forming the control electrode of the threshold compensation transistor. The third scan line extends along a first direction. The channel region of the driving transistor is located at the orthogonal projection of the first metal block onto the first active region. The channel region of the threshold compensation transistor is located at the orthogonal projection of the third scan line onto the first active region. The first metal block is connected to the first electrode of the threshold compensation transistor through a first connection portion. The second electrode of the driving transistor is connected to the second electrode of the threshold compensation transistor through the first active region.

[0046] The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a second metal block forming the second electrode of a coupling capacitor. The second metal block is reused as the first electrode of the coupling capacitor. The orthogonal projection of the second metal block on the substrate covers the orthogonal projection of the first metal block on the substrate.

[0047] The second active layer is located on the side of the second conductive layer away from the substrate. The second active layer includes a third active region, which has a channel region for a data write transistor.

[0048] A fourth conductive layer is located on the side of the second active layer away from the substrate. The fourth conductive layer includes a first scan line forming the control electrode of the data writing transistor. The first scan line extends along the first direction. The channel region of the data writing transistor is located at the orthogonal projection of the first scan line onto the third active region. The second electrode of the data writing transistor is connected to the second metal block through a second connection portion.

[0049] The first active layer and the second active layer are made of different materials.

[0050] Optionally, the first active layer further includes a second active region, the second active region including the channel region of a reset transistor, and the second terminal of the reset transistor is connected to the second terminal of the coupling capacitor;

[0051] The first conductive layer further includes a second scan line extending along the first direction, and the channel region of the reset transistor is located at the orthogonal projection of the second scan line onto the second active region;

[0052] Preferably, the extension direction of the threshold compensation transistor channel region is perpendicular to the extension direction of the reset transistor channel region;

[0053] Preferably, in the second direction, the threshold compensation transistor channel region and the reset transistor channel region are distributed on both sides of the channel region of the driving transistor, and the first direction intersects the second direction;

[0054] Preferably, the first metal block includes a first protrusion located at one end of the first metal block facing the threshold compensation transistor, and the first electrode of the threshold compensation transistor is connected to the first protrusion.

[0055] Preferably, the second metal block includes a second protrusion located at one end of the second metal block facing the reset transistor, and the second electrode of the reset transistor is electrically connected to the second protrusion.

[0056] Optionally, the second active layer further includes a fourth active region, the fourth active region including the channel region of the light-emitting control transistor, the third active region and the fourth active region being spaced apart and both extending along the second direction;

[0057] Preferably, the orthographic projections of the third active region and the fourth active region on the substrate both overlap with the orthographic projections of the first active region on the substrate.

[0058] The fourth conductive layer further includes a light-emitting control line extending along the first direction, and the channel region of the light-emitting control transistor is located at the orthogonal projection of the light-emitting control line in the fourth active region;

[0059] Preferably, the channel region of the driving transistor is U-shaped, and the third active region is L-shaped.

[0060] Optionally, the array substrate further includes a third conductive layer located between the second conductive layer and the second active layer;

[0061] The third conductive layer includes a third metal block forming a first electrode of a storage capacitor. The orthographic projection of the third metal block on the substrate covers the orthographic projection of the second metal block on the substrate. The second metal block is reused as the second electrode of the storage capacitor.

[0062] In the first direction, adjacent third metal blocks are interconnected, and the interconnected third metal blocks are multiplexed as a first power line to transmit a first power signal. The first terminal of the storage capacitor is connected to the first terminal of the driving transistor.

[0063] Preferably, the third metal block includes a third protrusion that extends toward the third active region;

[0064] Preferably, both the first connecting portion and the second connecting portion are located in the third conductive layer;

[0065] Preferably, the orthographic projections of the third active region and the fourth active region onto the substrate are located within the orthographic projection range of the third metal block onto the substrate;

[0066] Preferably, the third scan line includes a main body and an extension, the main body extends in the same direction as the channel region of the threshold compensation transistor, the extension extends in a direction perpendicular to the extension direction of the main body, and the channel region of the threshold compensation transistor is located at the orthogonal projection of the extension onto the first active region.

[0067] Preferably, the width of the main body portion is the same as that of the first scan line.

[0068] Optionally, the second conductive layer further includes a plurality of reset power signal lines extending along a first direction, wherein the orthographic projection of the reset power signal lines on the substrate overlaps with the orthographic projection of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines; or

[0069] The third conductive layer also includes multiple reset power signal lines, the orthographic projection of the reset power signal lines on the substrate overlaps with the orthographic projection of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines;

[0070] The reset power signal line extends along the first direction, and the end of the second active region away from the second metal block is electrically connected to one of the reset power signal lines.

[0071] Optionally, the array substrate further includes a first insulating layer located between the first active layer and the first conductive layer, a second insulating layer located between the first conductive layer and the second conductive layer, and a third insulating layer located between the second conductive layer and the third conductive layer;

[0072] The second terminal of the reset transistor is connected to the second metal block through a first via penetrating the first and second insulating layers. The first terminal of the reset transistor is connected to the reset power signal line through a second via. The second via penetrates the first and second insulating layers, or the second via penetrates the first, second, and third insulating layers.

[0073] Preferably, the first electrode of the driving transistor is connected to the third metal block through a third via, the third via penetrating the first insulating layer, the second insulating layer and the third insulating layer;

[0074] Preferably, the control electrode of the driving transistor is connected to the first connection portion through a fourth via, and the first connection portion is also connected to the first electrode of the threshold compensation transistor through a fifth via.

[0075] The fourth via penetrates the second and third insulating layers, and the fifth via sequentially penetrates the third, second, and first insulating layers.

[0076] Optionally, the array substrate further includes a fourth conductive layer and a fifth conductive layer located on the side of the third conductive layer away from the substrate; the array substrate further includes a fourth insulating layer located between the third conductive layer and the second active layer, a fifth insulating layer located between the second active layer and the fourth conductive layer, and a sixth insulating layer located on the side of the fourth conductive layer away from the substrate;

[0077] The fifth conductive layer includes multiple data transmission lines extending along the second direction, and the first electrode of the data writing transistor is connected to the data transmission lines through a sixth via penetrating the sixth insulating layer and the fifth insulating layer;

[0078] Preferably, the fifth conductive layer further includes a third connection portion extending along a first direction and a fourth connection portion extending along a second direction, the second terminal of the data writing transistor is connected to the third connection portion through a seventh via, the end of the third connection portion away from the seventh via is connected to the second connection portion through an eighth via, and the second connection portion is connected to the second terminal of the coupling capacitor through a ninth via.

[0079] The eighth via penetrates the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in sequence; the seventh via penetrates the sixth insulating layer and the fifth insulating layer; and the ninth via penetrates the third insulating layer.

[0080] Preferably, the ninth via overlaps with the orthographic projection of the first via on the substrate;

[0081] Preferably, the first electrode of the light-emitting control transistor is connected to the fourth connection portion through the tenth via, and the end of the fourth connection portion away from the tenth via is connected to the fifth connection portion through the eleventh via;

[0082] The tenth via penetrates the sixth and fifth insulating layers in sequence, and the eleventh via penetrates the sixth, fifth, and fourth insulating layers in sequence.

[0083] Preferably, the second electrode of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through a twelfth via penetrating the sixth insulating layer and the fifth insulating layer.

[0084] According to another aspect of the present invention, a method for driving a pixel circuit is provided for driving the pixel circuit described in any embodiment of the present invention, the method comprising:

[0085] During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module;

[0086] During the threshold compensation phase, the threshold compensation module performs threshold compensation on the drive module based on the first power signal;

[0087] The voltage of the first power signal is different in the reset phase and other phases. The first power signal includes a second reset voltage and a first power supply voltage. The first power line is used to transmit the second reset voltage and the first power supply voltage to the first terminal of the drive module in a time-division multiplexing manner.

[0088] Optionally, during the reset phase, the first power supply signal is the second reset voltage; during the remaining phases, the first power supply signal is the first power supply voltage.

[0089] During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module, including:

[0090] During the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the drive module;

[0091] During the threshold compensation phase, the threshold compensation module performs threshold compensation on the drive module based on the first power signal, including:

[0092] During the threshold compensation phase, the threshold compensation module performs threshold compensation on the drive module based on the first power supply voltage.

[0093] Optionally, during the reset phase, the threshold compensation module transmits a first power signal to the control terminal of the drive module, and the data writing module transmits a first reset voltage to the coupling module, including:

[0094] In the first sub-stage of the reset phase, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage;

[0095] In the second sub-stage of the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the drive module to reset the control terminal of the drive module;

[0096] In the third sub-stage of the reset phase, the data writing module transmits the first reset voltage to the coupling module;

[0097] Preferably, the second reset voltage is less than the first reset voltage;

[0098] Preferably, in one of the reset phases, the duration of the second sub-phase is greater than the duration of the third sub-phase;

[0099] Preferably, in one of the reset phases, the duration of the second sub-phase is greater than the duration of the first sub-phase.

[0100] According to another aspect of the present invention, a display panel is provided, the display panel including the array substrate described in any embodiment of the present invention.

[0101] The technical solution of this invention allows the first power line to transmit different voltages in a time-division multiplexing manner by setting the voltage of the first power signal to be different in at least two driving stages. When the first power signal is a second reset voltage, the second reset voltage is transmitted to the control terminal of the driving module through the driving module and the threshold compensation module, and the threshold compensation module resets the driving module. When the first power signal is a first power supply voltage, the voltage at the control terminal of the driving module can be made to be a voltage related to the first power supply voltage and the threshold voltage of the transistor in the driving module, and the threshold compensation module performs threshold compensation on the driving module. In this way, the threshold compensation module performs time-division multiplexing of the driving module for reset and threshold compensation. This eliminates the need for a large number of modules to perform compensation and reset, reduces the number of transistors, and helps to improve the pixel density of the display panel corresponding to the pixel circuit. Therefore, while ensuring a high pixel density of the display panel, the normal operation of the pixel circuit is guaranteed, and the performance of the display panel is improved.

[0102] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0103] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0104] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0105] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0106] Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0107] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0108] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0109] Figure 6 This is a schematic diagram of the structure of the display panel corresponding to the pixel circuit provided in the embodiment of the present invention;

[0110] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0111] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0112] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0113] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0114] Figure 11 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0115] Figure 12 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0116] Figure 13 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0117] Figure 14 This is a top view schematic diagram of an array substrate provided in an embodiment of the present invention;

[0118] Figure 15 This is a schematic diagram of the layout structure of the first active layer and the first conductive layer of an array substrate provided in an embodiment of the present invention;

[0119] Figure 16 This is a schematic diagram of the layout structure of the second and third conductive layers of an array substrate provided in an embodiment of the present invention;

[0120] Figure 17 This is a schematic diagram of the layout structure of the second active layer and the fourth conductive layer of an array substrate provided in an embodiment of the present invention;

[0121] Figure 18 This is a schematic diagram of the structure of a first active layer, a first conductive layer, a second conductive layer, and a third conductive layer of an array substrate provided in an embodiment of the present invention;

[0122] Figure 19This is a schematic diagram of the layout structure of the second conductive layer, the third conductive layer, the second active layer and the fourth conductive layer of an array substrate provided in an embodiment of the present invention;

[0123] Figure 20 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0124] Figure 21 yes Figure 14 A sectional view along the a1-a2 direction;

[0125] Figure 22 This is a schematic diagram of the layout structure of the first active layer, the first conductive layer, and the third active layer of an array substrate provided in an embodiment of the present invention;

[0126] Figure 23 yes Figure 18 A sectional view along the b1-b2 direction;

[0127] Figure 24 yes Figure 18 A sectional view along the e1-e2 direction;

[0128] Figure 25 yes Figure 19 A sectional view along the f1-f2 direction;

[0129] Figure 26 This is a schematic diagram of the layout structure of the third conductive layer, the second active layer and the sixth insulating layer of an array substrate provided in an embodiment of the present invention;

[0130] Figure 27 This is a schematic diagram of the layout structure of the fifth conductive layer of an array substrate provided in an embodiment of the present invention;

[0131] Figure 28 yes Figure 14 A sectional view along the h1-h2 direction;

[0132] Figure 29 yes Figure 14 A sectional view along the h3-h4 direction;

[0133] Figure 30 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention;

[0134] Figure 31 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0135] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0136] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0137] As mentioned in the background section, existing display panels suffer from performance limitations. The inventors have discovered that this issue arises because, while display technology has advanced and display panels are increasingly widely used, their array processes and film structures limit their ability to achieve high pixel densities (Pixels Per Inch, PPI). This prevents them from displaying images at high density, and lower density results in lower fidelity. Consequently, display devices cannot achieve high fidelity, leading to poor display quality and impacting overall performance. A display panel comprises multiple pixel circuits and light-emitting elements. Pixel circuits generate driving current to power the light-emitting elements. To achieve higher pixel density, related technologies reduce the number of transistors in the pixel circuits, for example, using a 2T1C pixel circuit. However, reducing the number of transistors diminishes the functionality of the pixel circuits, such as the inability to perform initialization or threshold compensation. This results in residual charge and threshold drift causing variations in the driving current, leading to a significant difference between the brightness of the light-emitting elements and the target brightness. Consequently, the display panel's image quality is poor, negatively affecting its performance.

[0138] To address the aforementioned technical problems, embodiments of the present invention provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 1 The pixel circuit includes:

[0139] The driving module 110 has a first terminal connected to a first power line VDD; wherein, in each driving cycle, the voltage of the first power signal on the first power line VDD is different in at least two driving phases.

[0140] A threshold compensation module 120 is connected between the second terminal of the drive module 110 and the control terminal of the drive module. The threshold compensation module 120 is used to perform time-division resetting and threshold compensation on the drive module 110. The first power signal includes a second reset voltage and a first power supply voltage. The first power line VDD is used to transmit the second reset voltage and the first power supply voltage to the first terminal of the drive module 110 in a time-division manner.

[0141] In this embodiment, one driving cycle of the pixel circuit is one display frame of the display panel formed by the pixel circuit. One driving cycle of the pixel circuit includes multiple driving stages, such as a reset stage, a data writing stage, a compensation stage, and a light-emitting stage, which are not limited here. The pixel circuit can be connected to the light-emitting element 200 to drive the corresponding light-emitting element 200 to emit light. For example, the second terminal of the driving module 110 is connected to the first terminal of the light-emitting element 200, and the second terminal of the light-emitting element 200 is connected to the second power line VSS. The driving module 110 can generate a driving current, causing the light-emitting element 200 to emit light in response to the driving current. The first power signal includes a first power supply voltage, for example, the first power supply voltage is a positive voltage, and the second power supply voltage on the second power line VSS is a negative voltage or zero; or the first power supply voltage is a negative voltage or zero, and the second power supply voltage on the second power line VSS is a positive voltage, which is not limited in this embodiment.

[0142] Specifically, the first power line VDD can transmit a first power signal. By setting the voltage of the first power signal to be different in at least two driving stages, the first power line VDD can transmit different voltages in a time-division manner. The first power signal includes a second reset voltage and a first power supply voltage. The second reset voltage is less than the first power supply voltage. When the first power signal is the second reset voltage, the second reset voltage is transmitted to the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, thereby resetting the control terminal of the drive module 110. That is, the threshold compensation module 120 resets the drive module 110. When the first power signal is the first power supply voltage, the first power supply voltage charges the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, making the voltage of the control terminal of the drive module 110 a voltage related to the first power supply voltage and the threshold voltage of the transistor in the drive module 110, thereby achieving threshold compensation for the drive module 110. That is, the threshold compensation module 120 performs threshold compensation for the drive module 110. In this way, the threshold compensation module 120 performs time-division reset and threshold compensation for the drive module 110. This eliminates the need for numerous modules for compensation and reset, reducing the number of transistors and facilitating a higher pixel density in the display panel. Thus, while minimizing the number of components in the pixel circuit, it ensures that the pixel circuit can perform reset and compensation. In other words, it guarantees the normal operation of the pixel circuit while maintaining a high pixel density in the display panel, thereby improving the overall performance of the display panel.

[0143] Furthermore, the second reset voltage can be transmitted to the first terminal of the light-emitting element 200 via the driving module 110, thereby resetting the light-emitting element 200. This eliminates the need for a separate reset device for the light-emitting element 200, further improving the pixel density of the display panel corresponding to the pixel circuit. Moreover, when the first power signal is the first power supply voltage, the first power supply voltage, the driving module 110, the light-emitting element 200, and the second power supply voltage can form a current path, causing the driving module 110 to generate a driving current, which in turn allows the light-emitting element 200 to emit light in response to the driving current.

[0144] The technical solution of this embodiment enables the first power line to transmit different voltages in a time-division multiplexing manner by setting the voltage of the first power signal to be different in at least two driving stages. When the first power signal is the second reset voltage, the second reset voltage is transmitted to the control terminal of the driving module through the driving module and the threshold compensation module, and the threshold compensation module resets the driving module. When the first power signal is the first power supply voltage, the voltage at the control terminal of the driving module can be made to be a voltage related to the first power supply voltage and the threshold voltage of the transistor in the driving module, and the threshold compensation module performs threshold compensation on the driving module. In this way, the threshold compensation module performs time-division multiplexing of the driving module for reset and threshold compensation. Therefore, it is not necessary to set up a large number of modules to implement compensation and reset, reducing the number of transistors and helping to improve the pixel density of the display panel corresponding to the pixel circuit. Thus, while ensuring a large pixel density of the display panel, the normal operation of the pixel circuit is guaranteed, and the performance of the display panel is improved.

[0145] Based on the above technical solution, optionally, during the reset phase of a drive cycle, the first power supply signal is the second reset voltage, and during the remaining phases of the drive cycle, the first power supply signal is the first power supply voltage.

[0146] Specifically, a driving cycle of a pixel circuit refers to the time from the end of the previous frame's light-emitting element to the end of the current frame's light-emitting element. This cycle includes a reset phase, and may also include a compensation phase, a data writing phase, and a light-emitting phase. During the reset phase, the first power signal is set to a second reset voltage. This second reset voltage is transmitted to the control terminal of the driving module 110 via the driving module 110 and the threshold compensation module 120, thus resetting the control terminal of the driving module 110 during the reset phase. In the remaining phases, the first power signal is a first power supply voltage, allowing the threshold compensation module 120 to use this voltage to perform threshold compensation on the driving module 110. This ensures that the first power supply voltage, the driving module 110, the light-emitting element 200, and the second power supply voltage can form a current path, enabling the driving module 110 to generate a driving current.

[0147] Based on the above technical solutions, optionally, the voltage of the first power supply signal changes from the first power supply voltage to the second reset voltage in the first sub-stage of the reset phase. Thus, at the beginning of the reset phase, the first power supply signal becomes the second reset voltage, facilitating the reset of the driving module 110 according to the second reset voltage and eliminating the influence of the previous frame's emission voltage on the driving module 110.

[0148] Optionally, the threshold compensation module 120 is used to transmit the second reset voltage to the control terminal of the drive module 110 in the second sub-stage of the reset phase, so as to reset the control terminal of the drive module 110.

[0149] Specifically, the second sub-stage follows the first sub-stage. After the first power signal changes to the second reset voltage, the threshold compensation module 120 transmits the second reset voltage to the control terminal of the drive module 110 in the second sub-stage of the reset phase. That is, the second reset voltage is transmitted to the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, which can clear the residual voltage at the first terminal and the control terminal of the drive module 110, thereby resetting the drive module 110.

[0150] Optionally, the threshold compensation module 120 is also used to perform threshold compensation on the drive module 110 during the threshold compensation stage, wherein the voltage of the first power supply signal jumps from the second reset voltage to the first power supply voltage during the threshold compensation stage.

[0151] Specifically, during the threshold compensation stage, the voltage of the first power supply signal jumps from the second reset voltage to the first power supply voltage. The first power supply voltage charges the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, so that the voltage of the control terminal of the drive module 110 is a voltage related to the first power supply voltage and the threshold voltage of the transistor in the drive module 110, thereby realizing threshold compensation for the drive module 110. That is, the threshold compensation module 120 performs threshold compensation for the drive module 110.

[0152] Based on the above technical solutions, Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 2 The pixel circuit also includes a data writing module 130 and a coupling module 140; the first terminal of the data writing module 130 is connected to the data voltage Vdata or the first reset voltage Vini, and the coupling module 140 is connected between the second terminal of the data writing module 130 and the control terminal of the drive module 110; the data writing module 130 is used to transmit the data voltage Vdata and the first reset voltage Vini to the coupling module 140 in a time-division manner.

[0153] For example, the first end of the coupling module 140 is connected to the control end of the drive module 110, and the second end of the coupling module 140 is connected to the second end of the data writing module 130.

[0154] Specifically, the first terminal of the data writing module 130 can be connected to the data voltage Vdata and the first reset voltage Vini in a time-division manner, so that the data writing module 130 can transmit the data voltage Vdata and the first reset voltage Vini to the second terminal of the coupling module 140 in a time-division manner. The coupling module 140 can couple the first reset voltage Vini and the data voltage Vdata to the control terminal of the driving module 110 in a time-division manner, realizing the reset and data writing of the control terminal of the driving module 110. For example, in the reset phase, the data writing module 130 transmits the first reset voltage Vini to the second terminal of the coupling module 140, and the coupling module 140 couples the first reset voltage Vini to the control terminal of the driving module 110, realizing the reset of the driving module 110. In the data writing phase, the data writing module 130 transmits the data voltage Vdata to the second terminal of the coupling module 140, and the coupling module 140 couples the data voltage Vdata to the control terminal of the driving module 110, so that in the light-emitting phase, the driving module 110 can generate a driving current according to the data voltage Vdata, so that the light-emitting element 200 can emit light in response to the driving current.

[0155] Optionally, the data writing module 130 transmits the first reset voltage Vini to the coupling module 140 in the third sub-stage of the reset phase, so as to reset the control terminal of the drive module 110 through the coupling module 140. In this way, through the coupling effect of the coupling module 140, the control terminal of the drive module 110 can be reset during the reset phase, thereby realizing the control of the potential of the control terminal of the drive module 110.

[0156] Optionally, the third sub-stage is located after the second sub-stage.

[0157] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control terminal of the drive module 110, the first terminal and control terminal of the drive module 110 are at the second reset voltage. By setting the third sub-stage after the second sub-stage, and with the data writing module 130 in the third sub-stage of the reset stage, the first reset voltage Vini is transmitted to the coupling module 140. For example, if the drive module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control terminal of the drive module 110 is slightly increased, but still remains a lower voltage, thus achieving the reset of the control terminal of the drive module 110. For example, if the drive module 110 requires a higher voltage for reset, and the first reset voltage Vini is less than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control terminal of the drive module 110 is slightly decreased, but still remains a higher voltage, thus achieving the reset of the control terminal of the drive module 110.

[0158] Optionally, in a reset phase, the duration of the second sub-phase is longer than the duration of the third sub-phase. This results in a longer reset time for the drive module 110 using the second reset voltage, thereby bringing the potential of the control terminal of the drive module 110 closer to the second reset voltage and achieving better reset of the control terminal of the drive module 110.

[0159] Optionally, in a reset phase, the duration of the second sub-phase is longer than that of the first sub-phase. The first sub-phase is primarily a voltage transition phase and is relatively short, while the second sub-phase is longer, allowing the second reset voltage to be more fully written to the control terminal of the drive module 110. This makes the potential of the control terminal of the drive module 110 closer to the second reset voltage, thus achieving better reset of the control terminal of the drive module 110.

[0160] Based on the above technical solutions, the possible structure of the data writing module 130 will be described below, but this is not intended to limit the scope of this application.

[0161] In one implementation, Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 3 The data writing module 130 includes a data writing transistor T1. The first terminal of the data writing transistor T1 is connected to the data voltage Vdata and / or the first reset voltage Vini. The second terminal of the data writing transistor T1 is connected to the coupling module 140. The control terminal of the data writing transistor T1 is connected to the first scan line S1. The data writing transistor T1 is used to transmit the data voltage Vdata and the first reset voltage Vini to the coupling module 140 in a time-division manner.

[0162] Specifically, the data writing transistor T1, based on the first scan signal of the first scan line S1, can time-division multiplex the data voltage Vdata and the first reset voltage Vini to the second terminal of the coupling module 140. The coupling module 140 can then time-division multiplex the first reset voltage Vini and the data voltage Vdata to the control terminal of the drive module 110, thereby resetting the control terminal of the drive module 110 and writing data. The data writing transistor T1 can be an N-type transistor or a P-type transistor. Figure 3 The diagram shows the case where the data writing transistor T1 is an N-type transistor, but it is not limited to this case.

[0163] Optionally, refer to Figure 3 The data writing transistor T1 is used to transmit the data voltage Vdata to the coupling module 140 during the data writing phase and to transmit the first reset voltage Vini to the coupling module 140 during at least a portion of the reset phase.

[0164] Specifically, during the data writing stage, the data writing transistor T1 transmits the data voltage Vdata to the second terminal of the coupling module 140, and the coupling module 140 couples the data voltage Vdata to the control terminal of the driving module 110, so that during the light emission stage, the driving module 110 can generate a driving current according to the data voltage Vdata, and the light emission element 200 can emit light in response to the driving current.

[0165] During at least a portion of the reset phase, the data writing transistor T1 transmits the first reset voltage Vini to the coupling module 140, for example, to the second terminal of the coupling module 140, thereby resetting the second terminal of the coupling module 140. This also allows the coupling module 140 to couple the first reset voltage Vini to the control terminal of the drive module 110, thus resetting the drive module 110.

[0166] Optionally, refer to Figure 3 The data writing transistor T1 is used in the third sub-stage of the reset phase to transmit the first reset voltage Vini to the coupling module 140.

[0167] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control terminal of the drive module 110, the control terminal of the drive module 110 is at the second reset voltage. In the third sub-stage of the reset phase, the data writing transistor T1 transmits the first reset voltage Vini to the coupling module 140. For example, if the drive module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control terminal of the drive module 110 is slightly increased, but still remains a lower voltage, thereby resetting the control terminal of the drive module 110.

[0168] In another implementation, Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 4 The data writing module 130 includes a data writing transistor T1 and a reset transistor T2;

[0169] The control terminal of the data writing transistor T1 is connected to the first scan line S1, the first terminal of the data writing transistor T1 is connected to the data voltage Vdata, and the second terminal of the data writing transistor T1 is connected to the coupling module 140. The data writing transistor T1 is used to transmit the data voltage Vdata to the coupling module 140 during the data writing stage, and the coupling module 140 is used to couple the data voltage Vdata to the control terminal of the drive module 110.

[0170] The first terminal of the reset transistor T2 is connected to the first reset voltage Vini, and the second terminal of the reset transistor T2 is connected to the coupling module 140. The reset transistor T2 is used to transmit the first reset voltage Vini to the coupling module 140 during at least a part of the reset phase.

[0171] Specifically, during at least a portion of the reset phase, the reset transistor T2 is turned on, transmitting the first reset voltage Vini to the coupling module 140, for example, to the second terminal of the coupling module 140, thereby resetting the second terminal of the coupling module 140. Furthermore, the coupling module 140 can couple the first reset voltage Vini to the control terminal of the drive module 110, thus resetting the drive module 110.

[0172] During the data writing stage, the first scan signal on the first scan line S1 controls the data writing transistor T1 to turn on. The data writing transistor T1 transmits the data voltage Vdata to the second terminal of the coupling module 140. The coupling module 140 couples the data voltage Vdata to the control terminal of the driving module 110, so that during the light emission stage, the driving module 110 can generate a driving current according to the data voltage Vdata, so that the light emission element 200 can emit light in response to the driving current.

[0173] Optionally, refer to Figure 4 The reset transistor T2 is used in the third sub-stage of the reset phase to transmit the first reset voltage Vini to the coupling module 140.

[0174] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control terminal of the drive module 110, the control terminal of the drive module 110 is at the second reset voltage. In the third sub-stage of the reset stage, the reset transistor T2 transmits the first reset voltage Vini to the coupling module 140. For example, if the drive module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control terminal of the drive module 110 is slightly increased, but still remains a lower voltage, thereby achieving the reset of the control terminal of the drive module 110.

[0175] Based on the above technical solutions, optionally, reference can be made to... Figure 4 The control electrode of the reset transistor T2 is connected to the second scan line S2. Thus, the reset transistor T2 can be turned on or off according to the second scan signal on the second scan line S2, so that when the reset transistor T2 is turned on in response to the second scan signal, it can reset the second terminal of the coupling module 140 and the control terminal of the drive module 110.

[0176] Optionally, refer to Figure 4The threshold compensation module 120 includes a threshold compensation transistor T3, the control electrode of which is connected to the third scan line S3; the threshold compensation transistor T3 is connected between the second terminal of the drive module 110 and the control terminal of the drive module 110.

[0177] Specifically, when the first power supply signal is the second reset voltage, the third scan signal on the third scan line S3 controls the threshold compensation transistor T3 to turn on. The second reset voltage is transmitted to the control terminal of the drive module 110 through the drive module 110 and the threshold compensation transistor T3, thereby resetting the control terminal of the drive module 110. In other words, the threshold compensation transistor T3 resets the drive module 110. When the first power supply signal is the first power supply voltage, the third scan signal on the third scan line S3 controls the threshold compensation transistor T3 to turn on. The first power supply voltage charges the control terminal of the drive module 110 through the drive module 110 and the threshold compensation transistor T3, making the voltage at the control terminal of the drive module 110 a voltage related to the first power supply voltage and the threshold voltage of the transistor in the drive module 110. This achieves threshold compensation for the drive module 110. Thus, the threshold compensation transistor T3 performs time-sharing reset and threshold compensation on the drive module 110.

[0178] Optionally, refer to Figure 4 The threshold compensation transistor T3 is of the same type as the reset transistor T2.

[0179] Specifically, the display panel corresponding to the pixel circuit includes a shift register, which comprises multiple cascaded gate drive circuits that provide scanning signals to the pixel circuit. By setting the threshold compensation transistor T3 to be of the same type as the reset transistor T2, the second scan line S2 and the third scan line S3 can be connected to the same shift register, for example, to different stages of gate drive circuits within the same shift register. This reduces the number of shift registers and helps to reduce the bezel size.

[0180] In one implementation, alternatively, reference is made to... Figure 4 Both the threshold compensation transistor T3 and the reset transistor T2 are P-type. Thus, when the third scan signal is low, the threshold compensation transistor T3 is turned on, allowing the third scan signal to couple low to the control terminal of the drive module 110, thus enabling better reset of the drive module 110's control terminal. Furthermore, this design allows for a smaller size of the threshold compensation transistor T3 and the reset transistor T2, which is beneficial for increasing the pixel density of the display panel.

[0181] In another implementation, Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 5 Both the threshold compensation transistor T3 and the reset transistor T2 are of type N. This reduces the leakage current at the control terminal of the drive module 110, thereby preventing drive current fluctuations generated by the drive module 110 and ensuring stable light emission from the light-emitting element 200, thus improving the display quality of the display panel.

[0182] Optionally, refer to Figure 4 The start time of the effective level of the second scan signal on the second scan line S2 is delayed by one line time relative to the start time of the effective level of the third scan signal on the third scan line S3; the second scan signal and the third scan signal have the same period and the same waveform. This allows the second and third scan signals to be provided by different stages of gate driving circuits in the same shift register. For example, the m-th stage gate driving circuit outputs the second scan signal corresponding to the m-th row pixel circuit; the (m+1)-th stage gate driving circuit outputs the third scan signal corresponding to the (m+1)-th row pixel circuit, which is also the second scan signal corresponding to the m-th row pixel circuit. This allows the second scan line S2 and the third scan line S3 to be connected to the same shift register, thereby reducing the number of shift registers and thus reducing the border size. Here, m is a positive integer.

[0183] One line time is the time interval between the start times of the effective level of the third scan signal S3 corresponding to two adjacent rows of pixel circuits. One line time can be calculated based on the display panel's resolution and refresh rate. The resolution determines the number of rows of pixel circuits (i.e., the number of rows of light-emitting elements), thus the line time is... .

[0184] Figure 6 This is a schematic diagram of the structure of the display panel corresponding to the pixel circuit provided in the embodiment of the present invention. Optionally, refer to... Figure 6 The second scan line S2 and the third scan line S3 extend along the first direction X. In two adjacent pixel circuits 10 in the second direction Y, the third scan line S3 corresponding to one pixel circuit 10 is connected to the second scan line S2 corresponding to the other pixel circuit 10. The first direction X intersects the second direction Y.

[0185] like Figure 6As shown, the display panel corresponding to the pixel circuit includes a shift register 300. The shift register 300 includes multiple cascaded gate driving circuits 310. The input terminal of the first-stage gate driving circuit 310 is connected to the input voltage SIN. The input terminal of the (m+1)th-stage gate driving circuit 310 is connected to the output terminal of the m-th-stage gate driving circuit 310. The first clock terminal SCK1 of the m-th-stage gate driving circuit 310 is connected to the first clock signal CLK1. The second clock terminal SCK2 of the m-th-stage gate driving circuit 310 is connected to the second clock signal CLK2. The first clock terminal SCK1 of the (m+1)th-stage gate driving circuit 310 is connected to the second clock signal CLK2. The second clock terminal SCK2 of the (m+1)th-stage gate driving circuit 310 is connected to the first clock signal CLK1.

[0186] The output terminal OUT(m+1) of the (m+1)th level gate drive circuit is connected to the third scan line S3 corresponding to the (m+1)th row pixel circuit 10, and also to the second scan line S2 corresponding to the mth row pixel circuit. This allows the second scan line S2 and the third scan line S3 to be connected to the same shift register, thereby reducing the number of shift registers and helping to reduce the border size.

[0187] Based on the above technical solution, optionally, the second reset voltage is less than the first reset voltage Vini.

[0188] Specifically, in the second sub-stage, after the threshold compensation module 120 resets the control terminal of the drive module 110, the control terminal of the drive module 110 is at the second reset voltage. In the third sub-stage, through the coupling effect of the coupling module 140, the voltage of the control terminal of the drive module 110 is slightly increased, but still remains a low voltage, thereby resetting the control terminal of the drive module 110.

[0189] Optionally, refer to Figure 3 , Figure 4 or Figure 5 The light-emitting element 200 includes an organic light-emitting diode (OLED) D1, with a first electrode of the OLED D1 being the first terminal of the light-emitting element 200 and a second electrode of the OLED D1 being the second terminal of the light-emitting element 200. The first electrode of the OLED D1 is the anode, and the second electrode is the cathode; or, the first electrode of the OLED D1 is the cathode, and the second electrode is the anode.

[0190] Optionally, refer to Figure 3 , Figure 4 or Figure 5 The driving module 110 includes a driving transistor T4. The control electrode of the driving transistor T4 is connected to the coupling module 140. The first electrode of the driving transistor T4 is connected to the first power supply signal, and the second electrode of the driving transistor T4 is connected to the threshold compensation module 120.

[0191] Specifically, when the first power supply signal is the second reset voltage, the threshold compensation module 120 transmits the second reset voltage to the control electrode of the driving transistor T4 to reset the control electrode of the driving transistor T4. When the first power supply signal is the first power supply voltage, the threshold compensation module 120 transmits the voltage related to the threshold voltage of the driving transistor T4 to the control electrode of the driving transistor T4 to perform threshold compensation on the driving transistor T4.

[0192] Optionally, refer to Figure 3 , Figure 4 or Figure 5 The coupling module 140 includes a coupling capacitor C1. The first terminal of the coupling capacitor C1 is connected to the control terminal of the driving transistor T4, and the second terminal of the coupling capacitor C1 is connected to the data writing module 130.

[0193] Specifically, when the data writing module 130 transmits the first reset voltage Vini to the second terminal of the coupling capacitor C1, the coupling capacitor C1 couples the first reset voltage Vini to the control terminal of the driving transistor T4, resetting the driving transistor T4. When the data writing module 130 transmits the data voltage Vdata to the second terminal of the coupling capacitor C1, the coupling capacitor C1 couples the data voltage Vdata to the control terminal of the driving transistor T4, so that the driving transistor T4 can generate a driving current according to the data voltage Vdata.

[0194] Based on the above technical solutions, Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 7 The pixel circuit also includes a storage module 150;

[0195] The first end of the storage module 150 is connected to the first power signal, and the second end of the storage module 150 is connected to the second end of the coupling module 140 or the control end of the drive module 110.

[0196] The first end of the coupling module 140 is connected to the control end of the drive module 110.

[0197] Specifically, the second terminal of the storage module 150 is connected to the second terminal of the coupling module 140, which can maintain the potential of the second terminal of the coupling module 140, and thus maintain the potential of the control terminal of the driving module 110. The connection between the second terminal of the storage module 150 and the control terminal of the driving module 110 maintains the potential of the control terminal of the driving module 110. This ensures a relatively stable potential at the control terminal of the driving module 110, allowing the driving module 110 to generate a stable driving current, thereby enabling the light-emitting element 200 to emit light stably.

[0198] It should be noted that, Figure 7 The diagram shows the second end of the storage module 150 connected to the second end of the coupling module 140, but does not limit the connection.

[0199] Optionally, refer to Figure 7 The pixel circuit also includes a light emission control module 160. The control terminal of the light emission control module 160 is connected to the light emission control line EM. The light emission control module 160 is connected between the second terminal of the driving module 110 and the light emission element 200.

[0200] Specifically, the light-emitting control module 160 can control whether the driving current generated by the driving module 110 is transmitted to the light-emitting element 200, thereby controlling whether the light-emitting element 200 emits light. When the light-emitting control signal on the light-emitting control line EM is at an effective level, the light-emitting control module 160 is turned on, so that the first power line VDD, the driving module 110, the light-emitting control module 160, the light-emitting element 200 and the second power line VSS can form a current path, thereby causing the driving module 110 to generate a driving current, and the light-emitting element 200 to emit light in response to the driving current.

[0201] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 8 , Figure 9 or Figure 10 The storage module 150 includes a storage capacitor C2. The first terminal of the storage capacitor C2 is connected to a first power supply signal, and the second terminal of the storage capacitor C2 is connected to the second terminal of the coupling module 140. In this way, the storage capacitor C2 can maintain the voltage at the second terminal of the coupling module 140, thereby maintaining the potential of the control electrode of the driving transistor T4, so that the driving transistor T4 can generate a stable driving current.

[0202] Optionally, refer to Figure 8 , Figure 9 or Figure 10 The light-emitting control module 160 includes a light-emitting control transistor T5. The control electrode of the light-emitting control transistor T5 is connected to the light-emitting control line EM. The light-emitting control transistor T5 is connected between the second terminal of the driving module 110 and the light-emitting element 200. Thus, the light-emitting control transistor T5 can control whether the driving current generated by the driving transistor T4 is transmitted to the light-emitting element 200, thereby controlling whether the light-emitting element 200 emits light. Figure 8 and Figure 9 As shown, the light-emitting control transistor T5 can be an N-type transistor, such as... Figure 10As shown, the light-emitting control transistor T5 can be a P-type transistor, but this embodiment does not limit the type of the light-emitting control transistor T5.

[0203] Based on the above technical solutions, optionally, the driving module 110 includes a driving transistor T4, the active layer material of which is different from that of the data writing transistor T1. That is, the driving transistor T4 and the data writing transistor T1 are of different types, which allows the active layers of the driving transistor T4 and the data writing transistor T1 to be stacked. In other words, the stacking of different types of transistors can reduce the area occupied by the pixel circuit, thereby increasing the pixel density of the display panel.

[0204] Optionally, refer to Figure 8 , Figure 9 or Figure 10 The active layer of the driving transistor T4 is made of polycrystalline silicon semiconductor material, while the active layer of the data writing transistor T1 is made of oxide semiconductor material. That is, the driving transistor T4 is a P-type transistor, and the data writing transistor T1 is an N-type transistor. This allows different types of transistors to be stacked, thereby reducing the area occupied by the pixel circuitry.

[0205] The pixel circuit provided in this embodiment has a small number of transistors, and the pixel circuit can perform functions such as reset, data writing and threshold compensation. It can ensure the normal operation of the pixel circuit while increasing the pixel density of the display panel, which is conducive to improving the accuracy and stability of the driving current generated by the pixel circuit, thereby improving the display quality of the display panel.

[0206] The following description of the pixel circuit's operation, based on its structure and driving timing, is intended to limit the scope of this application.

[0207] In one implementation, Figure 11 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 8 and Figure 11 The driving process of a pixel circuit (i.e., one driving cycle) includes the following stages.

[0208] In the first sub-stage t11 of the reset phase t1, the first power signal Vdd on the first power line VDD jumps from the first power supply voltage to the second reset voltage. Figure 11 The diagram illustrates the case where the second reset voltage is lower than the first power supply voltage, but it is not limiting. This allows the control terminal g of the driving transistor T4 and the second terminal n1 of the coupling capacitor C1 to be downwardly coupled.

[0209] In the second sub-stage t12 of the reset phase t1, the third scan signal Scan3 on the third scan line S3 is at a low level, the threshold compensation transistor T3 is turned on, and the control electrode g of the driving transistor T4 is shorted to the second electrode of the driving transistor T4. After a period of leakage, the voltage Vg of the control electrode g of the driving transistor T4 and the voltage of the second electrode of the driving transistor T4 become the second reset voltage Vdd1, so Vg = Vdd1. This achieves the reset of the control electrode g of the driving transistor T4. Furthermore, the light emission control signal Em on the light emission control line EM is at a high level, the light emission control transistor T5 is turned on, and the light emission control transistor T5 transmits the second reset voltage to the first terminal of the light emission element 200, resetting the first terminal of the light emission element 200.

[0210] In the third sub-stage t13 of the reset phase t1, the third scan signal Scan3 on the third scan line S3 is low, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is high, and the data writing transistor T1 is turned on. At this time, the data writing transistor T1 is connected to the first reset voltage Vini, and the data writing transistor T1 transmits the first reset voltage Vini to the second terminal n1 of the coupling capacitor C1, resetting the second terminal n1 of the coupling capacitor C1. Furthermore, the coupling capacitor C1 couples to the control terminal of the driving transistor T4, slightly raising the potential of the control terminal g of the driving transistor T4, but the voltage of the control terminal g of the driving transistor T4 remains a relatively low voltage, thus achieving the reset of the control terminal of the driving transistor T4.

[0211] During the threshold compensation stage t2, the third scan signal Scan3 on the third scan line S3 is low, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is high, and the data writing transistor T1 is turned on, at which time the data writing transistor T1 is connected to the first reset voltage Vini. The light emission control signal Em on the light emission control line EM is low, and the light emission control transistor T5 is not turned on. The first power supply signal Vdd on the first power supply line VDD becomes the first power supply voltage Vdd2. The first power supply voltage Vdd2 charges the first terminal of the coupling capacitor C1 through the driving transistor T4 and the threshold compensation transistor T3 until the voltage of the first terminal of the coupling capacitor C1 is Vdd2 + Vth (Vth is the threshold voltage of the driving transistor T4), that is, the voltage of the control terminal g of the driving transistor T4 is Vdd2 + Vth. The data writing transistor T1 transmits the first reset voltage Vini to the second terminal n1 of the coupling capacitor C1, and the voltage of the second terminal n1 of the coupling capacitor C1 is maintained at the first reset voltage Vini. In this way, the threshold compensation transistor T3 performs threshold compensation on the driving transistor T4.

[0212] During the data writing phase t3, the first scan signal Scan1 on the first scan line S1 is high, and the data writing transistor T1 is turned on. At this time, the data writing transistor T1 is connected to the data voltage Vdata. The third scan signal Scan3 on the third scan line S3 is high, and the threshold compensation transistor T3 is not turned on. The data writing transistor T1 transmits the data voltage Vdata to the second terminal n1 of the coupling capacitor C1. The voltage change at the first terminal of the coupling capacitor C1 is k*(Vdata-Vini), where... Where C1 is the capacitance of coupling capacitor C1, and Other is the other capacitance of the control electrode of driving transistor T4. Then the potential of the control electrode of driving transistor T4 becomes Vdd2+Vth+k*(Vdata-Vini). For example, if the other capacitance of the control electrode of driving transistor T4 is small and can be ignored, then k is 1, and the potential of the control electrode of driving transistor T4 is Vdd2+Vth+(Vdata-Vini).

[0213] During the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a high level, and the light-emitting control transistor T5 is turned on. The first power line VDD, the driving transistor T4, the light-emitting control transistor T5, the light-emitting element 200, and the second power line VSS form a current path. The voltage difference between the control electrode and the first electrode of the driving transistor T4 is Vth + (Vdata - Vini). Therefore, the driving current generated by the driving transistor T4 is... .in, The electron mobility of the driving transistor T4 in the driving module 110, Let W be the channel capacitance per unit area of ​​the driving transistor T4, W be the channel width of the driving transistor T4, and L be the channel length of the driving transistor T4. In this way, the driving current generated by the driving module 110 is only related to the data voltage Vdata and the first reset voltage Vini, and is independent of the threshold voltage of the driving transistor T4 in the driving module 110, as well as the first power supply voltage and the second power supply voltage. This avoids fluctuations in the driving current caused by fluctuations in the threshold voltage of the driving transistor T4, and also avoids fluctuations in the driving current caused by voltage drops on the first power supply line VDD or the second power supply line VSS. This ensures the stability and accuracy of the driving current, which is beneficial for improving the display effect of the display panel, and thus improving the display performance of the display panel.

[0214] In another implementation, Figure 12 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 9 and Figure 12 The driving process of a pixel circuit (i.e., one driving cycle) includes the following stages.

[0215] In the first sub-stage t11 of the reset phase t1, the first power supply signal Vdd on the first power supply line VDD jumps from the first power supply voltage to the second reset voltage. This allows the control electrode g of the driving transistor T4 and the second electrode n1 of the coupling capacitor C1 to be coupled downwards.

[0216] In the second sub-stage t12 of the reset phase t1, the third scan signal Scan3 on the third scan line S3 is at a low level, the threshold compensation transistor T3 is turned on, and the control electrode g of the driving transistor T4 is shorted to the second electrode of the driving transistor T4. After a period of leakage, the voltage Vg of the control electrode g of the driving transistor T4 and the voltage of the second electrode of the driving transistor T4 become the second reset voltage Vdd1, so Vg = Vdd1. This achieves the reset of the control electrode g of the driving transistor T4, and at the same time, it can reset the first electrode s of the driving transistor T4. Furthermore, the light emission control signal Em on the light emission control line EM is at a high level, the light emission control transistor T5 is turned on, and the light emission control transistor T5 transmits the second reset voltage to the first terminal of the light emission element 200, resetting the first terminal of the light emission element 200.

[0217] In the third sub-stage t13 of the reset phase t1, the third scan signal Scan3 on the third scan line S3 is low, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is low, and the data writing transistor T1 is not turned on. The second scan signal Scan2 on the second scan line S2 is low, and the reset transistor T2 is turned on. The reset transistor T2 transmits the first reset voltage Vini to the second terminal n1 of the coupling capacitor C1, resetting the second terminal n1 of the coupling capacitor C1. Furthermore, the coupling capacitor C1 couples to the control terminal of the driving transistor T4, slightly raising the potential of the control terminal g of the driving transistor T4, but the voltage of the control terminal g of the driving transistor T4 remains a low voltage, thus achieving the reset of the control terminal of the driving transistor T4.

[0218] During the threshold compensation stage t2, the third scan signal Scan3 on the third scan line S3 is low, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is low, and the data writing transistor T1 is not turned on. The second scan signal Scan2 on the second scan line S2 is low, and the reset transistor T2 is turned on. The light emission control signal Em on the light emission control line EM is low, and the light emission control transistor T5 is not turned on. The first power supply signal Vdd on the first power supply line VDD becomes the first power supply voltage Vdd2. The first power supply voltage Vdd2 charges the first terminal of the coupling capacitor C1 through the driving transistor T4 and the threshold compensation transistor T3 until the voltage of the first terminal of the coupling capacitor C1 is Vdd2 + Vth (Vth is the threshold voltage of the driving transistor T4), that is, the voltage of the control terminal g of the driving transistor T4 is Vdd2 + Vth. The reset transistor T2 transmits the first reset voltage Vini to the second terminal n1 of the coupling capacitor C1, and the voltage of the second terminal n1 of the coupling capacitor C1 is maintained at the first reset voltage Vini. In this way, threshold compensation transistor T3 performs threshold compensation on driving transistor T4.

[0219] During the data writing phase t3, the first scan signal Scan1 on the first scan line S1 is high, and the data writing transistor T1 is turned on. The third scan signal Scan3 on the third scan line S3 and the second scan signal Scan2 on the second scan line S2 are high, and the reset transistor T2 and the threshold compensation transistor T3 are not turned on. The data writing transistor T1 transmits the data voltage Vdata to the second terminal n1 of the coupling capacitor C1. The voltage change at the first terminal of the coupling capacitor C1 is k*(Vdata-Vini), where... Where C1 is the capacitance of coupling capacitor C1, and Other is the other capacitance of the control electrode of driving transistor T4. Then the potential of the control electrode of driving transistor T4 becomes Vdd2+Vth+k*(Vdata-Vini). For example, if the other capacitance of the control electrode of driving transistor T4 is small and can be ignored, then k is 1, and the potential of the control electrode of driving transistor T4 is Vdd2+Vth+(Vdata-Vini).

[0220] During the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a high level, and the light-emitting control transistor T5 is turned on. The first power line VDD, the driving transistor T4, the light-emitting control transistor T5, the light-emitting element 200, and the second power line VSS form a current path. The voltage difference between the control electrode and the first electrode of the driving transistor T4 is Vth + (Vdata - Vini). Therefore, the driving current generated by the driving transistor T4 is... .in, The electron mobility of the driving transistor T4 in the driving module 110, Let W be the channel capacitance per unit area of ​​the driving transistor T4, W be the channel width of the driving transistor T4, and L be the channel length of the driving transistor T4. In this way, the driving current generated by the driving module 110 is only related to the data voltage Vdata and the first reset voltage Vini, and is independent of the threshold voltage of the driving transistor T4 in the driving module 110, as well as the first power supply voltage and the second power supply voltage. This avoids fluctuations in the driving current caused by fluctuations in the threshold voltage of the driving transistor T4, and also avoids fluctuations in the driving current caused by voltage drops on the first power supply line VDD or the second power supply line VSS. This ensures the stability and accuracy of the driving current, which is beneficial for improving the display effect of the display panel, and thus improving the display performance of the display panel.

[0221] In yet another implementation, Figure 13 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 10 and Figure 13 The driving process of a pixel circuit (i.e., one driving cycle) includes the following stages.

[0222] In the first sub-stage t11 of the reset phase t1, the first power supply signal Vdd on the first power supply line VDD jumps from the first power supply voltage to the second reset voltage. This allows the control electrode g of the driving transistor T4 and the second electrode n1 of the coupling capacitor C1 to be coupled downwards.

[0223] In the second sub-stage t12 of the reset phase t1, the third scan signal Scan3 on the third scan line S3 is at a high level, the threshold compensation transistor T3 is turned on, and the control electrode g of the driving transistor T4 is shorted to the second electrode of the driving transistor T4. After a period of leakage, the voltage Vg of the control electrode g of the driving transistor T4 and the voltage of the second electrode of the driving transistor T4 become the second reset voltage Vdd1, so Vg = Vdd1. This achieves the reset of the control electrode g of the driving transistor T4. Furthermore, the light emission control signal Em on the light emission control line EM is at a low level, the light emission control transistor T5 is turned on, and the light emission control transistor T5 transmits the second reset voltage to the first terminal of the light emission element 200, resetting the first terminal of the light emission element 200.

[0224] In the third sub-stage t13 of the reset phase t1, the third scan signal Scan3 on the third scan line S3 is high, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is low, and the data writing transistor T1 is not turned on. The second scan signal Scan2 on the second scan line S2 is high, and the reset transistor T2 is turned on. The reset transistor T2 transmits the first reset voltage Vini to the second terminal n1 of the coupling capacitor C1, resetting the second terminal n1 of the coupling capacitor C1. Furthermore, the coupling capacitor C1 couples to the control terminal of the driving transistor T4, slightly raising the potential of the control terminal g of the driving transistor T4, but the voltage of the control terminal g of the driving transistor T4 remains a low voltage, thus achieving the reset of the control terminal of the driving transistor T4.

[0225] During the threshold compensation stage t2, the third scan signal Scan3 on the third scan line S3 is high, and the threshold compensation transistor T3 is turned on. The first scan signal Scan1 on the first scan line S1 is low, and the data writing transistor T1 is not turned on. The second scan signal Scan2 on the second scan line S2 is high, and the reset transistor T2 is turned on. The light emission control signal Em on the light emission control line EM is high, and the light emission control transistor T5 is not turned on. The first power supply signal Vdd on the first power supply line VDD becomes the first power supply voltage Vdd2. The first power supply voltage Vdd2 charges the first terminal of the coupling capacitor C1 through the driving transistor T4 and the threshold compensation transistor T3 until the voltage of the first terminal of the coupling capacitor C1 is Vdd2 + Vth (Vth is the threshold voltage of the driving transistor T4), that is, the voltage of the control terminal g of the driving transistor T4 is Vdd2 + Vth. The reset transistor T2 transmits the first reset voltage Vini to the second terminal n1 of the coupling capacitor C1, and the voltage of the second terminal n1 of the coupling capacitor C1 is maintained at the first reset voltage Vini. In this way, threshold compensation transistor T3 performs threshold compensation on driving transistor T4.

[0226] During the data writing phase t3, the first scan signal Scan1 on the first scan line S1 is high, and the data writing transistor T1 is turned on. The third scan signal Scan3 on the third scan line S3 and the second scan signal Scan2 on the second scan line S2 are low, and the reset transistor T2 and the threshold compensation transistor T3 are not turned on. The data writing transistor T1 transmits the data voltage Vdata to the second terminal n1 of the coupling capacitor C1. The voltage change at the first terminal of the coupling capacitor C1 is k*(Vdata-Vini), where... Where C1 is the capacitance of coupling capacitor C1, and Other is the other capacitance of the control electrode of driving transistor T4. Then the potential of the control electrode of driving transistor T4 becomes Vdd2+Vth+k*(Vdata-Vini). For example, if the other capacitance of the control electrode of driving transistor T4 is small and can be ignored, then k is 1, and the potential of the control electrode of driving transistor T4 is Vdd2+Vth+(Vdata-Vini).

[0227] During the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a low level, and the light-emitting control transistor T5 is turned on. The first power line VDD, the driving transistor T4, the light-emitting control transistor T5, the light-emitting element 200, and the second power line VSS form a current path. The voltage difference between the control electrode and the first electrode of the driving transistor T4 is Vth + (Vdata - Vini). Therefore, the driving current generated by the driving transistor T4 is... .in, The electron mobility of the driving transistor T4 in the driving module 110, Let W be the channel capacitance per unit area of ​​the driving transistor T4, W be the channel width of the driving transistor T4, and L be the channel length of the driving transistor T4. In this way, the driving current generated by the driving module 110 is only related to the data voltage Vdata and the first reset voltage Vini, and is independent of the threshold voltage of the driving transistor T4 in the driving module 110, as well as the first power supply voltage and the second power supply voltage. This avoids fluctuations in the driving current caused by fluctuations in the threshold voltage of the driving transistor T4, and also avoids fluctuations in the driving current caused by voltage drops on the first power supply line VDD or the second power supply line VSS. This ensures the stability and accuracy of the driving current, which is beneficial for improving the display effect of the display panel, and thus improving the display performance of the display panel.

[0228] This invention also provides an array substrate, which includes pixel circuits provided in any embodiment of this invention. Figure 14 This is a top view schematic diagram of an array substrate provided in an embodiment of the present invention. Figure 15 This is a schematic diagram of the layout structure of the first active layer and the first conductive layer of an array substrate provided in an embodiment of the present invention. Figure 16 This is a schematic diagram of the layout structure of the second and third conductive layers of an array substrate provided in an embodiment of the present invention. Figure 17 This is a schematic diagram of the layout structure of the second active layer and the fourth conductive layer of an array substrate provided in an embodiment of the present invention. (Refer to...) Figure 14 , Figure 15 , Figure 16 and Figure 17 The array substrate includes:

[0229] Substrate 101;

[0230] The first active layer 102 is located on one side of the substrate 101. The first active layer 102 includes a first active region 1021. The first active region 1021 is provided with a channel region T41 for driving transistor T4 and a channel region T31 for threshold compensation transistor T3.

[0231] The first conductive layer M1 is located on the side of the first active layer 102 away from the substrate 101. The first conductive layer M1 includes a first metal block M11 forming the control electrode of the driving transistor T4 and a third scan line S3 forming the control electrode of the threshold compensation transistor T3. The third scan line S3 extends along the first direction X. The channel region T41 of the driving transistor T4 is located at the orthographic projection of the first metal block M11 onto the first active region 1021. The channel region T31 of the threshold compensation transistor T3 is located at the orthographic projection of the third scan line S3 onto the first active region 1021. The first metal block M11 is connected to the first electrode T32 of the threshold compensation transistor T3 through the first connection portion L1. The second electrode of the driving transistor T4 is connected to the second electrode T33 of the threshold compensation transistor T3 through the first active region 1021.

[0232] The second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 101. The second conductive layer M2 includes a second metal block M21 that forms the second pole C12 of the coupling capacitor C1. The second metal block M21 is reused as the first pole C11 of the coupling capacitor C1. The orthogonal projection of the second metal block M21 on the substrate 101 covers the orthogonal projection of the first metal block M11 on the substrate 101.

[0233] The second active layer 103 is located on the side of the second conductive layer M2 away from the substrate 101. The second active layer 103 includes a third active region 1031, and the third active region 1031 is provided with a channel region T11 for the data writing transistor T1.

[0234] The fourth conductive layer M4 is located on the side of the second active layer 103 away from the substrate 101. The fourth conductive layer M4 includes a first scan line S1 forming the control electrode of the data writing transistor T1. The first scan line S1 extends along the first direction X. The channel region T11 of the data writing transistor T1 is located at the orthogonal projection of the first scan line S1 onto the third active region 1031. The second electrode T12 of the data writing transistor T1 is connected to the second metal block M21 through the second connection portion L2.

[0235] The first active layer 102 and the second active layer 103 are made of different materials.

[0236] For example, the first direction X is the row direction. The portion where the first scan line S1 overlaps with the third active region 1031 forms the control electrode of the data writing transistor T1, and the portion where the third scan line S3 overlaps with the first active region 1021 can form the control electrode of the threshold compensation transistor T3, which can reduce the number of electrodes and improve space utilization.

[0237] Specifically, by stacking active layers (first active layer 102 and third active layer 103) made of different materials, different types of transistors can be stacked, thereby maximizing space utilization and resulting in a higher pixel density for the display panel formed by the array substrate. Furthermore, the array substrate includes a threshold compensation transistor T3, which, while increasing pixel density, ensures that the pixel circuit can perform threshold compensation and reset functions, guaranteeing the normal operation of the pixel circuit.

[0238] Based on the above technical solutions, optionally, refer to Figure 14 and Figure 15 The first active layer 102 also includes a second active region 1022, which includes the channel region T21 of the reset transistor T2. The second terminal T22 of the reset transistor T2 is connected to the second terminal C12 of the coupling capacitor C1.

[0239] The first conductive layer M1 also includes a second scan line S2 extending along the first direction X, and the channel region T21 of the reset transistor T2 is located at the orthogonal projection of the second scan line S2 on the second active region 1022.

[0240] Specifically, the overlapping portion of the second scan line S2 and the second active region 1022 forms the control electrode of the reset transistor T2, which can reduce the number of electrodes and improve space utilization. The second electrode T22 of the reset transistor T2 is connected to the second electrode C12 of the coupling capacitor C1, which facilitates writing the first reset voltage Vini to the second electrode C12 of the coupling capacitor C1, thereby enabling the coupling capacitor C1 to couple and reset the control electrode of the driving transistor T4.

[0241] Optionally, such as Figure 14 and Figure 15 As shown, the extension direction of the channel region T31 of the threshold compensation transistor T3 is perpendicular to the extension direction of the channel region T21 of the reset transistor T2. Thus, compared to the threshold compensation transistor T3's channel region T31 and the reset transistor T2's channel region T21 being arranged sequentially along the first direction X, the space occupied in the first direction X can be reduced. Similarly, compared to the threshold compensation transistor T3's channel region T31 and the reset transistor T2's channel region T21 being arranged sequentially along the second direction Y, the space occupied in the second direction Y can be reduced. This improves the space utilization of the array substrate.

[0242] Optionally, such as Figure 14 and Figure 15 As shown, in the second direction Y, the channel region T31 of the threshold compensation transistor T3 and the channel region T21 of the reset transistor T2 are distributed on both sides of the channel region T41 of the driving transistor T4, and the first direction X intersects with the second direction Y. In this way, the space occupied in the first direction X can be reduced, making it easier to arrange multiple pixel circuits in the first direction X, thereby increasing the pixel density of the display panel formed by the array substrate.

[0243] Optionally, such as Figure 14 and Figure 15 As shown, the first metal block M11 includes a first protrusion A1, which is located at the end of the first metal block M11 facing the threshold compensation transistor T3. The first electrode T32 of the threshold compensation transistor T3 is connected to the first protrusion A1. This facilitates the connection of the first electrode T32 of the threshold compensation transistor T3 to the first metal block M11 via the first protrusion A1, i.e., to the control electrode of the driving transistor T4, enabling the threshold compensation transistor T3 to perform time-division multiplexing of threshold compensation and reset of the driving transistor T4.

[0244] Figure 18 This is a schematic diagram of the structure of a first active layer, a first conductive layer, a second conductive layer, and a third conductive layer of an array substrate provided in an embodiment of the present invention. Optionally, as shown... Figure 14 , Figure 16 and Figure 18 As shown, the second metal block M21 includes a second protrusion A2, which is located at the end of the second metal block M21 facing the reset transistor T2. The second terminal T22 of the reset transistor T2 is electrically connected to the second protrusion A2. This facilitates the connection between the reset transistor T2 and the second metal block M21, thereby connecting it to the second terminal C12 of the coupling capacitor C1. This allows the first reset voltage Vini to be written to the second terminal C12 of the coupling capacitor C1, enabling the coupling capacitor C1 to couple and reset the control terminal of the driving transistor T4.

[0245] Based on the above technical solutions, optionally, refer to Figure 17 The second active layer 103 further includes a fourth active region 1032, which includes the channel region T51 of the light-emitting control transistor T5. The third active region 1031 and the fourth active region 1032 are spaced apart and both extend along the second direction Y. In this way, the space occupied in the first direction X can be further reduced, making it easier to arrange multiple pixel circuits in the first direction X, thereby increasing the pixel density of the display panel formed by the array substrate.

[0246] Optionally, the orthographic projections of the third active region 1031 and the fourth active region 1032 on the substrate 101 both overlap with the orthographic projections of the first active region 1021 on the substrate. This reduces the space occupied in the first direction X and the second direction Y, thereby improving space utilization and facilitating the achievement of higher pixel densities.

[0247] Optionally, refer to Figure 17 The fourth conductive layer M4 also includes a light-emitting control line EM extending along the first direction X. The channel region T51 of the light-emitting control transistor T5 is located on the orthogonal projection of the light-emitting control line EM onto the fourth active region 1032. Thus, the overlapping portion of the light-emitting control line EM and the fourth active region 1032 forms the control electrode of the light-emitting control transistor T5, which can reduce the number of electrodes and improve space utilization.

[0248] Optionally, refer to Figure 15 and Figure 17 The channel region T41 of the driving transistor T4 is shaped like a zigzag, and the third active region 1031 is L-shaped.

[0249] Specifically, the channel region T41 of the driving transistor T4 is U-shaped, which facilitates the connection of the driving transistor T4 with the threshold compensation transistor T3 and the reset transistor T2 located on both sides of it. The third active region 1031 is L-shaped, which facilitates the connection of the data writing transistor T1 with the second metal block M21.

[0250] Based on the above technical solutions, optionally, refer to Figure 14 and Figure 16 The array substrate also includes a third conductive layer M3 located between the second conductive layer M2 and the second active layer 103;

[0251] The third conductive layer M3 includes a third metal block M31 that forms the first electrode C21 of the storage capacitor C2. The orthogonal projection of the third metal block M31 on the substrate 101 covers the orthogonal projection of the second metal block M21 on the substrate 101. The second metal block M21 is reused as the second electrode C22 of the storage capacitor C2.

[0252] In the first direction X, adjacent third metal blocks M31 are interconnected, and the interconnected third metal blocks M31 are multiplexed as the first power line VDD to transmit the first power signal. The first terminal C21 of the storage capacitor C2 is connected to the first terminal of the driving transistor T4.

[0253] Specifically, by reusing the second metal block M21 as the second electrode C22 of the storage capacitor C2, the number of metal plates can be reduced, thereby reducing the thickness of the array substrate and facilitating a thinner and lighter design. Furthermore, reusing the third metal block M31 as the first power line VDD to transmit the first power signal can reduce the space occupied by the wiring, thereby further improving the space utilization of the array substrate and helping to increase the pixel density of the display panel formed by the array substrate.

[0254] Optionally, refer to Figure 16 The third metal block M31 includes a third protrusion A3, which extends toward the third active region 1031. This facilitates the extension of the third metal block M31 toward the third active region 1031, resulting in an overlap between the formed first power line VDD and the third active region 1031, thereby reducing space occupation and further improving the space utilization of the array substrate.

[0255] Optionally, refer to Figure 16 The first connection portion L1 and the second connection portion L2 are both located in the third conductive layer M3. This arrangement facilitates the connection of the first terminal T32 of the threshold compensation transistor T3, located in the third conductive layer M3, to the coupling capacitor C1 via the first connection portion L1 in the third conductive layer M3; that is, the first connection portion L1 functions as a jumper. Similarly, it facilitates the connection of the second terminal T12 of the data writing transistor T1, located on the side of the third conductive layer M3 away from the substrate 101, to the second metal block M21 via the second connection portion L2; that is, the second connection portion L2 functions as a jumper.

[0256] Figure 19 This is a schematic diagram of the layout structure of the second conductive layer, the third conductive layer, the second active layer, and the fourth conductive layer of an array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 19 The orthographic projections of the third active region 1031 and the fourth active region 1032 onto the substrate 101 are located within the orthographic projection range of the third metal block M31 onto the substrate 101. This reduces the space occupied in the second direction Y, allowing for the arrangement of more pixel circuits in the second direction Y, further improving the space utilization of the array substrate, and consequently increasing the pixel density of the display panel formed by the array substrate, which is beneficial for improving the display quality of the display panel.

[0257] Optionally, refer to Figure 15 The third scan line S3 includes a main body S31 and an extension S32. The main body S31 extends in the same direction as the channel region T31 of the threshold compensation transistor T3. The extension direction of the extension S32 is perpendicular to the extension direction of the main body S31. The channel region T31 of the threshold compensation transistor T3 is located at the orthogonal projection of the extension on the first active region 1021.

[0258] Specifically, by setting the third scan line S3 to include a main body S31 and an extension S32, the main body S31 extends along the first direction X and can be connected to the threshold compensation transistors T3 in multiple pixel circuits, facilitating line-by-line driving. Furthermore, the extension S32 can be connected to the corresponding threshold compensation transistor T3. Moreover, the extension S32 overlaps with the first active region 1021, thereby forming the control electrode of the threshold compensation transistor T3, reducing the number of electrodes and further improving space utilization.

[0259] Optionally, the width of the main body S31 is the same as the width of the first scan line S1. This facilitates the fabrication of the scan line, and both the main body S31 and the first scan line S1 can be relatively narrow, saving space and improving space utilization. In some embodiments, for example, the width of the main body S31 is the same as the width of the second scan line S2.

[0260] Based on the above technical solution, the second conductive layer M2 further includes multiple reset power signal lines Vin extending along the first direction X. The orthographic projection of the reset power signal lines Vin on the substrate 101 overlaps with the orthographic projection of the first electrode T23 of the reset transistor T2 on the substrate 101. The first electrode T23 of the reset transistor T2 is connected to the reset power signal lines Vin; or

[0261] Figure 20 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 20 The third conductive layer M3 also includes multiple reset power signal lines Vin. The orthographic projection of the reset power signal line Vin on the substrate 101 overlaps with the orthographic projection of the first electrode T23 of the reset transistor T2 on the substrate 101. The first electrode T23 of the reset transistor T2 is connected to the reset power signal line Vin.

[0262] The reset power signal line Vin extends along the first direction X, and the end of the second active region 1022 away from the second metal block M21 is electrically connected to a reset power signal line Vin.

[0263] Specifically, the reset power signal line Vin extends along the first direction X, and can be connected to the reset transistor T2 in multiple pixel circuits, thereby providing a first reset voltage Vini to the multiple pixel circuits. By connecting the reset power signal line Vin to the first terminal T23 of the reset transistor T2, the reset transistor T2 can transmit the first reset voltage Vini on the reset power signal line Vin to the second terminal of the coupling capacitor C1, facilitating the reset of the second terminal of the coupling capacitor C1.

[0264] Figure 20 The diagram shows the case where the reset power signal line Vin is located in the third conductive layer M3, but it is not limited to this case.

[0265] Based on the above technical solutions, Figure 21 yes Figure 14 A sectional view along the a1-a2 direction. Figure 22 This is a schematic diagram of the layout structure of the first active layer, the first conductive layer, and the third active layer of an array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 20 , Figure 21 and Figure 22 The array substrate also includes a first insulating layer 104 located between the first active layer 102 and the first conductive layer M1, a second insulating layer 105 located between the first conductive layer M1 and the second conductive layer M2, and a third insulating layer 106 located between the second conductive layer M2 and the third conductive layer M3.

[0266] The second terminal of the reset transistor T2 is connected to the second metal block M21 through a first via V1 that penetrates the first insulating layer 104 and the second insulating layer 105. The first terminal of the reset transistor T2 is connected to the reset power signal line Vin through a second via V2 that penetrates the first insulating layer 104 and the second insulating layer 105, or the second via V2 that penetrates the first insulating layer 104, the second insulating layer 105, and the third insulating layer 106. This facilitates the connection of the reset transistor T2 to the reset power signal line Vin and to the second metal block M21 (the second terminal of the coupling capacitor C1). The first insulating layer 104 can be an organic or inorganic insulating layer. The second insulating layer 105 can be an organic or inorganic insulating layer, such as an insulating layer formed of silicon dioxide or silicon nitride. The third insulating layer 106 can be an inorganic or organic insulating layer; for example, the material of the third insulating layer 106 can be the same as that of the second insulating layer 105, but this embodiment is not limited to this.

[0267] Figure 23 yes Figure 18 A sectional view along the b1-b2 direction, optionally, refer to Figure 18 , Figure 22 and Figure 23 The first terminal of the driving transistor T4 is connected to the third metal block M31 through the third via V3, which penetrates the first insulating layer 104, the second insulating layer 105, and the third insulating layer 106. This facilitates the connection between the first terminal of the driving transistor T4 and the third metal block M31, and also facilitates the connection between the driving transistor T4 and the first power line VSS.

[0268] Figure 24 yes Figure 18 A sectional view along the e1-e2 direction, optionally, refer to Figure 18 , Figure 22 and Figure 23The control electrode of the driving transistor T4 is connected to the first connection part L1 through the fourth via V4, and the first connection part L1 is also connected to the first electrode of the threshold compensation transistor T3 through the fifth via V5.

[0269] The fourth via V4 penetrates the second insulating layer 105 and the third insulating layer 106, and the fifth via V5 sequentially penetrates the third insulating layer 106, the second insulating layer 105, and the first insulating layer 104. This allows the control electrode of the driving transistor T4 to be connected to the first electrode of the threshold compensation transistor T3 via the first connection portion L1, thereby facilitating the threshold compensation transistor T3 to reset and perform threshold compensation on the driving transistor T4.

[0270] Based on the above technical solutions, Figure 25 yes Figure 19 A sectional view along the f1-f2 direction. Figure 26 This is a schematic diagram of the layout structure of the third conductive layer, the second active layer, and the sixth insulating layer of an array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 25 and Figure 26 The array substrate also includes a fourth conductive layer M4 and a fifth conductive layer M5 located on the side of the third conductive layer M3 away from the substrate 101; the array substrate also includes a fourth insulating layer 107 located between the third conductive layer M3 and the second active layer 103, a fifth insulating layer 108 located between the second active layer 103 and the fourth conductive layer M4, and a sixth insulating layer 109 located on the side of the fourth conductive layer M4 away from the substrate 101.

[0271] The fifth conductive layer M5 includes multiple data transmission lines Data extending along the second direction Y. The first terminal of the data writing transistor T1 is connected to the data transmission lines Data through a sixth via V6 that penetrates the sixth insulating layer 109 and the fifth insulating layer 108. This facilitates the connection between the data writing transistor T1 and the data transmission lines Data, allowing the data writing transistor T1 to transmit the data voltage Vdata on the data transmission lines Data to the control terminal of the driving transistor T4, enabling the driving transistor T4 to generate a drive current based on the data voltage Vdata.

[0272] Figure 27 This is a schematic diagram of the layout structure of the fifth conductive layer of an array substrate provided in an embodiment of the present invention. Figure 28 yes Figure 14 A sectional view along the h1-h2 direction, optionally, refer to Figure 26 , Figure 27 and Figure 28The fifth conductive layer M5 also includes a third connection portion L3 extending along the first direction X and a fourth connection portion L4 extending along the second direction Y. The second terminal of the data writing transistor T1 is connected to the third connection portion L3 through the seventh via V7. The end of the third connection portion L3 away from the seventh via V7 is connected to the second connection portion L2 through the eighth via V8. The second connection portion L2 is connected to the second terminal of the coupling capacitor C1 through the ninth via V9.

[0273] The seventh via V7 penetrates the sixth insulating layer 109 and the fifth insulating layer 108; the eighth via V8 penetrates the sixth insulating layer 109, the fifth insulating layer 108 and the fourth insulating layer 107; and the ninth via V9 penetrates the third insulating layer 106. This facilitates the connection between the data writing transistor T1 and the second terminal of the coupling capacitor C1.

[0274] Optionally, refer to Figure 28 The orthographic projections of the ninth via V9 and the first via V1 on the substrate 101 overlap. This improves space utilization, thereby increasing the pixel density of the display panel formed by the array substrate.

[0275] Figure 29 yes Figure 14 A sectional view along the h3-h4 direction, optionally, refer to Figure 26 and Figure 29 The first electrode of the light-emitting control transistor T5 is connected to the fourth connection part L4 through the tenth via V10, and the end of the fourth connection part L4 away from the tenth via V10 is connected to the fifth connection part L5 through the eleventh via V11.

[0276] The tenth via V10 passes through the sixth insulating layer 109 and the fifth insulating layer 108 in sequence, and the eleventh via V11 passes through the sixth insulating layer 109, the fifth insulating layer 108 and the fourth insulating layer 107 in sequence. This facilitates the connection between the light-emitting control transistor T5 and the driving transistor T4.

[0277] Optionally, such as Figure 29 As shown, the second terminal of the light-emitting control transistor T5 is electrically connected to the first terminal 210 of the light-emitting element 200 through a twelfth via V12 penetrating the sixth insulating layer 109 and the fifth insulating layer 108. This facilitates the connection between the light-emitting control transistor T5 and the first terminal 210 of the light-emitting element 200. The first terminal 210 of the light-emitting element 200 is the first end of the light-emitting element 200, and it can be either an anode or a cathode.

[0278] Optionally, such as Figure 29As shown, the array substrate also includes a first planarization layer PLN1 located on the side of the fifth conductive layer M5 facing away from the substrate 101, a sixth conductive layer M6 located on the side of the first planarization layer PLN1 facing away from the substrate 101, a second planarization layer PLN2 located on the side of the sixth conductive layer M6 facing away from the substrate 101, and a pixel definition layer PDL located on the side of the second planarization layer PLN2 facing away from the substrate 101. The pixel definition layer PDL is used to define the size of the light-emitting element 200, and the first electrode 210 of the light-emitting element 200 is connected to the second electrode of the light-emitting control transistor T5 through a conductive connection portion located on the sixth conductive layer M6.

[0279] This invention also provides a method for driving a pixel circuit, which is used to drive the pixel circuit provided in any embodiment of this invention. Figure 30 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, see reference. Figure 30 The driving methods for pixel circuits include:

[0280] S1000. During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module.

[0281] Specifically, the first power line VDD is used to transmit a first power signal. By setting the voltage of the first power signal to be different in at least two driving phases, the first power line VDD can transmit different voltages in a time-division manner. The first power signal includes a second reset voltage and a first power supply voltage. For example, in the reset phase, the first power signal is the second reset voltage. The second reset voltage is transmitted to the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, thereby resetting the control terminal of the drive module 110. That is, the threshold compensation module 120 resets the drive module 110.

[0282] S2000. In the threshold compensation stage, the threshold compensation module performs threshold compensation on the drive module based on the first power supply signal.

[0283] The voltage of the first power signal is different during the reset phase and other phases. The first power signal includes a second reset voltage and a first power supply voltage. The first power line is used to transmit the second reset voltage and the first power supply voltage to the first terminal of the drive module in a time-division multiplexing manner.

[0284] Specifically, in the threshold compensation stage, the first power signal is the first power supply voltage. This first power supply voltage charges the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, making the voltage at the control terminal of the drive module 110 a voltage related to the first power supply voltage and the threshold voltage of the transistors in the drive module 110. This achieves threshold compensation for the drive module 110, meaning the threshold compensation module 120 performs threshold compensation on the drive module 110. In this way, the threshold compensation module 120 performs time-sharing reset and threshold compensation on the drive module 110. This eliminates the need for numerous modules for compensation and reset, reducing the number of transistors and improving the pixel density of the display panel corresponding to the pixel circuit. Therefore, while reducing the number of components in the pixel circuit, it ensures that the pixel circuit can be reset and compensated, thus ensuring the normal operation of the pixel circuit while maintaining a high pixel density in the display panel, thereby improving the performance of the display panel.

[0285] Based on the above technical solution, optionally, during the reset phase, the first power supply signal is the second reset voltage, and during the remaining phases, the first power supply signal is the first power supply voltage.

[0286] During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module, including:

[0287] During the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the drive module.

[0288] Specifically, during the reset phase, the first power supply signal is the second reset voltage. The second reset voltage is transmitted to the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, thereby resetting the control terminal of the drive module 110. That is, the threshold compensation module 120 resets the drive module 110.

[0289] During the threshold compensation stage, the threshold compensation module performs threshold compensation on the drive module based on the first power supply signal, including:

[0290] Optionally, during the threshold compensation stage, the threshold compensation module performs threshold compensation on the drive module based on the first power supply voltage.

[0291] Specifically, during the threshold compensation stage, the first power supply signal is the first power supply voltage. This first power supply voltage charges the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, making the voltage at the control terminal of the drive module 110 a voltage related to the first power supply voltage and the threshold voltage of the transistor in the drive module 110. This achieves threshold compensation for the drive module 110; that is, the threshold compensation module 120 performs threshold compensation on the drive module 110. Thus, the threshold compensation module 120 performs time-sharing reset and threshold compensation on the drive module 110.

[0292] Based on the above technical solution, optionally, during the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module, and the data writing module transmits the first reset voltage to the coupling module, including:

[0293] Step a11: In the first sub-stage of the reset phase, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage;

[0294] Step a12: In the second sub-stage of the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the drive module to reset the control terminal of the drive module.

[0295] Step a13: In the third sub-stage of the reset phase, the data writing module transmits the first reset voltage to the coupling module.

[0296] Specifically, in the first sub-stage of the reset phase, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage. That is, at the beginning of the reset phase, the first power supply signal becomes the second reset voltage, thus facilitating the reset of the drive module 110 based on the second reset voltage. After the first power supply signal becomes the second reset voltage, in the second sub-stage of the reset phase, the threshold compensation module 120 transmits the second reset voltage to the control terminal of the drive module 110. That is, the second reset voltage is transmitted to the control terminal of the drive module 110 through the drive module 110 and the threshold compensation module 120, which can clear the residual voltage at the control terminal of the drive module 110 and realize the reset of the drive module 110. In the third sub-stage, the first reset voltage Vini is transmitted to the coupling module 140. For example, if the drive module 110 requires a lower voltage for reset, and the first reset voltage Vini is greater than the second reset voltage, then in the third sub-stage, through the coupling effect of the coupling module 140, the voltage at the control terminal of the drive module 110 is slightly increased, but still remains a lower voltage, thus realizing the reset of the control terminal of the drive module 110.

[0297] Optionally, the second reset voltage is less than the first reset voltage.

[0298] Optionally, in a reset phase, the duration of the second sub-phase is longer than the duration of the third sub-phase.

[0299] Optionally, in a reset phase, the duration of the second sub-phase is longer than the duration of the first sub-phase.

[0300] This invention also provides a display panel. Figure 31 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 31As shown, the display panel includes the array substrate provided in any of the above embodiments. The display panel can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, or digital photo frame. Since the display panel includes the array substrate provided in any embodiment of the present invention, it possesses the same beneficial effects as the array substrate provided in any embodiment of the present invention, which will not be elaborated further here.

[0301] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0302] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized by comprising: include: A driving module, wherein a first end of the driving module is connected to a first power line; wherein, in each driving cycle, the voltage of a first power signal on the first power line is different in at least two driving phases; A threshold compensation module is connected between the second end of the drive module and the control end of the drive module. The threshold compensation module is used to perform time-division resetting and threshold compensation on the drive module. The first power signal includes a second reset voltage and a first power supply voltage; the first power line is used to transmit the second reset voltage and the first power supply voltage to the first terminal of the drive module in a time-division multiplexing manner. The voltage of the first power supply signal changes from the first power supply voltage to the second reset voltage in the first sub-stage of the reset phase; The threshold compensation module is used to transmit the second reset voltage to the control terminal of the drive module in the second sub-stage of the reset phase, so as to reset the control terminal of the drive module. The second sub-stage follows the first sub-stage; The threshold compensation module is also used to perform threshold compensation on the drive module during the threshold compensation stage, wherein the voltage of the first power supply signal changes from the second reset voltage to the first power supply voltage during the threshold compensation stage.

2. The pixel circuit according to claim 1, characterized in that, During the reset phase of one drive cycle, the first power supply signal is the second reset voltage; during the remaining phases of the drive cycle, the first power supply signal is the first power supply voltage.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a data writing module and a coupling module; the first end of the data writing module is connected to a data voltage or a first reset voltage, and the coupling module is connected between the second end of the data writing module and the control end of the driving module; the data writing module is used to transmit the data voltage and the first reset voltage to the coupling module in a time-division manner.

4. The pixel circuit of claim 3, wherein, The data writing module is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset phase, so as to reset the control terminal of the drive module through the coupling module.

5. The pixel circuit of claim 4, wherein, The third sub-stage is located after the second sub-stage.

6. The pixel circuit of claim 5, wherein, In one of the reset phases, the duration of the second sub-phase is greater than the duration of the third sub-phase.

7. The pixel circuit of claim 6, wherein, In one of the reset phases, the duration of the second sub-phase is greater than the duration of the first sub-phase.

8. The pixel circuit of claim 7, wherein, The data writing module includes a data writing transistor, the first terminal of which is connected to the data voltage and / or the first reset voltage, and the second terminal of which is connected to the coupling module; the control terminal of the data writing transistor is connected to the first scan line; the data writing transistor is used to transmit the data voltage and the first reset voltage to the coupling module in a time-division manner.

9. The pixel circuit of claim 8, wherein, The data writing transistor is used to transmit the data voltage to the coupling module during the data writing phase and to transmit the first reset voltage to the coupling module during at least a portion of the reset phase.

10. The pixel circuit of claim 9, wherein, The data writing transistor is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset phase.

11. The pixel circuit of claim 7, wherein, The data writing module includes a data writing transistor and a reset transistor; The control electrode of the data writing transistor is connected to the first scan line, the first electrode of the data writing transistor is connected to the data voltage, and the second electrode of the data writing transistor is connected to the coupling module; the data writing transistor is used to transmit the data voltage to the coupling module during the data writing stage, and the coupling module is used to couple the data voltage to the control terminal of the driving module; The first terminal of the reset transistor is connected to the first reset voltage, and the second terminal of the reset transistor is connected to the coupling module; the reset transistor is used to transmit the first reset voltage to the coupling module during at least a portion of the reset phase.

12. The pixel circuit of claim 11, wherein, The reset transistor is used to transmit the first reset voltage to the coupling module in the third sub-stage of the reset phase.

13. The pixel circuit of claim 12, wherein, The control electrode of the reset transistor is connected to the second scan line.

14. The pixel circuit of claim 13, wherein, The threshold compensation module includes a threshold compensation transistor, the control electrode of which is connected to the third scan line; the threshold compensation transistor is connected between the second terminal of the driving module and the control terminal of the driving module.

15. The pixel circuit of claim 14, wherein, The threshold compensation transistor is of the same type as the reset transistor.

16. The pixel circuit of claim 15, wherein, Both the threshold compensation transistor and the reset transistor are of type N or P.

17. The pixel circuit of claim 16, wherein, The start time of the effective level of the second scan signal on the second scan line is delayed by one line time relative to the start time of the effective level of the third scan signal on the third scan line; the second scan signal and the third scan signal have the same period and the same waveform.

18. The pixel circuit of claim 17, wherein, The second scan line and the third scan line extend along the first direction. In two adjacent pixel circuits in the second direction, the third scan line corresponding to one pixel circuit is connected to the second scan line corresponding to the other pixel circuit. The first direction intersects the second direction.

19. The pixel circuit of claim 7, wherein, The second reset voltage is less than the first reset voltage.

20. The pixel circuit of claim 7, wherein, The driving module includes a driving transistor, the control electrode of the driving transistor is connected to the coupling module, the first electrode of the driving transistor is connected to the first power supply signal, and the second electrode of the driving transistor is connected to the threshold compensation module.

21. The pixel circuit of claim 20, wherein, The coupling module includes a coupling capacitor, the first terminal of which is connected to the control terminal of the driving transistor, and the second terminal of which is connected to the data writing module.

22. The pixel circuit of claim 21, wherein, The pixel circuit also includes a storage module; The first end of the storage module is connected to the first power signal, and the second end of the storage module is connected to the second end of the coupling module or the control end of the drive module. The first end of the coupling module is connected to the control end of the drive module.

23. The pixel circuit of claim 22, wherein, The pixel circuit also includes a light-emitting control module, the control terminal of which is connected to the light-emitting control line, and the light-emitting control module is connected between the second terminal of the driving module and the light-emitting element.

24. The pixel circuit according to claim 23, characterized in that, The storage module includes a storage capacitor, the first terminal of which is connected to the first power signal, and the second terminal of which is connected to the second end of the coupling module.

25. The pixel circuit of claim 24, wherein, The light-emitting control module includes a light-emitting control transistor, the control electrode of which is connected to the light-emitting control line, and the light-emitting control transistor is connected between the second terminal of the driving module and the light-emitting element.

26. The pixel circuit according to any one of claims 8-12, characterized in that, The driving module includes a driving transistor, the active layer material of which is different from that of the data writing transistor.

27. The pixel circuit of claim 26, wherein, The active layer of the driving transistor comprises polycrystalline silicon semiconductor material, and the active layer of the data writing transistor comprises oxide semiconductor material.

28. An array substrate comprising the pixel circuit according to any one of claims 1 to 27, characterized by, include: Substrate; The first active layer is located on one side of the substrate. The first active layer includes a first active region, which has a channel region for driving transistors and a channel region for threshold compensation transistors. A first conductive layer is located on the side of the first active layer opposite to the substrate. The first conductive layer includes a first metal block forming the control electrode of the driving transistor and a third scan line forming the control electrode of the threshold compensation transistor. The third scan line extends along a first direction. The channel region of the driving transistor is located at the orthogonal projection of the first metal block onto the first active region. The channel region of the threshold compensation transistor is located at the orthogonal projection of the third scan line onto the first active region. The first metal block is connected to the first electrode of the threshold compensation transistor through a first connection portion. The second electrode of the driving transistor is connected to the second electrode of the threshold compensation transistor through the first active region. The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a second metal block forming the second electrode of a coupling capacitor. The second metal block is reused as the first electrode of the coupling capacitor. The orthogonal projection of the second metal block on the substrate covers the orthogonal projection of the first metal block on the substrate. The second active layer is located on the side of the second conductive layer away from the substrate. The second active layer includes a third active region, which has a channel region for a data write transistor. A fourth conductive layer is located on the side of the second active layer away from the substrate. The fourth conductive layer includes a first scan line forming the control electrode of the data writing transistor. The first scan line extends along the first direction. The channel region of the data writing transistor is located at the orthogonal projection of the first scan line onto the third active region. The second electrode of the data writing transistor is connected to the second metal block through a second connection portion. The first active layer and the second active layer are made of different materials.

29. The array substrate of claim 28, wherein, The first active layer further includes a second active region, which includes the channel region of a reset transistor, and the second terminal of the reset transistor is connected to the second terminal of the coupling capacitor; The first conductive layer further includes a second scan line extending along the first direction, and the channel region of the reset transistor is located at the orthogonal projection of the second scan line onto the second active region.

30. The array substrate of claim 29, wherein, The extension direction of the threshold compensation transistor channel region is perpendicular to the extension direction of the reset transistor channel region.

31. The array substrate of claim 30, wherein, In the second direction, the threshold compensation transistor channel region and the reset transistor channel region are distributed on both sides of the channel region of the driving transistor, and the first direction intersects the second direction.

32. The array substrate of claim 31, wherein, The first metal block includes a first protrusion located at one end of the first metal block facing the threshold compensation transistor, and the first electrode of the threshold compensation transistor is connected to the first protrusion.

33. The array substrate according to claim 32, characterized in that, The second metal block includes a second protrusion located at one end of the second metal block facing the reset transistor, and the second electrode of the reset transistor is electrically connected to the second protrusion.

34. The array substrate according to claim 33, characterized in that, The second active layer further includes a fourth active region, which includes the channel region of the light-emitting control transistor. The third active region and the fourth active region are spaced apart and both extend along the second direction.

35. The array substrate of claim 34, wherein, The orthographic projections of the third active region and the fourth active region on the substrate both overlap with the orthographic projections of the first active region on the substrate. The fourth conductive layer further includes a light-emitting control line extending along the first direction, wherein the channel region of the light-emitting control transistor is located at the orthogonal projection of the light-emitting control line into the fourth active region.

36. The array substrate of claim 35, wherein, The channel region of the driving transistor is shaped like a zigzag, and the third active region is L-shaped.

37. The array substrate of claim 36, wherein, The array substrate further includes a third conductive layer located between the second conductive layer and the second active layer; The third conductive layer includes a third metal block forming a first electrode of a storage capacitor. The orthographic projection of the third metal block on the substrate covers the orthographic projection of the second metal block on the substrate. The second metal block is reused as the second electrode of the storage capacitor. In the first direction, adjacent third metal blocks are interconnected, and the interconnected third metal blocks are multiplexed as a first power line to transmit a first power signal. The first terminal of the storage capacitor is connected to the first terminal of the driving transistor.

38. The array substrate according to claim 37, characterized in that, The third metal block includes a third protrusion that extends toward the third active region.

39. The array substrate of claim 38, wherein, Both the first connecting portion and the second connecting portion are located in the third conductive layer.

40. The array substrate of claim 39, wherein, The orthographic projections of the third and fourth active regions onto the substrate are located within the orthographic projection range of the third metal block onto the substrate.

41. The array substrate of claim 40, wherein, The third scan line includes a main body and an extension. The main body extends in the same direction as the channel region of the threshold compensation transistor. The extension extends in a direction perpendicular to the extension direction of the main body, and the channel region of the threshold compensation transistor is located at the orthogonal projection of the extension onto the first active region.

42. The array substrate of claim 41, wherein, The main body portion has the same width as the first scan line.

43. The array substrate of claim 42, wherein, The second conductive layer further includes multiple reset power signal lines extending along a first direction. The orthographic projection of the reset power signal lines on the substrate overlaps with the orthographic projection of the first electrode of the reset transistor on the substrate. The first electrode of the reset transistor is connected to the reset power signal lines; or The third conductive layer also includes multiple reset power signal lines, the orthographic projection of the reset power signal lines on the substrate overlaps with the orthographic projection of the first electrode of the reset transistor on the substrate, and the first electrode of the reset transistor is connected to the reset power signal lines; The reset power signal line extends along the first direction, and the end of the second active region away from the second metal block is electrically connected to one of the reset power signal lines.

44. The array substrate of claim 43, wherein, The array substrate further includes a first insulating layer located between the first active layer and the first conductive layer, a second insulating layer located between the first conductive layer and the second conductive layer, and a third insulating layer located between the second conductive layer and the third conductive layer. The second terminal of the reset transistor is connected to the second metal block through a first via penetrating the first and second insulating layers. The first terminal of the reset transistor is connected to the reset power signal line through a second via. The second via penetrates the first and second insulating layers, or the second via penetrates the first, second, and third insulating layers.

45. The array substrate of claim 44, wherein, The first electrode of the driving transistor is connected to the third metal block through a third via, which penetrates the first insulating layer, the second insulating layer and the third insulating layer.

46. ​​The array substrate according to claim 45, characterized in that, The control electrode of the driving transistor is connected to the first connection portion through a fourth via, and the first connection portion is also connected to the first electrode of the threshold compensation transistor through a fifth via. The fourth via penetrates the second and third insulating layers, and the fifth via sequentially penetrates the third, second, and first insulating layers.

47. The array substrate of claim 46, wherein, The array substrate further includes a fourth conductive layer and a fifth conductive layer located on the side of the third conductive layer away from the substrate; the array substrate further includes a fourth insulating layer located between the third conductive layer and the second active layer, a fifth insulating layer located between the second active layer and the fourth conductive layer, and a sixth insulating layer located on the side of the fourth conductive layer away from the substrate. The fifth conductive layer includes multiple data transmission lines extending along the second direction, and the first electrode of the data writing transistor is connected to the data transmission lines through a sixth via penetrating the sixth insulating layer and the fifth insulating layer.

48. The array substrate of claim 47, wherein, The fifth conductive layer further includes a third connection portion extending along a first direction and a fourth connection portion extending along a second direction. The second terminal of the data writing transistor is connected to the third connection portion through a seventh via. The end of the third connection portion away from the seventh via is connected to the second connection portion through an eighth via. The second connection portion is connected to the second terminal of the coupling capacitor through a ninth via. The eighth via penetrates the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in sequence; the seventh via penetrates the sixth insulating layer and the fifth insulating layer; and the ninth via penetrates the third insulating layer.

49. The array substrate of claim 48, wherein, The ninth via overlaps with the orthographic projection of the first via on the substrate.

50. The array substrate of claim 49, wherein, The first electrode of the light-emitting control transistor is connected to the fourth connection part through the tenth via, and the end of the fourth connection part away from the tenth via is connected to the fifth connection part through the eleventh via. The tenth via penetrates the sixth and fifth insulating layers in sequence, and the eleventh via penetrates the sixth, fifth, and fourth insulating layers in sequence.

51. The array substrate of claim 50, wherein, The second electrode of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through a twelfth via penetrating the sixth insulating layer and the fifth insulating layer.

52. A driving method of a pixel circuit, comprising: The method for driving the pixel circuit according to any one of claims 1-27 includes: During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module; During the threshold compensation phase, the threshold compensation module performs threshold compensation on the drive module based on the first power signal; The voltage of the first power signal is different in the reset phase and other phases. The first power signal includes a second reset voltage and a first power supply voltage. The first power line is used to transmit the second reset voltage and the first power supply voltage to the first terminal of the drive module in a time-division multiplexing manner.

53. The method of claim 52, wherein, During the reset phase, the first power signal is the second reset voltage; during the remaining phases, the first power signal is the first power supply voltage. During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module, including: During the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the drive module; During the threshold compensation phase, the threshold compensation module performs threshold compensation on the drive module based on the first power signal, including: During the threshold compensation phase, the threshold compensation module performs threshold compensation on the drive module based on the first power supply voltage.

54. The method of claim 53, wherein, During the reset phase, the threshold compensation module transmits the first power signal to the control terminal of the drive module, and the data writing module transmits the first reset voltage to the coupling module, including: In the first sub-stage of the reset phase, the voltage of the first power supply signal jumps from the first power supply voltage to the second reset voltage; In the second sub-stage of the reset phase, the threshold compensation module transmits the second reset voltage to the control terminal of the drive module to reset the control terminal of the drive module; In the third sub-stage of the reset phase, the data writing module transmits the first reset voltage to the coupling module.

55. The method of claim 54, wherein, The second reset voltage is less than the first reset voltage.

56. The method of claim 55, wherein, In one of the reset phases, the duration of the second sub-phase is greater than the duration of the third sub-phase.

57. The method of claim 56, wherein, In one of the reset phases, the duration of the second sub-phase is greater than the duration of the first sub-phase.

58. A display panel, comprising: Includes the array substrate as described in any one of claims 28-51.

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