Gate drive circuit, display panel and display device

Abstract

The invention provides a gate drive circuit, a display panel and a display device.The gate drive circuit comprises a plurality of cascaded shift registers, each shift register comprises a cascade selection module and a row drive module which are electrically connected, the first control end of each cascade selection module is used for inputting a first control signal, and the second control end of each cascade selection module is used for inputting a second control signal; the first control end of the cascade selection module is used for inputting a first control signal, the second control end of the cascade selection module is used for inputting a second control signal, the output end of the cascade selection module is used for outputting a scanning control signal, and under the condition that the first control signal is a first level and the second control signal is a second level, the shift registers are cascaded in a first cascade mode; under the condition that the first control signal is the second level and the second control signal is the first level, the shift registers are cascaded in a second cascade mode; and the row driving module is used for outputting a gate driving signal under the action of the scanning control signal. According to the circuit, switching of two sets of cascade relations can be realized on the same panel, and different function requirements of the display panel are met.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel and a display device. Background Art

[0002] Display panels mostly use array substrate gate driver (Gate Driver on Array, GOA) technology. GOA technology uses the thin film transistor (Thin Film Transistor, TFT) liquid crystal display array process to manufacture the gate scanning drive circuit on the thin film transistor array substrate to achieve line-by-line scanning driving technology. It has the advantages of reducing production costs and realizing narrow frame design of the panel.

[0003] The existing gate drive circuit is composed of a plurality of cascaded shift registers: SR(1), SR(2) ... SR(n), SR(n+1) ... SR(N-1), SR(N) (a total of N shift registers, 1≤n≤N), and each shift register SR(n) is used to provide a gate-on signal to a gate line connected to a signal output terminal Output_n of the shift register SR(n) of that stage to turn on the TFT of the pixel area of ​​the corresponding row.

[0004] However, the existing shift register cascade mode is fixed to one, and it is not possible to take into account both the high performance and the low cost of the display panel under the functional requirements of different display panels. Summary of the invention

[0005] The main purpose of the present application is to provide a gate drive circuit, a display panel and a display device, so as to at least solve the problem that the cascading method of the shift register in the prior art is fixed in only one way and it is impossible to take into account both the high performance and the low cost of the display panel under the functional requirements of different display panels.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a gate driving circuit is provided, comprising a plurality of cascaded shift registers, the shift register comprising an electrically connected cascade selection module and a row driving module, wherein the first control end of the cascade selection module is used to input a first control signal, the second control end of the cascade selection module is used to input a second control signal, the output end of the cascade selection module is used to output a scan control signal, and when the first control signal is a first level and the second control signal is a second level, each shift register is cascaded in a first cascade manner, and when the first control signal is a second level and the second control signal is a first level, each shift register is cascaded in a second cascade manner; the row driving module is used to output a gate driving signal under the action of the scan control signal, and the gate driving signal is used to drive the display element of the current row to display or not display.

[0007] According to another aspect of the present application, a display panel is provided, comprising: an array substrate and an opposing substrate arranged opposite to each other; the array substrate comprises a base substrate and any one of gate driving circuits located on the base substrate.

[0008] According to another aspect of the present application, a display device is provided, including: a display area and any type of display panel.

[0009] Applying the technical solution of the present application, the above-mentioned gate drive circuit includes a plurality of cascaded shift registers, and the shift registers include an electrically connected cascade selection module and a row drive module, wherein, when the first control signal input to the first control end of the cascade selection module is at the first level and the second control signal input to the second control end of the cascade selection module is at the second level, each shift register is cascaded in a first cascade manner, and when the first control signal is at the second level and the second control signal is at the first level, each shift register is cascaded in a second cascade manner; the row drive module outputs a gate drive signal according to a scanning control signal output by the cascade selection module. The circuit can realize the switching of two sets of cascade relationships on the same panel, meet the different functional requirements of the display panel, and can simultaneously meet the high performance requirements and low cost requirements of the display panel, solving the problem that the cascade mode of the shift register in the prior art is only fixed in one way, and the high performance and low cost of the display panel cannot be taken into account at the same time under the functional requirements of different display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0011] Figure 1 A schematic structural diagram of a gate driving circuit provided in an embodiment of the present application is shown;

[0012] Figure 2 A schematic structural diagram of another gate driving circuit provided in an embodiment of the present application is shown;

[0013] Figure 3 A schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application is shown;

[0014] Figure 4 A schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application is shown;

[0015] Figure 5 A schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application is shown;

[0016] Figure 6A schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application is shown;

[0017] Figure 7 A schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application is shown;

[0018] Figure 8 A schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application is shown;

[0019] Fig. 9 A timing diagram of a gate driving circuit with a clock number of 2phase provided in an embodiment of the present application is shown;

[0020] Fig.10 A timing diagram of a gate driving circuit with a clock number of 4 phases provided in an embodiment of the present application is shown;

[0021] Fig.11 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown;

[0022] Fig.12 A schematic structural diagram of a display device provided in an embodiment of the present application is shown.

[0023] The above drawings include the following reference numerals:

[0024] 01, cascade selection module; 10, forward scanning signal input unit; 11, reverse scanning signal input unit; 02, row driving module; 20, scanning control module; 21, reset module; 22, output control module; 221, first switch unit; 222, second switch unit; 223, third switch unit; 23, output module; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; M9, ninth transistor; M10, tenth transistor; M11, eleventh transistor; M12, twelfth transistor; M13, thirteenth transistor; M14, fourteenth transistor; M15, fifteenth transistor; M16, sixteenth transistor; C1, first capacitor; C2, second capacitor. 100, substrate; 200, gate driving circuit; 300, display panel. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] As introduced in the background technology, in order to save costs, the prior art usually adopts an ASG circuit to drive the display panel to emit light. However, as the panel size increases, the resolution increases, and the reliability requirements increase, the number of clocks required by the ASG circuit continues to increase, resulting in increasing costs. In addition, during the use of the display panel, the performance of the display panel is not required to be too high at some times, which will lead to unnecessary consumption of so much cost, but due to the fixed cascade mode of the display panel, the cost increases. That is, the display panel in the prior art can only fix one cascade mode. When the display panel adopts a low-cost and low-performance cascade mode, it cannot meet the user's high-performance requirements. When the display panel adopts a high-cost and high-performance cascade mode, it cannot meet the user's low-cost requirements.

[0029] To solve the problem in the prior art that the shift register cascade mode is fixed to one and that high performance and low cost of the display panel cannot be taken into account at the same time under the functional requirements of different display panels, the embodiments of the present application provide a gate drive circuit, a display panel and a display device.

[0030] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0031] An embodiment of the present invention provides a shift register, such as Figure 1As shown, it includes multiple cascaded shift registers, and the shift register includes an electrically connected cascade selection module 01 and a row driving module 02, wherein the first control end of the cascade selection module 01 is used to input the first control signal RES1, the second control end of the cascade selection module 01 is used to input the second control signal RES2, and the output end of the cascade selection module 01 is used to output the scan control signal. When the first control signal RES1 is at the first level and the second control signal RES2 is at the second level, each shift register is cascaded in a first cascade manner, and when the first control signal RES1 is at the second level and the second control signal RES2 is at the first level, each shift register is cascaded in a second cascade manner; the row driving module 02 is used to output a gate driving signal Gout under the action of the scan control signal, and the gate driving signal Gout is used to drive the display element of the current row to display or not display.

[0032] The above-mentioned gate driving circuit of the present application includes a plurality of cascaded shift registers, and the shift registers include an electrically connected cascade selection module and a row driving module, wherein, when the first control signal RES1 input to the first control end of the cascade selection module is at the first level and the second control signal RES2 input to the second control end of the cascade selection module is at the second level, each shift register is cascaded in a first cascade manner, and when the first control signal RES1 is at the second level and the second control signal RES2 is at the first level, each shift register is cascaded in a second cascade manner; the row driving module outputs a gate driving signal Gout according to a scanning control signal output by the cascade selection module. The circuit can realize the switching of two sets of cascade relationships on the same panel, meet the different functional requirements of the display panel, and can simultaneously meet the high performance requirements and low cost requirements of the display panel, solving the problem that the cascade mode of the shift register in the prior art is only fixed in one way, and the high performance and low cost of the display panel cannot be taken into account at the same time under the functional requirements of different display panels.

[0033] The first level is a high level, the second level is a low level, and the number of pulses in the first cascade mode is half of the number of pulses in the second cascade mode, that is, when the number of pulses in the first cascade mode is 2phase, the number of pulses in the second cascade mode is 4phase, and so on. In addition, since the clock signals of the gate drive circuit in this example are multiple sets of complementary clock signals, the number of pulses in the first cascade mode and the second cascade mode are both even numbers.

[0034] In some instances, the number of pulses in the first cascade mode is 2phase, and the number of pulses in the second cascade mode is 4phase. When the shift registers are cascaded in the first cascade mode, the Nth row of shift registers is cascaded with the N+1th row of shift registers, and the clock signals of the Nth row of shift registers and the N+2th row of shift registers are the same; when the shift registers are cascaded in the second cascade mode, the Nth row of shift registers is cascaded with the N+2th row of shift registers, and the clock signals of the Nth row of shift registers and the N+4th row of shift registers are the same.

[0035] In some instances, the number of pulses in the first cascade mode is 4phase, and the number of pulses in the second cascade mode is 8phase. When the shift registers are cascaded in the first cascade mode, the Nth row of shift registers are cascaded with the N+2th row of shift registers, and the clock signals of the Nth row of shift registers and the N+4th row of shift registers are the same; when the shift registers are cascaded in the second cascade mode, the Nth row of shift registers are cascaded with the N+4th row of shift registers, and the clock signals of the Nth row of shift registers and the N+8th row of shift registers are the same.

[0036] That is, the number of rows between two adjacent cascaded shift registers is half the number of pulses in the current cascade mode, and the clock signal of the shift register corresponding to the current row is the same as the clock signal of the shift register corresponding to the row after one pulse number.

[0037] In some instances, such as Figure 2 As shown, the cascade selection module 01 includes: a positive scan signal input unit 10, the positive scan signal input unit 10 is used to convert the first positive scan signal G under the control of the first control signal RES1 n-i The second positive scan signal G is input to the row driving module 02, and under the control of the second control signal RES2, the ... the second positive scan signal G is input to the row driving module 02, and the second positive scan signal G is input to the row driving module 02, and the second positive scan signal G is input to the row driving module n-2i Input to the row driving module 02, the first positive scanning signal G n-i When the shift registers are cascaded in the first cascade mode, the first gate drive signal Gout1 output by the previous shift register and the second positive scan signal G n-2i When each shift register is cascaded in a second cascade manner, the second gate drive signal Gout2 output by the previous shift register; the reverse scan signal input unit 11, the reverse scan signal input unit 11 is used to convert the first reverse scan signal Gout2 into the first gate drive signal Gout2 under the control of the first control signal RES1; n+i The second reverse scan signal G is input to the row driving module 02, and under the control of the second control signal RES2, the ... the second reverse scan signal G is input to the row driving module 02, and the second reverse scan signal G is input to the row driving module 02, and the second reverse scan signal G is input to the row driving module n+2i Input to the row driving module 02, the first reverse scan signal G n+i When the shift registers are cascaded in the first cascade mode, the third gate drive signal Gout3 output by the next stage shift register and the second reverse scan signal Gn+2i It is the fourth gate driving signal Gout4 output by the next stage shift register when the shift registers are cascaded in the second cascade manner.

[0038] Among them, when i=1, since the number of pulses of the first cascade method is half of the number of pulses of the second cascade method, the n-th shift register and the n+1-th shift register when cascaded using the second cascade method are the n-th shift register and the n+2-th shift register when cascaded using the first cascade method.

[0039] Specifically, in the display device, during forward scanning, the forward scanning input signal terminal INF of the first-stage shift register is generally used to receive the start signal, and the forward scanning input signal terminal INF of the shift registers other than the first-stage shift register is used to receive the signal output by the gate signal output terminal Gout of the previous-stage shift register. During reverse scanning, the reverse scanning input signal terminal INB of the last-stage shift register is generally used to receive the start signal, and the reverse scanning input signal terminal INB of the shift registers other than the last-stage shift register is used to receive the signal output by the gate signal output terminal Gout of the next-stage shift register.

[0040] In some instances, such as Figure 3 As shown, the positive scan signal input unit 10 includes: a first transistor M1, a gate of the first transistor M1 is used to input a first control signal RES1, and a first electrode of the first transistor M1 is used to input a first positive scan signal G n-i The second electrode of the first transistor M1 is used to be electrically connected to the positive scan signal input terminal of the row driving module 02; the second transistor M2, the gate of the second transistor M2 is used to input the second control signal RES2, and the first electrode of the second transistor M2 is used to input the second positive scan signal G n-2i The second electrode of the second transistor M2 is used to be electrically connected to the positive scan signal input terminal of the row driving module 02.

[0041] The first transistor M1 is an n-type TFT, and the second transistor M2 is an n-type TFT. When the first control signal RES1 is at a high level and the second control signal RES2 is at a low level, the first transistor M1 is turned on and the second transistor M2 is turned off. The first transistor M1 converts the first positive scan signal G n-i The first control signal RES1 is at a low level and the second control signal RES2 is at a high level, the first transistor M1 is turned off and the second transistor M2 is turned on. The second transistor M2 converts the second positive scan signal G n-2i The data are transmitted to the row driving module 02, and the shift registers are cascaded in a second cascade manner.

[0042] In some instances, such as Figure 3 As shown, the reverse scan signal input unit 11 includes: a third transistor M3, the gate of the third transistor M3 is used to input the first control signal RES1, and the first electrode of the third transistor M3 is used to input the first reverse scan signal G n+i The second electrode of the third transistor M3 is used to be electrically connected to the reverse scan signal input terminal of the row driving module 02; the fourth transistor M4, the gate of the fourth transistor M4 is used to input the second control signal RES2, and the first electrode of the fourth transistor M4 is used to input the second reverse scan signal G n+2i The second electrode of the fourth transistor M4 is used to be electrically connected to the reverse scan signal input terminal of the row driving module 02.

[0043] The third transistor M3 is an n-type TFT, and the fourth transistor M4 is an n-type TFT. When the first control signal RES1 is at a high level and the second control signal RES2 is at a low level, the third transistor M3 is turned on and the fourth transistor M4 is turned off. The third transistor M3 converts the first reverse scan signal G n+i The first control signal RES1 is at a low level and the second control signal RES2 is at a high level, the third transistor M3 is turned off and the fourth transistor M4 is turned on. The fourth transistor M4 converts the second reverse scan signal G n+2i The data are transmitted to the row driving module 02, and the shift registers are cascaded in a second cascade manner.

[0044] In some instances, such as Figure 4 As shown, the row driving module 02 includes an electrically connected scanning control module 20, a reset module 21, an output control module 22 and an output module 23, wherein the scanning control module 20 is used to provide the signal of the forward scanning control signal terminal INF to the input node N1 under the control of the signal of the forward scanning input signal terminal INF, or to provide the signal of the reverse scanning control signal terminal INB to the input node N1 under the control of the signal of the reverse scanning input signal terminal INB; the reset module 21 is used to reset the input node N1 and the gate signal output terminal Gout under the control of the reset signal RES; the output control module 22, the output module 23 and the scanning control module 20 are connected at the input node N1, the output control module 22, the output module 23 and the reset module 21 are all connected to the gate signal output terminal Gout, the gate signal output terminal Gout is used to output the gate driving signal Gout, the output control module 22 is used to control the level of the gate driving signal Gout under the control of the signal of the input node N1; the output module 23 is used to output the gate driving signal Gout under the control of the signal of the input node N1.

[0045] The output control module is used to control the level of the gate drive signal to be low level under the control of the signal of the input node.

[0046] In some instances, such as Figure 4 and Figure 5 As shown, the scanning control module 20 includes: a fifth transistor M5, the gate of the fifth transistor M5 is connected to the forward scanning input signal terminal INF, the first electrode of the fifth transistor M5 is connected to the forward scanning control signal terminal FW, and the second electrode of the fifth transistor M5 is connected to the input node N1; a sixth transistor M6, the gate of the sixth transistor M6 is connected to the reverse scanning input signal terminal INB, the first electrode of the sixth transistor M6 is connected to the reverse scanning control signal terminal BW, and the second electrode of the sixth transistor M6 is connected to the input node N1.

[0047] Among them, the fifth transistor M5 is an n-type TFT, and the sixth transistor M6 is an n-type TFT. The fifth transistor M5 is used to input the signal of the forward scan control signal terminal FW to the input node N1 under the control of the signal of the forward scan input signal terminal INF, and the sixth transistor M6 is used to input the signal of the reverse scan control signal terminal BW to the input node N1 under the control of the signal of the reverse scan input signal terminal INB.

[0048] In such Figure 6 In the illustrated embodiment, the forward scan input signal terminal INF is used to control the conduction or cutoff of the fifth transistor M5. When the fifth transistor M5 is turned on, the signal of the forward scan control signal terminal FW can be transmitted to the input node N1; the reverse scan input signal terminal INB is used to control the conduction or cutoff of the sixth transistor M6. When the sixth transistor M6 is turned on, the signal of the reverse scan control signal terminal BW can be transmitted to the input node N1.

[0049] In some instances, such as Figure 5 As shown, the output control module 22 includes: a first switch unit 221, a first end of the first switch unit 221 is connected to the input node N1, a second end of the first switch unit 221 is connected to the first node N2, a third end of the first switch unit 221 is connected to the first reference voltage terminal VGL, and a fourth end of the first switch unit 221 is connected to the gate signal output terminal Gout; a second switch unit 222, a first end of the second switch unit 222 is connected to the input node N1, a second end of the second switch unit 222 is connected to the first node N2, and a third end of the second switch unit 222 is connected to the first reference voltage terminal VGL; a third switch unit 223, a first end of the third switch unit 223 is connected to the first node N2, a second end of the third switch unit 223 is connected to the input node N1, a third end of the third switch unit 223 is connected to the first reference voltage terminal VGL, and a fourth end of the third switch unit 223 is connected to the second reference voltage terminal VGH.

[0050] The present invention is described in detail below in conjunction with specific embodiments. It should be noted that the embodiments are for better explanation of the present invention, but not for limiting the present invention.

[0051] It should be noted that in a specific implementation, the first electrode of the transistor can be used as its source and the second electrode as its drain, depending on the type of transistor and the signal of its gate; or, conversely, the first electrode of the transistor can be used as its drain and the second electrode can be used as its source, without making a specific distinction here.

[0052] It should be noted that transistors are generally divided into N-type transistors and P-type transistors, wherein the N-type transistor is turned on by a high-level signal and turned off by a low-level signal, and the P-type transistor is turned on by a low-level signal and turned off by a high-level signal.

[0053] Optionally, in the shift register provided in the embodiment of the present invention, Figure 6 As shown, the first switch unit includes: a seventh transistor M7, a gate of the seventh transistor M7 is connected to the first node N2, a first electrode of the seventh transistor M7 is connected to the input node N1, and a second electrode of the seventh transistor M7 is connected to the first reference voltage terminal VGL; an eighth transistor M8, a gate of the eighth transistor M8 is connected to the first node N2, a first electrode of the eighth transistor M8 is connected to the gate signal output terminal Gout, and a second electrode of the seventh transistor M7 is connected to the first reference voltage terminal VGL.

[0054] The seventh transistor M7 is an n-type TFT, and the eighth transistor M8 is an n-type TFT. When the signal at the first node N2 is at a high level, the seventh transistor M7 and the eighth transistor M8 are turned on, the seventh transistor M7 transmits the signal at the first reference voltage terminal VGL to the input node N1, and keeps the input node N1 at a low level, and the eighth transistor M8 transmits the signal at the first reference voltage terminal VGL to the gate signal output terminal Gout, and keeps the signal at the gate signal output terminal Gout at a low level. When the signal at the first node N2 is at a low level, the seventh transistor M7 and the eighth transistor M8 are turned off.

[0055] In some instances, such as Figure 6 As shown, the second switch unit includes: a ninth transistor M9, a gate of the ninth transistor M9 is connected to the input node N1, a first electrode of the ninth transistor M9 is connected to the first node N2, and a second electrode of the ninth transistor M9 is connected to the first reference voltage terminal VGL.

[0056] Among them, the ninth transistor M9 is an n-type TFT. When the signal of the input node N1 is at a high level, the ninth transistor M9 is turned on and transmits the signal of the first reference voltage terminal VGL to the first node N2, so that the signal of the first node N2 is at a low level, so that the seventh transistor M7 and the eighth transistor M8 are turned off under the action of the signal of the first node N2.

[0057] In some instances, such as Figure 6 As shown, the third switch unit includes: a tenth transistor M10, the gate of the tenth transistor M10 is connected to the input node N1, and the first electrode of the tenth transistor M10 is connected to the first reference voltage terminal VGL; an eleventh transistor M11, the gate of the eleventh transistor M11 is connected to the second electrode of the tenth transistor M10, the first electrode of the eleventh transistor M11 is connected to the first node N2, and the second electrode of the eleventh transistor M11 is connected to the second reference voltage terminal VGH; a twelfth transistor M12, the gate of the twelfth transistor M12 is connected to the second reference voltage terminal VGH, the first electrode of the twelfth transistor M12 is connected to the second reference voltage terminal VGH, and the second electrode of the twelfth transistor M12 is connected to the gate of the eleventh transistor M11.

[0058] Among them, the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are all n-type TFTs. The twelfth transistor M12 is turned on under the control of the signal of the second reference voltage terminal VGH, and the twelfth transistor M12 is used to transmit the signal of the second reference voltage terminal VGH to the gate of the eleventh transistor M11 under the control of the signal of the second reference voltage terminal VGH. The eleventh transistor M11 is turned on under the control of the signal of the second reference voltage terminal VGH, and the eleventh transistor M11 is used to transmit the signal of the second reference voltage terminal VGH to the first node N2 under the control of the signal of the second reference voltage terminal VGH. When the signal of the first node N2 is at a high level, the seventh transistor M7 and the eighth transistor M8 are turned on, and the seventh transistor M7 is used to transmit the signal of the first reference voltage terminal VGL to the input node N1 under the control of the signal of the first node N2. When the input node N1 is at a low level, the ninth transistor M9 and the tenth transistor M10 are turned off. At the same time, the eighth transistor M8 is used to transmit the signal of the first reference voltage terminal VGL to the gate signal output terminal Gout under the control of the signal of the first node N2, so as to ensure that the signal output by the gate signal output terminal Gout is at a low level.

[0059] In some instances, such as Figure 7As shown, the output control module 22 includes: a first switch unit 221, a first end of the first switch unit 221 is connected to the input node N1, a second end of the first switch unit 221 is connected to the first node N2, a third end of the first switch unit 221 is connected to the first reference voltage terminal VGL, and a fourth end of the first switch unit 221 is connected to the gate signal output terminal Gout; a second switch unit 222, a first end of the second switch unit 222 is connected to the input node N1, a second end of the second switch unit 222 is connected to the first node N2, and a third end of the second switch unit 222 is connected to the first reference voltage terminal VGL; a thirteenth transistor M13, a gate of the thirteenth transistor M13 is connected to the first clock signal terminal CK, a first electrode of the thirteenth transistor M13 is connected to the gate signal output terminal Gout, and a second electrode of the thirteenth transistor M13 is connected to the first reference voltage terminal VGL; a first capacitor C1, a first electrode of the first capacitor C1 is connected to the second clock signal terminal CKB, and a second electrode of the first capacitor C1 is connected to the first node N2.

[0060] The thirteenth transistor M13 is an n-type TFT. The output control module can be connected in two ways. The first connection way is: Figure 6 The second connection mode is as follows: Figure 8 The connection mode between the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the thirteenth transistor M13 and the first capacitor C1. Both connection modes can realize the control of the low level signal of the gate signal output terminal Gout.

[0061] In some instances, such as Figure 6 and Figure 8 As shown, the reset module 21 includes: a fourteenth transistor M14, the gate of the fourteenth transistor M14 is connected to the reset signal terminal RES, the first electrode of the fourteenth transistor M14 is connected to the input node N1, and the second electrode of the fourteenth transistor M14 is connected to the first reference voltage terminal VGL; a fifteenth transistor M15, the gate of the fifteenth transistor M15 is connected to the reset signal terminal RES, the first electrode of the fifteenth transistor M15 is connected to the gate signal output terminal Gout, and the second electrode of the fifteenth transistor M15 is connected to the first reference voltage terminal VGL.

[0062] Among them, the fourteenth transistor M14 and the fifteenth transistor M15 are both n-type TFTs. The fourteenth transistor is used to transmit the first reference voltage terminal VGL to the input node N1 when the signal at the reset signal terminal RES is at a high level to reset the input node N1. The fifteenth transistor M15 is used to transmit the first reference voltage terminal VGL to the gate signal output terminal Gout when the signal at the reset signal terminal RES is at a high level to reset the gate signal output terminal Gout.

[0063] In some instances, such as Figure 6 and Figure 8 As shown, the output module 23 includes: a sixteenth transistor M16, the gate of the sixteenth transistor M16 is connected to the input node N1, the first electrode of the sixteenth transistor M16 is connected to the second clock signal terminal CKB, and the second electrode of the sixteenth transistor M16 is connected to the gate signal output terminal Gout; a second capacitor C2, the first electrode of the second capacitor C2 is connected to the input node N1, and the second electrode of the second capacitor C2 is connected to the gate signal output terminal Gout.

[0064] The sixteenth transistor is an n-type TFT, and the sixteenth transistor M16 is used for transmitting the signal of the second clock signal terminal CKB to the gate signal output terminal Gout when the signal of the input node N1 is at a high level.

[0065] In some embodiments, the number of clocks of the gate driving signal Gout output by the shift register when the second cascade connection is adopted is twice the number of clocks of the gate driving signal Gout output by the shift register when the first cascade connection is adopted.

[0066] In this way, two sets of cascade relationships can be switched on the same panel to meet the different functional requirements of the display panel, and can simultaneously meet the high performance and low cost requirements of the display panel.

[0067] In some instances, the cascading mode of each shift register is a first cascading mode, wherein, when the driving mode of the gate drive circuit is forward scan drive, the gate signal output terminal Gout of the Nth shift register is electrically connected to the forward scan input signal terminal INF of the N+kth shift register, and the signal output by the gate signal output terminal Gout of the Nth shift register is used to drive the N+kth shift register, wherein N≥1, k≥1; when the driving mode of the gate drive circuit is reverse scan drive, the gate signal output terminal Gout of the M+kth shift register is electrically connected to the reverse scan input signal terminal INB in ​​the Mth shift register, and the signal output by the gate signal output terminal Gout of the M+kth shift register is used to drive the Mth shift register, wherein M≥1; wherein the high and low levels of the forward scan input signal terminal INF and the reverse scan input signal terminal INB are opposite.

[0068] Specifically, in the display device, during forward scanning, the forward scanning input signal terminal INF of the first-stage shift register is generally used to receive the start signal, and the forward scanning input signal terminal INF of the shift registers other than the first-stage shift register is used to receive the signal output by the gate signal output terminal Gout of the previous-stage shift register. During reverse scanning, the reverse scanning input signal terminal INB of the last-stage shift register is generally used to receive the start signal, and the reverse scanning input signal terminal INB of the shift registers other than the last-stage shift register is used to receive the signal output by the gate signal output terminal Gout of the next-stage shift register.

[0069] The value of k is related to the number of pulses of the shift register. k is half of the number of pulses of the shift register, and the number of pulses of the shift register is an even number. For example, when the number of pulses of the shift register is 2, k=1, and when the number of pulses of the shift register is 4, k=2.

[0070] It should be noted that Figure 6 For example, when the number of pulses of the shift register is 2, the clock signal of the second clock signal terminal CKB of the shift register corresponding to the kth row on the display panel is the same as the clock signal of the second clock signal terminal CKB of the shift register corresponding to the k+2th row on the display panel. Similarly, when the number of pulses of the shift register is 4, the clock signal of the second clock signal terminal CKB of the shift register corresponding to the kth row on the display panel is the same as the clock signal of the second clock signal terminal CKB of the shift register corresponding to the k+4th row on the display panel. That is, when the number of pulses of the shift register is j, the clock signal of the second clock signal terminal CKB of the shift register corresponding to the kth row on the display panel is the same as the clock signal of the second clock signal terminal CKB of the shift register corresponding to the k+jth row on the display panel.

[0071] In some instances, the cascading mode of each shift register is the second cascading mode, wherein, when the driving mode of the gate drive circuit is forward scan drive, the gate signal output terminal Gout of the Nth shift register is electrically connected to the forward scan input signal terminal of the N+2kth shift register, and the signal output by the gate signal output terminal Gout of the Nth shift register is used to drive the N+2kth shift register, wherein N≥1, k≥1; when the driving mode of the gate drive circuit is reverse scan drive, the gate signal output terminal Gout of the M+2kth shift register is electrically connected to the reverse scan input signal terminal in the Mth shift register, and the signal output by the gate signal output terminal Gout of the M+2kth shift register is used to drive the Mth shift register, wherein M≥1; wherein the high and low levels of the forward scan input signal terminal and the reverse scan input signal terminal are opposite.

[0072] Among them, since the number of pulses of the shift register when cascaded in the second cascade mode is twice the number of pulses of the shift register when cascaded in the first cascade mode, therefore,

[0073] When the number of pulses of the shift registers cascaded in the first cascade mode is 2, k=1, and the corresponding number of pulses of the shift registers cascaded in the first cascade mode is 4. When the driving mode of the gate drive circuit is positive scan drive, the gate signal output terminal Gout of the Nth shift register is electrically connected to the positive scan input signal terminal of the N+2th shift register, that is, when the driving mode of the gate drive circuit is positive scan drive, the gate signal output terminal Gout of the Nth shift register is electrically connected to the positive scan input signal terminal of the N+2kth shift register. Other quantitative relationships can be obtained in the same way.

[0074] Fig. 9 This is the timing diagram of the gate drive circuit using the first cascade method and a clock number of 2phase. Fig.10 The timing diagram of the gate driving circuit adopting the second cascade mode and the clock number is 4phase. Among them, Gout1 is the signal outputted from the gate signal output terminal of the shift register corresponding to the first row on the display panel, Gout2 is the signal outputted from the gate signal output terminal of the shift register corresponding to the second row on the display panel, Gout3 is the signal outputted from the gate signal output terminal of the shift register corresponding to the third row on the display panel, Gout4 is the signal outputted from the gate signal output terminal of the shift register corresponding to the fourth row on the display panel, ck1 is the clock signal inputted from the second clock signal terminal of the shift register corresponding to the first row on the display panel, ck2 is the clock signal inputted from the second clock signal terminal of the shift register corresponding to the second row on the display panel, ck3 is the clock signal inputted from the second clock signal terminal of the shift register corresponding to the third row on the display panel, and ck4 is the clock signal inputted from the second clock signal terminal of the shift register corresponding to the fourth row on the display panel.

[0075] like Fig. 9 As shown, when the clock number is 2phase, the cascade mode of the gate driving circuit is row-by-row cascade, that is, the number of cascade rows is 1, 2, ... n, and the clock signal input to the second clock signal end of the first row is the same as the clock signal input to the second clock signal end of the third row, and the clock signal input to the second clock signal end of the second row is the same as the clock signal input to the second clock signal end of the fourth row, that is, there are only two clock signals in the entire display panel, and the high and low levels of the two signals are opposite.

[0076] like Fig.10As shown, when the clock number is 4phase, the cascade mode of the gate driving circuit is interlaced cascade, that is, the number of cascade rows is 1, 3, 5, 7, ..., and 2, 4, 6, 8, ..., and the clock signal input to the second clock signal end of the first row is the same as the clock signal input to the second clock signal end of the fifth row, the clock signal input to the second clock signal end of the second row is the same as the clock signal input to the second clock signal end of the sixth row, the clock signal input to the second clock signal end of the third row is the same as the clock signal input to the second clock signal end of the seventh row, the clock signal input to the second clock signal end of the fourth row is the same as the clock signal input to the second clock signal end of the eighth row, and the first clock signal ck1 and the third clock signal ck3 are clock signals with opposite high and low levels, and the second clock signal ck2 and the fourth clock signal ck4 are clock signals with opposite high and low levels, that is, there are four clock signals in the entire display panel, and these four clock signals are two groups of complementary signals.

[0077] Based on the same inventive concept, the present invention also provides a display panel, such as Fig.11 As shown, it includes: an array substrate and a counter substrate arranged opposite to each other; the array substrate includes a base substrate 100 and any one of gate driving circuits 200 located on the base substrate 100 .

[0078] The above-mentioned display panel of the present application can realize the switching of two sets of cascade relationships, meet the different functional requirements of the display panel, and can simultaneously meet the high performance requirements and low cost requirements of the display panel, thereby solving the problem that the cascade method of the shift register in the prior art is only fixed in one way, and the high performance and low cost of the display panel cannot be taken into account at the same time under the functional requirements of different display panels.

[0079] In some embodiments, the display panel further includes: a plurality of rows of pixel units, and the gate driving circuit is configured to provide a gate driving signal Gout to the pixel units.

[0080] The present invention also provides a display device, such as Fig.12 As shown, it includes: a display area and any display panel 300. The display device can be: electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator and any other product or component with display function.

[0081] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0082] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0083] 1) The above-mentioned gate driving circuit of the present application includes a plurality of cascaded shift registers, and the shift registers include an electrically connected cascade selection module and a row driving module, wherein, when the first control signal input to the first control end of the cascade selection module is the first level and the second control signal input to the second control end of the cascade selection module is the second level, each shift register is cascaded in a first cascade manner, and when the first control signal is the second level and the second control signal is the first level, each shift register is cascaded in a second cascade manner; the row driving module outputs a gate driving signal according to a scanning control signal output by the cascade selection module. The circuit can realize the switching of two sets of cascade relationships on the same panel, meet the different functional requirements of the display panel, and can simultaneously meet the high performance requirements and low cost requirements of the display panel, solving the problem that the cascade mode of the shift register in the prior art is only fixed in one way, and the high performance and low cost of the display panel cannot be taken into account at the same time under the functional requirements of different display panels.

[0084] 2) The above-mentioned display panel of the present application can realize the switching of two sets of cascade relationships to meet the different functional requirements of the display panel, and can simultaneously meet the high performance requirements and low cost requirements of the display panel, thereby solving the problem that the cascade method of the shift register in the prior art is only fixed in one way, and it is impossible to take into account the high performance and low cost of the display panel at the same time under the functional requirements of different display panels.

[0085] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of cascaded shift registers, wherein the shift register comprises an electrically connected cascade selection module and a row driving module, wherein: The first control end of the cascade selection module is used to input a first control signal, the second control end of the cascade selection module is used to input a second control signal, and the output end of the cascade selection module is used to output a scan control signal. When the first control signal is at a first level and the second control signal is at a second level, the shift registers are cascaded in a first cascade manner, and when the first control signal is at a second level and the second control signal is at a first level, the shift registers are cascaded in a second cascade manner. The row driving module is used to output a gate driving signal under the action of the scanning control signal, and the gate driving signal is used to drive the display element of the current row to display or not display.

2. The gate driving circuit according to claim 1, characterized in that: The cascade selection module comprises: a positive scanning signal input unit, the positive scanning signal input unit being used to input a first positive scanning signal to the row driving module under the control of the first control signal, and to input a second positive scanning signal to the row driving module under the control of the second control signal, wherein the first positive scanning signal is a first gate driving signal output by the shift register of the previous stage when the shift registers are cascaded in a first cascade manner, and the second positive scanning signal is a second gate driving signal output by the shift register of the previous stage when the shift registers are cascaded in a second cascade manner; A back-scan signal input unit, the back-scan signal input unit is used to input a first back-scan signal to the row driving module under the control of the first control signal, and to input a second back-scan signal to the row driving module under the control of the second control signal, the first back-scan signal being a third gate driving signal output by the next stage of the shift register when the shift registers are cascaded in a first cascade manner, and the second back-scan signal being a fourth gate driving signal output by the next stage of the shift register when the shift registers are cascaded in a second cascade manner.

3. The gate driving circuit according to claim 2, characterized in that: The positive scan signal input unit comprises: a first transistor, wherein a gate of the first transistor is used to input the first control signal, a first electrode of the first transistor is used to input the first positive scan signal, and a second electrode of the first transistor is used to be electrically connected to a positive scan signal input terminal of the row driving module; A second transistor, wherein the gate of the second transistor is used to input the second control signal, the first electrode of the second transistor is used to input the second positive scan signal, and the second electrode of the second transistor is used to be electrically connected to the positive scan signal input terminal of the row driving module.

4. The gate driving circuit according to claim 2, characterized in that: The reverse sweep signal input unit comprises: a third transistor, wherein a gate of the third transistor is used to input the first control signal, a first electrode of the third transistor is used to input the first reverse scan signal, and a second electrode of the third transistor is used to be electrically connected to the reverse scan signal input terminal of the row driving module; A fourth transistor, wherein the gate of the fourth transistor is used to input the second control signal, the first electrode of the fourth transistor is used to input the second reverse scan signal, and the second electrode of the fourth transistor is used to be electrically connected to the reverse scan signal input terminal of the row driving module.

5. The gate driving circuit according to claim 1, characterized in that: The row driving module includes a scanning control module, a reset module, an output control module and an output module which are electrically connected, wherein: The scanning control module is used to provide the signal of the forward scanning control signal terminal to the input node under the control of the signal of the forward scanning input signal terminal, or to provide the signal of the reverse scanning control signal terminal to the input node under the control of the signal of the reverse scanning input signal terminal; The reset module is used to reset the input node and the gate signal output terminal under the control of the reset signal; The output control module, the output module and the scan control module are connected at the input node, the output control module, the output module and the reset module are all connected to the gate signal output terminal, the gate signal output terminal is used to output the gate drive signal, and the output control module is used to control the level of the gate drive signal under the control of the signal of the input node; The output module is used to output the gate driving signal under the control of the signal of the input node.

6. The gate driving circuit according to claim 5, characterized in that: The scanning control module comprises: a fifth transistor, wherein a gate of the fifth transistor is connected to the positive scan input signal terminal, a first electrode of the fifth transistor is connected to the positive scan control signal terminal, and a second electrode of the fifth transistor is connected to the input node; A sixth transistor, wherein a gate of the sixth transistor is connected to the reverse scan input signal terminal, a first electrode of the sixth transistor is connected to the reverse scan control signal terminal, and a second electrode of the sixth transistor is connected to the input node.

7. The gate driving circuit according to claim 5, characterized in that: The output control module comprises: a first switch unit, wherein a first end of the first switch unit is connected to the input node, a second end of the first switch unit is connected to the first node, a third end of the first switch unit is connected to the first reference voltage end, and a fourth end of the first switch unit is connected to the gate signal output end; a second switch unit, wherein a first end of the second switch unit is connected to the input node, a second end of the second switch unit is connected to the first node, and a third end of the second switch unit is connected to the first reference voltage end; A third switch unit, wherein a first end of the third switch unit is connected to the first node, a second end of the third switch unit is connected to the input node, a third end of the third switch unit is connected to the first reference voltage end, and a fourth end of the third switch unit is connected to the second reference voltage end.

8. The gate driving circuit according to claim 7, characterized in that: The first switch unit comprises: a seventh transistor, wherein a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the input node, and a second electrode of the seventh transistor is connected to the first reference voltage terminal; An eighth transistor, wherein a gate of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the gate signal output terminal, and a second electrode of the seventh transistor is connected to the first reference voltage terminal.

9. The gate driving circuit according to claim 7, characterized in that: The second switch unit comprises: A ninth transistor, wherein a gate of the ninth transistor is connected to the input node, a first electrode of the ninth transistor is connected to the first node, and a second electrode of the ninth transistor is connected to the first reference voltage terminal.

10. The gate driving circuit according to claim 7, characterized in that: The third switch unit comprises: a tenth transistor, a gate of the tenth transistor being connected to the input node, and a first electrode of the tenth transistor being connected to the first reference voltage terminal; an eleventh transistor, wherein a gate of the eleventh transistor is connected to the second electrode of the tenth transistor, a first electrode of the eleventh transistor is connected to the first node, and a second electrode of the eleventh transistor is connected to the second reference voltage terminal; A twelfth transistor, wherein a gate of the twelfth transistor is connected to the second reference voltage terminal, a first electrode of the twelfth transistor is connected to the second reference voltage terminal, and a second electrode of the twelfth transistor is connected to the gate of the eleventh transistor.

11. The gate driving circuit according to claim 5, characterized in that: The output control module comprises: a first switch unit, wherein a first end of the first switch unit is connected to the input node, a second end of the first switch unit is connected to the first node, a third end of the first switch unit is connected to the first reference voltage end, and a fourth end of the first switch unit is connected to the gate signal output end; a second switch unit, wherein a first end of the second switch unit is connected to the input node, a second end of the second switch unit is connected to the first node, and a third end of the second switch unit is connected to the first reference voltage end; a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the first clock signal terminal, a first electrode of the thirteenth transistor is connected to the gate signal output terminal, and a second electrode of the thirteenth transistor is connected to the first reference voltage terminal; A first capacitor, wherein a first electrode of the first capacitor is connected to the second clock signal terminal, and a second electrode of the first capacitor is connected to the first node.

12. The gate driving circuit according to claim 5, characterized in that: The reset module comprises: a fourteenth transistor, wherein a gate of the fourteenth transistor is connected to the reset signal terminal, a first electrode of the fourteenth transistor is connected to the input node, and a second electrode of the fourteenth transistor is connected to the first reference voltage terminal; A fifteenth transistor, wherein the gate of the fifteenth transistor is connected to the reset signal terminal, the first electrode of the fifteenth transistor is connected to the gate signal output terminal, and the second electrode of the fifteenth transistor is connected to the first reference voltage terminal.

13. The gate driving circuit according to claim 5, characterized in that: The output module comprises: a sixteenth transistor, a gate of the sixteenth transistor being connected to the input node, a first electrode of the sixteenth transistor being connected to the second clock signal terminal, and a second electrode of the sixteenth transistor being connected to the gate signal output terminal; A second capacitor, wherein a first electrode of the second capacitor is connected to the input node, and a second electrode of the second capacitor is connected to the gate signal output terminal.

14. The gate driving circuit according to claim 1, characterized in that: When the second cascade mode is adopted, the number of clocks of the gate driving signal output by the shift register is twice the number of clocks of the gate driving signal output by the shift register when the first cascade mode is adopted.

15. The gate driving circuit according to claim 1, characterized in that: The cascade connection mode of each of the shift registers is a first cascade connection mode, wherein: When the driving mode of the gate driving circuit is positive scanning driving, the gate signal output terminal of the Nth shift register is electrically connected to the positive scanning input signal terminal of the N+kth shift register, and the signal output by the gate signal output terminal of the Nth shift register is used to drive the N+kth shift register, wherein N≥1, k≥1; In the case where the driving mode of the gate driving circuit is reverse scanning driving, the gate signal output terminal of the M+kth shift register is electrically connected to the reverse scanning input signal terminal of the Mth shift register, and the signal output by the gate signal output terminal of the M+kth shift register is used to drive the Mth shift register, wherein M≥1; The high and low levels of the forward scanning input signal terminal and the reverse scanning input signal terminal are opposite.

16. The gate driving circuit according to claim 1, characterized in that: The cascade connection mode of each of the shift registers is a second cascade connection mode, wherein: When the driving mode of the gate driving circuit is positive scanning driving, the gate signal output terminal of the Nth shift register is electrically connected to the positive scanning input signal terminal of the N+2kth shift register, and the signal output by the gate signal output terminal of the Nth shift register is used to drive the N+2kth shift register, wherein N≥1, k≥1; In the case where the driving mode of the gate driving circuit is reverse scanning driving, the gate signal output terminal of the M+2kth shift register is electrically connected to the reverse scanning input signal terminal of the Mth shift register, and the signal output by the gate signal output terminal of the M+2kth shift register is used to drive the Mth shift register, wherein M≥1; The high and low levels of the forward scanning input signal terminal and the reverse scanning input signal terminal are opposite.

17. A display panel, characterized in that: include: An array substrate and a counter substrate arranged opposite to each other; The array substrate comprises a base substrate and a gate driving circuit according to any one of claims 1 to 16 located on the base substrate.

18. The display panel according to claim 17, characterized in that: The display panel further includes: There are multiple rows of pixel units, and the gate driving circuit is configured to provide gate driving signals to the pixel units.

19. A display device, characterized in that: include: A display area and a display panel as claimed in any one of claims 17 to 18.

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