Interframe interval communication control method and chip

Abstract

The invention discloses an inter-frame interval communication control method and a chip, and the method comprises the steps: 1, starting timing and recording an initial moment after a transmitting device transmits the last bit of current frame data, driving a configuration signal line to be at a low level according to the level condition in the last half bit period of the last bit, and enabling the configuration signal line to be at a low level; controlling the configuration signal line to maintain a low level in a prediction time period, releasing the configuration signal line to be in a high resistance state, and detecting and receiving an interrupt response; step 2, keeping timing and detecting a sending request after the sending equipment detects the receiving interruption response; and step 3, after the sending device detects the sending request, the sending device starts to send the frame header of the next frame of data, and meanwhile, the time interval from the initial moment to the current moment is determined as the inter-frame interval.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication control method and chip for an inter-frame interval. Background Art

[0002] According to the Chinese invention patent application number CN201810679019.1, the latest USB Type-C Power Delivery protocol (hereinafter referred to as the PD protocol) is based on the USB 3.1 version, that is, a power transmission protocol based on the Type-C interface. USB PD can support a maximum power transmission of 100W (20V / 5A), and supports power role conversion, which can meet the power supply needs of most electronic devices. In the USB Type-C interface, USB PD communication uses biphase mark coding (BMC) to transmit data on the CC channel. This method is simple and flexible. It has been released as a PD communication standard and is gradually being widely used. BMC coding is a phase modulation coding technology, which is a coding method that mixes clock and data for transmission. The characteristic of BMC coding is that the level must jump at the beginning of each bit period. Level changes are used to represent logic within a bit period. If the level jumps in the middle of the bit period, it represents logic "1", otherwise it represents logic "0". The use of BMC coding allows the transmitter and receiver to correctly transmit and receive data using only one data line, and maintain good synchronization between the two ends. The PD protocol stipulates that the BMC code transmission frequency is 300K, that is, each bit period is 3.33us. Each communication data packet carries a 64-bit preamble as a synchronization header.

[0003] A BMC code adaptive decoding system and decoding method disclosed in the Chinese invention patent with patent application number CN201810679019.1 focuses on processing the synchronization header signal of the BMC signal, including the number of transition edges; specifically, the parameters of the decoding threshold are adaptively configured according to the BMC data leading synchronization code, and then the level transition in the middle of the single bit signal is analyzed according to the decoding threshold, and corresponding decoding is performed. The decoding performance is improved, but the problem of frequency deviation at the receiving end is solved. The time interval between two adjacent frames of message packets transmitted by the physical layer (including the transmitter and the receiver) used to transmit the USB power transmission message is not predicted, and a stable inter-frame interval (i.e., the time interval between two adjacent frames of message packets) cannot be obtained. If the inter-frame interval is unstable, it will cause timing disorder, clock synchronization difficulty, serious timeout (the delay time generated when transmitting two adjacent frames of data packets exceeds 2 bit periods) and other problems during the PD protocol communication process, thereby affecting the stability and reliability of the communication. Summary of the invention

[0004] The present application discloses a communication control method and chip for inter-frame interval, and the specific technical solution is as follows: A communication control method for an inter-frame interval, comprising: step 1, after a sending device sends the last bit of the current frame data, start timing and record the initial time, and at the same time drive a configuration signal line to a low level according to the level in the last half bit period of the last bit, and control the configuration signal line to maintain a low level within a predicted time period, and then release the configuration signal line to a high impedance state, and detect a receiving interrupt response, and then execute step 2; wherein the receiving interrupt response is an interrupt signal generated by timing triggering after the receiving device receives the last bit of the current frame data; step 2, after the sending device detects the receiving interrupt response, keep timing and detect a sending request, and then execute step 3; wherein , the sending request is a request signal for sending the next frame of data generated by timing triggering after the sending device detects the receiving interrupt response; step 3, after the sending device detects the sending request, the sending device starts to send the frame header of the next frame of data, and at the same time determines the time interval from the initial moment to the current moment as the inter-frame interval; wherein, the receiving interrupt response and the sending request are used to constrain the time error of the inter-frame interval to be within a controllable time range under different levels in the last half bit period of the last bit; wherein the sending device is connected to the receiving device by configuring a signal line; each frame of data is transmitted between the sending device and the receiving device in the form of dual-phase mark encoding.

[0005] Based on step 1 to step 3, the communication control method of the inter-frame interval disclosed in the present application starts from the frame tail stage of the current frame data, and sequentially configures the signal line to a low level, detects the receiving interrupt response, and generates the fixed / dynamic configuration required timing value of the boundary timing moment corresponding to the sending request, so that the inter-frame interval becomes a configurable fixed value when two frames of data are transmitted successively. Therefore, by fixing the time error corresponding to the inter-frame interval, the communication reliability and efficiency between the sending device and the receiving device are improved, the bit error rate is reduced, and the communication protocol stack design is simplified, and the robustness of the system is enhanced.

[0006] A chip, the chip includes a processing unit, a storage unit and a computer program stored in the storage unit and can be run on the processing unit, and the computer program is executed by the processing unit to implement the communication control method as described. The chip disclosed in the present application is equivalent to generating the receiving interrupt response and the sending request at a fixed triggering moment through a pre-configured first target timing time and a second target timing time. No matter how long the data frame received by the receiving device is, whether the last half bit period of the last bit is high or low, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request is controllable; after the sending request is generated, a pre-configured time error is formed by timing the third target timing time, and the next frame of data is sent after the timing of the third target timing time. Therefore, the chip dynamically adjusts according to different situations so that the absolute error range of the time generated by the inter-frame interval in various situations is controllable, and the communication reliability and efficiency between the sending device and the receiving device are improved by fixing the time error corresponding to the inter-frame interval, reducing the bit error rate, simplifying the communication protocol stack design, and enhancing the robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a connection diagram of a sending device and a receiving device provided by this application.

[0008] Figure 2 This is a schematic diagram of the data encoding format transmitted in the CC line (configuration signal line) provided by the present application.

[0009] Figure 3 Embodiment 1 of the present application provides a waveform diagram of the case where the last bit of the current frame data is 1 and the last half bit period in the UI of the last bit alignment is detected to be a high level.

[0010] Figure 4 Embodiment 2 of the present application provides a waveform diagram of the case where the last bit of the current frame data is 0 and the last half bit period in the UI of the last bit alignment is detected to be a high level.

[0011] Figure 5 Embodiment 3 of the present application provides a waveform diagram of the case where the last bit of the current frame data is 1 and the last half bit period in the UI of the last bit alignment is detected to be a low level.

[0012] Figure 6 Embodiment 4 of the present application provides a waveform diagram of the case where the last bit of the current frame data is 0 and the last half bit period in the UI of the last bit alignment is detected to be a low level.

[0013] Figure 7 It is a flow chart of a communication control method of an inter-frame interval provided by the present application.

[0014] Reference numerals: tHoldlowBMC: preset low level hold time; soft programmable range: configurable interval segment; max tEndDriveBMC: the maximum measurement interval of the final edge, equal to the maximum value of the prediction time period; T1: the time from when the sending device sends the last bit of the current frame data to when it detects the receiving interrupt response, recorded as the first target timing time; High impedance: high impedance state; T2: The time from when the level of the configuration signal line is pulled high to when the sending device detects the sending request, recorded as the second target timing time; tInterframeGap: The ideal interframe gap, which covers the time period from the final edge sent by the sending device to the time when the configuration signal line is pulled down from a high-impedance state to a low level; tx_message_req: send request; T3: The time from when the sending device detects the sending request to when the frame header of the next frame of data starts to be sent, recorded as the third target timing time or the preset transition time; peamable for next frame: Sending ready state, used to indicate the time period corresponding to the sending ready state of the next frame of data; UI: Bit period, used to indicate the transmission time of one bit. DETAILED DESCRIPTION

[0015] The present application is further described in detail below in conjunction with the examples and drawings, but the implementation methods of the present application are not limited thereto. It should be noted that a frame of data packaged during the communication process includes three parts: a frame header, a data portion, and a frame trailer. Among them, the frame header and the frame trailer contain some necessary control information. The frame header is the starting part of the frame and contains some control information, such as the source address, destination address, sequence number, etc., which are used to identify and synchronize data. The frame trailer contains some check codes or end identifiers, which are used for data error detection and frame end identifiers. The data portion contains a data packet, which is the main content portion of the frame and contains the data information actually transmitted. The length of this part can be adjusted according to actual needs. In data communication, a "packet" is contained in a "frame".

[0016] like Figure 1As shown in the figure, a pair of transmitting devices and receiving devices communicate through the configuration signal line CC. The transmitting device can add a checksum to the data to be sent, and transmit the payload including the checksum through the biphase mark coding (BMC) on CC. The receiving device recovers the clock and locks to a frame of data sent by the transmitting device. It will first detect the frame header, then decode the received data, including the checksum; then detect the frame tail and verify the checksum.

[0017] The CC line (Configuration Channel) is a type of USB Type-C. The CC line transmission signal is encoded with BMC (Biphase Mark Coding). A phase change once indicates logic 0, and a phase change twice indicates logic 1. The CC line supports pull-up and pull-down resistors and power role monitoring. The interface circuit in the sending device is connected to the interface circuit in the receiving device through the CC1 pin or CC2 pin of the Type C line. The sending device or the receiving device includes both the sending end and the receiving end, and its application scenario is to communicate with the mobile terminal device for power transfer. The sending device and the receiving device are both set with a receiving end and a sending end; when the sending device is responsible for sending data, the receiving device is responsible for receiving data; when the sending device is responsible for receiving data, the receiving device is responsible for sending data. The data sending and receiving roles of the sending device and the receiving device support interchange.

[0018] Since hardware timing itself requires a clock, if there are multiple clocks in the circuit, there will be a cycle error when the same signal crosses from one clock of the sending device to another clock (internal clock of the receiving device). In addition, the time when the hardware starts to recognize the instructions sent by the software is also uncertain, and the time interval between different frame data (inter-frame interval) cannot be stably predicted. The unstable inter-frame interval will lead to timing disorder, clock synchronization difficulties, timeout errors, increased bit error rate and other problems in the USB PD communication process. Therefore, it is necessary to determine the interval between different frame data through timing. By pre-configuring or dynamically configuring the boundary conditions of the relevant level of the frame end, an inter-frame interval with a fixed error can be timed out during timing detection, which can be used for actual data transmission and communication in the CC line.

[0019] In view of the above technical defects, the present application discloses a communication control method for interframe spacing. In the present application, the execution subject of the communication control method can be regarded as a sending device, or a software system capable of controlling the sending device and the receiving device. The sending device is connected to the receiving device by configuring a signal line, and the sending device and the receiving device communicate data in the form of dual-phase mark encoding. Its application scenarios include power transfer communication. Figure 7 As shown, the communication control method includes: Step 1: After the sending device sends the last bit of the current frame data, start timing and record the initial time to start timing from the completion of the last bit of the current frame data (i.e., the frame tail is sent). From the perspective of signal timing, the initial time can be the time of the last edge of the last bit of the current frame data; schematically, the initial time is as follows: Figure 3 and Figure 4 The last falling edge of the last bit of the current frame data is shown, or as Figure 5 and Figure 6 as shown by the last rising edge moment of the last bit of the current frame data; at the same time, according to the level situation in the last half bit period of the last bit, the configuration signal line is driven to be set to a low level, and the configuration signal line is controlled to remain at a low level within the predicted time period. At this time, the moment when the configuration signal line is set to a low level and the time for the configuration signal line to remain at a low level can be determined; in order to prevent the length of the data part (payload) in the current frame data and the level situation in the last half bit period of the last bit from affecting the time when the configuration signal line is pulled low, step 1 can fix the time for the configuration signal line to remain at a low level by timing. Of course, the fixed time is a pre-configured timing value, as long as the configuration signal line is driven to be set to a low level and the fixed time is directly timed; for example, step 1 is timed to the time when the configuration signal line remains at a low level to reach Figures 3 to 6 After the maximum measurement interval max tEndDriveBMC of the final edge shown, it enters the high impedance state and waits for the sending device to detect the receiving interrupt response, wherein the maximum measurement interval maxtEndDriveBMC of the final edge is equal to the maximum value of the predicted time period, and the preset low level holding time is as follows Figures 3 to 6 The square wave width occupied by tHoldlowBMC in the waveform diagram is shown as a configurable time period. Preferably, when the configuration signal line is released to a high impedance state, the level of the configuration signal line increases from 0V to 3V, but is lower than the high level; and the configuration signal line is not driven to transmit data.

[0020] Then release the configuration signal line to a high impedance state, at which time the configuration signal line is not in a pull-up or pull-down state, the configuration signal line is in a non-driven state, and the receiving device has received a frame of data, so it is necessary to detect a receiving interrupt response, and then execute step 2. The receiving interrupt response is an interrupt signal generated by a timing trigger after the receiving device receives the last bit of the current frame of data.

[0021] Step 2: After the sending device detects the receiving interrupt response, keep timing and detect the sending request, and then execute step 3, so as to start controlling the sending device to start sending the next frame of data when executing step 3. It is worth noting that the time period from the time when the sending device sends the last bit of the current frame data to the time when the receiving interrupt response is detected is as follows: Figures 3 to 6 The square wave width occupied by T1 in the waveform diagram is shown as follows, which is different from Figures 3 to 6 The square wave width occupied by tHoldlowBMC in the waveform diagram can be considered as independent time periods. The moment of detecting the receiving interrupt response is delayed from the rising edge moment of the high impedance state High impedance.

[0022] Since the receiving device will trigger the software to generate an interrupt signal when it completes receiving data, after the sending device has sent the last bit of the current frame data in step 1, the receiving device triggers the software system to generate the receiving interrupt response after receiving the last bit of the current frame data, so that the sending device will start timing the new level state of the configuration signal line after detecting the receiving interrupt response; wherein, there is an interrupt time interval from the receiving device receiving the last bit of the current frame data to triggering the software system to generate the receiving interrupt response, such as Figures 3 to 6 T1 in the waveform diagram; the present application pre-configures the interrupt time interval or dynamically adjusts the interrupt time interval according to the real-time signal situation. Then, after the receiving device receives the last bit of the current frame data, it immediately generates the receiving interrupt response by timing the specific interrupt time interval and is detected by the sending device, so that the time from receiving the last bit of the current frame data to triggering the generation / detection of the receiving interrupt response is controllable and is not affected by the high and low state of the level in the last half bit period of the last bit and the length of the data received by the receiving device.

[0023] After the receiving interrupt response is recognized, a transition time (corresponding to Figures 3 to 6 T2 as shown), the timing T2 is completed, triggering the software system to generate a sending request. Therefore, it can be understood that the sending request is a request signal for sending the next frame of data generated by timing triggering after the sending device detects the receiving interrupt response; it should be noted that after executing step 2 and before executing step 3, it is a period from when the configuration signal line is released to a high impedance state to when the sending request (i.e., the request signal generated for sending the next frame of data) is detected. This period is as follows Figures 3 to 6As shown in the square wave width occupied by T2 in the waveform diagram, it covers a moment after the rising edge of the square wave indicated by High impedance to the rising edge of the pulse corresponding to the sending request tx_message_req. In the present application, by configuring the period in advance or dynamically configuring the period, after the receiving interrupt response is subsequently detected, the sending request is immediately generated by timing the period, so that the time from the detection of the receiving interrupt response to the generation of the sending request is controllable and is not affected by the level high and low state in the last half bit period of the last bit and the length of the data sent by the sending device.

[0024] Step 3: After the sending device detects the sending request, the sending device starts to send the frame header of the next frame data, and at the same time determines the time interval from the initial moment to the current moment as the inter-frame interval, so that the sending device sends data according to the inter-frame interval, and the inter-frame interval is dynamically adjustable. Specifically, after the sending device detects the sending request, it starts to drive the configuration signal line to send data in the form of BMC code, and the time interval between the generation of the sending request and the detection of the sending request by the sending device contains a pre-configured fixed time error, which is less than or equal to one bit period; it can be understood that when the timing of this time interval ends, the sending device starts to send the frame header of the next frame data.

[0025] It is worth noting that the receive interrupt response and the send request are used to constrain the time error of the inter-frame interval to be within a controllable time range under different levels in the last half bit period of the last bit. Specifically, the time interval from the initial moment to the moment when the receive interrupt response is detected, and the time interval between the detection of the receive interrupt response and the generation of the send request can be configured as a fixed time period, and the time interval between the moment when the send request is generated and the moment when the sending device detects the send request (the moment when the sending device starts to send the frame header of the next frame of data) contains a pre-configured fixed time error, so the controllable time range can be regarded as a timing time period jointly determined by the receive interrupt response, the send request and the preset transition time.

[0026] Schematically, the time interval from when a sending request is generated to when the sending device detects the sending request is, for example, Figures 3 to 6As shown in the square wave width occupied by T3 in the waveform diagram of the transmission request tx_message_req, the rising edge of the pulse corresponding to the transmission request tx_message_req is covered to the rising edge of the time period of peamable for next frame, and the timing is sequentially crossed over the stage of High impedance and the stage of the configuration signal line maintaining a low level (aligned with the edge of peamable for next frame). In order to simplify the description, the time interval from the generation of the transmission request to the detection of the transmission request by the transmitting device is recorded as the preset transition time, and the preset transition time preferably has a time error within a bit period, such as Figures 3 to 6 The time interval from the last falling edge of the tInterframeGap phase in the waveform diagram to the last rising edge of the peamable for next frame in the same figure is shown in FIG. Figure 3 and Figure 4 The difference is equivalent to the sum of T1, T2 and T3 minus tInterframeGap, which is a pre-configured fixed timing value and is less than one bit period; based on this, starting from the generation of the sending request, the error in the time interval for transmitting two adjacent frames of data between the sending device and the receiving device can be configured to be a specific time error value by timing T3, and the specific time error value is a time error that cannot be avoided due to the influence of the clock.

[0027] Indicatively, when the time error of the interframe interval determined in step 3 is limited to one bit period, the interframe interval is equal to Figure 3 , Figure 4 , Figure 5 and Figure 6 The sum of T1, T2 and T3 in any of the figures, but not equal to the inter-frame interval tInterframeGap in the ideal state; wherein the square wave waveform occupied by T1, T2 and T3 in the same figure covers the time interval required for sending two adjacent frames of data. If the preset transition time is regarded as a timing time period obtained by timing, its timing value can be pre-configured, so the time error allowed by the preset transition time is a controllable error. When the time interval T1 from the initial moment to the moment when the receiving interrupt response is detected, and the time interval T2 from the moment when the receiving interrupt response is detected to the generation of the sending request are configured as fixed time periods, the preset transition time can be dynamically adjusted according to different data frame transmission conditions, so that the time error of the inter-frame interval determined in various situations does not exceed a single bit period, so that under different levels in the last half bit period of the last bit, the time error constraining the existence of the inter-frame interval is within a controllable time range, and the controllable time range can be a bit period.

[0028] comprehensive Figures 3 to 6 It can be seen that the present application can pre-configure fixed T1 and T2, then no matter what the length of the data frame received by the receiving device is, whether the last half bit period of the last bit is high or low, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request is controllable; after the sending request is generated, a pre-configured time error is formed by timing T3, and the next frame of data is sent after timing T3. Therefore, no matter how long the sending device sends a frame of data or the type of the frame end of the frame data (the level within the last half bit period of the last bit) is, the error from the sending request generated by the software to the sending device starting to send the next frame of data is controllable, and dynamic regulation is achieved according to different situations so that the absolute error range of the time generated by the frame interval in various situations can be controlled.

[0029] Based on steps 1 to 3, the present application discloses a communication control method for an inter-frame interval, starting from the frame tail stage of the current frame data, sequentially configuring the required timing value for setting the configuration signal line to a low level, detecting the receiving interrupt response, and generating the boundary timing moment corresponding to the sending request, so that the inter-frame interval becomes a configurable fixed value when two frames of data are transmitted successively; from the perspective of the sending device: no matter how much the length of the data to be sent is and how the level is in the last half bit period of the last bit, the time for keeping the configuration signal line at a low level at the end of the frame is controllable and can be controlled to a fixed value; from the perspective of the receiving device: no matter how much the length of the received data is and how the level is in the last half bit period of the last bit, the time between the completion of the reception of the current frame data and the detection of the receiving interrupt response is controllable and can be controlled to a fixed value; from the perspective of the sending device: no matter how much the length of the single frame data to be sent is or what the type of data frame is, the time error existing in the time interval from the generation of the sending request to the start of sending the next frame of data is controllable. In summary, by fixing the time error corresponding to the inter-frame interval, the communication reliability and efficiency between the sending device and the receiving device are improved, the bit error rate is reduced, the communication protocol stack design is simplified, and the robustness of the system is enhanced.

[0030] As an embodiment, in step 1, after driving the configuration signal line to a low level, the time for which the configuration signal line remains at a low level is timed; it is worth noting that after the last bit of the current frame data is sent in step 1, if the last half bit period of the last bit of the current frame data is output as a high level, the configuration signal line is driven to flip from a high level to a low level; if the last half bit period of the last bit of the current frame data is output as a low level, the configuration signal line is driven to first be pulled high for a bit period and then flipped to a low level. Thereby, the configuration signal line is pulled low after the last falling edge of the frame. On this basis, the time for which the configuration signal line remains at a low level is timed from the falling edge moment when the configuration signal line is set to a low level. In order to make the time for the configuration signal line to remain at a low level designed to be software programmable, this embodiment will be timed according to a pre-configured fixed timing value, so that the configuration signal line remains at a low level within a fixed timing value at the end of the frame. The fixed timing value is configured as a preset low level holding time.

[0031] After the configuration signal line is counted to maintain a low level for a preset low level holding time, the timing is maintained, and after the configuration signal line is counted to maintain a low level for a configurable interval, the configuration signal line is released to a high impedance state to wait for the sending device to detect the receiving interrupt response; wherein the predicted time period includes a preset low level holding time and a configurable interval, and the preset low level holding time and the configurable interval are both configurable time periods. The preset low level holding time is as follows: Figures 3 to 6 The square wave width occupied by tHoldlowBMC is shown in the waveform diagram, where Figure 3 and Figure 4 When the last half bit period of the last bit of the current frame data is output at a high level, the low level is pulled down and maintained for the preset low level holding time tHoldlowBMC. Figure 5 and Figure 6 When the last half bit period of the last bit of the current frame data is output at a low level, it is first pulled high to maintain a bit period UI and then pulled low and maintained at the low level for the preset low level holding time tHoldlowBMC. Then continue timing the configurable interval, that is, the low level can be maintained within the configurable interval, the time the configuration signal line is pulled low at the end of the frame is controllable, and the time it is pulled low can be maintained at the same preset low level holding time; on this basis, the configurable interval and / or the preset low level holding time can be dynamically adjusted according to the length of the data frame to be sent and the level of the last bit, and the maximum value of the sum of the preset low level holding time tHoldlowBMC and the soft programmable range of the configurable interval can reach Figures 3 to 6The maximum measurement interval max tEndDriveBMC of the final edge is shown to ensure that T1 remains unchanged; therefore, no matter whether the last bit of the current frame data is a low level or a high level, the preset low level holding time and the configurable interval are counted successively on the basis of the configuration signal line being flipped to a low level. Since the preset low level holding time and the configurable interval can be configured in advance or dynamically adjusted, the sending device can adjust the inter-frame interval to be stable when sending frame tails of different level states.

[0032] As an embodiment, the communication control method further includes: when the sending device detects the receiving interrupt response, determining the time interval between the initial moment and the moment when the receiving interrupt response is detected as a first target timing time; wherein the sum of the preset low level holding time and the configurable interval segment is less than or equal to the first target timing time, such as Figures 3 to 6 As shown, if the first target timing time T1 is timed, the end time of timing T1 is after the rising edge of the high-impedance state, that is, the first target timing time T1 is ended within a period of time after the timing of the configurable interval soft programmable range; therefore, starting from the last edge of the last bit, the sum of the preset low-level holding time tHoldlowBMC and the configurable interval soft programmable range is less than or equal to the first target timing time T1.

[0033] It should be noted that when the sending device sends the current frame data, the receiving device receives the current frame data through the configuration signal line; the time interval from the receiving device receiving the last bit of the current frame data to detecting the receiving interrupt response is a configurable time period, so that the first target timing time remains fixed under different levels in the last half bit period of the last bit. Specifically, the first target timing time will cover the preset low level holding time, the time interval from the completion of sending / receiving the current frame data to the detection of the receiving interrupt response, and the preset low level holding time (corresponding to Figures 3 to 6 tHoldlowBMC in the transmission / reception of the current frame data until the reception interrupt response is detected (corresponding to Figures 3 to 6 The soft programmable range in the last bit can be dynamically adjusted so that the first target timing time remains fixed under different level conditions within the last half bit period of the last bit.

[0034] It can also be understood that when the sending device completes sending the last bit of the current frame data (i.e., the frame tail signal edge is sent), the receiving device synchronously receives the last bit of the current frame data, and the current moment is the initial moment. At this time, the timing starts, that is, the timing starts from the initial moment and continues until the receiving interrupt response is detected. Since the receiving interrupt response is triggered at a pre-configured moment, the first target timing time is a controllable timing time and can be adjusted to a fixed time.

[0035] Schematically, the initial moment is Figure 3 and Figure 4 As shown in the last falling edge moment of the last bit of the current frame data, correspondingly, the last half bit period of the last bit of the current frame data shown in the figure is output as a high level, then the last falling edge moment of the UI occupied by the last bit of the current frame data is recorded as the initial moment, at the initial moment, the current frame data is preferably received by the receiving device, and the last falling edge of the UI occupied by the last bit of the current frame data is the falling edge of the last bit shown in the figure; then the timing passes through tHoldlowBMC and the soft programmable range, and then the configuration signal line is released to enter the high impedance state High impedance to wait for the detection of the receiving interrupt response, then the time interval from the initial moment to the rising edge moment of entering the high impedance state High impedance is less than Figure 3 and Figure 4 In T1, the configurable interval soft programmable range is adjusted through software instructions, and the sum of tHoldlowBMC and the soft programmable range is adjusted to the maximum measurement interval max tEndDriveBMC of the final edge. The maximum measurement interval max tEndDriveBMC of the final edge can be further fixed, where the final edge here can refer to the last falling edge of the UI occupied by the last bit of the current frame data.

[0036] Schematically, the initial moment is Figure 5 and Figure 6As shown in the last rising edge moment of the last bit of the current frame data, correspondingly, the last half bit period of the last bit of the current frame data shown in the figure is output as a low level, then the last rising edge moment of the UI occupied by the last bit of the current frame data is recorded as the initial moment, at the initial moment, the current frame data is preferably received by the receiving device, and the last rising edge of the UI occupied by the last bit of the current frame data is the rising edge of the last bit shown in the figure; then the timing passes through the high level bit period UI, the preset low level holding time tHoldlowBMC and the configurable interval soft programmable range, and then the configuration signal line is released to enter the high impedance state Highimpedance to wait for the detection of the receiving interrupt response, then the time interval from the initial moment to the rising edge moment of entering High impedance is less than Figure 5 and Figure 6 In T1, when the bit period UI and the preset low-level holding time tHoldlowBMC are both set to fixed values, the configurable interval soft programmable range is adjusted through software instructions, and the sum of the bit period UI, the preset low-level holding time tHoldlowBMC and the configurable interval soft programmable range is adjusted to the maximum measurement interval max tEndDriveBMC of the final edge. The maximum measurement interval max tEndDriveBMC of the final edge can be further fixed, where the final edge here can refer to the last rising edge of the UI occupied by the last bit of the current frame data.

[0037] In summary, the present application designs the time interval between the sending device sending the last bit of the current frame data or the receiving device receiving the last bit of the current frame data to detecting the receiving interrupt response to be software programmable, so that no matter what the data length of the receiving device is and what the level state of the last bit period is, it will not affect the time interval between the receiving device receiving the last bit of the current frame data to detecting the receiving interrupt response. The size of the time interval can be configured in advance or accepted in real time to adapt to the formation of a stable inter-frame interval when the last bit of data is sent / received in different level states.

[0038] Based on the above embodiment, the communication control method further includes: in the step 2, after the sending device detects the receiving interrupt response, timing the time for the configuration signal line to maintain the high impedance state; when the timing reaches the second target timing time for the configuration signal line to maintain the high impedance state, it is determined that the sending request has been generated; before the sending request tx_message_req arrives, in step 2, after the sending device detects the receiving interrupt response, the configuration signal line is already in the high impedance state, the configuration signal line enters the high impedance state High impedance, the timing stage has entered other timing stages from the first target timing time T1, until the sending request tx_message_req is generated, and the time interval between the timing end time of the first target timing time T1 and the rising edge time of the sending request tx_message_req is determined as the second target timing time T2. Wherein, the second target timing time is a configurable time period, so that the second target timing time remains fixed under different level conditions in the last half bit period of the last bit.

[0039] On the basis of the above embodiment, after the sending request is generated, the configuration signal line is controlled from a high impedance state to a low level to guide the sending device into a sending preparation state; after the sending device crosses the sending preparation state, the sending device detects the sending request to execute step 3; in step 3, the configuration signal line is driven to start sending the next frame of data to enable the sending device to start sending the frame header of the next frame of data, and the time interval between the generation of the sending request and the start of sending the frame header of the next frame of data is set as a third target timing time.

[0040] If the third target timing time is counted, the configuration signal line is pulled down during the timing period, and can be pulled down to 0V to 1V by the pull-down resistor, and the sending device is guided to enter the sending preparation state when the configuration signal line is pulled down; starting from the generation of the sending request, the pre-configured third target timing time is counted, combined with Figures 3 to 6 It can be seen that in the process of timing the third target timing time T3, the pulse signal corresponding to the sending request tx_message_req, the configuration signal line is set to a low level, and the sending ready state peamable for next frame is timed in sequence until it is detected that the level of the configuration signal line is driven to a high level again, and the sending ready state peamable for next frame is timed, and the high level is higher than the level output by the configuration signal line when it is in the high impedance state High impedance.

[0041] Based on this, after timing the third target timing time, the sending device crosses the sending preparation state and starts to send the frame header of the next frame data, and at the same time determines the sum of the first target timing time, the second target timing time and the third target timing time as the inter-frame interval, and the inter-frame interval is schematically equivalent to Figures 3 to 6 The sum of T1, T2 and T3 in any of the accompanying drawings; the time error existing in the third target timing time is configurable, and the time error that can be reserved for the inter-frame interval is a controllable time error existing in the inter-frame interval within the third target timing time or in the sending preparation state, and the controllable time error is constrained within a bit period, which is equal to a pre-configured fixed value, for example, equal to the clock period (3.3us) of the BMC code generated on the CC line.

[0042] It should be noted that the third target timing time is the preset transition time mentioned in the above embodiment, so that the time error of the inter-frame interval is within the controllable time range under different levels in the last half bit period of the last bit. Figures 3 to 6 It can be seen that the present application can generate the receive interrupt response and the send request at fixed triggering times by configuring the first target timing time T1 and the second target timing time T2 in advance or adjusting them dynamically. Then, no matter how long the data frame received by the receiving device is, whether the last half bit period of the last bit is high or low, the time from the completion of data frame reception to the generation of the receive interrupt response and the send request is controllable; after detecting the send request, the third target timing time T3 will be kept timing before timing to the frame header of the next frame of data to be sent, thereby forming a fixed time error.

[0043] Therefore, no matter how long the data frame is or what the type of data frame is, the time error reserved within the third target timing time is controllable, so that the time range required from the generation of the sending request to the start of sending the frame header of the next frame of data is predicted, and the timing is expressed using the third target timing time. Therefore, after timing the third target timing time, it is possible to confirm when to start sending the next frame of data, and then based on the pre-configured fixed first target timing time and second target timing time, the inter-frame interval is configured as a fixed time interval, and then based on the fixed time interval, multiple frames of different lengths or different types of data transmission are performed in succession, so that the bit error rate is controllable and the reliability of sending the next frame of data is improved.

[0044] The third target timing time designed in the prior art generally serves as a transition stage in the inter-frame interval, including the successive transmission of two adjacent frames of data and the transition from software issuing a sending request to hardware detecting a sending request, both of which may have the time error; the third target timing time in the prior art brings an uncertain time range due to the time error relative to the inter-frame interval tInterframeGap in the ideal state shown in the figure, but step 3 disclosed in the present application is controllable and even negligible for the time error, which will not affect the stability of the inter-frame interval; therefore, the present application overcomes the influence of the uncertain time range in the prior art on data communication stability and reliability.

[0045] Specifically, in step 1, the method of driving the configuration signal line to a low level according to the level in the last half bit period of the last bit includes: after detecting that the level of the configuration signal line in the last half bit period of the last bit is a high level, pulling down the level of the configuration signal line to a low level, so as to drive the configuration signal line to a low level when the falling edge of the last bit arrives, and at the same time determining that the sending device has sent the last bit of the current frame data, and recording the time of the last falling edge of the last bit as the initial time; in step 1, the sending device ensures that the receiving device locks the last bit through the last bit of the current frame data, and the last half bit period of the last bit is a high level, causing the sending device to drive the configuration signal line to pull down the level, not only based on this, determining that the sending device has sent the last bit of the current frame data, but also allowing the receiving device to receive the last bit of the current frame data, and also establishing the timing starting point of the first target timing time (corresponding to the initial time).

[0046] The case where the level of the configuration signal line in the last half bit period of the last bit is high includes that the configuration signal line is high only in the last half bit period in the bit period of the last bit, corresponding to Figure 3 or, the case where the level of the configuration signal line in a bit period of the last bit is a high level includes the level of the configuration signal line in the bit period of the last bit being a high level, corresponding to Figure 4 Schematic diagram of the waveform. Schematically, at the initial moment Figure 3 and Figure 4 As shown in the last falling edge moment of the last bit of the current frame data, correspondingly, the last half bit period of the last bit of the current frame data shown in the figure is output as a high level, then the last falling edge moment of the UI occupied by the last bit of the current frame data is recorded as the initial moment. At the initial moment, the current frame data is preferably received by the receiving device.

[0047] The last bit is the latest bit sent in the frame tail of the current frame data. It should be noted that during the data transmission between the sending device and the receiving device, the sending device packages the data into frames for transmission, and the receiving device parses and processes the frame according to the information in the frame header after receiving the data. After the step 1 sends the last bit of the current frame data, if the last half bit period of the last bit of the current frame data is a high level, the configuration signal line is driven from a high level to a low level to confirm that a frame of data has been sent. In this way, different types of data can be efficiently and accurately transmitted between different devices. The size of a frame of data can be adjusted according to the specific protocol and application requirements, but its structured and standardized design ensures the correct transmission and processing of data.

[0048] As an example 1, Figure 3 As shown in FIG. 1 , within the bit period occupied by the last bit of the current frame data, the configuration signal line (CC line) is high only in the last half bit period of the last bit of the current frame data, indicating that the data on the last bit of the current frame data is logic 1; then Figure 3 At the falling edge of the last bit indicated, the configuration signal line is driven to a low level, and then the configuration signal line is controlled to maintain the preset low level holding time tHoldlowBMC at a low level to maintain the stability of the inter-frame interval, and then a configurable interval soft programmable range is reserved, and tHoldlowBMC and soft programmable range are respectively set to adjustable time periods, and the sum of the two is equal to the maximum measurement interval max tEndDriveBMC of the final edge, and then the configuration signal line is released to a high impedance state, that is, the configuration signal line is released to a high impedance state High impedance (pulled up to 3V by a pull-up resistor, but lower than a high level) after the falling edge of the last bit passes through max tEndDriveBMC, so as to wait for the receiving interrupt response in a sufficiently long time; then when the receiving interrupt response is detected, the second target timing time T2 is started to be counted until the sending request tx_message_req is generated, and then the third target timing time T3 is started to be counted to make the configuration signal line jump from the high impedance state High impedance to the sending ready state peamable for next frame; within the third target timing time T3, after the sending request tx_message_req is generated, the configuration signal line is controlled to be set to a low level (pulled up to 0V to 1V by a pull-down resistor) to enter the sending ready state peamable for next frame; after the timing T3 is completed, the configuration signal line is driven to start sending the frame header of the next frame of data.

[0049] When the last bit (frame tail) of the current frame data is at a high level in the last half bit period, no matter how long the data frame received by the receiving device is, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request is controllable; after the sending request is generated, before the frame header of the next frame data is sent, the third target timing time T3 will be kept counting to form a fixed inter-frame interval. Figure 3 It can be seen that the present application can fix the first target timing time T1 and the second target timing time T2, and then time the frame header from the generation of the sending request to the start of sending the next frame of data, and time the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the sequential transmission of two adjacent frames of data and the transition from the software sending the sending request to the hardware detecting the sending request, at least relative to Figure 3 The inter-frame interval tInterframeGap under the ideal state shown in the figure may cause a time error, but the step 3 disclosed in the present application is controllable for the time error, limited to one bit period UI, and will not affect the stability of the inter-frame interval; therefore, when it is at a high level in the last half bit period of the frame end, no matter how long a frame of data is sent by the sending device, the error during the period from the sending request generated by the software to the start of the sending device to send the next frame of data is controllable, and the time error is dynamically adjusted according to different situations, thereby reducing the time error caused by the transmission of different frame data, and overcoming the influence of the uncertain time range in the prior art on the stability and reliability of data communication.

[0050] It should be noted that in the USB PD (Power Delivery) protocol, the "UI" mentioned in the above embodiment refers to "Unit Interval". This term comes from the field of communications, especially a unit used to represent time intervals in digital communications and serial interfaces, indicating the transmission time of 1 bit. It can be configured as the clock cycle of the CC line according to the communication protocol, preferably 3.3us, which can be used as the time error allowed by the system.

[0051] As a second embodiment, Figure 4 As shown in FIG. 1 , the configuration signal line (CC line) is at a high level during the bit period occupied by the last bit of the current frame data, indicating that the data on the last bit of the current frame data is logic 0; then Figure 4At the falling edge of the last bit indicated, the configuration signal line is driven to a low level, and then the configuration signal line is controlled to maintain the preset low level holding time tHoldlowBMC at a low level to maintain the stability of the inter-frame interval, and then a configurable interval segment softprogrammable range is reserved, and tHoldlowBMC and soft programmable range are respectively set to adjustable time periods, and the sum of the two is equal to the maximum measurement interval segment max tEndDriveBMC of the final edge, and then the configuration signal line is released to a high impedance state High impedance (pulled up to 3V by a pull-up resistor, but lower than a high level) after the falling edge of the last bit passes through max tEndDriveBMC, so that the sending device detects the receiving interrupt response within a sufficiently long and controllable time period; after detecting the receiving interrupt response, the second target timing time T2 is continued to be counted until the sending request tx_message_req is generated, and the third target timing time T3 is started to be counted to make the configuration signal line jump from the high impedance state High impedance to the sending ready state peamable for next frame; within the third target timing time T3, after the sending request tx_message_req is generated, the configuration signal line is controlled to be set to a low level (pulled up to 0V to 1V by a pull-down resistor) to enter the sending ready state peamable for next frame, and after the timing T3 is completed, the configuration signal line is driven to start sending the frame header of the next frame of data.

[0052] When the last bit (frame tail) of the current frame data is at a high level during the entire bit period, no matter how long the data frame received by the receiving device is, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request is controllable; after the sending request is generated, before the frame header of the next frame data is sent, the third target timing time T3 will be kept timing, forming a pre-configured time error, combined with Figure 4 It can be seen that the present application can fix the first target timing time T1 and the second target timing time T2, and then time the frame header from the generation of the sending request to the start of sending the next frame of data, and time the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the sequential transmission of two adjacent frames of data and the transition from the software sending the sending request to the hardware detecting the sending request, at least relative to Figure 4The inter-frame interval tInterframeGap under the ideal state shown in the figure may cause a time error, but the step 3 disclosed in the present application is controllable for the time error, limited to one bit period UI, and will not affect the stability of the inter-frame interval; therefore, when the frame end is at a high level throughout the entire bit period, no matter how long a frame of data is sent by the sending device, the error during the period from the sending request generated by the software to the start of the sending device to send the next frame of data is controllable, and the time error is dynamically adjusted according to different situations, thereby reducing the time error caused by the transmission of different frame data, and overcoming the influence of the uncertain time range in the prior art on the stability and reliability of data communication.

[0053] It is worth noting that since the high impedance state is equivalent to the cut-off state, it refers to an output state of the circuit, which is neither a high level nor a low level. The level of the configuration signal line in the high impedance state is lower than the high level and higher than the low level, so as to stop the configuration signal line from transmitting data.

[0054] Specifically, within the first target timing time T1, when the current frame data is finished being sent, no matter whether the last bit of the current frame data is logic 0 or logic 1, as long as the configuration signal line is at a high level in the second half of the bit period of the last bit of the current frame data, the configuration signal line is subsequently continuously pulled down for a preset low level holding time tHoldLowBMC and a configurable soft programmable range, and then the configuration signal line is released to a high impedance state, that is, a configurable low level time must be added at the end of a frame of data before driving data transmission is stopped, wherein the configurable soft programmable range is the time interval from determining that the time for the configuration signal line to maintain a low level reaches the preset low level holding time tHoldLowBMC to releasing it to a high impedance state. Since the time interval from determining that the time for the configuration signal line to maintain a low level reaches the preset low level holding time tHoldLowBMC to releasing it to a high impedance state is configurable, and the receive interrupt response is pre-configured to be generated at the corresponding trigger moment, the soft programmable range is The time interval range is configurable, so the time from determining that the time for the configuration signal line to maintain a low level reaches the preset low level holding time tHoldLowBMC to the time for the sending device to detect the reception interrupt response is configurable. Finally, by dynamically adjusting tHoldLowBMC and soft programmable range, the first target timing time T1 is adjusted to a fixed value, so that when the level of the configuration signal line in the last half bit period of the last bit is high, the second half bit period of the last bit of the current frame data is compatible with being high to cope with different data length transmission situations.

[0055] On the other hand, in step 1, the method of driving the configuration signal line to a low level according to the level of the last half bit period of the last bit includes: after detecting that the level of the configuration signal line in the last half bit period of the last bit is a low level, first pull up the level of the configuration signal line to a high level, and at the same time determine that the sending device has sent the last bit of the current frame data, and record the moment of the last rising edge of the last bit as the initial moment, and then drive the configuration signal line to maintain a high level in a bit period, and then pull down the level of the configuration signal line to a low level, thereby delaying the last bit of the current frame data by one bit period to drive the configuration signal line to a low level; and also delaying the action of driving the configuration signal line to a low level by one bit period when the level of the configuration signal line in the last half bit period of the last bit is a high level, and the two form a time difference of one bit period. Therefore, in combination with the above-mentioned embodiment, the first target timing time can be fixed according to the different level conditions in the last half bit period to compensate for the time difference of the bit period, otherwise, combined with the time error in the sending preparation state, two UI errors will be accumulated.

[0056] In this embodiment, after detecting that the level of the configuration signal line in the last half bit period of the last bit is a low level, the level of the configuration signal line is first pulled up to a high level and maintained for one bit period for the following purposes: 1. Designing a fixed delay time so that a fixed time difference is formed with the last bit whose level in the last half bit period is a high level state, thereby reducing the time error caused by the low level state; 2. Allowing the frame end to end with a high level, and then starting the timing of the preset low level holding time tHoldLowBMC by uniformly lowering the level of the configuration signal line.

[0057] In step 1, the sending device ensures that the receiving device locks the last bit through the last bit of the current frame data. The last half bit period of the last bit is low level, causing the sending device to drive the configuration signal line to pull up the level. Based on this, it is not only determined that the sending device has sent the last bit of the current frame data, but also allows the receiving device to receive the last bit of the current frame data, and also establishes the timing starting point of the first target timing time (corresponding to the initial time). Schematically, the initial time is as follows Figure 5 and Figure 6 As shown in the last rising edge moment of the last bit of the current frame data, correspondingly, the last half bit period of the last bit of the current frame data shown in the figure is output as a low level, then the last rising edge moment of the UI occupied by the last bit of the current frame data is recorded as the initial moment. At the initial moment, the current frame data is preferably received by the receiving device.

[0058] The case where the level of the configuration signal line in the last half bit period of the last bit is a low level includes that the configuration signal line is at a low level only in the last half bit period in the bit period of the last bit, corresponding to Figure 5 Schematic diagram of a waveform, at this time, the bit value in the last bit is logic 1; or, the situation in which the level of the configuration signal line in a bit period of the last bit is a low level includes the level of the configuration signal line in the bit period of the last bit being a low level, corresponding to Figure 6 Schematic diagram of the waveform, at this time the bit value in the last bit is logic 0.

[0059] The last bit is the latest bit sent in the frame tail of the current frame data. It should be noted that during the data transmission process between the sending device and the receiving device, the sending device packages the data into frames for transmission. After receiving the data, the receiving device will parse and process the frame according to the information in the frame header. After the step 1 sends the last bit of the current frame data, if the last half bit period of the last bit of the current frame data is a low level, the configuration signal line is driven to be pulled up to a high level and maintained for a bit period, and then flipped from a high level to a low level, so as to confirm that the sending device can perform the action after sending a frame of data, and it is also convenient for the sending device and the receiving device to distinguish frame tails of different level types.

[0060] As embodiment 3, Figure 5 As shown, in the bit period occupied by the last bit of the current frame data, the configuration signal line is at a low level only in the last half bit period of the last bit of the current frame data, indicating that the bit data of the last bit of the current frame data is logic 1; then Figure 5At the rising edge of the last bit indicated, the configuration signal line is driven to a low level, and then the configuration signal line is controlled to maintain the preset low level holding time tHoldlowBMC at a low level, and then a configurable interval soft programmable range is reserved, and tHoldlowBMC and soft programmablerange are respectively set to adjustable time periods, and the sum of the two is equal to the maximum measurement interval maxtEndDriveBMC of the final edge, and then the configuration signal line is released, and the configuration signal line is released to a high impedance state High impedance after passing through max tEndDriveBMC from the falling edge of the last bit, so that the sending device detects the receiving interrupt response within a sufficiently long and controllable time period, and at this time, the first target timing time T1 is exceeded; then the second target timing time T2 is continued to be counted until the sending request tx_message_req is generated, and the third target timing time T3 is started to be counted to make the configuration signal line jump from the high impedance state High impedance to the sending ready state peamable for nextframe; within the third target timing time T3, after the sending request tx_message_req arrives, the configuration signal line is controlled to be set to a low level (pulled up to 0V to 1V by a pull-down resistor) to enter the sending ready state peamable fornext frame. After timing T3, the configuration signal line is driven to start sending the frame header of the next frame of data.

[0061] In the third implementation, when the last bit (frame tail) of the current frame data is at a low level in the last half bit period, no matter how long the data frame received by the receiving device is, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request is controllable; after the sending request is generated, before the frame header of the next frame data is sent, the third target timing time T3 will be kept counting, forming a fixed inter-frame interval. Figure 5It can be seen that the present application can fix the first target timing time T1 and the second target timing time T2, and then time the frame header from the generation of the sending request to the start of sending the next frame of data, and time out the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the successive transmission of two adjacent frames of data and the transition from the software sending the sending request to the hardware detecting the sending request; however, step 3 disclosed in the present application is controllable for the time error, limited to one bit period UI, and will not affect the stability of the inter-frame interval; therefore, in the case of a low level in the last half bit period of the frame end, relative to the case of a high level in the last half bit period of the frame end, no matter how long the same sending device sends a frame of data, the error from the sending request generated by the software to the start of the sending device sending the next frame of data is controllable, thereby realizing dynamic regulation of the time error according to different situations, reducing the time error caused by the transmission of different frame data, and overcoming the influence of the uncertain time range in the prior art on the stability and reliability of data communication.

[0062] As embodiment 4, Figure 6 As shown, in the bit period occupied by the last bit of the current frame data, the configuration signal line is at a low level only in one bit period of the last bit of the current frame data, indicating that the bit data of the last bit of the current frame data is logic 0; then Figure 6At the rising edge of the last bit indicated, the configuration signal line is driven to a low level, and then the configuration signal line is controlled to maintain the preset low level holding time tHoldlowBMC at a low level, and then a configurable interval soft programmable range is reserved, and tHoldlowBMC and soft programmable range are respectively set to adjustable time periods, and the sum of the two is equal to the maximum measurement interval max tEndDriveBMC of the final edge, and then the configuration signal line is released to a high impedance state, and the configuration signal line is released to a high impedance state High impedance after passing through maxtEndDriveBMC from the falling edge of the last bit, so that the sending device detects the receiving interrupt response within a sufficiently long and controllable time period, and the first target timing time can also be maintained at a fixed value; then the second target timing time T2 is continued to be counted until the sending request tx_message_req is generated, and then the third target timing time T3 is started to be counted to make the configuration signal line jump from the high impedance state High impedance to the sending ready state peamable fornext frame; within the third target timing time T3, after the sending request tx_message_req is generated, the configuration signal line is controlled to be set to a low level, entering the sending ready state peamable for next frame, and after the timing T3, the configuration signal line is driven to start sending the frame header of the next frame data.

[0063] In the fourth implementation, when the last bit (frame tail) of the current frame data is at a low level during the entire bit period, no matter how long the data frame received by the receiving device is, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request is controllable; after the sending request is generated, the third target timing time T3 is kept counting before the frame header of the next frame data is sent. Figure 6It can be seen that the present application can fix the first target timing time T1 and the second target timing time T2, and then time the frame header from the generation of the sending request to the start of sending the next frame data, and time out the third target timing time T3, which becomes the transition stage in the inter-frame interval, including the successive transmission of two adjacent frames of data and the transition from the software sending the sending request to the hardware detecting the sending request. At least relative to the inter-frame interval tInterframeGap in the ideal state, a time error may be generated. However, step 3 disclosed in the present application is controllable for the time error, limited to one bit period UI, and will not affect the stability of the inter-frame interval; therefore, when the entire bit period at the end of the frame is at a low level, relative to the entire bit period at the end of the frame, when the entire bit period at the end of the frame is at a high level, no matter how long the sending device sends a frame of data, the error from the sending request generated by the software to the start of the sending device sending the next frame of data is controllable, and the time error is dynamically adjusted according to different situations, reducing the time error caused by the transmission of different frame data, and overcoming the influence of the uncertain time range in the prior art on the stability and reliability of data communication.

[0064] Combination Figures 5 and 6 It can be seen that before the sending request tx_message_req arrives, in step 2, when the sending device detects the receiving interrupt response, the configuration signal line is released to enter the high impedance state High impedance, and at this time, the time interval between the falling edge of the last bit shown in the figure and the rising edge of the high impedance state High impedance (the moment when the level of the configuration signal line is pulled up) is determined to be less than or equal to the first target timing time T1. Specifically, within the first target timing time T1, when the current frame data is sent, no matter whether the last bit of the current frame data is logic 0 or logic 1, as long as the configuration signal line is at a low level in the second half of the bit period of the last bit of the current frame data, it is subsequently pulled high and maintained for a bit period, and then the configuration signal line is continuously pulled low for a preset low level holding time tHoldLowBMC and a configurable soft programmable range, and then the configuration signal line is released to the high impedance state, that is, a controllable low level time is added at the end of a frame of data before the data transmission is terminated, so as to reduce the influence of the level state of the last bit of the current frame data on the first target timing time T1.

[0065] The configurable soft programmable range is the time interval from the time when the configuration signal line is determined to maintain a low level to the preset low level holding time tHoldLowBMC to the time when it is released to a high impedance state. Since the time interval from the time when the configuration signal line is determined to maintain a low level to the preset low level holding time tHoldLowBMC to the time when it is released to a high impedance state is configurable, and the receiving interrupt response is pre-configured to be generated at the corresponding triggering moment, the soft programmable range is configurable. Therefore, the time interval from the time when the configuration signal line is determined to maintain a low level to the preset low level holding time tHoldLowBMC to the time when the sending device detects the receiving interrupt response is configurable. Finally, by dynamically adjusting tHoldLowBMC and the soft programmable range, the first target timing time T1 is adjusted to a fixed value, so that when the level of the configuration signal line in the last half bit period of the last bit is high, it is compatible with the second half bit period of the last bit of the current frame data being high to cope with different data length transmission situations.

[0066] Based on the above embodiment, in order to constrain the time error of the inter-frame interval to be within a controllable time range under different levels in the last half bit period of the last bit, it is selected that when the preset low level holding time is configured as a fixed value, the configurable interval required to be timed when the level in the last half bit period of the last bit is a high level is smaller than the configurable interval required to be timed when the level in the last half bit period of the last bit is a low level, so that the first target timing time is configured as a fixed value when the level in the last half bit period of the last bit is a high level or a low level. Finally, by dynamically adjusting tHoldLowBMC and soft programmable range, the first target timing time T1 is adjusted to a fixed value, so that when the level of the configuration signal line in the last half bit period of the last bit is a high level or a low level, it is compatible with the second half bit period of the last bit of the current frame data being a high level to cope with different data length transmission situations.

[0067] As an embodiment, a method for transmitting each frame of data between a transmitting device and a receiving device in the form of bi-phase mark coding includes: First, for each frame of data to be transmitted, including the current frame of data and the next frame of data, the specific bi-phase mark encoding is in the form of: If the level of the configuration signal line at the start of the current bit period jumps once relative to its level in the last half bit period of the previous bit period, the current bit period is timed and the level of the configuration signal line is detected during the timing process.

[0068] If it is detected that the level of the configuration signal line changes only once in the middle of the current bit period during the current bit period, the data transmitted during the current bit period is identified as logic 1, corresponding to Figure 2 The Data in indicates a high level.

[0069] Corresponding to Figure 2 In the present invention, the current bit period is the second bit period UI, and the level of the configuration signal line is represented by BMC; in the second bit period UI, the level of the configuration signal line changes only once in the middle of the current bit period, that is, the level of the configuration signal line maintains a high level in the first half of the bit period, and then maintains a low level in the second half of the bit period.

[0070] Corresponding to Figure 2 In the figure, the current bit period is the 4th bit period UI, and the level of the configuration signal line is represented by BMC; within the 4th bit period UI, the level of the configuration signal line changes only once in the middle of the current bit period, that is, the level of the configuration signal line first maintains a low level in the first half of the bit period, and then maintains a high level in the second half of the bit period.

[0071] If it is detected that the level of the configuration signal line does not jump in the current bit period, the data transmitted in the current bit period is identified as logic 0, corresponding to Figure 2 The Data in indicates a low level.

[0072] Corresponding to Figure 2 In the present invention, the current bit period is the first bit period UI, and the level of the configuration signal line is represented by BMC; within the first bit period UI, if the level of the configuration signal line does not change within the current bit period, the level of the configuration signal line remains at a low level.

[0073] Corresponding to Figure 2 In the present invention, the current bit period is the third bit period UI, and the level of the configuration signal line is represented by BMC; within the third bit period UI, if the level of the configuration signal line does not jump within the current bit period, the level of the configuration signal line remains at a high level.

[0074] Since the bi-phase mark coding reverses the level at the beginning of each bit period, the level change can be used to represent logic within a bit period. If the level is reversed in the middle of the bit period, it represents logic 1, otherwise it represents logic 0. Therefore, as long as it is determined whether there is a level reversal in a bit period at the end of each bit, logic 0 and 1 can be distinguished.

[0075] It should be noted that Bi-Phase Mark Coding (BMC) is a physical layer signaling scheme for transmitting USB power delivery messages. This encoding assumes that there is a dedicated DC connection, identified as the CC line, for sending PD messages. Bi-Phase Mark Coding is a version of Manchester encoding (see [IEC 60958-1]). In BMC, there is a transition at the beginning of each bit time (UI), and a second transition in the middle of the UI when a 1 is transmitted. BMC is effectively DC balanced, (each 1 is DC balanced, and two consecutive 0s are DC balanced, regardless of the number of intervening 1s). It has limited parallax (limited to 1 bit, so a very low DC level).

[0076] According to the definition in Chapter 4, Section 2 of the IEC60958-1:2021 version of the standard specification, each bit to be transmitted is represented by a symbol consisting of two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. If the bit to be transmitted is a logical 0, the second state of the symbol is the same as the first state, but if the bit is a logical 1, it will be different; in short, within a CLOCK cycle, if the level jumps, it is 1, and if the level does not change, it is 0. Encoded as 0, there is only one jump at the beginning of the UI (the jump can be from low to high when it was originally low, and from high to low when it was originally high), and it does not change during the UI. Encoded as 1, in addition to the jump at the beginning of the UI, it will also jump in the middle of the UI.

[0077] The present application also discloses a chip, which includes a processing unit, a storage unit, and a computer program stored in the storage unit and executable on the processing unit, wherein the computer program implements the communication control method as described above when executed by the processing unit.

[0078] PD (power delivery) is a fast charging technology, which is a charging method that can make the battery reach or approach a fully charged state within 1 to 5 hours. It is often used for charging traction batteries when they need to recover to a fully charged state in a shorter time. The PD chip is a chip with a fast charging function, which is generally used as a chip module of a power adapter. The chip disclosed in the present application can be applied as a PD chip. A communication protocol is established between the mobile terminal and the power adapter, and the power adapter adjusts the output voltage and output current in real time according to the request of the mobile terminal, and realizes the adjustment and control of each link of the system. Therefore, the communication stability and reliability between the mobile terminal and the power adapter will directly affect the stability and safety of the charging process, so the PD chip is required to execute the communication control method.

[0079] The communication protocol between the mobile terminal and the power adapter may be verified by connecting two PD chips. The CC (Channel Configuration) line is used to configure the power supply of the two connected devices. USB PD uses BMC (Bi-Phase Mark Coding) for transmission. The aforementioned sending device is the power supply device (for example, the power adapter), and the receiving device is the powered device.

[0080] The chip executes steps 1 to 3 of the aforementioned communication control method, starting from the frame tail stage of the current frame data, sequentially configures the required timing value for setting the configuration signal line to a low level, detecting the receiving interrupt response and the fixed / dynamic configuration of the boundary timing moment corresponding to the sending request, so that the inter-frame interval becomes a configurable fixed value when two frames of data are transmitted successively; The chip disclosed in the present application is equivalent to generating the receiving interrupt response and the sending request at fixed triggering moments successively through pre-configured first target timing time and second target timing time. Therefore, no matter how long the data frame received by the receiving device is, whether the last half bit period of the last bit is high level or low level, the time from the completion of data frame reception to the generation of the receiving interrupt response and the sending request successively is controllable; after the sending request is generated, a pre-configured time error is formed by timing the third target timing time, and the next frame of data is sent only after the third target timing time is timing. Therefore, from the perspective of the sending device: no matter how long the data is sent and what the level is in the last half bit period of the last bit, the time for keeping the configuration signal line at a low level at the end of the frame is controllable and can be controlled to a fixed value; from the perspective of the receiving device: no matter how long the received data is and what the level is in the last half bit period of the last bit, the time between the completion of the reception of the current frame data and the detection of the receiving interrupt response is controllable and can be controlled to a fixed value; from the perspective of the sending device: no matter how long the single frame data is sent or what the type of data frame is, the time error from the generation of the sending request to the start of sending the next frame data is controllable and can be controlled to a fixed value. In summary, the chip dynamically adjusts according to different situations so that the absolute error range of the time generated by the inter-frame interval in various situations is controllable, and the communication reliability and efficiency between the sending device and the receiving device are improved by fixing the time error corresponding to the inter-frame interval, reducing the bit error rate, simplifying the design of the communication protocol stack, and enhancing the robustness of the system.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or some technical features can be replaced by equivalents without departing from the spirit of the technical solution of the present invention, which should be included in the scope of the technical solution for protection of the present invention.

Claims

1. A communication control method for interframe spacing, characterized in that: include: Step 1: After the sending device sends the last bit of the current frame data, start timing and record the initial time, and at the same time drive the configuration signal line to a low level according to the level in the last half bit period of the last bit, and control the configuration signal line to maintain a low level within the predicted time period, and then release the configuration signal line to a high impedance state, and detect the receiving interrupt response, and then execute step 2; wherein the receiving interrupt response is an interrupt signal generated by timing triggering after the receiving device receives the last bit of the current frame data; Step 2, after the sending device detects the receiving interrupt response, keep timing and detect the sending request, and then execute step 3; wherein the sending request is a request signal for sending the next frame of data generated by timing triggering after the sending device detects the receiving interrupt response; Step 3: After the sending device detects the sending request, the sending device starts to send the frame header of the next frame of data, and determines the time interval from the initial moment to the current moment as the inter-frame interval; The receiving interrupt response and the sending request are used to constrain the time error existing in the inter-frame interval to be within a controllable time range under different levels in the last half bit period of the last bit; The sending device is connected to the receiving device via a configuration signal line; each frame of data is transmitted between the sending device and the receiving device in the form of bi-phase mark coding.

2. The communication control method according to claim 1, characterized in that: In step 1, after driving the configuration signal line to a low level, timing the time the configuration signal line maintains a low level; After counting that the time for which the configuration signal line is kept at a low level reaches a preset low level holding time, keep counting, and after counting that the time for which the configuration signal line is kept at a low level reaches a configurable interval, release the configuration signal line to a high impedance state to wait for the reception interrupt response to be detected; The predicted time period includes a preset low-level holding time and a configurable interval period, and both the preset low-level holding time and the configurable interval period are configurable time periods.

3. The communication control method according to claim 2, characterized in that: The communication control method further includes: When the sending device detects the receiving interrupt response, determining the time interval between the initial moment and the moment when the receiving interrupt response is detected as a first target timing time; Among them, the sum of the preset low-level holding time and the configurable interval segment is less than or equal to the first target timing time; when the sending device sends the current frame data, the receiving device receives the current frame data through the configured signal line; the time interval from the receiving device receiving the last bit of the current frame data to detecting the receive interrupt response is a configurable time period, so that the first target timing time remains fixed under different level conditions within the last half bit period of the last bit.

4. The communication control method according to claim 3, characterized in that: In step 2, after the sending device detects a receive interrupt response, the time during which the configuration signal line remains in a high-impedance state is timed; when the time during which the configuration signal line remains in a high-impedance state reaches a second target timing time, it is determined that the sending request has been generated; wherein the second target timing time is a configurable time period, so that the second target timing time remains fixed under different levels within the last half bit period of the last bit.

5. The communication control method according to claim 4, characterized in that: After the sending request is generated, the configuration signal line is controlled to be set from a high impedance state to a low level, so as to guide the sending device to enter a sending preparation state; after the sending device crosses the sending preparation state, the sending device detects the sending request to execute step 3; In step 3, the configuration signal line is driven to start sending the next frame of data so that the sending device starts sending the frame header of the next frame of data, and the time interval between the generation of the sending request and the start of sending the frame header of the next frame of data is set to the third target timing time, so that the sum of the first target timing time, the second target timing time and the third target timing time is determined as the inter-frame interval, wherein the time error of the third target timing time is configurable, so that the time error of the inter-frame interval is within a controllable time range under different levels within the last half bit period of the last bit.

6. The communication control method according to claim 3, characterized in that: The method of driving the configuration signal line to a low level according to the level condition in the last half bit period of the last bit comprises: After detecting that the level of the configuration signal line is at a high level in the last half bit period of the last bit, the level of the configuration signal line is pulled down to a low level, so as to drive the configuration signal line to a low level when the falling edge of the last bit arrives, and at the same time determine that the sending device has sent the last bit of the current frame data, and record the time of the last falling edge of the last bit as the initial time; The last bit is a bit that is sent last in the frame tail of the current frame data.

7. The communication control method according to claim 6, characterized in that: The method of driving the configuration signal line to a low level according to the level condition in the last half bit period of the last bit comprises: After detecting that the level of the configuration signal line in the last half bit period of the last bit is a low level, firstly pull up the level of the configuration signal line to a high level, and at the same time determine that the sending device has sent the last bit of the current frame data, and record the time of the last rising edge of the last bit as the initial time, then drive the configuration signal line to maintain a high level within a bit period, and then pull down the level of the configuration signal line to a low level; The last bit is a bit that is sent last in the frame tail of the current frame data.

8. The communication control method according to claim 7, characterized in that: When the preset low-level holding time is configured as a fixed value, the configurable interval required for timing when the level in the last half bit period of the last bit is a high level is smaller than the configurable interval required for timing when the level in the last half bit period of the last bit is a low level, so that the first target timing time is configured as a fixed value when the level in the last half bit period of the last bit is a high level or a low level.

9. The communication control method according to claim 1, characterized in that: The method for transmitting each frame of data between a transmitting device and a receiving device in the form of bi-phase mark encoding includes: If the level of the configuration signal line at the start of the current bit period jumps once relative to the level of the configuration signal line at the last half bit period of the previous bit period, timing the current bit period and detecting the level of the configuration signal line during the timing process; If it is detected that the level of the configuration signal line changes only once in the middle of the current bit period during the current bit period, the data transmitted during the current bit period is identified as logic 1; in the current bit period, the situation that the level of the configuration signal line changes only once in the middle of the current bit period is that the level of the configuration signal line first maintains a high level in the first half of the bit period and then maintains a low level in the second half of the bit period; or the situation that the level of the configuration signal line changes only once in the middle of the current bit period is that the level of the configuration signal line first maintains a low level in the first half of the bit period and then maintains a high level in the second half of the bit period; If it is detected that the level of the configuration signal line does not change during the current bit period, the data transmitted during the current bit period is identified as logic 0; if the level of the configuration signal line does not change during the current bit period, the level of the configuration signal line remains high or low.

10. A chip, characterized in that: The chip includes a processing unit, a storage unit, and a computer program stored in the storage unit and executable on the processing unit. When the computer program is executed by the processing unit, the communication control method according to any one of claims 1 to 9 is implemented.

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