Data searching method and system

Abstract

The invention relates to the technical field of communication, and provides a data search method and system.The method comprises the steps that a first search instruction is obtained in response to a search request, and the first search instruction is sent to a second network search chip from a first network search chip through cross-asynchronous operation, the first network search chip and the second network search chip are connected in series; according to the first search instruction, executing a search operation in a first network search chip to output a first return result, and executing the search operation in a second network search chip to output a second return result; according to the first return result and the second return result, a search result is output, and the search capacity of the search result is the sum of the first network search chip and the second network search chip. According to the method, the network search capacity is improved in a cascading mode under the condition that the cost is not increased, so that the problem that the network search capacity is limited is solved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data search method and system. Background Art

[0002] The network search table capacity is the storage capacity of network devices, such as routers and switches, used to store routing table entries, access control lists, QoS (Quality of Service) policies and other rules. The capacity of these entries affects the performance and function of the device.

[0003] As data centers have increasing capacity requirements for network equipment, for example, there is a greater demand for specification items such as routing, MAC (Media Access Control), and ACL (Access Control List). Network equipment meets higher specification item requirements by expanding TCAM (Ternary Content Addressable Memory / network search chip) chips.

[0004] However, the TCAM chip matches and searches in the RAM (Random Access Memory) built into the chip according to the search instructions. The search capacity depends on the size of the RAM space. For a single TCAM chip, due to size and cost constraints, the size of its built-in RAM is limited, resulting in limited network search capacity. Summary of the invention

[0005] The present application provides a data search method and system to solve the problem of limited network search capacity.

[0006] In a first aspect, the present application provides a data search method, comprising: In response to the search request, obtaining a first search instruction; Sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation, wherein the first network search chip and the second network search chip are arranged in series; According to the first search instruction, performing a search operation in the first network search chip to output a first return result, and performing a search operation in the second network search chip to output a second return result; A search result is output according to the first returned result and the second returned result, wherein the search capacity of the search result is the sum of the search capacity of the first network search chip and the second network search chip.

[0007] In some feasible embodiments, sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation includes: Converting the first search instruction into a second search instruction through a first serial interface of a first network search chip; storing the second search instruction in a first-in-first-out queue; performing cross-clock domain processing on the second search instruction through the first-in-first-out queue to output a third search instruction; The third search instruction is sent to the second network search chip through the second serial interface of the first network search chip.

[0008] In some feasible embodiments, performing a search operation in the second network search chip to output a second return result includes: converting the third search instruction into a fourth search instruction through the third serial interface of the second network search chip; The fourth search instruction is parsed, and according to the parsed fourth search instruction, a search operation is performed in a memory in the second network search chip to output a second return result.

[0009] In some feasible embodiments, outputting the search result according to the first returned result and the second returned result includes: Parsing the second returned result to output a third returned result, wherein the second returned result at least includes control information, a check code, and a search result, and the third returned result includes the search result; A priority comparison is performed on the first returned result and the third returned result to output a search result, wherein the search result is a return result with a higher priority.

[0010] In some feasible embodiments, performing a priority comparison on the first returned result and the third returned result to output a search result includes: Preset priority rules, where the priority rules are field-based comparison rules; Extracting a field of the first returned result to output a first field, extracting a field of the third returned result to output a second field, wherein the field is a binary number; If the first field is smaller than the second field, output the search result, which is the first field; If the first field is greater than the second field, output the search result, where the search result is the second field; If the first field is equal to the second field, a first number and a second number are obtained, wherein the first number is the number of the first network search chip and the second number is the number of the second network search chip; If the first number is less than the second number, output the search result, where the search result is the first field; If the first number is greater than the second number, the search result is output, and the search result is the second field.

[0011] In some feasible embodiments, the first network search chip includes a plurality of first network search sub-chips arranged in series; Before sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation, the method includes: The first search instruction is sent from the first first network search sub-chip to the next first network search sub-chip through a cross asynchronous operation, until the last first network search sub-chip obtains the first search instruction from the previous first network search sub-chip.

[0012] In some feasible embodiments, sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation includes: Converting the first search instruction into a fifth search instruction through the first serial interface of the previous first network search sub-chip; storing the fifth search instruction in a first-in-first-out queue; Performing cross-clock domain processing on the fifth search instruction through the first-in-first-out queue to output a sixth search instruction to the next first network search sub-chip until the last first network search sub-chip outputs the third search instruction; The third search instruction is sent to the second network search chip through the second serial interface of the last first network search sub-chip.

[0013] In some feasible embodiments, the first returned result includes a plurality of first returned sub-results; The outputting the search result according to the first returned result and the second returned result includes: Acquire a target sub-chip, where the target sub-chip is a first network search sub-chip that sends a third search instruction to a second network search chip; Parsing the first search instruction, and performing a search operation in the memory of the target sub-chip according to the parsed fourth search instruction to output a first first return sub-result, and performing a search operation in the memory of the previous first network search sub-chip of the target sub-chip to output a second first return sub-result; Performing a priority comparison on the first returned sub-result and the second returned result to output a sub-search result; A priority comparison is performed on the sub-search result and the second first returned sub-result to output a search result.

[0014] In some feasible embodiments, the method further includes: Packaging the search results; The packaged search results are sent to the network processor via the first serial interface of the first network search chip.

[0015] In a second aspect, the present application also provides a data search system, comprising: An acquisition unit, configured to acquire a first search instruction in response to a search request; an asynchronous transmission unit, configured to send the first search instruction from the first network search chip to the second network search chip through a cross-asynchronous operation, wherein the first network search chip and the second network search chip are arranged in series; A search unit, configured to perform a search operation in a first network search chip according to the first search instruction to output a first return result, and perform a search operation in a second network search chip to output a second return result; The arbitration unit is used to output a search result according to the first returned result and the second returned result, wherein the search capacity of the search result is the sum of the search capacity of the first network search chip and the second network search chip.

[0016] As can be seen from the above technical solutions, the present application provides a data search method and system, wherein the method obtains a first search instruction in response to a search request, and sends the first search instruction from a first network search chip to a second network search chip through a cross-asynchronous operation, wherein the first network search chip and the second network search chip are arranged in series; according to the first search instruction, a search operation is performed in the first network search chip to output a first return result, and a search operation is performed in the second network search chip to output a second return result; according to the first return result and the second return result, a search result is output, and the search capacity of the search result is the sum of the search capacity of the first network search chip and the second network search chip. The method improves the network search capacity by cascading without increasing the cost, so as to solve the problem of limited network search capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A flowchart of a data search method is provided for an embodiment of the present application; Figure 2 A schematic diagram of a process of cascading two chips provided in an embodiment of the present application; Figure 3 A schematic diagram of a first-in-first-out queue process provided in an embodiment of the present application; Figure 4 A schematic diagram of a process of cascading three chips provided in an embodiment of the present application; Figure 5 A schematic diagram of a process for comparing priority fields provided in an embodiment of the present application; Figure 6 A schematic diagram of a priority number comparison process provided in an embodiment of the present application; Figure 7 A schematic diagram of a priority comparison process of three chips cascaded according to an embodiment of the present application; Figure 8 A schematic diagram of a priority comparison process of four chips cascaded according to an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a data search system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0020] During the design and manufacturing process of a single network search chip, the size of its built-in RAM is restricted by many factors, mainly due to the chip's size, cost, power consumption and the diversity of application scenarios.

[0021] First, the size of a chip is limited because manufacturers need to integrate as many functions and components as possible within a limited physical space. As a component of a chip, the size of RAM is directly limited by the total size of the chip. If the RAM is too large, it will take up too much space inside the chip, which may prevent other key components from being integrated, thus affecting the overall performance and functionality of the chip.

[0022] Secondly, the increase in RAM capacity means that more silicon wafers and more complex manufacturing processes are required, which will lead to an increase in chip costs. Manufacturers need to control costs while ensuring performance to maintain product competitiveness. Therefore, the size of RAM needs to find a balance between cost and performance.

[0023] Third, the power consumption of RAM increases with its capacity. In chip design, for battery-powered devices, power consumption directly affects the heat generated by the chip and the battery life. Too much RAM will increase the power consumption of the chip, which may cause the chip to heat up severely and even require additional cooling measures, further increasing cost and complexity.

[0024] Different application scenarios have different requirements for RAM capacity. For example, some simple web search tasks may only require a small amount of memory space, while complex image or video processing tasks may require a larger amount of memory. If chips are designed according to the maximum capacity, then in many application scenarios, this design will not be optimal, and too much memory will be wasted, while the chip area, cost and power consumption will not be reduced.

[0025] In summary, the RAM size of a single network search chip is restricted by volume, cost, power consumption, and diversity of application scenarios. Therefore, during the network search process, the network search capacity is limited due to the limited RAM size.

[0026] To solve the problem of limited network search capacity, such as Figure 1 As shown, some embodiments of the present application provide a data search method, including: S100: In response to a search request, obtain a first search instruction.

[0027] In a network device, a lookup request can be a lookup operation, such as a route lookup, an ACL match, etc. A network device, such as a router or a switch, receives a data packet or a data stream through its network interface, and then based on the destination, source address, protocol type, etc. of the data packet or the data stream, the network device determines that a lookup operation needs to be performed to determine the next processing method.

[0028] like Figure 2 As shown, in this embodiment, the network processor (NP) generates a search request based on the information of the received data packet or data stream, and the search request includes key information that needs to be searched, such as the destination IP address, source MAC address, etc., and parameters required for the search operation, such as the search type, priority, etc.

[0029] After generating the search request, the network processor generates one or more search instructions according to the content of the search request and the configuration of the device. In this embodiment, the first search instruction is a search instruction generated by the network processor and sent to the TCAM chip.

[0030] The TCAM chip is a high-performance storage chip used to quickly search for ACL (Access Control List) and routing entries. The TCAM chip can store additional "don't care" states in addition to the conventional 0 and 1, enabling TCAM to achieve more flexible and fast data matching and searching. In TCAM, each bit has three states: 0, 1, and "don't care", also known as "wildcard" or "X", which means ignore. This three-state storage capability enables TCAM to perform both exact match searches and fuzzy match searches.

[0031] The first search instruction includes the key field and value to be searched, and the type of search operation to be performed by the TCAM chip, such as exact match, longest prefix match, etc.

[0032] The network processor sends the first search instruction to the TCAM chip through the SerDes interface (Serializer / Deserializer). Inside the network processor, since parallel processing can improve data throughput and processing speed, data exists and is processed in parallel. The first search signal is parallel data. The SerDes interface is used to convert parallel data signals into high-speed serial data signals for transmission, ensuring the integrity and accuracy of data during transmission.

[0033] S200: Sending a first search instruction from a first network search chip to a second network search chip through a cross asynchronous operation.

[0034] Among them, the first network search chip and the second network search chip are both TCAM chips. Due to the size and cost of a single network search chip, the size of its built-in RAM is limited. Too large RAM will increase the power consumption and cost of a single chip, and even exceed the design rules in certain scenarios and cannot be implemented; in addition, the capacity requirements are different for different application scenarios. If the chips are designed according to the maximum capacity, in some scenarios, it is not the optimal solution in terms of area, cost, power consumption, etc.

[0035] Therefore, in this embodiment, by adjusting the chip design architecture, the chip can be cascaded to increase the network search capacity. Multiple chips can be cascaded. For example, the first network search chip and the second network search chip are set in series. For ease of explanation, in this embodiment, the first network search chip is defined as TCAM1 and the second network search chip is defined as TCAM2. TCAM1 and TCAM2 can jointly process a search request, that is, jointly process the first search instruction.

[0036] To achieve data transmission and synchronization between TCAM1 and TCAM2, cross-asynchronous processing is used. Cross-asynchronous processing refers to the technology of collaborative processing and data exchange between multiple asynchronous systems or components. Cross-asynchronous processing allows different chips to communicate and operate without the need for complete synchronization, thereby improving flexibility and reliability.

[0037] To transmit the first search instruction, in some embodiments, the first search instruction is converted into a second search instruction through the first serial interface of the first network search chip, the second search instruction is stored in a first-in-first-out queue, cross-clock domain processing is performed on the second search instruction through the first-in-first-out queue to output a third search instruction, and the third search instruction is sent to the second network search chip through the second serial interface of the first network search chip.

[0038] TCAM1 includes two serial interfaces, namely, a first serial interface (local side serial interface) and a second serial interface (cascade side serial interface). The first serial interface is used to convert a received first search instruction into a second search instruction. The first search instruction is parallel data, and the second search instruction is high-speed serial data, that is, parallel data is converted into high-speed serial data through the first serial interface.

[0039] When TCAM1 receives the first search request and generates the first search instruction, the first search instruction is first converted into a format suitable for transmission on the serial interface, namely, the second search instruction. The conversion process may include operations such as encoding, packaging, and adding checksums to ensure the integrity and accuracy of the data during transmission.

[0040] like Figure 3 As shown, in order to handle the clock domain differences that may exist between different chips, TCAM1 includes a first-in-first-out queue (FIFO). The first-in-first-out queue is used to temporarily store the converted second search instructions until the second search instructions can be safely sent to TCAM2. When the second search instructions are written into the FIFO, they are stored in the order in which they are written. When the exit of the FIFO is ready to send data, the instructions stored therein are read and sent according to the first-in-first-out principle.

[0041] In network equipment, different chips may run at different clock frequencies, which may cause timing problems when data is transmitted between different chips. To solve the timing problem, the read and write operations of FIFO need to be processed across clock domains. Cross-clock domain processing includes the use of double buffering, handshake signals, delay lines and other technologies to ensure the safe transmission of data between different clock domains. Because different chips may run on different clock domains, direct data transmission may cause data errors or loss. Cross-clock domain processing involves data synchronization and conversion to ensure the correct transmission of data between different clock domains.

[0042] After cross-clock domain processing, the second search instruction stored in the FIFO is converted into a format suitable for processing on TCAM2, that is, the third search instruction. The third search instruction is parallel data, and the conversion process includes data decoding, depacketization, verification and other operations. When the third search instruction is ready to be sent, it will be written into the sending buffer of the second serial interface and sent to TCAM2 through the interface.

[0043] It can be understood that during the transmission of instructions, there is no need to wait for the response or confirmation of TCAM2, and the asynchronous transmission method can improve the throughput and response speed of the system.

[0044] like Figure 4 As shown, for the cascade of multiple chips, the first network search chip includes multiple first network search sub-chips arranged in series, wherein the first network search sub-chip has the same structure as the first network search chip, has the same interface and function, and is connected in series through an internal connection or a dedicated communication link. In some embodiments, the first search instruction is sent from the first first network search sub-chip to the next first network search sub-chip through a cross-asynchronous operation until the last first network search sub-chip obtains the first search instruction from the previous first network search sub-chip.

[0045] When the first network search sub-chip receives the first search instruction, it converts the first search instruction into a format suitable for transmission on the internal connection or dedicated communication link according to the process of cross-asynchronous operation. The converted instruction is stored in a first-in-first-out queue (FIFO) and waits to be sent to the next network search sub-chip. The FIFO queue can ensure the first-in-first-out order of the instructions to avoid data loss or confusion. When the next network search sub-chip is ready to receive data, it will read the instruction from the FIFO queue and perform necessary synchronization and conversion operations. This process is repeated until the first search instruction is transmitted to the last first network search sub-chip.

[0046] Specifically, the first search instruction is converted into a fifth search instruction through the first serial interface of the previous first network search sub-chip, and the fifth search instruction is stored in a first-in-first-out queue; cross-clock domain processing is performed on the fifth search instruction through the first-in-first-out queue to output the sixth search instruction to the next first network search sub-chip, until the last first network search sub-chip outputs the third search instruction, the sixth search instruction is parallel data, and the third search instruction is sent to the second network search chip through the second serial interface of the last first network search sub-chip.

[0047] When the first first network search sub-chip receives the first search instruction, the first serial interface is used to convert the first search instruction into serial data, that is, the fifth search instruction is in a high-speed serial data format, and the fifth search instruction is stored in the FIFO, waiting for further cross-clock domain processing, and then performing cross-clock domain processing on the fifth search instruction to convert the fifth search instruction into a sixth search instruction, and converted into a parallel data format to improve data transmission efficiency.

[0048] The processed sixth search instruction is sent to the next first network search sub-chip, i.e., the second first network search sub-chip, through the second serial interface of the second first network search sub-chip. The second first network search sub-chip receives the sixth search instruction and repeats the above data conversion and cross-clock domain processing process.

[0049] When the instruction reaches the last first network search sub-chip, the chip will perform final processing on the instruction it receives. After the processing is completed, the third search instruction is sent to TCAM2 through the second serial interface of the chip, so that TCAM2 can perform the search process through the third search instruction.

[0050] For the conversion of data format, taking two first network search sub-chips as an example, the first first network search sub-chip receives the first search instruction, which is parallel, and is converted into the fifth search instruction through the first serial interface, which is serial. The fifth search instruction is stored in the FIFO, and cross-clock domain processing is performed to obtain the sixth search instruction, which is parallel and is sent to the second first network search sub-chip through the internal link.

[0051] The second first network search sub-chip receives the sixth search instruction, converts it into a third search instruction through the second serial interface, the third search instruction is serial, and sends it to TCAM2 through the second serial interface.

[0052] S300: According to the first search instruction, a search operation is performed in the first network search chip to output a first return result, and a search operation is performed in the second network search chip to output a second return result.

[0053] TCAM1 and TCAM2 can work in parallel, that is, search at the same time, that is, TCAM1 needs to send the first search instruction to TCAM2 first, and when TCAM2 receives the search instruction, TCAM1 and TCAM2 search at the same time. TCAM1 and TCAM2 can work non-parallel, that is, search non-simultaneously, that is, when TCAM1 receives the first search instruction, it can perform a search operation according to the first search instruction, and send the first search instruction to TCAM2 at the same time, and when TCAM2 receives the search instruction, TCAM2 starts searching. In this case, TCAM1 does not need to wait for TCAM2 to receive the instruction before starting the search, and the two chips perform the search task independently.

[0054] For the search operation of TCAM1, the first search instruction reaches the search engine, which includes a key processing unit (KPU), a comparison unit (compare), and multiple RAMs. The first search instruction is transmitted to the KPU, which parses the first search instruction and identifies its key information, such as the search target, search conditions, etc. Based on the parsing results, the KPU generates a master key, which is a keyword or index used to search and match in the RAM.

[0055] RAM is a component used to store and quickly access data in the network. In network search chips, RAM is used to store search indexes, keyword mappings, result caches, and other data. RAM searches and matches based on the master key to find relevant search results or index entries. The RAM uses the address bus and data bus to quickly locate and access data to ensure the efficiency of the search process.

[0056] RAM returns multiple results that match the master key, which may include multiple candidate search entries, index locations, or related data. For multiple matching results, they will be further compared and analyzed by the comparison unit. The comparison process may involve the evaluation of factors such as the weight, relevance, and ranking of the results.

[0057] In this embodiment, the first return result is returned by priority comparison. For example, four RAMs are included, and four RAMs are matched to obtain four results. For the four results, priority comparison is performed to obtain the first return result. In this embodiment, the comparison rule of the comparison unit inside TCAM1 is the same as the comparison rule of the return results of TCAM1 and TCAM2. The priority comparison rule is described in detail in S400.

[0058] For the search operation of TCAM2, after receiving the third search instruction, TCAM2 performs the search operation, wherein the third search instruction may be sent through the last first network search sub-chip or may be sent by TCAM1.

[0059] In some embodiments, the third search instruction is converted into a fourth search instruction through the third serial interface of the second network search chip, the fourth search instruction is parsed, and a search operation is performed in the memory within the second network search chip according to the parsed fourth search instruction to output a second return result.

[0060] It is understandable that, due to the different numbers of the first network search sub-chips, the third search instruction may be in parallel data format or serial data format. Regardless of the format of the third search instruction, the third serial interface converts between parallel format and serial data format.

[0061] To parse the fourth search instruction, first decode the data according to the Interlaken_LA protocol specification to restore the original search instruction information, and then start to identify the type of instruction. The Interlaken_LA protocol can support multiple types of instructions, such as read, write, search, etc., and the type of the current instruction needs to be identified based on the header information or specific identification of the instruction. For the fourth search instruction, it is identified that this is an instruction that needs to perform a search operation.

[0062] Extract the keywords or data specified in the instruction. These keywords or data are used to determine what to look for in the memory. In the Interlaken_LA protocol, keywords or data can be embedded in the instruction in a specific format or encoding. During parsing, it is necessary to extract this information according to the protocol specification and ensure accuracy and completeness.

[0063] In addition to keywords or data, the search instruction may also specify a search range, which may be a specific memory address range, a data type set, or any other condition that can limit the search boundary. The search range will be determined based on the information in the instruction during parsing. The parsed instruction information is passed to the search engine in TCAM2.

[0064] The search engine of TCAM2 also includes KPU, comparison unit and multiple RAMs. The search process of TCAM2 is the same as that of TCAM1. KPU generates a master key based on the parsed instruction information, and RAM returns multiple results that match the masterkey. For the multiple matching results, they will be further compared and analyzed by the comparison unit, and the second return result will be returned through priority comparison.

[0065] After obtaining the second returned result, it needs to be packaged into a format suitable for transmission. In this embodiment, it is packaged through the Interlaken protocol. Interlaken is a high-speed serial interface protocol suitable for application scenarios with high data transmission rate and large bandwidth requirements. According to the Interlaken protocol specification, a data packet containing the search result is constructed. This construction process includes steps such as data formatting and adding a checksum to ensure the integrity and accuracy of the data.

[0066] The constructed data packet is sent back to TCAM1 through the third serial interface. This sending process may involve steps such as data serialization and encoding conversion to meet the needs of serial transmission.

[0067] S400: Output the search result according to the first returned result and the second returned result.

[0068] Based on the result found by TCAM1, i.e., the first returned result, and the result found by TCAM2, i.e., the second returned result, a priority comparison is performed and the search result is output. For the search result, since the search is performed through TCAM1 and TCAM2 together, the search capacity of the search result is the sum of TCAM1 and TCAM2, that is, the number of entries that can be processed or searched at the same time is the sum of the number of entries in TCAM1 and TCAM2.

[0069] For the second return result, since the second return result is packaged in TCAM2 and then transmitted to TCAM1, after receiving the second return result, in some embodiments, the second return result is parsed to output the third return result, and then a priority comparison is performed on the first return result and the third return result to output the search result, and the search result is a return result with a high priority.

[0070] In TCAM1, after receiving the second return result from TCAM2, decoding is first performed to restore the original result data. The decoding process is the opposite of the packaging process in TCAM2, including identifying and removing any added format information, checksum or protocol frame header. The decoded data is further parsed to generate a third return result that TCAM1 can understand and process. The parsing process may include extracting key information, converting data formats, or performing any necessary logical judgments.

[0071] After the third return result is obtained, there are two return results in TCAM1, the first return result and the third return result. Before comparison, it is necessary to clarify the priority comparison rules, which may be based on the content of the entry, the degree of matching with a specific field, the timestamp of the entry, or any other factors that can determine the priority. According to the priority rules, the first return result and the third return result are compared, and the result with the highest priority is selected as the final search result.

[0072] As Figure 5 shown, in some embodiments, a preset priority rule is provided, where the priority rule is a field-based comparison rule, the field is a 9-bit binary number, the field of the first return result is extracted to output a first field, and the field of the third return result is extracted to output a second field; if the first field is less than the second field, the search result is output, and the search result is the first field; if the first field is greater than the second field, the search result is output, and the search result is the second field.

[0073] If the fields are different, directly compare the field values. If the fields are the same, further compare the numbers of the network search chips that generate these fields. If the first field is Field1 and the second field is Field2, if Field1 < Field2 (comparing as binary numbers), the output search result is Field1. If Field1 > Field2 (comparing as binary numbers), the output search result is Field2.

[0074] Exemplarily, the first field is 000010101 (binary, equal to 21 in decimal), and the second field is 000010011 (binary, equal to 19 in decimal). 000010101 (21) is greater than 000010011 (19). Therefore, Field2 is output.

[0075] If Field1 = Field2, compare the numbers of the network search chips that generate these fields. As Figure 6 shown, if the first field is equal to the second field, obtain a first number and a second number. The first number is the number of the first network search chip, and the second number is the number of the second network search chip. If the first number is less than the second number, the search result is output, and the search result is the first field; if the first number is greater than the second number, the search result is output, and the search result is the second field.

[0076] Exemplarily, if Field1 = Field2, the first number is 001 and the second number is 010. 001 is less than 010. Therefore, Field1 is output.

[0077] The comparison units in TCAM1 and TCAM2 compare the results matched in the RAM, which also applies to the rule of field-based comparison priority and will not be elaborated here.

[0078] For the cascading of multiple chips, the first return result includes multiple first return sub-results, and the first return sub-result is the return result obtained by multiple first network search sub-chips through a search operation.

[0079] In this embodiment, if multiple chips are cascaded, the last one is TCAM2, and the others are all first network search sub-chips, and when performing priority comparison, comparison is performed for every two chips. For example, if four chips are cascaded, the first three chips are all first network search sub-chips, and the last one is TCAM2.

[0080] Since the first network search sub-chip has the same structure as TCAM1, the difference between TCAM1 and TCAM2 is that TCAM1 includes two serial interfaces and an arbitration module, while TCAM2 does not need to further transmit search instructions and only includes one serial structure, namely, the third serial interface.

[0081] like Figure 7 , Figure 8 As shown, during the priority comparison process, the return result of a chip needs to be compared with the return result of the previous chip connected to it through the arbitration module. The comparison result is then compared with the return result of the previous chip until it reaches the first chip. After the last comparison, the search result is output.

[0082] In some embodiments, a target sub-chip is obtained, the target sub-chip is a first network search sub-chip that sends a third search instruction to a second network search chip, the first search instruction is parsed, and according to the parsed fourth search instruction, a search operation is performed in the memory of the target sub-chip to output a first first return sub-result, and a search operation is performed in the memory of the previous first network search sub-chip of the target sub-chip to output a second first return sub-result, a priority comparison is performed on the first first return sub-result and the second return result to output a sub-search result; a priority comparison is performed on the sub-search result and the second first return sub-result to output the search result.

[0083] The first network search sub-chip connected to TCAM2 is determined by the third search instruction, a search operation is performed in the memory of the target sub-chip, and the first first return sub-result is output according to the parsed fourth search instruction. A search operation is also performed in the memory of the previous first network search sub-chip of the target sub-chip, and a second first return sub-result is output.

[0084] Finally, the priority comparison is performed through the aforementioned preset priority rules, and then the search result is output. For the search result, since multiple cascaded chips search together, the search capacity of the search result is the sum of the multiple cascaded chips, that is, the number of entries that can be processed or searched at the same time is the sum of the number of entries in the multiple cascaded chips.

[0085] After obtaining the search results, in some embodiments, the search results are packaged and sent to the network processor via the first serial interface of the first network search chip. The packaging process may encode the search results into a specific data format, add necessary metadata, such as a timestamp, chip number, etc., and perform any necessary encryption or verification to ensure the integrity and security of the data.

[0086] The packaged search result is sent to the network processor through the first serial interface of TCAM1. The sending process may include loading the data packet into the sending buffer of the serial interface, setting appropriate communication parameters, such as baud rate, data bit, etc., and triggering the sending operation. In some embodiments, after receiving the search result, the network processor will send a confirmation signal or feedback message to TCAM1 to confirm the correct reception of the data. TCAM1 can monitor this confirmation signal and perform error handling or retransmission operations when necessary.

[0087] It should be noted that, in this embodiment, although the structures of the first search instruction, the second search instruction, the third search instruction, the fourth search instruction, the fifth search instruction, and the sixth search instruction are different, the substantive contents of the instructions are the same, that is, the search intentions are consistent, and the same search objectives are achieved, for example, they are all looking for specific data records, keywords, or entries that meet specific conditions. The search parameters are the same, and the instruction may contain a series of search parameters, such as keywords, date ranges, data types, etc. Although the formats of the instructions are different, the values ​​of these parameters are the same in all instructions. And regardless of the format of the instruction, the party sending the instruction expects to obtain the same type of search results, for example, they all look for documents or data records related to a specific topic.

[0088] The present application improves the TCAM chip structure without increasing the search capacity of a single TCAM chip, so as to support increasing the network search capacity by cascading multiple TCAM chips.

[0089] Based on the above data search method, such as Fig. 9 As shown, some embodiments of the present application also provide a data search system, including: An acquisition unit, configured to acquire a first search instruction in response to a search request; an asynchronous transmission unit, configured to send the first search instruction from the first network search chip to the second network search chip through a cross-asynchronous operation, wherein the first network search chip and the second network search chip are arranged in series; A search unit, configured to perform a search operation in a first network search chip according to the first search instruction to output a first return result, and perform a search operation in a second network search chip to output a second return result; The arbitration unit is used to output a search result according to the first returned result and the second returned result, wherein the search capacity of the search result is the sum of the search capacity of the first network search chip and the second network search chip.

[0090] The effects of the above system embodiment when running can refer to the effects of the above method embodiment, which will not be described in detail here.

[0091] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A data search method, characterized in that: include: In response to the search request, obtaining a first search instruction; Sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation, wherein the first network search chip and the second network search chip are arranged in series; According to the first search instruction, performing a search operation in the first network search chip to output a first return result, and performing a search operation in the second network search chip to output a second return result; A search result is output according to the first returned result and the second returned result, wherein the search capacity of the search result is the sum of the search capacity of the first network search chip and the second network search chip.

2. The data search method according to claim 1, characterized in that: The step of sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation includes: Converting the first search instruction into a second search instruction through a first serial interface of a first network search chip; storing the second search instruction in a first-in-first-out queue; performing cross-clock domain processing on the second search instruction through the first-in-first-out queue to output a third search instruction; The third search instruction is sent to the second network search chip through the second serial interface of the first network search chip.

3. The data search method according to claim 2, characterized in that: The performing a search operation in the second network search chip to output a second return result includes: converting the third search instruction into a fourth search instruction through the third serial interface of the second network search chip; The fourth search instruction is parsed, and according to the parsed fourth search instruction, a search operation is performed in a memory in the second network search chip to output a second return result.

4. The data search method according to claim 3, characterized in that: The outputting the search result according to the first returned result and the second returned result includes: Parsing the second returned result to output a third returned result, wherein the second returned result at least includes control information, a check code, and a search result, and the third returned result includes the search result; A priority comparison is performed on the first returned result and the third returned result to output a search result, wherein the search result is a return result with a higher priority.

5. The data search method according to claim 4, characterized in that: The performing a priority comparison on the first returned result and the third returned result to output a search result includes: Preset priority rules, where the priority rules are field-based comparison rules; Extracting a field of the first returned result to output a first field, and extracting a field of the third returned result to output a second field, wherein the field is a binary number; If the first field is smaller than the second field, output the search result, which is the first field; If the first field is greater than the second field, output the search result, where the search result is the second field; If the first field is equal to the second field, a first number and a second number are obtained, wherein the first number is the number of the first network search chip, and the second number is the number of the second network search chip; If the first number is less than the second number, output the search result, where the search result is the first field; If the first number is greater than the second number, the search result is output, and the search result is the second field.

6. The data search method according to claim 5, characterized in that: The first network search chip includes a plurality of first network search sub-chips arranged in series; Before sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation, the method includes: The first search instruction is sent from the first first network search sub-chip to the next first network search sub-chip through a cross asynchronous operation, until the last first network search sub-chip obtains the first search instruction from the previous first network search sub-chip.

7. The data search method according to claim 6, characterized in that: The step of sending the first search instruction from the first network search chip to the second network search chip through a cross asynchronous operation includes: Converting the first search instruction into a fifth search instruction through the first serial interface of the previous first network search sub-chip; storing the fifth search instruction in a first-in-first-out queue; Performing cross-clock domain processing on the fifth search instruction through the first-in-first-out queue to output a sixth search instruction to the next first network search sub-chip until the last first network search sub-chip outputs the third search instruction; The third search instruction is sent to the second network search chip through the second serial interface of the last first network search sub-chip.

8. The data search method according to claim 7, characterized in that: The first returned result includes a plurality of first returned sub-results; The outputting the search result according to the first returned result and the second returned result includes: Acquire a target sub-chip, where the target sub-chip is a first network search sub-chip that sends a third search instruction to a second network search chip; Parsing the first search instruction, and performing a search operation in the memory of the target sub-chip according to the parsed fourth search instruction to output a first first return sub-result, and performing a search operation in the memory of the previous first network search sub-chip of the target sub-chip to output a second first return sub-result; Performing a priority comparison on the first returned sub-result and the second returned result to output a sub-search result; A priority comparison is performed on the sub-search result and the second first returned sub-result to output a search result.

9. The data search method according to claim 1, characterized in that: The method further comprises: Packaging the search results; The packaged search results are sent to the network processor via the first serial interface of the first network search chip.

10. A data search system, characterized in that: include: An acquisition unit, configured to acquire a first search instruction in response to a search request; an asynchronous transmission unit, configured to send the first search instruction from the first network search chip to the second network search chip through a cross-asynchronous operation, wherein the first network search chip and the second network search chip are arranged in series; A search unit, configured to perform a search operation in a first network search chip according to the first search instruction to output a first return result, and perform a search operation in a second network search chip to output a second return result; The arbitration unit is used to output a search result according to the first returned result and the second returned result, wherein the search capacity of the search result is the sum of the search capacity of the first network search chip and the second network search chip.

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