Address allocation system and address allocation method
By designing an address allocation method for the module series communication link in the address allocation system, the problems of cumbersome manual configuration and low intelligence in the prior art are solved, and the automatic address allocation of highly intelligent addresses is realized, reducing the error rate.
Patent Information
- Application Number
- CN202411801764.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-02-18
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The existing address allocation method requires manual participation, cumbersome configuration, low intelligence, and error-prone.
Design an address allocation system, form a series of communication links through multiple modules, and the control module outputs address information to the modules in the link header. Each module determines its own target address based on the received address information and outputs it to the following One module, thus realizing automatic address allocation of all modules.
It improves the intelligence of address allocation, significantly reduces the error rate of address allocation, and realizes the automatic allocation of module addresses.
Smart Images
Figure CN119484481A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of address allocation, and in particular, relates to an address allocation system and an address allocation method. Background Art
[0002] When there are multiple modules in a system, in order to be able to access each module in the system individually, a unique identifier is usually set for each module, that is, a corresponding address is assigned to each module.
[0003] At present, the address of each module is usually configured manually, or the address board corresponding to each module is pre-configured manually, and the module reads the pre-set address on the address board as its own address. The current address allocation method requires manual participation and tedious configuration work, has a low degree of intelligence, and address allocation is prone to errors. Summary of the invention
[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes an address allocation system and an address allocation method, which have a high degree of intelligent address allocation and can greatly reduce the error rate of address allocation.
[0005] In a first aspect, the present application provides an address allocation system, the address allocation system comprising:
[0006] A control module, the control module comprising a control port;
[0007] A plurality of first modules, each of which comprises an address receiving port and an address output port, the plurality of first modules form a serial communication link, the address receiving port of the first module at the head of the communication link is communicatively connected to the control port, the address receiving port of each first module except the first module at the head of the communication link is communicatively connected to the address output port of the previous first module, and the address output port of the first module at the end of the communication link is left unconnected;
[0008] The control module is used to output address information to the address receiving port of the first module at the head of the communication link through the control port, and each of the first modules is used to determine its own target address based on the address information received by the corresponding address receiving port, and determine the address information output by the corresponding address output port based on its own target address.
[0009] According to the address allocation system of the present application, a series communication link is formed through multiple first modules, and the control module outputs address information to the address receiving port of the first module at the head of the communication link. Each first module determines its own target address based on the received address information, and determines the address information to be output by the address output port based on its own target address, and outputs it to the address receiving port of the next first module, thereby realizing automatic address allocation of all first modules. The address allocation is highly intelligent and can greatly reduce the error rate of address allocation.
[0010] According to an embodiment of the present application, the plurality of first modules are divided into a plurality of module columns arranged in sequence, and each of the module columns includes at least one of the first modules;
[0011] The address output port includes a first address output port and a second address output port. In each module column, except for the first module at the end, the first address output port of each first module is communicatively connected to the address receiving port of the next first module. The first address output port of the first module at the end of each module column is suspended. The second address output port of the first module at the end of each module column is communicatively connected to the address receiving port of the first module at the head of the next module column. The second address output port of the first module at the end of the last module column is suspended. In each module column, except for the first module at the end, the second address output port of each first module is suspended.
[0012] Each of the first modules is used to determine its own target column address and target column bit address based on the address information received by the corresponding address receiving port, each of the first modules is used to determine the address information output by the corresponding first address output port based on the target column address and the target column bit address, and each of the first modules is used to determine the address information output by the corresponding second address output port based on the target column address;
[0013] The target address includes the target column address and the target column bit address.
[0014] According to one embodiment of the present application, each of the first modules is used to determine its own target column address as the column address output by the corresponding first address output port, perform a first address allocation operation on its own target column address to obtain a first address allocation result, and determine the first address allocation result as the column address output by the corresponding first address output port.
[0015] According to one embodiment of the present application, each of the first modules is used to perform a second address allocation operation on its own target column address to obtain a second address allocation result, determine the second address allocation result as the column address output by the corresponding second address output port, and determine the address allocation preset value as the column address output by the corresponding second address output port.
[0016] According to an embodiment of the present application, the address information is represented by a frequency value.
[0017] According to an embodiment of the present application, the address information is characterized by a duty cycle.
[0018] In a second aspect, the present application provides an address allocation method, used in the address allocation system as described in the first aspect above, the method comprising:
[0019] Control the control module to output address information to the address receiving port of the first module at the head of the communication link through the control port;
[0020] Control each of the first modules to determine its own target address based on the address information received by the corresponding address receiving port;
[0021] Each of the first modules is controlled to determine the address information output by the corresponding address output port based on the target address of the first module.
[0022] According to the address allocation method of the present application, a series communication link is formed through multiple first modules, and the control module outputs address information to the address receiving port of the first module at the head of the communication link. Each first module determines its own target address based on the received address information, and determines the address information to be output by the address output port based on its own target address, and outputs it to the address receiving port of the next first module, thereby realizing automatic address allocation for all first modules. The address allocation is highly intelligent and can greatly reduce the error rate of address allocation.
[0023] According to an embodiment of the present application, the plurality of first modules are divided into a plurality of module columns arranged in sequence, each of the module columns includes at least one first module, the address output port includes a first address output port and a second address output port, and in each of the module columns, except for the first module at the end, the first address output port of each of the first modules is communicatively connected to the address receiving port of the next first module, the first address output port of the first module at the end of each of the module columns is left unconnected, the second address output port of the first module at the end of each of the module columns is communicatively connected to the address receiving port of the first module at the head of the next module column, the second address output port of the first module at the end of the last module column is left unconnected, and in each of the module columns, except for the first module at the end, the second address output port of each of the first modules is left unconnected, and the controlling each of the first modules to determine its own target address based on the address information received by the corresponding address receiving port comprises:
[0024] Control each of the first modules to determine its own target column address and target column bit address based on the address information received by the corresponding address receiving port;
[0025] The controlling each of the first modules to determine the address information output by the corresponding address output port based on the target address of the first module includes:
[0026] Control each of the first modules to determine the address information output by the corresponding first address output port based on the target column address and the target column bit address of the first module;
[0027] Control each of the first modules to determine the address information output by the corresponding second address output port based on the target column address of the first module;
[0028] The target address includes the target column address and the target column bit address.
[0029] According to an embodiment of the present application, the controlling each first module to determine the address information output by the corresponding first address output port based on the target column address and the target column bit address of the first module itself includes:
[0030] Control each of the first modules to determine its own target column address as the column address output by the corresponding first address output port, perform a first address allocation operation on its own target column address to obtain a first address allocation result, and determine the first address allocation result as the column address output by the corresponding first address output port.
[0031] According to an embodiment of the present application, the controlling each first module to determine the address information output by the corresponding second address output port based on the target column address of the first module includes:
[0032] Control each of the first modules to perform a second address allocation operation on its own target column address to obtain a second address allocation result, determine the second address allocation result as the column address output by the corresponding second address output port, and determine the address allocation preset value as the column address output by the corresponding second address output port.
[0033] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the address allocation method as described in the first aspect above when executing the computer program.
[0034] In a fourth aspect, the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the address allocation method as described in the first aspect above.
[0035] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the address allocation method as described in the first aspect above.
[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0038] Figure 1 It is one of the structural diagrams of the address allocation system provided in the embodiment of the present application;
[0039] Figure 2 This is the second structural diagram of the address allocation system provided in the embodiment of the present application;
[0040] Figure 3 It is a flowchart of the address allocation method provided in the embodiment of the present application;
[0041] Figure 4 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
[0042] Reference numerals:
[0043] Control module 110, first module 120, control port 130, address receiving port 140,
[0044] Address output port 150 , controller 121 , module list 210 . DETAILED DESCRIPTION
[0045] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0046] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0047] The address allocation system, address allocation method, electronic device and readable storage medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.
[0048] like Figure 1 As shown, the address allocation system includes a control module 110 and a plurality of first modules 120 .
[0049] The control module 110 is a module that can issue control instructions. The control module 110 includes a control port 130 , and the control module 110 outputs control instructions through the control port 130 .
[0050] The first module 120 is a basic functional unit in the address allocation system. The first module 120 can assume the main functions of the address allocation system, and the functions of multiple first modules 120 can be the same.
[0051] For example, the address allocation system may be an energy storage system, and the first module 120 may be a battery pack or an inverter, etc.; the address allocation system may be a power supply cabinet, and the first module 120 may be a single power supply.
[0052] In this embodiment, a corresponding address may be allocated to each first module 120 in the address allocation system, so that the first module 120 may be accessed according to the address of the first module 120 .
[0053] In this embodiment, if Figure 1 As shown, each first module 120 includes an address receiving port 140 and an address output port 150 , and a plurality of first modules 120 form a serial communication link.
[0054] The address receiving port 140 is a port of the first module 120 for receiving external signals or instructions, and the address output port 150 is a port of the first module 120 for sending signals or instructions.
[0055] The address receiving ports 140 and the address output ports 150 of the multiple first modules 120 are connected in sequence to form a continuous signal path, that is, a communication link. The formed communication link can enable address information and control commands to be transmitted in sequence between the multiple first modules 120.
[0056] In this embodiment, the address receiving port 140 of the first module 120 at the head of the communication link is communicatively connected to the control port 130, the address receiving port 140 of each first module 120 except the first module 120 at the head of the communication link is communicatively connected to the address output port 150 of the previous first module 120, and the address output port 150 of the first module 120 at the end of the communication link is left floating.
[0057] The control port 130 of the control module 110 is communicatively connected to the address receiving port 140 of the first first module 120 in the communication link, the address output port 150 of the first first module 120 in the communication link is communicatively connected to the address receiving port 140 of the second first module 120, and so on, the address output port 150 of each first module 120 is communicatively connected to the address receiving port 140 of the next first module 120, and the address output port 150 of the last first module 120 in the communication link is left floating.
[0058] In this embodiment, the control module 110 is used to output address information to the address receiving port 140 of the first module 120 at the head of the communication link through the control port 130, and each first module 120 is used to determine its own target address based on the address information received by the corresponding address receiving port 140, and determine the address information output by the corresponding address output port 150 based on its own target address.
[0059] Among them, the address information is information used for address allocation, and the address information can be in the form of a digital sequence. The target address is the address allocated to the first module 120 in the address allocation system, that is, the unique identifier of the first module 120 in the address allocation system, and each first module 120 corresponds to a target address.
[0060] In this embodiment, the control module 110 outputs address information to the address receiving port 140 of the first module 120 at the head of the communication link through the control port 130. The first module 120 at the head of the communication link obtains its own target address through the address information received by the address receiving port 140, calculates its own target address, obtains the address information output by the corresponding address output port 150, and outputs the calculated address information to the address receiving port 140 of the second first module 120 through the address output port 150.
[0061] The second first module 120 then obtains its own target address through the address information received by the corresponding address receiving port 140, and calculates its own target address to obtain the address information output by the corresponding address output port 150. And so on. Each first module 120 determines its own target address through the address information received by the corresponding address receiving port 140. After determining its own target address, it determines the address information output by the corresponding address output port 150 based on its own target address, and outputs it to the address receiving port 140 of the next first module 120.
[0062] In actual implementation, the first module 120 may determine the address information received by the address receiving port 140 as its own target address, and may perform mathematical operations on its own target address to obtain the address information output by the corresponding address output port 150 .
[0063] For example, the address allocation system includes three first modules 120, namely the first module 120A, the first module 120B and the first module 120C. The first module 120A, the first module 120B and the first module 120C form a communication link, wherein the first module 120A is the first module 120 at the head of the communication link, the control port 130 of the control module 110 of the address allocation system is communicatively connected with the address receiving port 140 of the first module 120A, the address output port 150 of the first module 120A is communicatively connected with the address receiving port 140 of the first module 120B, the address output port 150 of the first module 120B is communicatively connected with the address receiving port 140 of the first module 120C, and the address output port 150 of the first module 120C is suspended.
[0064] The control module 110 sends the decimal address information 10 to the address receiving port 140 of the first module 120A through the control port 130. The first module 120A determines the received address information 10 as its own target address, and then calculates its own target address, adds 10 to the address information 10, obtains the address information 20 output by the corresponding address output port 150, and outputs it to the address receiving port 140 of the first module 120B.
[0065] The first module 120B determines the received address information 20 as its own target address, and then calculates its own target address, adds 10 to the address information 20, obtains the address information 30 output by the corresponding address output port 150, and outputs it to the address receiving port 140 of the first module 120C.
[0066] The first module 120C determines the received address information 30 as its own target address, and then calculates its own target address, adding 10 to the address information 30 to obtain the address information 40 that can be output by the corresponding address output port 150. The address output port 150 of the first module 120C is left floating, and the address output port 150 of the first module 120C does not output address information.
[0067] According to the address allocation system provided in the embodiment of the present application, a series communication link is formed through multiple first modules 120, and the control module 110 outputs address information to the address receiving port 140 of the first module 120 at the head of the communication link. Each first module 120 determines its own target address based on the received address information, and determines the address information to be output by the address output port 150 based on its own target address, and outputs it to the address receiving port 140 of the next first module 120, thereby realizing automatic address allocation of all first modules 120. The address allocation is highly intelligent and can greatly reduce the error rate of address allocation.
[0068] In some embodiments, Figure 2 As shown, the plurality of first modules 120 are divided into a plurality of module columns 210 arranged in sequence, and each module column 210 includes at least one first module 120 .
[0069] The multiple first modules 120 are divided into multiple module columns 210 arranged in sequence, and the target address of each first module 120 includes a target column address and a target column position address, wherein the target column address represents the module column 210 in which the first module 120 is located, and the target column position address represents the module column 210 in which the first module 120 is located.
[0070] In this embodiment, the address output port 150 includes a first address output port and a second address output port, and the first address output port and the second address output port can be used to output different instructions or information.
[0071] In each module column 210 , except for the last first module 120 , the first address output port of each first module 120 is communicatively connected to the address receiving port 140 of the next first module 120 , and the first address output port of the last first module 120 of each module column 210 is left floating.
[0072] It can be understood that, within each module column 210, except for the first module 120 at the end of the module column 210, the first address output port of each first module 120 is communicatively connected to the address receiving port 140 of the next first module 120, and each first module 120 can output information or instructions to the next first module 120 in the module column 210 through the corresponding first address output port.
[0073] In this embodiment, the second address output port of the first module 120 at the end of each module column 210 is communicatively connected to the address receiving port 140 of the first module 120 at the head of the next module column 210, and the second address output port of the first module 120 at the end of the last module column 210 is left floating. In each module column 210, except for the last first module 120, the second address output port of each first module 120 is left floating.
[0074] It can be understood that, between the module columns 210, except for the last module column 210, the second address output port of the first module 120 at the end of each module column 210 is communicatively connected with the address receiving port 140 of the first module 120 at the head of the next module column 210, and the first module 120 at the end of each module column 210 can output information or instructions to the first module 120 at the head of the next module column 210 through the corresponding second address output port.
[0075] In this embodiment, in each module column 210, except for the last first module 120, the second address output port of each first module 120 is left floating, the first address output port of the first module 120 at the end of each module column 210 is left floating, and the second address output port of the first module 120 at the end of the last module column 210 is left floating.
[0076] In this embodiment, each first module 120 is used to determine its own target column address and target column bit address based on the address information received by the corresponding address receiving port 140, each first module 120 is used to determine the address information output by the corresponding first address output port based on its own target column address and target column bit address, and each first module 120 is used to determine the address information output by the corresponding second address output port based on its own target column address.
[0077] In this embodiment, the address information may include column address information and column position address information. The first module 120 may determine its own target column address based on the received column address information, and may determine its own target column position address based on the received column position address information.
[0078] In this embodiment, the control module 110 outputs address information to the first module 120 at the communication link head, which may include column address information and column position address information. The first module 120 at the communication link head determines its own target column address through the column address information and determines its own target column position address through the column position address information.
[0079] The first module 120 at the head of the communication link determines the column address information and column bit address information output by the corresponding first address output port based on its own target column address and target column bit address, and outputs it to the second first module 120 in the same module column 210 .
[0080] The second first module 120 determines its own target column address through the received column address information, determines its own target column position address through the received column position address information, and based on its own target column address and target column position address, determines the column address information and column position address information output by the corresponding first address output port, and outputs them to the third first module 120 in the same module column 210. Similarly, addresses can be assigned to all first modules 120 in the first module column 210.
[0081] The first module 120 at the end of the first module column 210 can determine the column address information output by the corresponding second address output port based on its own target column address, and can determine a fixed numerical value as the column position address information output by the corresponding second address output port, and output the column address information and the column position address information to the first module 120 at the head of the second module column 210.
[0082] The first module 120 at the head in the second module column 210 determines its own target column address through the received column address information, determines its own target column position address through the received column position address information, and based on its own target column address and target column position address, determines the column address information and column position address information output by the corresponding first address output port, and outputs them to the second first module 120 in the same module column 210. Similarly, addresses can be assigned to all first modules 120 in each module column 210.
[0083] In actual implementation, the first module 120 may determine the received column address information as its own target column address, and determine the received column bit address information as its own target column bit address.
[0084] The first module 120 can calculate its own target column address to determine the column address information output by the corresponding first address output port, and can calculate its own target column bit address to determine the column bit address information output by the corresponding first address output port.
[0085] The first module 120 can calculate its own target column address, determine the column address information output by the corresponding second address output port, and determine a fixed value as the column address information output by the corresponding second address output port.
[0086] In some embodiments, each first module 120 is used to determine its own target column address as the column address output by the corresponding first address output port, perform a first address allocation operation on its own target column address to obtain a first address allocation result, and determine the first address allocation result as the column address output by the corresponding first address output port.
[0087] The first address allocation operation may be to add a fixed value to the target column address, or to add 1 to the target column address to obtain the first address allocation result.
[0088] The column address outputted by the first address output port corresponds to the column address information, and the column bit address outputted by the first address output port corresponds to the column bit address information.
[0089] In some embodiments, each first module 120 is used to perform a second address allocation operation on its own target column address to obtain a second address allocation result, determine the second address allocation result as the column address output by the corresponding second address output port, and determine the address allocation preset value as the column address output by the corresponding second address output port.
[0090] The second address allocation operation may be to add a fixed value to the target column address itself, or to add 1 to the target column address, to obtain the second address allocation result.
[0091] The address allocation preset value is a preset value, and the address allocation preset value may be 1.
[0092] A specific embodiment of an address allocation system is introduced below.
[0093] The address allocation system includes a master controller, namely a control module 110, and a plurality of first modules 120, wherein the plurality of first modules 120 form an N-column stack, namely, the plurality of first modules 120 are divided into N sequentially arranged module columns 210, each module column 210 includes X1 to X N A first module 120, wherein N is an integer greater than or equal to 1, X1 to X N are integers greater than or equal to 1.
[0094] Each first module 120 includes at least one controller 121. The controller 121 of the first module 120 implements the address positioning function through three IO ports, wherein the three IO ports are an address receiving port 140, a first address output port, and a second address output port. The address receiving port 140 is defined as port 1, the second address output port is defined as port 2, and the first address output port is defined as port 3.
[0095] like Figure 2 As shown, the output signal of the control module 110 is connected to port 1 of the first module 1201-1 at the head of the first module column 210, the first module 1201-1 connects the corresponding port 3 to port 1 of the next first module 1201-2, the port 3 of the first module 1201-2 is connected to port 1 of the next first module 1201-3, and so on, until the first module 1201-X1 at the end of the first module column 210.
[0096] Port 2 of the first module 1201-X1 at the end is connected to port 1 of the first module 1202-1 at the head of the second module column 210, and the second module column 210 is connected in the same way as the first module column 210, and is synchronously extended to the Nth module column 210.
[0097] The last module NX N There is no connection between ports 2 and 3.
[0098] The control module 110 sends an address signal and outputs address information to the first module 1201 - 1 . The address information includes column address information and column position address information. The column address information is used to indicate the module column 210 in which the first module 120 is located, and the column position address information is used to indicate the position in the module column 210 in which the first module 120 is located.
[0099] Port 1 of each first module 120 receives address information, and the controller 121 of the first module 120 extracts the column address information and column position address information as its own target address. The controller 121 adds 1 to the received column address information as the corresponding column address information sent by port 2, uses 1 as the corresponding column position address information sent by port 2, uses the received column address information as the column address information sent by port 3, and adds 1 to the received column position address information as the column position address information sent by port 3.
[0100] In this embodiment, multiple first modules 120 are stacked, and multiple first modules 120 in each module column 210 form a serial sub-communication link. The first module 120 at the tail of each module column 210 sends a signal to the first module 120 at the head of the next module column 210. The address information sent by the control module 110 can realize automatic address recognition of all first modules 120, and the address includes a column address and a column position address.
[0101] The implementation method of sending address information by the IO port of the controller 121 of the first module 120 can be implemented through an agreed encoding method, for example, by sending frequency information of square wave signals of different frequencies through the IO port, or by sending duty cycle information of square wave signals through the IO port.
[0102] In some embodiments, the address information is represented by a frequency value.
[0103] In actual implementation, the frequency fields of 1 KHz and above may be used as column address information, and the fields below 1 KHz may be used as column bit address information.
[0104] For example, for 8020Hz, the KHz field is 8, the column address information is 8, the field below KHz is 020, and the column address information is 20.
[0105] In some embodiments, the address information is characterized by a duty cycle.
[0106] In actual implementation, the duty cycle represents a valid range from 5% to 95%, the tens digit of the duty cycle percentage represents the column address information, and the ones digit represents the column bit address information.
[0107] For example, 85%, the 8 in the tens place indicates that the column address information is the 8th column, and the 5 in the ones place indicates that the column address information is the 5th place in the column.
[0108] The embodiment of the present application also provides an address allocation method, which is used in the above-mentioned address allocation system.
[0109] The address allocation method provided in the embodiment of the present application may be executed by an electronic device or a functional module or functional entity in the electronic device that can implement the address allocation method. The address allocation method provided in the embodiment of the present application is described below using an electronic device as an example of the execution subject.
[0110] like Figure 3 As shown, the address allocation method includes: step 310, step 320 and step 330.
[0111] Step 310 : Control the control module 110 to output address information to the address receiving port 140 of the first module 120 at the head of the communication link through the control port 130 .
[0112] Step 320 : Control each first module 120 to determine its own target address based on the address information received by the corresponding address receiving port 140 .
[0113] Step 330 : Control each first module 120 to determine the address information output by the corresponding address output port 150 based on its own target address.
[0114] According to the address allocation method provided in the embodiment of the present application, a series communication link is formed through multiple first modules 120, and the control module 110 outputs address information to the address receiving port 140 of the first module 120 at the head of the communication link. Each first module 120 determines its own target address based on the received address information, and determines the address information to be output by the address output port 150 based on its own target address, and outputs it to the address receiving port 140 of the next first module 120, thereby realizing automatic address allocation of all first modules 120. The address allocation is highly intelligent and can greatly reduce the error rate of address allocation.
[0115] In some embodiments, the plurality of first modules 120 are divided into a plurality of module columns 210 arranged in sequence, each module column 210 includes at least one first module 120, the address output port 150 includes a first address output port and a second address output port, in each module column 210, except for the last first module 120, the first address output port of each first module 120 is communicatively connected with the address receiving port 140 of the next first module 120, the first address output port of the first module 120 at the end of each module column 210 is left unconnected, the second address output port of the first module 120 at the end of each module column 210 is communicatively connected with the address receiving port 140 of the first module 120 at the head of the next module column 210, the second address output port of the first module 120 at the end of the last module column 210 is left unconnected, and in each module column 210, except for the last first module 120, the second address output port of each first module 120 is left unconnected, and each first module 120 is controlled to determine its own target address based on the address information received by the corresponding address receiving port 140, including:
[0116] Control each first module 120 to determine its own target column address and target column bit address based on the address information received by the corresponding address receiving port 140;
[0117] Controlling each first module 120 to determine the address information output by the corresponding address output port 150 based on its own target address includes:
[0118] Control each first module 120 to determine the address information output by the corresponding first address output port based on its own target column address and target column bit address;
[0119] Control each first module 120 to determine the address information output by the corresponding second address output port based on its own target column address;
[0120] The target address includes a target column address and a target column bit address.
[0121] In some embodiments, controlling each first module 120 to determine the address information output by the corresponding first address output port based on its own target column address and target column bit address includes:
[0122] Control each first module 120 to determine its own target column address as the column address output by the corresponding first address output port, perform the first address allocation operation on its own target column address to obtain the first address allocation result, and determine the first address allocation result as the column address output by the corresponding first address output port.
[0123] In some embodiments, controlling each first module 120 to determine the address information output by the corresponding second address output port based on its own target column address includes:
[0124] Control each first module 120 to perform a second address allocation operation on its own target column address to obtain a second address allocation result, determine the second address allocation result as the column address output by the corresponding second address output port, and determine the address allocation preset value as the column address output by the corresponding second address output port.
[0125] In some embodiments, Figure 4 As shown, an embodiment of the present application also provides an electronic device 400, including a processor 401, a memory 402, and a computer program stored in the memory 402 and executable on the processor 401. When the program is executed by the processor 401, the various processes of the above-mentioned address allocation method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0126] An embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned address allocation method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0127] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium.
[0128] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned address allocation method when executed by a processor.
[0129] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium.
[0130] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned address allocation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.
[0131] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.
[0132] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.
[0133] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.
[0134] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.
[0135] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0136] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. An address allocation system, characterized in that: include: A control module, the control module comprising a control port; A plurality of first modules, each of which comprises an address receiving port and an address output port, the plurality of first modules form a serial communication link, the address receiving port of the first module at the head of the communication link is communicatively connected to the control port, the address receiving port of each first module except the first module at the head of the communication link is communicatively connected to the address output port of the previous first module, and the address output port of the first module at the end of the communication link is left unconnected; The control module is used to output address information to the address receiving port of the first module at the head of the communication link through the control port, and each of the first modules is used to determine its own target address based on the address information received by the corresponding address receiving port, and determine the address information output by the corresponding address output port based on its own target address.
2. The address allocation system according to claim 1, characterized in that: The plurality of first modules are divided into a plurality of module columns arranged in sequence, each of the module columns comprising at least one of the first modules; The address output port includes a first address output port and a second address output port. In each module column, except for the first module at the end, the first address output port of each first module is communicatively connected to the address receiving port of the next first module. The first address output port of the first module at the end of each module column is suspended. The second address output port of the first module at the end of each module column is communicatively connected to the address receiving port of the first module at the head of the next module column. The second address output port of the first module at the end of the last module column is suspended. In each module column, except for the first module at the end, the second address output port of each first module is suspended. Each of the first modules is used to determine its own target column address and target column bit address based on the address information received by the corresponding address receiving port, each of the first modules is used to determine the address information output by the corresponding first address output port based on the target column address and the target column bit address, and each of the first modules is used to determine the address information output by the corresponding second address output port based on the target column address; The target address includes the target column address and the target column bit address.
3. The address allocation system according to claim 2, characterized in that: Each of the first modules is used to determine its own target column address as the column address output by the corresponding first address output port, perform a first address allocation operation on its own target column address to obtain a first address allocation result, and determine the first address allocation result as the column address output by the corresponding first address output port.
4. The address allocation system according to claim 2, characterized in that: Each of the first modules is used to perform a second address allocation operation on its own target column address to obtain a second address allocation result, determine the second address allocation result as the column address output by the corresponding second address output port, and determine the address allocation preset value as the column address output by the corresponding second address output port.
5. The address allocation system according to any one of claims 1 to 4, characterized in that: The address information is represented by a frequency value.
6. The address allocation system according to any one of claims 1 to 4, characterized in that: The address information is characterized by a duty cycle.
7. An address allocation method, characterized in that: Used in the address allocation system according to any one of claims 1 to 6, the method comprising: Control the control module to output address information to the address receiving port of the first module at the head of the communication link through the control port; Control each of the first modules to determine its own target address based on the address information received by the corresponding address receiving port; Each of the first modules is controlled to determine the address information output by the corresponding address output port based on the target address of the first module.
8. The address allocation method according to claim 7, characterized in that: The multiple first modules are divided into multiple module columns arranged in sequence, each of the module columns includes at least one first module, the address output port includes a first address output port and a second address output port, and except for the first module at the end of each module column, the first address output port of each first module is communicatively connected with the address receiving port of the next first module, the first address output port of the first module at the end of each module column is suspended, the second address output port of the first module at the end of each module column is communicatively connected with the address receiving port of the first module at the head of the next module column, the second address output port of the first module at the end of the last module column is suspended, and except for the first module at the end of each module column, the second address output port of each first module is suspended, and the control of each first module to determine its own target address based on the address information received by the corresponding address receiving port includes: Control each of the first modules to determine its own target column address and target column bit address based on the address information received by the corresponding address receiving port; The controlling each of the first modules to determine the address information output by the corresponding address output port based on the target address of the first module includes: Control each of the first modules to determine the address information output by the corresponding first address output port based on the target column address and the target column bit address of the first module; Control each of the first modules to determine the address information output by the corresponding second address output port based on the target column address of the first module; The target address includes the target column address and the target column bit address.
9. The address allocation method according to claim 8, characterized in that: The controlling each of the first modules to determine the address information output by the corresponding first address output port based on the target column address and the target column bit address of the first module itself includes: Control each of the first modules to determine its own target column address as the column address output by the corresponding first address output port, perform a first address allocation operation on its own target column address to obtain a first address allocation result, and determine the first address allocation result as the column address output by the corresponding first address output port.
10. The address allocation method according to claim 8, characterized in that: The controlling each of the first modules to determine the address information output by the corresponding second address output port based on the target column address of the first module includes: Control each of the first modules to perform a second address allocation operation on its own target column address to obtain a second address allocation result, determine the second address allocation result as the column address output by the corresponding second address output port, and determine the address allocation preset value as the column address output by the corresponding second address output port.
11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the address allocation method as described in any one of claims 7 to 10 is implemented.