Multi-channel lvds format data receiving and storing device

Abstract

The application relates to the technical field of electronics, in particular to a multi-channel LVDS format data receiving and storing device which comprises an LVDS data conversion module, a data signal extraction module, a channel data cache module, a data synthesis module and a data storage module; wherein the channel data cache module is realized based on a FIFO in the FPGA (Field Programmable Gate Array) and completes the channel alignment function of image data; compared with a shift register, the channel data cache module has the advantages of deeper cache depth, support of different frequency clocks in reading and writing and higher system stability.

Description

Technical Field

[0001] This invention belongs to the field of electronics technology, and in particular relates to a multi-channel LVDS format data receiving and storage device. Background Technology

[0002] As image sensor resolution and frame rate continue to improve, higher demands are placed on image sensor drivers. A common industry practice is to crop a high-resolution image into multiple channels for output. Taking a two-dimensional image as an example, it has x-axis and y-axis. Existing image sensors typically use LVDS (Low-Voltage Differential Signaling) format as their image data output format. LVDS format data usually contains two physical connection signal lines, a positive line and a negative line. Image data is first converted from parallel to serial to serial bit data, and then transmitted through the two LVDS signal lines. FPGA-based drivers first receive LVDS data through an LVDS receiving module, convert it into parallel data, and then time-align the LVDS data from multiple channels through data training, byte alignment, and channel alignment, thereby achieving accurate image acquisition.

[0003] Existing LVDS training and channel alignment methods typically utilize mature modules provided by device manufacturers, such as LVDS receive buffers, DELAY delay modules, ISERDES serial-to-parallel conversion modules, shift register modules, and RAM caches. Figure 1 As shown in the diagram. In this type of method, the purpose of the shift register is to achieve channel alignment. However, due to the increased resolution of modern image sensors, the number of data channels in LVDS has also increased. Shift registers with too many channels (such as 32 channels) will consume a large amount of FPGA cache resources and also consume the placement and routing resources of the FPGA's internal program, leading to tight placement and routing. At the same time, the shift register needs to perform data shifting operations within the same clock domain, resulting in excessive fan-out of a single clock cycle, which is detrimental to clock stability. Summary of the Invention

[0004] In view of this, the present invention aims to provide a multi-channel LVDS format data receiving and storage device, which uses the mature FIFO (First Input First Output) buffer resource inside the FPGA to realize the channel alignment function of image data. Compared with the shift register, the advantage of FIFO is that the buffer depth is deeper, it supports reading and writing different frequency clocks, and the system stability is higher.

[0005] To achieve the above objectives, the technical solution created by this invention is implemented as follows:

[0006] A multi-channel LVDS format data receiving and storage device, comprising:

[0007] The LVDS data conversion module converts the transmitted multi-channel LVDS format data into multi-channel parallel data;

[0008] The data signal extraction module identifies and extracts the field synchronization signal, line synchronization signal, and data signal of each channel in the multi-channel parallel data.

[0009] The channel data buffer module receives the field synchronization signal, line synchronization signal and data signal of each channel, and writes the data signal into the FIFO of the corresponding channel according to the field synchronization signal and line synchronization signal;

[0010] The data integration module extracts data signals from the FIFO of each channel and outputs the data signals from the FIFO of each channel.

[0011] The data storage module receives and stores the data signals obtained by the data integration module, and combines the received data signals to obtain a complete image.

[0012] Furthermore, the LVDS data conversion module includes LVDS data conversion sub-modules, the number of which is consistent with the number of channels in the multi-channel parallel data. Each LVDS data conversion sub-module includes a delay sub-module and a serial-to-parallel conversion sub-module. Specifically: the LVDS format data of the current channel is acquired according to the clock, and the delay sub-module adds a delay to the LVDS format data of the current channel to synchronize the LVDS format data of the current channel with the clock; then the serial-to-parallel conversion sub-module is used to convert the LVDS format data of the current channel to obtain byte-aligned parallel data of the current channel, thereby obtaining multi-channel parallel data.

[0013] Furthermore, the data signal extraction module includes a data signal extraction sub-module, and the number of data signal extraction sub-modules is consistent with the number of channels of the multi-channel parallel data. In each data signal extraction sub-module, after identifying the start flag and stop flag in the parallel data of the current channel, the field synchronization signal, line synchronization signal and data signal of the parallel data of the current channel are generated.

[0014] Furthermore, the field synchronization signal indicates the data range of an acquired image, the line synchronization signal indicates the data range of a line in an acquired image, and the data signal indicates the image data at the corresponding position.

[0015] Furthermore, the channel data buffer module includes channel data buffer sub-modules, and the number of channel data buffer sub-modules is consistent with the number of channels of multi-channel parallel data; each data signal extraction sub-module inputs the current channel's field synchronization signal, line synchronization signal, and data signal into the corresponding channel data buffer sub-module; each channel data buffer sub-module inputs the current channel's data signal into the corresponding FIFO according to the current channel's field synchronization signal and line synchronization signal.

[0016] Furthermore, in the data integration module, the information in the FIFO of each channel is read. When the horizontal and vertical synchronization signals of the current channel are valid, the data signals in the FIFO of the corresponding channel are read. After the FIFO reading of a channel is completed, the image data packet of the image corresponding to the FIFO of that channel is output, and the reading of the FIFO of the next channel begins, until the FIFO reading of all channels is completed.

[0017] Furthermore, when reading data from the corresponding channel FIFO, the reading width is 1 to 8 pixels, and the reading length is the image data length corresponding to each channel.

[0018] Furthermore, the data storage module receives and stores the image data packets output by the data integration module.

[0019] Furthermore, in multi-channel parallel data, the bit width of the parallel data in each channel is no less than 2 bits and no more than 16 bits.

[0020] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0021] The multi-channel LVDS format data receiving and storage device described in this invention, compared with the shift register method, utilizes a FIFO for data buffering. On the one hand, it simplifies the overall image data receiving process by simplifying channel alignment; on the other hand, it avoids the requirement of simultaneous clock domain read and write clocks as with the shift register. Furthermore, the advantages of FIFO over shift registers are: deeper buffer depth, support for reading and writing different frequency clocks, and higher system stability; and, since FIFO is a commonly used chip resource, chip manufacturers have made more comprehensive optimizations to FIFO, resulting in a more stable and efficient overall driver program. Attached Figure Description

[0022] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0023] Figure 1A schematic diagram of an existing LVDS training and channel alignment device;

[0024] Figure 2 This is a schematic diagram of the structure of the multi-channel LVDS format data receiving and storage device described in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0027] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] The invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] like Figure 2As shown in the embodiment of the present invention, the multi-channel LVDS format data receiving and storage device includes an LVDS data conversion module, a data signal extraction module, a channel data buffer module, a data synthesis module, and a data storage module. The LVDS data conversion module converts the transmitted multi-channel LVDS format data into multi-channel parallel data, and then transmits the multi-channel parallel data to the data signal extraction module through an interface. Each channel's LVDS format data is serial data, and the bit width of the parallel data in each channel is no less than 2 bits and no more than 16 bits. The data signal extraction module identifies and extracts the field synchronization signal, line synchronization signal, and data signal of the parallel data in each channel of the multi-channel parallel data. The channel data buffer module receives the field synchronization signal, line synchronization signal, and data signal of each channel and writes the data signal into the corresponding channel's FIFO based on the field synchronization signal and line synchronization signal. The data synthesis module extracts the data signal from the FIFO of each channel and outputs the data signal in the FIFO of each channel. The data storage module receives and stores the data signal obtained by the data synthesis module and combines the received data signals to obtain a complete image.

[0031] The LVDS data conversion module includes LVDS data conversion submodules, the number of which matches the number of channels in the multi-channel parallel data conversion. Each LVDS data conversion submodule includes a delay submodule and a serial-to-parallel conversion submodule. During signal transmission in electronic circuit hardware, a certain delay occurs. Because clock and data signals propagate on different physical circuits, it's impossible to achieve consistent transmission delays. Furthermore, the synthesis, placement, and routing processes within the FPGA still introduce delays. The combined effect of these delays results in different delays for the first valid data bit on the clock and data lines when the signal travels from the external chip to the receiving device. Therefore, the delay submodule needs to add a delay to either the data or clock module to align the first valid bit of the clock and data lines. Additionally, before outputting image data, the image sensor cyclically outputs training data codes, which are typically specified in the user manual provided by the image sensor manufacturer. In each LVDS data conversion submodule, the LVDS format data of the current channel is first acquired using the clock specified in the manual. At this stage, the acquired training data code, which has not undergone data training, does not conform to the manual's specified training data code due to the offset between the clock and the current channel's LVDS format data. Furthermore, since the acquired training data code fluctuates over time and is not stable, a data training method is needed, utilizing a delay submodule to adjust the alignment between the current channel's LVDS format data and the clock. In this invention, a delay submodule adds a delay to the LVDS format data of the current channel transmitted via a single data line, synchronizing the current channel's LVDS format data with the clock. This achieves long-term stable acquisition of the current channel's LVDS format data. The serial-to-parallel conversion submodule converts the current channel's LVDS format data from a serial signal to a parallel signal by swapping data bits, simultaneously obtaining the manual's specified training data code. Once long-term, stable acquisition of the manual's specified training data code is achieved, the image data training and byte alignment process is complete, resulting in byte-aligned parallel data for the current channel, and subsequently, multi-channel parallel data.

[0032] The data signal extraction module includes data signal extraction sub-modules, and the number of these sub-modules corresponds to the number of channels in the multi-channel parallel data processing. Within each sub-module, after identifying the start and stop flags in the parallel data of the current channel, the image data between the start and stop flags can be determined. With the start and stop flags, field and line synchronization signals can be generated to indicate the image data position and the data signal between them. Different image sensors from different manufacturers use different start and stop flags; the data signal extraction module must rely on the user manual provided by the image sensor manufacturer to determine the image flags to be identified. Once the data signal extraction sub-module identifies the corresponding start flag, it generates the corresponding synchronization signal. Because data transmission involves not only image data but also other redundant data (which is invalid for the system), the overall transmission method involves overlapping image data and invalid data in a certain way. The horizontal and vertical synchronization signals indicate that the valid parts of these signals represent image data, while the invalid parts represent invalid data, and vice versa. Therefore, a complete image sensor data stream needs to include vertical synchronization signals, horizontal synchronization signals, and data signals. The vertical synchronization signal indicates the corresponding positions from the first to the last pixel of an image, while the horizontal synchronization signal indicates the positions from the first to the last pixel of each line. These two synchronization signals together indicate the entire image. The data signal indicates the image data at the corresponding position. After the data signal extraction submodule extracts the vertical synchronization signal, horizontal synchronization signal, and data signal of the parallel data for the current channel, it outputs these three types of signals to the subsequent channel data buffer module. The three types of signals output by the data signal extraction module only guarantee the alignment of the channel data it processes. However, the data content between channels cannot be guaranteed to be aligned; therefore, the channel data buffer module is needed to achieve alignment between channels.

[0033] The core of the channel data buffer module is based on the FIFO IP core provided by the FPGA chip manufacturer. The channel data buffer module receives the field synchronization signal, line synchronization signal, and image data sent by the data signal extraction module. It writes the valid image data indicated by the field and line synchronization signals into the FIFO module. Specifically, the channel data buffer module includes channel data buffer sub-modules, and the number of these sub-modules matches the number of channels in the multi-channel parallel data processing. Each data signal extraction sub-module inputs the field synchronization signal, line synchronization signal, and data signal of the current channel into its corresponding channel data buffer sub-module. Each channel data buffer sub-module inputs the data signal of the current channel into its corresponding FIFO based on the field and line synchronization signals.

[0034] In the data integration module, information is read from the FIFO of each channel. When the horizontal and vertical synchronization signals of the current channel are valid, the data signal in the corresponding channel's FIFO is read. After reading the FIFO of a channel is completed, the image data packet corresponding to that channel's FIFO is output, and the reading of the next channel's FIFO begins, until all channels' FIFOs are read. In this embodiment of the invention, the data integration module reads the data signal in the FIFO of each channel row by row.

[0035] In the data storage module, image data packets output by the data integration module are received and stored. In this embodiment of the invention, a RAM module is used as the data storage module to perform row caching of image data. That is, the data integration module reads the FIFO of the corresponding channel line by line according to the full image. Each time the data integration module reads an image data packet (which may contain multiple pixels), it writes it into the RAM module. This method can avoid intermediate data caching and reduce intermediate usage.

[0036] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0037] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A multi-channel LVDS format data receiving and storage device, characterized in that: include: The LVDS data conversion module converts the transmitted multi-channel LVDS format data into multi-channel parallel data; The LVDS data conversion module includes LVDS data conversion sub-modules, the number of which is consistent with the number of channels in the multi-channel parallel data. Each LVDS data conversion sub-module includes a delay sub-module and a serial-to-parallel conversion sub-module. Specifically: LVDS format data for the current channel is acquired according to a clock signal; the delay sub-module adds a delay to the LVDS format data for the current channel, synchronizing it with the clock; then, the serial-to-parallel conversion sub-module converts the LVDS format data for the current channel from a serial signal to a parallel signal by swapping data bits, obtaining a specified training data code. Once the specified training data code is acquired, the image data training and byte alignment process is completed, resulting in byte-aligned parallel data for the current channel, and thus multi-channel parallel data. The data signal extraction module includes a data signal extraction submodule, and the number of the data signal extraction submodules is consistent with the number of channels of the multi-channel parallel data; in each data signal extraction submodule, after identifying the start flag and stop flag in the parallel data of the current channel, the field synchronization signal, line synchronization signal and data signal of the parallel data of the current channel are generated. The channel data caching module includes a channel data caching submodule, and the number of the channel data caching submodules is consistent with the number of channels of the multi-channel parallel data; each data signal extraction submodule inputs the field synchronization signal, line synchronization signal and data signal of the current channel into the corresponding channel data caching submodule; each channel data caching submodule inputs the data signal of the current channel into the corresponding FIFO according to the field synchronization signal and line synchronization signal of the current channel; The data integration module extracts data signals from the FIFO of each channel and outputs the data signals from the FIFO of each channel. The data storage module receives and stores the data signals obtained by the data integration module, and combines the received data signals to obtain a complete image.

2. The multi-channel LVDS format data receiving and storage device according to any one of claims 1, characterized in that: The field synchronization signal indicates the data range of an acquired image, the line synchronization signal indicates the data range of a line in an acquired image, and the data signal indicates the image data at the corresponding position.

3. The multi-channel LVDS format data receiving and storage device according to claim 1, characterized in that: In the data integration module, information in the FIFO of each channel is read. When the current channel's line and field synchronization signals are valid, the data signal in the corresponding channel's FIFO is read. After completing the FIFO reading of one channel, the image data packet corresponding to that channel's FIFO is output, and the reading of the next channel's FIFO begins, until the FIFO reading of all channels is completed.

4. The multi-channel LVDS format data receiving and storage device according to claim 3, characterized in that: When reading data from the corresponding channel FIFO, the reading width is 1 to 8 pixels, and the reading length is the image data length corresponding to each channel.

5. The multi-channel LVDS format data receiving and storage device according to claim 4, characterized in that: The data storage module receives and stores the image data packets output by the data integration module.

6. The multi-channel LVDS format data receiving and storage device according to claim 1, characterized in that: In the multi-channel parallel data, the bit width of the parallel data in each channel is not less than 2 bits and not more than 16 bits.

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