Method for improving electric leakage of source electrode and grid electrode of trench gate product

Abstract

The invention provides a method for improving electric leakage of a source electrode and a grid electrode of a trench gate product, and the method comprises the steps: sequentially forming an oxide layer and an etching stop layer on a substrate, and forming a deep trench on the etching stop layer, a first oxide layer below the etching stop layer and the substrate; forming a first gate dielectric layer on the deep trench, and then forming a source polysilicon layer formed at the bottom of the deep trench by using a deposition and back etching method; a first isolation dielectric layer and a second isolation dielectric layer for filling the remaining deep trench are sequentially formed, the first dielectric layer does not fully fill the deep trench, and the etching rate of the second isolation dielectric layer is higher than that of the first isolation dielectric layer; the first isolation dielectric layer and the second isolation dielectric layer are ground to the etching stop layer, the etching stop layer is removed, the first isolation dielectric layer, the second isolation dielectric layer and the first gate dielectric layer are etched, and a dielectric layer between the source polycrystalline silicon and the gate polycrystalline silicon is formed; and forming a second gate dielectric layer in the remaining deep trench by using a thermal oxidation method, and forming a gate polycrystalline silicon layer for filling the remaining deep trench. Gate and source electric leakage can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving source and gate leakage of trench gate products. Background Art

[0002] As one of the main power semiconductor devices, power MOSFET is widely used in communications, computers, automobiles and consumer electronics, and is an important component of discrete devices and intelligent power integrated circuits.

[0003] High-density plasma chemical vapor deposition gate dielectric layer process for power MOS trench gate products, including:

[0004] Step 1, providing a substrate 101, sequentially forming an oxide layer 103 and an etch stop layer 104 on the substrate 101, and forming a deep trench 102 on the etch stop layer 104 and the first oxide layer 103 thereunder, and on the substrate 101;

[0005] Step 2: Form a first gate dielectric layer 105 on the deep trench 102, and then form a source polysilicon layer 106 at the bottom of the deep trench 102 by deposition and back etching. Figure 1 The structure shown;

[0006] Step 3: Using high density plasma chemical vapor deposition to sequentially form an isolation dielectric layer 107 filling the remaining deep trenches 102, forming a Figure 2 Step 4, grinding the isolation dielectric layer 107 to the etch stop layer 104, forming a Figure 3 The structure shown in FIG. 1 is shown in FIG. 2 , wherein the etching stop layer 104 is removed, and the isolation dielectric layer 107 and the first gate dielectric layer 105 are etched to form a flat top interface of the gate dielectric layer. The angle between the gate dielectric layer and the sidewall of the deep trench is close to 90°, forming a structure as shown in FIG. Figure 4 In the structure shown, the oxide layer 103 is etched away during this process;

[0007] Step 5: Form a second gate dielectric layer 109 in the remaining deep trench 102 by thermal oxidation to form Figure 5 In the structure shown, the contact area between the gate dielectric layer and the deep trench sidewall corner with the air is small, the thickness of the second gate dielectric layer 109 formed by thermal oxidation is much smaller than that in the normal area, and the angle is close to a right angle, resulting in large leakage.

[0008] In order to solve the above problems, it is necessary to propose a new method for improving the source and gate leakage of trench gate products. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the source and gate leakage of trench gate products, so as to solve the problem of large source and gate leakage of trench gate products in the prior art.

[0010] To achieve the above objectives and other related objectives, the present invention provides a method for improving source and gate leakage of trench gate products, comprising:

[0011] Step 1, providing a substrate, sequentially forming an oxide layer and an etch stop layer on the substrate, and forming deep trenches on the etch stop layer and the first oxide layer thereunder, and the substrate;

[0012] Step 2: forming a first gate dielectric layer on the deep trench, and then forming a source polysilicon layer formed at the bottom of the deep trench by a deposition and back etching method;

[0013] Step 3, sequentially forming a first and a second isolation dielectric layer to fill the remaining deep trench, wherein the first isolation dielectric layer does not completely fill the deep trench, and the etching rate of the second isolation dielectric layer is faster than that of the first isolation dielectric layer;

[0014] Step 4: grinding the first and second isolation dielectric layers onto the etch stop layer, removing the etch stop layer, etching the first and second isolation dielectric layers and the first gate dielectric layer to form a dielectric layer between the source polysilicon and the gate polysilicon;

[0015] Step 5: Form a second gate dielectric layer in the remaining deep trenches by thermal oxidation to form a gate polysilicon layer filling the remaining deep trenches.

[0016] Preferably, the material of the etch stop layer in step one is silicon nitride.

[0017] Preferably, in step one, the deep trench is formed by photolithography and etching.

[0018] Preferably, the first gate dielectric layer in step 2 is an oxide layer formed by thermal oxidation.

[0019] Preferably, the first isolation dielectric layer in step three is an oxide formed by high-density plasma chemical vapor deposition.

[0020] Preferably, the second isolation dielectric layer in step three is an oxide formed by chemical vapor deposition.

[0021] Preferably, the grinding method in step 4 is chemical mechanical planarization grinding.

[0022] Preferably, in step five, the gate polysilicon layer is formed by a deposition and back etching method.

[0023] As described above, the method of improving the source and gate leakage of trench gate products of the present invention has the following beneficial effects:

[0024] Due to the existence of the arc-shaped top interface of the dielectric layer between the gates, the present invention can form a thicker dielectric layer at the angle, improve the gate and source leakage at this location, and then form a gate polysilicon layer to fill the remaining deep trench. The angle of the gate polysilicon layer at the top interface of the arc-shaped dielectric layer between the gates is larger, the tip discharge is weakened, and the gate and source leakage at this location is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram showing the names of inventions that are prior art;

[0026] Figure 2 Schematic diagram showing the names of inventions that are prior art;

[0027] Figure 3 Schematic diagram showing the names of inventions that are prior art;

[0028] Figure 4 Schematic diagram showing the names of inventions that are prior art;

[0029] Figure 5 Schematic diagram showing the names of inventions that are prior art;

[0030] Figure 6 Shown is a schematic diagram of the process flow of the present invention;

[0031] Figure 7 It is a schematic diagram of etching back the source polysilicon layer of the present invention;

[0032] Figure 8 It is a schematic diagram showing the formation of the first and second isolation dielectric layers of the present invention;

[0033] Fig. 9 It is a schematic diagram showing the grinding of the first and second isolation dielectric layers of the present invention;

[0034] Fig.10 It is a schematic diagram showing etching of the first and second isolation dielectric layers and the first gate dielectric layer according to the present invention;

[0035] Fig.11 It is a schematic diagram of forming a second gate dielectric layer according to the present invention. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] See also Figure 6 The present invention provides a method for improving source and gate leakage of trench gate products, comprising:

[0038] Step 1: providing a substrate 201, sequentially forming an oxide layer 203 and an etch stop layer 204 on the substrate 201, and forming a deep trench 202 on the etch stop layer 204 and the first oxide layer 203 thereunder, and on the substrate 201;

[0039] In some embodiments, the material of the etch stop layer 204 in step 1 is silicon nitride.

[0040] In some embodiments, in step 1, the deep trench 202 is formed by photolithography and etching.

[0041] Step 2: Form a first gate dielectric layer 205 on the deep trench 202, and then form a source polysilicon layer 206 at the bottom of the deep trench 202 by deposition and back etching. Figure 7 The structure shown;

[0042] In some embodiments, the first gate dielectric layer 205 in step 2 is an oxide layer 203 formed by thermal oxidation.

[0043] Step 3: sequentially forming the first and second isolation dielectric layers filling the remaining deep trenches 202, wherein the first isolation dielectric layer 207 does not completely fill the deep trenches, forming a Figure 8 In the structure shown, the etching rate of the second isolation dielectric layer 208 is faster than that of the first isolation dielectric layer 207;

[0044] In some embodiments, the first isolation dielectric layer 207 in step three is an oxide formed by high-density plasma chemical vapor deposition.

[0045] In some embodiments, the second isolation dielectric layer 208 in step three is an oxide formed by chemical vapor deposition.

[0046] Step 4: Grind the first and second isolation dielectric layers onto the etching stop layer 204 to form Fig. 9 The structure shown in FIG. 1 is shown in FIG. 2 , the etching stop layer 204 is removed, and the first and second isolation dielectric layers and the first gate dielectric layer 205 are etched to form a dielectric layer between the source polysilicon and the gate polysilicon, whose upper surface is an arc-shaped top interface, forming a dielectric layer as shown in FIG. Fig.10 In the structure shown, the oxide layer 203 is etched away during this process;

[0047] In some embodiments, the polishing method in step 4 is chemical mechanical planarization polishing.

[0048] In some embodiments, in step 4, the etch stop layer 204 is removed by wet etching or dry etching.

[0049] In some embodiments, in step four, the first and second isolation dielectric layers and the first gate dielectric layer 205 are etched by wet etching or dry etching. The second isolation dielectric layer 208 in the center of the deep trench 202 is etched faster, and the first isolation dielectric layer 207 adjacent to the side wall of the deep trench 202 is etched slower, ultimately forming an arc-shaped top interface.

[0050] Step 5: Form a second gate dielectric layer 209 in the remaining deep trench 202 by thermal oxidation. Due to the presence of the arc-shaped top interface of the gate dielectric layer, a thicker dielectric layer can be formed at the angle, forming a second gate dielectric layer 209. Fig.11 The structure shown improves the gate and source leakage here, and then forms a gate polysilicon layer to fill the remaining deep trench 202. The angle between the gate polysilicon layer and the top interface of the arc-shaped gate dielectric layer is larger, and the tip discharge is weakened, thereby improving the gate and source leakage here.

[0051] In some embodiments, in step five, a gate polysilicon layer is formed by a deposition and etch-back method.

[0052] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] In summary, due to the existence of the arc-shaped top interface of the dielectric layer between the gates, the present invention can form a thicker dielectric layer at the angle, improve the gate and source leakage at this location, and then form a gate polysilicon layer to fill the remaining deep trench. The gate polysilicon layer has a larger angle at the top interface of the arc-shaped dielectric layer between the gates, and the tip discharge is weakened, thereby improving the gate and source leakage at this location. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving source and gate leakage of trench gate products, characterized in that: At least: Step 1, providing a substrate, sequentially forming an oxide layer and an etch stop layer on the substrate, and forming deep trenches on the etch stop layer and the first oxide layer thereunder, and the substrate; Step 2: forming a first gate dielectric layer on the deep trench, and then forming a source polysilicon layer formed at the bottom of the deep trench by a deposition and back etching method; Step 3, sequentially forming a first and a second isolation dielectric layer to fill the remaining deep trench, wherein the first isolation dielectric layer does not completely fill the deep trench, and the etching rate of the second isolation dielectric layer is faster than that of the first isolation dielectric layer; Step 4: grinding the first and second isolation dielectric layers onto the etch stop layer, removing the etch stop layer, etching the first and second isolation dielectric layers and the first gate dielectric layer to form a dielectric layer between the source polysilicon and the gate polysilicon; Step 5: Form a second gate dielectric layer in the remaining deep trenches by thermal oxidation to form a gate polysilicon layer filling the remaining deep trenches.

2. The method for improving source and gate leakage of trench gate products according to claim 1, characterized in that: The material of the etching stop layer in step 1 is silicon nitride.

3. The method for improving source and gate leakage of trench gate products according to claim 1, characterized in that: In step one, the deep trench is formed by photolithography and etching.

4. The method for improving source and gate leakage of trench gate products according to claim 1, characterized in that: The first gate dielectric layer in step 2 is an oxide layer formed by thermal oxidation.

5. The method for improving source and gate leakage of trench gate products according to claim 1, characterized in that: The first isolation dielectric layer in step three is an oxide formed by high-density plasma chemical vapor deposition.

6. The method for improving source and gate leakage of trench gate products according to claim 5, characterized in that: The second isolation dielectric layer in step three is an oxide formed by chemical vapor deposition.

7. The method for improving source and gate leakage of trench gate products according to claim 1, characterized in that: The grinding method in step 4 is chemical mechanical planarization grinding.

8. The method for improving source and gate leakage of trench gate products according to claim 1, characterized in that: In step five, the gate polysilicon layer is formed by deposition and back etching.

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