Display substrate and display device

Abstract

According to the display substrate and the display device, a shift register unit is located in a non-display area, and an input circuit responds to a first clock signal and inputs an input signal to a first node; the output circuit outputs an output signal to an output end and comprises an output transistor; the first control circuit controls the level of the second node in response to the level of the first node and a first clock signal; the output control circuit controls the level of the output end under the control of the level of the second node and comprises an output control transistor; a direction parallel to a direction from the non-display area to the display area is a first direction, and the shift register unit includes a first output semiconductor portion and a second output semiconductor portion spaced apart from each other in a second direction, the whole formed by the first output semiconductor part and the second output semiconductor part comprises an active layer of an output control transistor and an active layer of an output transistor; the length direction of the channel of the output control transistor and the length direction of the channel of the output transistor are both in the first direction.

Description

Display substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The driving of the gate lines can be achieved by a bound integrated drive circuit. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide switching state voltage signals (scanning signals) for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to open in sequence, and at the same time, the data line provides a data signal to the pixel units of the corresponding rows in the pixel array, so as to form the grayscale voltage required for each grayscale of the displayed image in each pixel unit, thereby displaying a frame of image.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate and a shift register unit. The base substrate includes a display area and a non-display area at least partially surrounding the display area; a shift register unit is disposed on the base substrate and located in the non-display area; the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit; the input circuit is configured to input an input signal to a first node in response to a first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control the level of a second node in response to a level of the first node and the first clock signal; the output control circuit is configured to control the level of the output terminal under control of the level of the second node; the output control circuit includes an output control transistor, the output circuit includes an output transistor, a direction parallel to a direction from the non-display area to the display area is a first direction, the shift register unit includes a first output semiconductor portion and a second output semiconductor portion arranged in a second direction, the second direction intersecting the first direction, the first output semiconductor portion and the second output semiconductor portion forming a whole including an active layer of the output control transistor and an active layer of the output transistor; the length direction of the channel of the output control transistor and the length direction of the channel of the output transistor are both along the first direction.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the input circuit includes an input transistor, the first control circuit includes a first control transistor and a second control transistor, and the active layer of the input transistor, the active layer of the first control transistor, and the active layer of the second control transistor are all located on the first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the second direction.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the shift register unit further includes a second control circuit, which is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and a second clock signal; the second control circuit includes a first noise reduction transistor and a second noise reduction transistor, and the active layer of the first noise reduction transistor and the active layer of the second noise reduction transistor are both located on the first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the second direction.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the active layer of the output control transistor and the active layer of the output transistor respectively include a plurality of sub-channel regions, and the output control transistor and the output transistor respectively include at least one first sub-channel region and at least one second sub-channel region; the at least one first sub-channel region of the output control transistor and the at least one first sub-channel region of the output transistor are located in the first output semiconductor part and arranged along the first direction, and the at least one second sub-channel region of the output control transistor and the at least one second sub-channel region of the output transistor are located in the second output semiconductor part and arranged along the first direction.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, the length of the first output semiconductor portion in the first direction is greater than the length of the first output semiconductor portion in the second direction; the length of the second output semiconductor portion in the first direction is greater than the length of the second output semiconductor portion in the second direction.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the output control circuit further includes a first capacitor, a first electrode of the first capacitor is electrically connected to the second node; the display substrate further includes a first power line, the first power line is configured to provide a first voltage to the shift register unit, and the second electrode of the first capacitor is electrically connected to the first power line; the first capacitor is located on the first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the second direction.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, in the second direction, the first capacitor is located between the active layer of the first noise reduction transistor and the entirety formed by the first output semiconductor portion and the second output semiconductor portion; the first electrode of the first capacitor is electrically connected to the gate of the first noise reduction transistor and the gate of the output control transistor to form a continuous integrated structure; the electrode where the gate of the output control transistor is located extends from the first electrode of the first capacitor along the second direction toward the entirety formed by the first output semiconductor portion and the second output semiconductor portion, and the orthographic projection of the gate of the output control transistor on the substrate at least partially overlaps with the orthographic projection of the first output semiconductor portion on the substrate, and at least partially overlaps with the orthographic projection of the second output semiconductor portion on the substrate; the electrode where the gate of the first noise reduction transistor is located extends from the first electrode of the first capacitor along the second direction toward the active layer of the first noise reduction transistor, and the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the first noise reduction transistor on the substrate.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first power line extends as a whole along the second direction, and the first power line is located on the first side of the whole formed by the active layer of the input transistor, the active layer of the first control transistor, the second control transistor and the active layer of the second noise reduction transistor in the first direction; the orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the second pole of the first capacitor on the substrate, and the first power line is electrically connected to the second pole of the first capacitor through a first via; and the first power line and the first pole of the output control transistor form an integrated structure, the orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the first output semiconductor part on the substrate and the orthographic projection of the second output semiconductor part on the substrate, and the first power line is electrically connected to the first output semiconductor part and the second output semiconductor part through a second via.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first power line covers at least part of the edge of the first output semiconductor portion extending along the second direction and at least part of the edge of the second output semiconductor portion extending along the second direction.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the output circuit further includes a second capacitor, a first electrode of the second capacitor is connected to the control end of the output circuit, and a second electrode of the second capacitor is connected to the output end; the second capacitor is located on one side of the whole formed by the first output semiconductor part and the second output semiconductor part in the first direction.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, the length of the second capacitor in the second direction is greater than the length of the second capacitor in the first direction.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the active layer of the second control transistor T3 on the plane parallel to the first direction at least partially overlaps with the orthographic projection of the active layer of the input transistor T1 on the plane parallel to the first direction, and at least partially overlaps with the orthographic projection of the second capacitor on the plane parallel to the first direction.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the active layer of the input transistor, the active layer of the first noise reduction transistor, and the active layer of the second noise reduction transistor are arranged in the first direction, and the active layer of the input transistor, the active layer of the first control transistor, and the active layer of the second control transistor are arranged in the second direction.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, in the first direction, there is a gap between the active layer of the input transistor and the active layer of the second noise reduction transistor, and the active layer of the first control transistor at least partially overlaps with the gap in the second direction; the first electrode of the input transistor and the first electrode of the second noise reduction transistor are both connected to the first node, and the first electrode of the input transistor and the first electrode of the second noise reduction transistor constitute a continuous, integrated first connecting electrode, the first connecting electrode is at least partially located in the gap, and the electrode where the gate of the first control transistor is located extends through the gap to be electrically connected to the first connecting electrode.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the active layer of the input transistor, the active layer of the second noise reduction transistor, and the first connecting electrode are respectively in the shape of bars extending along the first direction; the two ends of the first connecting electrode in the first direction are respectively electrically connected to the active layer of the input transistor and the two ends of the active layer of the second noise reduction transistor that are opposite to each other in the first direction.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the shift register unit further includes a voltage stabilizing circuit, which is connected to the first node and the third node and is configured to stabilize the level of the third node; the control end of the output circuit is connected to the third node, and the output circuit is configured to output the output signal to the output end under the control of the level of the third node; the voltage stabilizing circuit includes a voltage stabilizing transistor, the active layer of the voltage stabilizing transistor and the second capacitor are both located on the first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the first direction, and the orthographic projections of the active layer of the voltage stabilizing transistor and the second capacitor on a plane parallel to the second direction at least partially overlap with the orthographic projections of the whole formed by the first output semiconductor part and the second output semiconductor part on a plane parallel to the second direction; the active layer of the voltage stabilizing transistor is located on the side of the second capacitor close to the input transistor in the second direction, and the orthographic projection of the active layer of the voltage stabilizing transistor on a plane parallel to the first direction at least partially overlaps with the orthographic projection of the second capacitor on a plane parallel to the first direction.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the voltage-stabilizing transistor is located on a side of the first control transistor close to the second capacitor in the second direction, and the first electrode of the voltage-stabilizing transistor is electrically connected to the first electrode of the second capacitor; the orthographic projection of the voltage-stabilizing transistor on a plane parallel to the first direction does not overlap with the orthographic projection of the first control transistor on a plane parallel to the first direction, and overlaps with the orthographic projection of the second control transistor on a plane parallel to the first direction.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the electrode where the gate of the first control transistor is located includes an inclined portion, the extension direction of the inclined portion intersects both the first direction and the second direction, and the end of the inclined portion close to the voltage-stabilizing transistor in the second direction is electrically connected to the second pole of the voltage-stabilizing transistor through a third via.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the electrode where the gate of the first control transistor is located also includes a vertical portion connected to the inclined portion and extending along the second direction, the vertical portion extends through the gap, and the end of the vertical portion in the second direction away from the inclined portion is electrically connected to the first connection electrode through a fourth via hole.

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, the gate of the second noise reduction transistor and the first electrode of the output transistor are both connected to the second clock signal end to receive the second clock signal; the electrode where the gate of the second noise reduction transistor is located is in the shape of a strip extending along the second direction, the first electrode of the output transistor includes a second connecting electrode, the second connecting electrode includes a first strip-shaped portion extending along the first direction, an end of the electrode where the gate of the second noise reduction transistor is located close to the output transistor in the second direction is electrically connected to the first end of the first strip-shaped portion in the first direction through a fifth via, and the second connecting electrode is electrically connected to the second clock signal end.

[0024] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes an output signal line electrically connected to the output end, and the portion of the output signal line located in the non-display area includes a first direction portion and a second direction portion; the first direction portion of the output signal line extends along the first direction and an end of the first direction portion away from the display area in the first direction is electrically connected to the electrode where the second pole of the output transistor is located through a first output via hole so that the second pole of the output transistor is electrically connected to the output end, and the second direction portion of the output signal line is connected to the first direction portion, is located on a side of the first direction portion close to the display area, and extends as a whole along the second direction and then enters the display area.

[0025] For example, in at least one embodiment of the present disclosure, in the display substrate provided by at least one embodiment, the electrode at the second pole of the output transistor includes: a strip-shaped main portion extending along the first direction, a plurality of strip-shaped extension portions connected to the strip-shaped main portion and located on a first side of the strip-shaped main portion in the second direction, spaced apart from each other and extending along the second direction, and a protrusion protruding from the strip-shaped main portion in the second direction away from the plurality of strip-shaped extension portions; the orthographic projections of the plurality of strip-shaped extension portions on the base substrate at least partially overlap with the orthographic projections of the first output semiconductor portion and the orthographic projections of the second output semiconductor portion on the base substrate; the protrusion is located on a second side of the entirety formed by the first output semiconductor portion and the second output semiconductor portion in the second direction, opposite to the first side thereof; the first-direction portion of the output signal line is located on the second side of the entirety formed by the first output semiconductor portion and the second output semiconductor portion in the second direction, and an end of the first-direction portion away from the display area in the first direction is connected to the protrusion via the first output via; the second-direction portion is connected to the first-direction portion, located on a side of the first-direction portion close to the display area, and extends entirely along the second direction.

[0026] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first power line is located on the side of the second pole of the output transistor close to the display area in the first direction, and the orthographic projection of the first power line on the base substrate overlaps with the orthographic projection of the output signal line on the base substrate.

[0027] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes: a second power supply line, a trigger signal line, a first clock signal line, and a second clock signal line. The second power supply line is configured to provide a second voltage to the shift register unit, the first electrode of the second control transistor is connected to the second node, and the second electrode of the second control transistor is connected to the second power supply line to receive the second voltage; the display substrate includes a plurality of cascaded shift register units, the first electrode of the input transistor in the first stage shift register unit is connected to the input end, and the input end is configured to be connected to the trigger signal line to receive a trigger signal from the trigger signal line as an input signal; the first clock signal line is configured to provide the first clock signal to the shift register unit; the second clock signal line is configured to provide the second clock signal to the shift register unit; the second power supply line, the trigger signal line, the first clock signal line, the second clock signal line, and the first power supply line are all arranged on the same layer as the second electrode of the second control transistor.

[0028] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second capacitor is located on one side of the whole formed by the first output semiconductor part and the second output semiconductor part, close to the display area in the first direction; the display substrate also includes an output signal line, which is electrically connected to the second pole of the second capacitor, and the second pole of the second capacitor is electrically connected to the electrode where the second pole of the output transistor is located through a second output via so that the second pole of the output transistor is electrically connected to the output end.

[0029] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes: a second power line, a trigger signal line, a first clock signal line, and a second clock signal line. The second power line is configured to provide a second voltage to the shift register unit, the first electrode of the second control transistor is connected to the second node, and the second electrode of the second control transistor is connected to the second power line to receive the second voltage; the display substrate includes a plurality of cascaded shift register units, the first electrode of the input transistor in the first stage shift register unit is connected to the input end, and the input end is configured to be connected to the trigger signal line to receive a trigger signal from the trigger signal line as an input signal; the first clock signal line is configured to provide the first clock signal to the shift register unit; the second clock signal line is configured to provide the second clock signal to the shift register unit; at least one of the second power line, the trigger signal line, the first clock signal line, and the second clock signal line overlaps with the shift register unit in a direction perpendicular to the base substrate and is arranged at a different layer from the second electrode of the second control transistor.

[0030] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second power line extends as a whole along the second direction, at least partially overlaps with the electrode where the gate of the second control transistor is located in a direction perpendicular to the base substrate, and at least partially overlaps with the second pole of the second control transistor in a direction perpendicular to the base substrate; the second power line and the second pole of the second control transistor are arranged in different layers, the second pole of the second control transistor is located between the second power line and the electrode where the gate of the second control transistor is located, the second pole of the second control transistor includes a portion that does not overlap with the electrode where the gate of the second control transistor is located in a direction perpendicular to the base substrate, the second power line is electrically connected to the second pole of the second control transistor through a first power via, and the second pole of the second control transistor is electrically connected to the active layer of the second control transistor through a first auxiliary via.

[0031] For example, in the display substrate provided in at least one embodiment of the present disclosure, the shift register unit further includes a voltage stabilizing circuit, which is connected to the first node and the third node and configured to stabilize the level of the third node; the control end of the output circuit is connected to the third node, and the output circuit is configured to output the output signal to the output end under the control of the level of the third node; the voltage stabilizing circuit includes a voltage stabilizing transistor, the active layer of the voltage stabilizing transistor and the second capacitor are both located on the first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the first direction, the second power line and the electrode where the gate of the voltage stabilizing transistor is located at least partially overlap in a direction perpendicular to the substrate, and the second power line is electrically connected to the electrode where the gate of the voltage stabilizing transistor is located through a second power via.

[0032] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second power line also at least partially overlaps with the input transistor and the second capacitor in a direction perpendicular to the base substrate.

[0033] For example, in the display substrate provided in at least one embodiment of the present disclosure, the trigger signal line extends along the second direction and at least partially overlaps with the first pole of the input transistor of the first-stage shift register unit in a direction perpendicular to the base substrate, and the trigger signal line is electrically connected to the first pole of the input transistor of the first-stage shift register unit through a trigger via.

[0034] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first clock signal line extends as a whole along the second direction and at least partially overlaps with the electrodes where the gate of the input transistor and the gate of the second control transistor are located in a direction perpendicular to the base substrate, and the first clock signal line is electrically connected to the electrodes where the gate of the input transistor and the gate of the second control transistor of the first-stage shift register unit are located through a first clock via.

[0035] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second clock signal line extends along the second direction and at least partially overlaps with the electrode where the first pole of the output transistor is located in a direction perpendicular to the base substrate, and the second clock signal line is electrically connected to the electrode where the first pole of the output transistor is located through a second clock via.

[0036] For example, in the display substrate provided in at least one embodiment of the present disclosure, the electrode where the gate of the second noise reduction transistor is located is in the shape of a strip extending along the second direction, the first pole of the output transistor includes a second connecting electrode, the second connecting electrode includes a first strip portion extending along the first direction, and the end of the electrode where the gate of the second noise reduction transistor is located close to the output transistor in the second direction is electrically connected to the first end of the first strip portion in the first direction through a fifth via. When the second connecting electrode is electrically connected to the second clock signal end, the second clock signal line and the first strip portion at least partially overlap in a direction perpendicular to the base substrate, and the second clock signal line is electrically connected to the first strip portion through the second clock via, so that the gate of the second noise reduction transistor and the first pole of the output transistor are both connected to the second clock signal end.

[0037] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second power line, the trigger signal line, the first clock signal line and the second clock signal line all overlap with the shift register unit in a direction perpendicular to the base substrate; the second power line, the trigger signal line, the first clock signal line and the second clock signal line are arranged on the same layer, and are all arranged on the first pole different layer of the output transistor.

[0038] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0039] For example, in the display device provided in at least one embodiment of the present disclosure, the display device further includes a plurality of pixel units located in the display area and arranged in an array, at least some of the plurality of pixel units include light-emitting devices, and the output signal output by the output circuit of the shift register unit serves as a gate scan signal to drive the light-emitting devices of the plurality of pixel units to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0041] FIG1A is a schematic diagram of an overall circuit structure of a display panel provided by an embodiment of the present disclosure;

[0042] FIG1B is a circuit diagram of a shift register unit provided in accordance with an embodiment of the present disclosure;

[0043] FIG1C is a signal timing diagram of the shift register unit shown in FIG1B when it is operating;

[0044] FIG2 is a schematic diagram of the layout of a portion of a display substrate including a shift register unit according to at least one embodiment of the present disclosure;

[0045] 3A-3G are schematic plan views respectively showing the structures of the layers of the shift register unit of the display substrate shown in FIG2 ;

[0046] FIG4 is a schematic cross-sectional view along line A1-A2 in FIG2 ;

[0047] 5A is a schematic layout diagram of a portion of another display substrate including a shift register unit according to at least one embodiment of the present disclosure;

[0048] 5B-5D are schematic diagrams of some layers in FIG. 5A ;

[0049] FIG6A is a schematic cross-sectional view along line B1-B2 in FIG5A;

[0050] FIG6B is a schematic cross-sectional view along line C1-C2 in FIG5A ;

[0051] 7 is a schematic diagram of the layout of a portion including a shift register unit of another display substrate provided by at least one embodiment of the present disclosure;

[0052] 8A-8G are schematic plan views respectively showing the structures of the layers of the shift register unit of the display substrate shown in FIG7 ;

[0053] FIG9A is a schematic cross-sectional view along line D1-D2 in FIG7;

[0054] FIG9B is a schematic cross-sectional view along line E1-E2 in FIG7 ;

[0055] 10 is a schematic layout diagram of a portion of another display substrate including a shift register unit according to at least one embodiment of the present disclosure;

[0056] FIG11 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0058] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the invention pertains. The terms "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish between different components. Similarly, terms such as "include" or "comprise" mean that the elements or objects appearing before the term encompass the elements or objects listed after the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0059] It should be noted that the "first direction" in the present disclosure refers to a direction parallel to the direction from the non-display area to the display area, that is, the first direction is not limited to the direction from the non-display area to the display area, but also includes the direction from the display area to the non-display area.

[0060] For the driving circuit of the display panel, such as the GOA driving circuit, bilateral driving or unilateral driving can be adopted. For example, one GOA unit drives two rows of pixels. Taking bilateral driving as an example, the GOA circuit is usually designed to be arranged on two opposite sides of the display area, that is, on two opposite sides of the pixel circuit arranged in the display area. The cascaded GOA unit includes a large number of capacitors, thin-film transistors and signal lines, which takes up a lot of space. Therefore, it is necessary to reasonably design the placement of the device and the shared signal routing to reduce the space occupied by the GOA unit and facilitate the narrowing of the frame of the display panel, especially for small-sized display panels, which have higher requirements for the degree of narrowing of the frame.

[0061] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate and a shift register unit. The base substrate includes a display area and a non-display area at least partially surrounding the display area; a shift register unit is disposed on the base substrate and located in the non-display area; the shift register unit includes an input circuit, an output circuit, a first control circuit, and an output control circuit; the input circuit is configured to input an input signal to a first node in response to a first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control the level of a second node in response to a level of the first node and the first clock signal; the output control circuit is configured to control the level of the output terminal under control of the level of the second node; the output control circuit includes an output control transistor, the output circuit includes an output transistor, a direction parallel to a direction from the non-display area to the display area is a first direction, the shift register unit includes a first output semiconductor portion and a second output semiconductor portion arranged in a second direction, the second direction intersecting the first direction, the first output semiconductor portion and the second output semiconductor portion forming a whole including an active layer of the output control transistor and an active layer of the output transistor; the length direction of the channel of the output control transistor and the length direction of the channel of the output transistor are both along the first direction.

[0062] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0063] The display substrate provided in the above-mentioned embodiments of the present disclosure optimizes the line connection and structural layout of the shift register unit, reduces the width of the shift register unit in the first direction, and is conducive to realizing a narrow-frame design of the display panel. In addition, it can utilize the relatively sufficient space in the second direction to increase the width (W) of the channel of the output control transistor and the output transistor, thereby increasing the aspect ratio (W / L) of the output control transistor and the output transistor, while ensuring the display quality of the display panel.

[0064] It should be noted that in the aspect ratio W / L of the transistor, W represents the channel width, which refers to the channel length in the direction perpendicular to the current from the source to the drain in the transistor, and L represents the channel length, which refers to the channel length in the same direction as the current direction.

[0065] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present invention appears in more than one figure, the component is represented by the same reference numeral in each figure.

[0066] FIG1A is a schematic diagram of the overall circuit architecture of a display panel provided by one embodiment of the present disclosure. For example, as shown in FIG1A , 101 represents the overall outer frame of the display panel; the display panel includes a display area (i.e., a pixel array area) 102 and a peripheral area 102B located around the display area 102, wherein the display area includes pixel units 103 arranged in an array; the peripheral area 102B includes a shift register unit 104, wherein a plurality of cascaded shift register units 104 constitute a gate drive circuit for providing, for example, row-by-row shifted gate scan signals to the pixel units 103 arranged in an array in the display area 102 of the display panel 101; and the peripheral area 102B also includes a light-emitting control unit 105, wherein a plurality of cascaded light-emitting control units 105 constitute a light-emitting control array for providing, for example, row-by-row shifted light-emitting control signals to the pixel units 103 arranged in an array in the display area 102 of the display panel 101.

[0067] For example, the shift register unit 104 provided in an embodiment of the present disclosure is a GOA (Gate Driver On Array) unit.

[0068] As shown in FIG1A , data lines D1-DN (N is an integer greater than 1) connected to the data driver chip IC pass through the display area 102 in the second direction to provide data signals to the pixel units 103 arranged in the array; gate lines G1-GM (M is an integer greater than 1) connected to the shift register unit 104 and the light-emitting control unit 105 pass through the display area 102 to provide gate scanning signals and light-emitting control signals to the pixel units arranged in the array. For example, each pixel unit 103 may include a pixel circuit and a light-emitting element having a circuit structure such as 7T1C, 8T2C, or 4T1C in the art. The pixel circuit operates under the control of the data signal transmitted via the data line and the gate scanning signal and light-emitting control signal transmitted via the gate line to drive the light-emitting element to emit light, thereby realizing display and other operations. The light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0069] FIG1B is a circuit diagram of a shift register unit provided in one embodiment of the present disclosure. For example, as shown in FIG1B , the shift register unit 104 includes an input circuit 1041, an output circuit 1043, a first control circuit 1042, and an output control circuit 1044. In other examples, the shift register unit 104 also includes a second control circuit 1045 and a voltage stabilization circuit 1046.

[0070] The input circuit 1041 is configured to input an input signal to the first node N1 in response to a first clock signal. For example, the input circuit 1041 is connected to the input terminal IN, the first node N1, and the first clock signal terminal CK. The input circuit 1041 is configured to be conductive under the control of the first clock signal received at the first clock signal terminal CK, connecting the input terminal IN to the first node N1, thereby inputting the input signal to the first node N1. For example, the input circuit 1041 is implemented as the input transistor T1 described below.

[0071] The output circuit 1043 is configured to output an output signal to the output terminal GOUT. For example, the output circuit 1043 is connected to the third node N3, the output terminal GOUT, and the second clock signal terminal CB. The output circuit 1043 is configured to be conductive under the control of the level of the third node N3, so that the second clock signal terminal CB is connected to the output terminal GOUT, thereby outputting the second clock signal at the output terminal GOUT, for example, outputting a low level of the second clock signal. For example, the output circuit 1043 is implemented as the output transistor T5 and the second capacitor C2 described below.

[0072] The first control circuit 1042 is configured to control the level of the second node N2 in response to the level of the first node N1 and the first clock signal. For example, the first control circuit is connected to the first node N1, the second node N2 and the first clock signal terminal CK, and is configured to be turned on under the control of the level of the first node N1, so that the second node N2 is connected to the first clock signal terminal CK, thereby providing the first clock signal provided by the first clock signal terminal CK to the second node N2. For example, the first control circuit 1042 is implemented as the first control transistor T2 and the second control transistor T3 described below. It should be noted that the first control circuit 1042 is not limited to being connected to the first node N1, and can also be connected to other independent voltage terminals (providing the same voltage as the voltage of the first node N1) or a separately provided circuit that is the same as the input circuit. The embodiments of the present disclosure are not limited to this. The connections of other circuits of the shift register unit are similar to this and will not be repeated here.

[0073] The output control circuit 1044 is configured to control the level of the output terminal GOUT under the control of the level of the second node N2. For example, the output control circuit 1044 is connected to the second node N2, the first power line VGH, and the output terminal GOUT. The output control circuit 1044 is configured to connect the output terminal GOUT to the first power line VGH under the control of the level of the second node N2, thereby outputting the first voltage provided by the first power line VGH to the output terminal GOUT, thereby controlling the output terminal GOUT to be at a high level, thereby preventing the shift register unit from erroneously outputting during the non-output phase. For example, the output control circuit 1044 is implemented as the output control transistor T4 and the first capacitor C1 described below.

[0074] The second control circuit 1045 is connected to the first node N1 and the second node N2 and is configured to control the level of the first node N1 under the control of the level of the second node N2 and the second clock signal. The second control circuit 1045 is connected to the first node N1, the second node N2, the first power supply line VGH, and the second clock signal terminal CB. It is configured to be turned on under the control of the level of the second node N2 and the second clock signal received at the second clock signal terminal CB, connecting the first power supply line VGH and the first node N1. This charges the potential of the first node N1 to a high level, thereby preventing the output circuit 1042 from turning on during the non-output phase, thereby preventing erroneous output. For example, the second control circuit 1045 is implemented as the first noise reduction transistor T6 and the second noise reduction transistor T7 described below.

[0075] The voltage stabilization circuit 1046 is connected to the first node N1 and the third node N3 and is configured to stabilize the voltage level of the third node N3. For example, the voltage stabilization circuit 1046 is connected to the first node N1, the third node N3, and the second power line VGL. The voltage stabilization circuit 1046 is configured to be turned on under the control of the second voltage provided by the second power line VGL, so that the first node N1 and the third node N3 are electrically connected. For example, the voltage stabilization circuit 1046 is implemented as a voltage stabilization transistor T8 described below.

[0076] For example, the voltage-stabilizing transistor T8 is always in the on state under the control of the second voltage provided by the second power line VGL, so that the third node N3 is electrically connected to the first node N1 through the voltage-stabilizing transistor T8, thereby preventing the voltage level of the third node N3 from leaking through the input transistor T1 connected to the first node N1, the first control transistor T2, and the second noise reduction transistor T7. At the same time, the stress of the voltage level of the third node N3 on the first control transistor T1 can be reduced, which can help maintain the voltage level of the third node N3, so that the output transistor T5 can be fully turned on in the output stage.

[0077] The working process of the shift register unit will be briefly described below with reference to FIG1B and FIG1C.

[0078] As shown in FIG1B , the shift register unit 104 includes eight transistors (an input transistor T1, a first control transistor T2, a second control transistor T3, an output control transistor T4, an output transistor T5, a first noise reduction transistor T6, a second noise reduction transistor T7, and a voltage stabilizing transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2). For example, the input circuit 1041 includes an input transistor T1, the first control circuit 1042 includes a first control transistor T2 and a second control transistor T3, the output control circuit 1044 includes an output control transistor T4 and a first capacitor C1, the output circuit 1043 includes an output transistor T5 and a second capacitor C2, the second control circuit 1045 includes a first noise reduction transistor T6 and a second noise reduction transistor T7, and the voltage stabilizing circuit 1046 includes a voltage stabilizing transistor T8.

[0079] For example, when multiple shift register units 104 are cascaded, the first electrode of the input transistor T1 in the first-stage shift register unit 104 is connected to the input terminal IN, and the input terminal IN is configured to be connected to the trigger signal line GSTV to receive the trigger signal as an input signal, while the first electrode of the input transistor T1 in the other stages of the shift register unit 104 is electrically connected to the output terminal of the previous stage shift register unit 104 to receive the output signal output by the output terminal GOUT of the previous stage shift register unit 104 as an input signal, thereby realizing shift output for performing, for example, row-by-row scanning of the array of pixel units in the active display area.

[0080] In addition, as shown in FIG1B , the shift register unit further includes a first clock signal terminal CK and a second clock signal terminal CB, where GCK represents a first sub-clock signal line and GCB represents a second sub-clock signal line. For example, when the first clock signal terminal CK is connected to the first sub-clock signal line GCK to receive the first clock signal, the first sub-clock signal line GCK serves as the first clock signal line. When the first clock signal terminal CK is connected to the second sub-clock signal line GCB to receive the first clock signal, the second sub-clock signal line GCB serves as the first clock signal line. This may be determined based on the specific circumstances, and the embodiments of the present disclosure are not limited thereto. The second clock signal terminal CB is connected to the second sub-clock signal line GCB or the first sub-clock signal line GCK to receive the second clock signal. The following description uses the example of the first clock signal terminal CK being connected to the first sub-clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB being connected to the second sub-clock signal line GCB to receive the second clock signal, i.e., the first sub-clock signal line GCK serves as the first clock signal line and the second sub-clock signal line GCB serves as the second clock signal line. The embodiments of the present disclosure are not limited thereto. For example, the first clock signal GCK and the second clock signal GCB can use pulse signals with a duty cycle greater than 50%, and the two can differ by half a cycle, for example; VGH represents the first power line and the first voltage provided by the first power line, for example, the first voltage is a DC high level, VGL represents the second power line and the second voltage provided by the second power line, for example, the second voltage is a DC low level, and the first voltage is greater than the second voltage; N1, N2 and N3 respectively represent the first node, the second node and the third node in the circuit schematic.

[0081] As shown in FIG1B , the gate of the input transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first sub-clock signal line GCK) to receive the first clock signal, the second electrode of the input transistor T1 is connected to the input terminal IN, and the first electrode of the input transistor T1 is connected to the first node N1. For example, when the shift register unit is a first-stage shift register unit, the input terminal IN is connected to the trigger signal line GSTV to receive the trigger signal. When the shift register unit is a shift register unit of any other stage except the first-stage shift register, the input terminal IN is connected to the output terminal GOUT of its upper-stage shift register unit.

[0082] A gate of the first control transistor T2 is connected to the first node N1 , a second electrode of the first control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal, and a first electrode of the first control transistor T2 is connected to the second node N2 .

[0083] A gate of the second control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, a second electrode of the second control transistor T3 is connected to the second power line VGL to receive the second voltage, and a first electrode of the second control transistor T3 is connected to the second node N2.

[0084] The gate of the output control transistor T4 is connected to the second node N2 , the first electrode of the output control transistor T4 is connected to the first power line VGH to receive the first voltage, and the second electrode of the output control transistor T4 is connected to the output terminal GOUT.

[0085] A first electrode of the first capacitor is connected to the second node N2 , and a second electrode of the first capacitor C1 is connected to the first power line VGH.

[0086] A gate of the output transistor T5 is connected to the third node N3 , a first electrode of the output transistor T5 is connected to the second clock signal terminal CB, and a second electrode of the output transistor T5 is connected to the output terminal GOUT.

[0087] A first electrode of the second capacitor C2 is connected to the third node N3 , and a second electrode of the second capacitor C2 is connected to the output terminal GOUT.

[0088] A gate of the first noise reduction transistor T6 is connected to the second node N2 , a first electrode of the first noise reduction transistor T6 is connected to the first power line VGH to receive the first voltage, and a second electrode of the first noise reduction transistor T6 is connected to the second electrode of the second noise reduction transistor T7 .

[0089] A gate of the second noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second sub-clock signal line GCB) to receive the second clock signal, and a first electrode of the second noise reduction transistor T7 is connected to the first node N1.

[0090] A gate of the voltage stabilizing transistor T8 is connected to the second power line VGL to receive the second voltage, a second electrode of the voltage stabilizing transistor T8 is connected to the first node N1 , and a first electrode of the voltage stabilizing transistor T8 is connected to the third node N3 .

[0091] The transistors in the shift register unit 104 shown in FIG1B are all described using P-type transistors as an example. That is, each transistor is turned on (on-level) when the gate is connected to a low level, and is turned off (off-level) when the gate is connected to a high level. In this case, the first electrode of the transistor can be a source electrode, and the second electrode of the transistor can be a drain electrode.

[0092] The shift register unit includes but is not limited to the configuration of Figure 1B. For example, each transistor in the shift register unit 104 can also use N-type transistors or a mixture of P-type transistors and N-type transistors. It is only necessary to connect the port polarities of the selected type of transistors according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0093] It should be noted that the transistors used in the shift register unit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. Here, thin film transistors are used as an example for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0094] FIG1C is a signal timing diagram of the shift register unit 104 shown in FIG1B during operation. The operation of the shift register will be described in detail below in conjunction with FIG1B and FIG1C . For example, the operation principle of the first-stage shift register unit 104 will be described below. The operation principles of the remaining stages of the shift register unit 104 are similar and will not be described in detail. As shown in FIG1C , the operation of the shift register unit 104 includes four phases: a first phase t1, a second phase t2, a third phase t3, and a fourth phase t4. FIG1C shows the timing waveforms of the various signals in each phase.

[0095] In the first stage t1, as shown in Figure 1C, the first clock signal terminal CK receives a low-level first clock signal, and the trigger signal line GSTV provides a low-level trigger signal, so the input transistor T1 and the second control transistor T3 are turned on, and the turned-on input transistor T1 transmits the low-level trigger signal to the first node N1, thereby making the level of the first node N1 become low, so the first control transistor T2 and the output transistor T5 are turned on. Since the voltage regulator transistor T8 is always in the on state in response to the second voltage (low level) provided by the second power line VGL, the level of the third node N3 is the same as the level of the first node N1, that is, a low level. At the same time, the low level is stored in the second capacitor C2. In addition, the turned-on second control transistor T3 transmits the low-level second voltage VGL to the second node N2, and the turned-on first control transistor T2 transmits the low-level first clock signal to the second node N2, thereby changing the level of the second node N2 to a low level and storing it in the first capacitor C1. Therefore, the output control transistor T4 is turned on in response to the low level of the second node N2, and outputs the high-level first voltage provided by the first power line VGH to the output terminal GOUT. At the same time, the output transistor T5 is turned on in response to the low level of the third node N3, and transmits the high-level second clock signal received by the second clock signal terminal CB to the output terminal GOUT. Therefore, at this stage, the shift register unit outputs a high level.

[0096] In the second phase t2, as shown in FIG1C , the second clock signal terminal CB receives a low-level second clock signal, turning on the second noise reduction transistor T7. The first clock signal terminal CK receives a high-level first clock signal, turning off the input transistor T1 and the second control transistor T3. Due to the storage function of the second capacitor C2, the first node N1 can continue to maintain the low level from the previous phase, turning on the first control transistor T2 and the output transistor T5. Since the first control transistor T2 is turned on, the high-level first clock signal received by the first clock signal terminal CK is transmitted to the second node N2, causing the second node N2 to reach a high level. Consequently, the first noise reduction transistor T6 and the output control transistor T4 are turned off, thereby preventing the high level provided by the first power line VGH from being output to the output terminal GOUT and the first node N1. Simultaneously, since the output transistor T5 is turned on, during this phase, the output terminal GOUT outputs the low level received by the second clock signal terminal GB. For example, this low level is used to control the operation of the pixel unit 103 shown in FIG1A .

[0097] In the third phase t3, as shown in Figure 1C, the first clock signal terminal CK receives a low-level first clock signal, turning on the input transistor T1 and the second control transistor T3. At this time, the high-level voltage provided by the trigger signal line GSTV is transmitted to the first node N1 and the third node N3, turning off the output transistor T5 and the first control transistor T2. The second clock signal terminal CB receives a high-level second clock signal, turning off the second noise reduction transistor T7. Since the second control transistor T3 is turned on, the low-level voltage provided by the second power line VGL is transmitted to the second node N2 and stored in the first capacitor C1. As a result, the output control transistor T4 and the first noise reduction transistor T6 are turned on. Therefore, in this phase, the output terminal GOUT outputs the high-level voltage provided by the first power line VGH.

[0098] In the fourth phase t4, as shown in FIG1C , the first clock signal terminal CK receives a high-level first clock signal, turning off the input transistor T1 and the second control transistor T3. The second clock signal terminal CB receives a low-level second clock signal, turning on the second noise reduction transistor T7. Due to the storage function of the second capacitor C2, the voltage level at the first node N1 remains at the high level from the previous phase, turning off the first control transistor T2 and the output transistor T5. Due to the storage function of the first capacitor C1, the second node N2 continues to maintain the low level from the previous phase, turning on the first noise reduction transistor T6. The high voltage level provided by the first power line VGH is transmitted to the first node N1 and the third node N3 through the turned-on first noise reduction transistor T6 and the turned-on second noise reduction transistor T7. As a result, the first node N1 and the third node N3 continue to maintain a high voltage level, effectively preventing the output transistor T5 from turning on and thus avoiding erroneous output.

[0099] FIG2 is a schematic layout diagram of a portion of a display substrate including a shift register unit 104 provided by at least one embodiment of the present disclosure.

[0100] By way of example, with reference to Figures 1A, 1B, and 2, a display substrate 10 provided in an embodiment of the present disclosure includes: a base substrate 1, and a shift register unit 104 disposed on the base substrate 1. The base substrate 1 includes a display area 102 and a non-display area 102B (i.e., a peripheral area 102B) at least partially surrounding the display area 102. The shift register unit 104 is disposed on the base substrate 1 and located in the non-display area 102B.

[0101] For example, as shown in FIG2 , the display substrate 10 further includes a first power line VGH, a second power line VGL, and a plurality of clock signal lines (for example, a first clock signal line GCK, a second clock signal line GCB, and a trigger signal line GSTV shown in the figure) provided on the base substrate 10. For example, the first power line VGH, the second power line VGL, and the plurality of clock signal lines extend along a second direction D2 shown in FIG2 on the base substrate 10, and are configured to provide a first voltage, a second voltage, and a plurality of clock signals (for example, the trigger signal, the first clock signal, or the second clock signal described above), respectively, to the shift register unit 104.

[0102] It should be noted that the first power line VGH, the second power line VGL and multiple clock signal lines can be arranged in parallel along the second direction D2, or they can cross at a certain angle (for example, less than or equal to 20°). They are not limited to being strictly straight lines, and they can also have a certain degree of bending. As a whole, they can extend along the second direction D2. The embodiments of the present disclosure do not impose any restrictions on this.

[0103] For example, the first power line VGH is configured to provide a first voltage to the plurality of cascaded shift register units 104 included in the scan driving circuit, and the second power line VGL is configured to provide a second voltage to the plurality of cascaded shift register units 104 included in the scan driving circuit. For example, the first voltage is greater than the second voltage, for example, the first voltage is a DC high level, and the second voltage is a DC low level.

[0104] For example, the display substrate 1 includes a pixel array area (i.e., the display area 102 shown in Figure 1A, hereinafter referred to as the pixel array area 102) and a peripheral area 102B other than the pixel array area. For example, in some embodiments, the above-mentioned first power line VGH, the second power line VGL, multiple clock signal lines and the shift register unit 104 can be located in the peripheral area and on one side of the pixel array area (as shown in Figure 1A, located between the pixel array area 102 and the side edge of the substrate). For example, as shown in Figure 1A, it can be located on the left side of the substrate. Of course, it can also be located in the peripheral area 102B on the right side of the substrate 1 or in the peripheral areas 102B on both the left and right sides of the substrate 1. The embodiments of the present disclosure are not limited to this.

[0105] It should be noted that the above wiring positions are merely exemplary, and as long as the wiring arrangement can facilitate connection with the shift register unit, the embodiments of the present disclosure do not impose any limitation thereto.

[0106] For example, the base substrate 1 may be made of glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0107] For example, the pixel array area 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel circuit, and may further include a light emitting element (not shown in the figure).

[0108] For example, a plurality of cascaded shift register units 104 form a gate drive circuit. For example, the output terminals GOUT of the plurality of shift register units 104 are respectively connected to the gate scan signal terminals of the pixel circuits in each row of the pixel array region to provide output signals (e.g., gate scan signals) to the pixel circuits in each row, thereby driving the light-emitting elements to emit light. For example, the pixel circuit can be a pixel circuit with a circuit structure such as 7T1C, 2T1C, 4T2C, or 8T2C, which is not further described here.

[0109] FIG2 only shows the first-stage shift register unit 104 and the second-stage shift register unit 104 in the gate drive circuit. For example, as shown in FIG2 , the first clock terminal CK (as shown in FIG1B ) of the first-stage shift register unit 104 is connected to the second sub-clock signal line GCB to receive the first clock signal, the second clock signal terminal CB of the first-stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal, the first clock signal terminal CK of the second-stage shift register unit is connected to the first clock signal line GCK to receive the first clock signal, the second clock signal terminal CB of the second-stage shift register unit is connected to the second sub-clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB of the second-stage shift register unit is connected to the second sub-clock signal line GCK to receive the first clock signal. The sub-clock signal line GCB is connected to receive the second clock signal. Similarly, the first clock terminal CK of the X-th (X is an odd number greater than 1) stage shift register unit 104 is connected to the second sub-clock signal line GCB to receive the first clock signal, the second clock signal terminal CB of the X-th stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal, the first clock signal terminal CK of the X+1-th stage shift register unit is connected to the first clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB of the X+1-th stage shift register unit is connected to the second sub-clock signal line GCB to receive the second clock signal. It should be noted that the connection method between the shift register units at each stage and the clock signal lines can also adopt other connection methods in the art, and the embodiments of the present disclosure are not limited to this. For example, the input terminal of the first-stage shift register unit 104 is connected to the trigger signal line GSTV to receive the trigger signal as an input signal, the input terminal of the second-stage shift register unit 104 is connected to the output terminal GOUT of the previous-stage shift register unit (i.e., the first-stage shift register unit), and the connection method of the remaining shift register units is similar. The structure of the first-stage shift register unit is used as an example for description below, and the embodiments of the present disclosure are not limited to this.

[0110] For example, in the example shown in Figure 2, since the first clock terminal CK of the first-stage shift register unit 104 (as shown in Figure 1B) is connected to the second sub-clock signal line GCB to receive the first clock signal, and the second clock signal terminal CB of the first-stage shift register unit 104 is connected to the first clock signal GCK to receive the second clock signal, in this example, the second sub-clock signal line GCB is used as the first clock signal line and the first clock signal line GCK is used as the second clock signal line for illustration, and the embodiments of the present disclosure are not limited to this.

[0111] Figures 3A-3G respectively illustrate schematic plan views of the structures of the various layers of the shift register unit 104 of the display substrate shown in Figure 2 . Figure 3A is a plan view of a semiconductor layer 310 of a display substrate according to at least one embodiment of the present disclosure. Figure 3B is a plan view of a first conductive layer 320 of a display substrate according to at least one embodiment of the present disclosure. Figure 3C is a plan view of a second conductive layer 330 of a display substrate according to at least one embodiment of the present disclosure. Figure 3D is a schematic view of vias in the first insulating layer ILD1, the second insulating layer ILD2, and the third insulating layer ILD3 of the display substrate according to at least one embodiment of the present disclosure. Figure 3E is a plan view of the third conductive layer 340 of the display substrate according to at least one embodiment of the present disclosure. Figure 3F is a schematic view of vias in the fourth insulating layer ILD4 of the display substrate according to at least one embodiment of the present disclosure. Figure 3G is a plan view of the fourth conductive layer 350 of the display substrate according to at least one embodiment of the present disclosure. Figure 4 is a schematic cross-sectional view taken along line A1-A2 in Figure 2 . It should be noted that the reference marks T1 to T8, GSTV, GCB, GCK, VGL, VGH, etc. in single-layer diagrams such as Figures 3D-3F only represent that the orthographic projections of the structures represented by these reference marks on the main surface of the base substrate 1 are located at the positions where the corresponding reference marks are located, so as to facilitate the understanding of the positional relationship between the various structures in the single-layer diagram in combination with Figure 2.

[0112] For example, on the main surface of the base substrate 1 and in a direction from close to the base substrate to away from the base substrate 1, the semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the third conductive layer 340, and the fourth conductive layer 350 are arranged in sequence. That is, the first conductive layer 320 is located on the side of the semiconductor layer 310 away from the base substrate 1, the second conductive layer 330 is located on the side of the first conductive layer 320 away from the base substrate 1, the third conductive layer 340 is located on the side of the second conductive layer 330 away from the base substrate 1, and the fourth conductive layer 350 is located on the side of the third conductive layer 340 away from the base substrate 1. Of course, the display substrate provided in other embodiments may also include some of the first conductive layer 320, the second conductive layer 330, the third conductive layer 340, and the fourth conductive layer 350. These four conductive layers are not required in the display substrate provided in every embodiment.

[0113] For example, interlayer insulating layers (e.g., including the first insulating layer ILD1, the second insulating layer ILD2, and the third insulating layer ILD3 shown in FIG. 4 ) may be located between the layer structures shown in FIG. 3A-3G . For example, the first insulating layer ILD1 (shown in FIG. 4 ) is located between the semiconductor layer 310 shown in FIG. 3A and the first conductive layer 320 shown in FIG. 3B , the second insulating layer ILD2 (shown in FIG. 4 ) is located between the first conductive layer 320 shown in FIG. 3B and the second conductive layer 330 shown in FIG. 3C , and the third insulating layer ILD3 (shown in FIG. 4 ) is located between the second conductive layer 330 shown in FIG. 3C and the third conductive layer 340 shown in FIG. 3E . For example, the third insulating layer ILD3 is a flat layer, so that the third conductive layer 340, which has a large number of wiring, is disposed on a flat surface, facilitating wiring.

[0114] For example, referring to Figure 3A, the active layers A1~A8 of each transistor are located in the semiconductor layer 310, the gates G1~G8 of each transistor, the first electrode of the first capacitor and the first electrode of the second capacitor are located in the first conductive layer 320, the second electrode of the first capacitor and the second electrode of the second capacitor are located in the second conductive layer 330, the first power line VGH, the second power line VGL and the various connecting electrodes are located in the third conductive layer 340; for example, the first clock signal line GCK and the second clock signal line GCB respectively include double-layer routings connected in parallel to each other to reduce the total resistance of the double-layer routings, therefore, as shown in Figure 3E, the first-layer routing GCK1 of the first clock signal line GCK and the first-layer routing GCB1 of the second clock signal line GCB are located in the third conductive layer 340, and as shown in Figure 3G, the second-layer routing GCK2 of the first clock signal line GCK and the second-layer routing GCB2 of the second clock signal line GCB are located in the fourth conductive layer 350, and for each of these three, the double-layer routings are electrically connected to each other. 3F , the two layers of the first clock signal line GCK are electrically connected through a via V17 passing through the fourth insulating layer ILD4 , and the two layers of the second clock signal line GCB are electrically connected through a via V16 passing through the fourth insulating layer ILD4 .

[0115] For example, in this embodiment, the trigger signal line GSTV is a single-layer wiring. Of course, in other embodiments, the trigger signal line can also be set as a double-layer wiring.

[0116] For example, the materials of the first insulating layer ILD1, the second insulating layer ILD2, and the third insulating layer ILD3 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resin, or other suitable materials, which are not limited in the embodiments of the present disclosure.

[0117] It should be noted that the display substrate shown in FIG2 is illustrated using the layout design of the first two shift register stages in the scan driver circuit and the first power line VGH, the second power line VGL, and the signal lines connected thereto as an example. The layout implementation of the remaining shift register stages can refer to the layout shown in FIG2 and will not be described in detail here. Of course, other layout implementations can also be adopted, and the embodiments of the present disclosure are not limited to this. Of course, the shift register stages in the remaining scan driver circuits can also refer to the layout shown in FIG2, and can also adopt other layout implementations, and the embodiments of the present disclosure are not limited to this.

[0118] The display substrate provided by at least one embodiment of the present disclosure will be described in detail below with reference to Figures 2-4.

[0119] As described above, the shift register unit 104 includes an input circuit 1041, an output circuit 1043, a first control circuit 1042, and an output control circuit 1044. The input circuit 1041 is configured to input an input signal to the first node N1 in response to a first clock signal. The output circuit 1043 is configured to output an output signal to the output terminal GOUT. The first control circuit 1042 is configured to control the level of the second node N2 in response to the level of the first node N1 and the first clock signal. The output control circuit 1044 is configured to control the level of the output terminal GOUT under the control of the level of the second node N2. The output control circuit 1044 includes an output control transistor T4, and the output circuit 1043 includes an output transistor T5. Here, a direction parallel to the direction from the non-display area 102B to the display area 102 is defined as a first direction D1. 2 and 3A , the shift register unit 104 includes a first output semiconductor portion A11 and a second output semiconductor portion A12 spaced apart from each other in a second direction D2, the second direction D2 intersecting the first direction D1, for example, the second direction D2 being perpendicular to the first direction D1, and the first output semiconductor portion A11 and the second output semiconductor portion A12 constituting a whole including an active layer A4 of the output control transistor T4 and an active layer A5 of the output transistor T5. Therefore, in the display substrate 10 provided in the embodiment of the present disclosure, the first output semiconductor part A11 and the second output semiconductor part A12 of the shift register unit 104 are arranged at intervals from each other in the second direction D2 instead of being arranged in the first direction D1. The active layer A4 of the output control transistor T4 and the active layer A5 of the output transistor T5 are formed by the whole formed by the first output semiconductor part A11 and the second output semiconductor part A12, thereby reducing the space occupied by the whole formed by the first output semiconductor part A11 and the second output semiconductor part A12 in the first direction D1, and can reduce the size of the shift register unit 104 in the first direction D1, which is conducive to achieving a narrower frame. In addition, it is convenient to make full use of the second direction space to arrange other transistors, capacitors and other components of the shift register, and can achieve a reasonable layout, thereby reducing the frame of the display panel while ensuring the display quality of the display panel.

[0120] For example, referring to Figure 2, if the range of the entire shift register unit 104 is defined as a region including various transistors, capacitors and other components, then the size of the whole composed of the first output semiconductor part A11 and the second output semiconductor part A12 in the first direction D1 accounts for a ratio greater than 1 / 2 of the size of the entire shift register unit 104 in the first direction D1; if the range of the entire shift register unit 104 is defined as a region including various transistors, capacitors and other components and the first clock signal line GCK, the second clock signal line GCB, the first power line VGH, the second power line VGL and the trigger signal line GSTV, then the size of the whole composed of the first output semiconductor part A11 and the second output semiconductor part A12 in the first direction D1 accounts for a ratio of 1 / 3 to 2 / 3 of the size of the entire shift register unit 104 in the first direction D1.

[0121] For example, in other embodiments described below, if the range of the entire shift register unit 104 is defined as a region including various components such as transistors and capacitors, as well as the first clock signal line GCK, the second clock signal line GCB, the first power line VGH, the second power line VGL, and the trigger signal line GSTV, since at least one of the first clock signal line GCK, the second clock signal line GCB, the first power line VGH, the second power line VGL, and the trigger signal line GSTV is in contact with the shift register unit 104, The transistors overlap, thereby further reducing the size of the entire shift register unit 104 in the first direction D1. At this time, the ratio of the size of the entire unit formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1 to the size of the entire shift register unit 104 in the first direction D1 is increased to varying degrees compared to the embodiment shown in FIG2 . For example, in the embodiment shown in FIG5A , the ratio is greater than or equal to 1 / 2, for example, 1 / 2 to 2 / 3; for example, in the embodiment shown in FIG5A , the ratio is greater than or equal to 1 / 2, for example, 1 / 2 to 2 / 3; for example, in the embodiment shown in FIG7 , the ratio is greater than 1 / 2, for example, greater than 2 / 3. When the size of the entire unit formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1 is larger, the effect of the first output semiconductor portion A11 and the second output semiconductor portion A12 being spaced apart from each other in the second direction D2 on reducing the size of the frame in the first direction is more significant.

[0122] The height of a shift register cell refers to the height of the shift register cell in the second direction D2, and the length of a shift register cell refers to the length of the shift register cell in the first direction D1. For example, referring to Figure 2, the aspect ratio of a shift register cell is approximately 1.2:1; for example, the height of a shift register cell in the second direction D2 is 100.8μm, and the length in the first direction D1 is 127μm. For a conventional shift register cell, the first output semiconductor portion A11 and the second output semiconductor portion A12 are arranged in the first direction D1. The height of the conventional shift register cell in the second direction D2 is 65μm, and the length in the first direction D1 is 180μm, resulting in an aspect ratio of approximately 3:1. It can be seen that the conventional shift register unit occupies 180 μm of the frame in the first direction D1, which is relatively large and can be applied to large-sized display substrates, for example, display substrates with a pixel size greater than or equal to 65 μm. Here, "pixel size" refers to the height of a row of pixels driven by the shift register unit in the display area in the second direction D2. When the pixel size is larger, the longitudinal space utilization rate of the conventional shift register unit is lower. The shift register unit of the display substrate provided by the embodiment of the present disclosure has the above-mentioned aspect ratio greatly reduced compared with the conventional shift register unit. It is not only applicable to display substrates with smaller pixel sizes, but also to display substrates with larger pixel sizes. For example, it can be adapted to drive a single row of pixels with a pixel size greater than or equal to 100 μm, or drive two rows of pixels, each with a pixel size greater than or equal to 50 μm. Moreover, for a small-sized display substrate, the conventional shift register unit will cause the frame size to be too large, which will greatly affect the narrow-frame display effect of the small-sized display substrate. The shift register unit of the display substrate provided in the embodiment of the present disclosure can significantly reduce the frame, and can also achieve a better narrow-frame display effect for a small-sized display substrate.

[0123] For example, the width of the trigger signal line GSTV in the first direction D1 is 4μm-8μm, the width of the first power line VGH in the first direction D1 is 5μm-20μm, the width of the second power line VGL in the first direction D1 is 5μm-20μm, and the width of each clock signal line in the first direction D1 is 5-25μm. The distance between each signal line is, for example, 2μm-10μm to ensure that the manufacturing process can be implemented and to avoid the influence of signal crosstalk. Therefore, when the arrangement of each transistor and capacitor is optimized to the extreme, it is still possible to ensure that there is enough space to arrange the signal lines of various functions side by side and to overlap the signal lines with the transistors or capacitors in a direction perpendicular to the main surface of the substrate 1.

[0124] For example, as described above, the input circuit 1041 includes an input transistor T1, and the first control circuit 1042 includes a first control transistor T2 and a second control transistor T3. Referring to Figures 2 and 3A, the active layer A1 of the input transistor T1, the active layer A2 of the first control transistor T2, and the active layer A3 of the second control transistor T3 are all located on the first side of the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the second direction D2. In this way, the active layer A1 of the input transistor T1, the active layer A2 of the first control transistor T2, and the active layer A3 of the second control transistor T3 are arranged in the second direction D2 with the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12, making full use of the space of the frame area in the second direction D2 and avoiding the active layers of these transistors being arranged in the first direction D1 and occupying too much space in the first direction D1, thereby further reducing the size of the shift register unit 104 in the first direction D1 and facilitating a narrower frame. At the same time, due to the realization of the input transistor T1, the first control transistor T2, and the active layer A3 of the second control transistor T3, the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 is arranged in the second direction D2. The connection between the body transistor T2 and the second control transistor T3 and other transistors and signal lines does not need to cross the first output semiconductor part A11 and the second output semiconductor part A12. Such an arrangement can also conveniently utilize the space on one side of the overall structure formed by the first output semiconductor part A11 and the second output semiconductor part A12 in the second direction D2 to set up signal lines to electrically connect the input transistor T1, the first control transistor T2 and the second control transistor T3 with other transistors and signal lines, thereby rationally arranging more transistors, capacitors and signal lines, thereby reducing the border of the display panel while ensuring the display quality of the display panel.

[0125] For example, in the shift register unit 104, the second control circuit 1045 is connected to the first node N1 and the second node N2, and is configured to control the level of the first node N1 based on the level of the second node N2 and the second clock signal. For example, as described above, the second control circuit 1045 includes a first noise reduction transistor T6 and a second noise reduction transistor T7. Referring to Figures 2 and 3A, the active layer A6 of the first noise reduction transistor T6 and the active layer A7 of the second noise reduction transistor T7 are both located on a first side of the entire structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the second direction D2. In this way, the active layer A6 of the first noise reduction transistor T6 and the active layer A7 of the second noise reduction transistor T7, and the first output semiconductor portion A11 and the second output semiconductor portion A12 are arranged in the second direction D2, making full use of the space of the frame area in the second direction D2, and avoiding the active layer A6 of the first noise reduction transistor T6 and the active layer A7 of the second noise reduction transistor T7 being arranged in the first direction D1 and occupying too much space in the first direction D1, thereby further reducing the size of the shift register unit 104 in the first direction D1, which is conducive to achieving a narrower frame. At the same time, due to the realization of the first noise reduction transistor T6 and the second noise reduction transistor The connection between the transistor T7 and other transistors and signal lines does not need to cross the first output semiconductor portion A11 and the second output semiconductor portion A12. In this way, the active layer A6 of the first noise reduction transistor T6 and the active layer A7 of the second noise reduction transistor T7 can also be arranged conveniently. The space on one side of the overall structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the second direction D2 can be used to set up signal lines to electrically connect the first noise reduction transistor T6 and the second noise reduction transistor T7 with other transistors and signal lines, thereby rationally arranging more transistors, capacitors and signal lines, while reducing the border of the display panel and ensuring the display quality of the display panel.

[0126] 2 and 3B , the electrode at which the gate G4 of the output control transistor T4 is located includes a strip structure extending along the second direction D2. Each strip structure includes two strip portions G41 / G42 that overlap with the first output semiconductor portion A11 and the second output semiconductor portion A12, respectively. Thus, the two strip portions A41 / A42 extend along the second direction D2, and the two strip portions G41 / G42 constitute the gate G4 of the output control transistor T4. Here, an example is used in which the electrode at which the gate G4 of the output control transistor T4 is located includes one strip structure, and this one strip structure includes two strip portions G41 / G42. The number of strip structures is not limited to one. The electrode on which the gate G5 of the output transistor T5 is located includes a plurality of strip structures G51 / G52 / G53 / G54 arranged at intervals in the first direction D1, each strip structure G51 / G52 / G53 / G54 extends along the second direction D2, and each strip structure G51 / G52 / G53 / G54 includes two strip portions G501 / G502 that overlap with the first output semiconductor portion A11 and the second output semiconductor portion A12, respectively. Thus, the two strip portions G501 / G502 extend along the second direction D2, respectively, and the strip portions of the plurality of strip structures G51 / G52 / G53 / G54 constitute the gate G5 of the output transistor T5.

[0127] It should be noted that the active layer of a transistor referred to in this disclosure refers to the channel region of the transistor, that is, the portion of the transistor's semiconductor layer that overlaps with the transistor's gate in a direction perpendicular to the main surface of the substrate. The active layer A4 of the output control transistor T4 refers to the channel region of the output control transistor T4, that is, the portion where the first and second output semiconductor portions A11 and A12 overlap with the gate G4 of the output control transistor T4, that is, the portion that overlaps with the two strip-shaped portions G41 and G42. The active layer A5 of the output transistor T5 refers to the channel region of the output transistor T5, that is, the portion where the first and second output semiconductor portions A11 and A12 overlap with the gate G5 of the output transistor T5, that is, the portion that overlaps with the multiple strip-shaped structures G51, G52, G53, and G54 of the gate G5 of the output transistor T5.

[0128] For example, referring to Figures 2 and 3A , the active layer A4 of the output control transistor T4 and the active layer A5 of the output transistor T5 each include multiple sub-channel regions. The multiple sub-channel regions of the output control transistor T4 include at least one first sub-channel region A41 and at least one second sub-channel region A42, while the multiple sub-channel regions of the output transistor T5 include at least one first sub-channel region A51 and at least one second sub-channel region A52. The at least one first sub-channel region A41 of the output control transistor T4 and the at least one first sub-channel region A51 of the output transistor T5 are both located in the first output semiconductor portion A11 and aligned in a first direction D1. The at least one first sub-channel region A41 is the portion of the first output semiconductor portion A11 that overlaps with the gate of the output control transistor T4, while the at least one first sub-channel region A51 is the portion of the first output semiconductor portion A11 that overlaps with the gate of the output transistor T5. At least one second sub-channel region A42 of the output control transistor T4 and at least one second sub-channel region A52 of the output transistor T5 are located in the second output semiconductor portion A12 and arranged in the first direction D1. At least one second sub-channel region A42 is the portion where the second output semiconductor portion A12 overlaps with the gate of the output control transistor T4. At least one second sub-channel region A52 is the portion where the second output semiconductor portion A12 overlaps with the gate of the output transistor T5.

[0129] Thus, corresponding to the shapes of the orthographic projections of the gates of the output control transistor T4 and the output transistor T5 on the substrate 1, the orthographic projections of each first sub-channel region A4 and each second sub-channel region A42 of the output control transistor T4 on the substrate 1 are both strips extending along the second direction D2, and the orthographic projections of each first sub-channel region A51 and each second sub-channel region A52 of the output transistor T5 on the substrate 1 are both strips extending along the second direction D2, so that each first sub-channel region A4 and each second sub-channel region A42 of the output control transistor T4 are both strips extending along the second direction D2. The lengths of the output transistors A51 and A52 in the second direction D2 are much longer than their respective lengths in the first direction D1, and the lengths of each first sub-channel region A51 and each second sub-channel region A52 in the second direction D2 are much longer than their respective lengths in the first direction D1, which is beneficial for increasing the width-to-length ratio of the output control transistor T4 and the width-to-length ratio of the output transistor T5, reducing the heat generation of the output control transistor T4 and the output transistor T5, thereby extending the service life of the output control transistor T4 and the output transistor T5, and improving the display quality of the display panel.

[0130] For example, referring to FIG3A , the length of each first sub-channel region A41 and each second sub-channel region A42 in the second direction D2 is greater than 2 times or 3 times the length of each sub-channel region A41 and each second sub-channel region A42 in the first direction D1; for example, the length of each first sub-channel region A51 and each second sub-channel region A52 in the second direction D2 is greater than 2 times or 3 times the length of each sub-channel region A52 in the first direction D1. As described below, referring to FIG2 and FIG3E , when the first power line VGH serves as the first electrode of the output control transistor T4 and the strip-shaped extension L52 is electrically connected to the output signal line OL to serve as the second electrode of the output control transistor T4 and the second electrode of the output transistor T5, since the channel width W of the output control transistor T4 is the sum of the lengths of all the sub-channel regions A41 and A42 of the output control transistor T4 in the second direction D2, the channel length L of the output control transistor T4 is the sum of the lengths of all the sub-channel regions A41 and A42 of the output control transistor T4 in the second direction D2. 42 in the first direction D1, the channel width W of the output transistor T5 is the sum of the lengths of all the sub-channel regions A51 and A52 of the output transistor T5 in the second direction D2, and the channel length L of the output transistor T5 is the average length of all the sub-channel regions A51 and A52 of the output transistor T5 in the first direction D1, thereby respectively increasing the width (W) of the channel of the output control transistor T4, thereby utilizing the space in the second direction D2 to increase the aspect ratio (W / L) of the output control transistor T4 and the output transistor T5.

[0131] For example, referring to FIG3A , the length of the first output semiconductor portion A11 in the first direction D1 is greater than the length of the first output semiconductor portion A11 in the second direction D2; and the length of the second output semiconductor portion A12 in the first direction D1 is greater than the length of the second output semiconductor portion A12 in the second direction D2. Because the plurality of transistors, the output control transistor T4, and the output transistor T5 are arranged in the second direction D2, sufficient space is reserved in the first direction D1 for arranging the output control transistor T4 and the output transistor T5. This allows the lengths of the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1 to be larger, thereby improving the width-to-length ratio of the output control transistor T4 and the output transistor T5, reducing heat generation of the output control transistor T4 and the output transistor T5, extending the lifespan of the output control transistor T4 and the output transistor T5, and improving the display quality of the display panel.

[0132] For example, referring to FIG2 and FIG3A, the first output semiconductor portion A11 includes a first portion A11-1 and a second portion A11-2 arranged in a first direction D1 and connected to each other, and the second output semiconductor portion A12 includes a first portion A12-1 and a second portion A12-2 arranged in the first direction D1 and connected to each other; the first portion A11-1 of the first output semiconductor portion A11 and the first portion A12-1 of the second output semiconductor portion A12 both overlap with the gate G4 of the output control transistor T4, for example, the entire length range of the first portion A11-1 of the first output semiconductor portion A11 in the second direction D2 overlaps with the gate G4 of the output control transistor T4, and the second output semiconductor portion A12 The entire length of the first portion A12-1 in the second direction D2 overlaps with the gate G4 of the output control transistor T4; the second portion A11-2 of the first output semiconductor portion A11 and the second portion A12-2 of the second output semiconductor portion A12 both overlap with the gate G5 of the output transistor T5; furthermore, the length of the first portion A11-1 of the first output semiconductor portion A11 in the second direction D2 is greater than the length of the second portion A11-2 of the first output semiconductor portion A11 in the second direction D2, and the length of the first portion A12-1 of the second output semiconductor portion A12 in the second direction D2 is greater than the length of the second portion A12-2 of the second output semiconductor portion A12 in the second direction D2. This allows the channel region of the output control transistor T4 to be longer, increasing the width-to-length ratio of the output control transistor T4. Since the output control transistor T4 typically suffers from severe heat generation during operation in a shift register unit, increasing the width-to-length ratio is particularly desirable to improve heat generation during operation of the output control transistor T4 and extend the operating life of the output control transistor T4.

[0133] For example, in Figure 3A, the edge of the first output semiconductor part A11 away from the second output semiconductor part A12 has a first recessed notch OP1, and the edge of the second output semiconductor part A12 away from the first output semiconductor part A11 has a second recessed notch OP2, so that the length of the first part A11-1 of the first output semiconductor part A11 in the second direction D2 is greater than the length of the second part A11-2 of the first output semiconductor part A11 in the second direction D2, and the space between the first recessed notch OP1 and the second recessed notch OP2 can be used to set connecting electrodes to realize the connection between the various transistors and other components of the shift register unit 104, thereby reducing the space occupied by the entire shift register unit 104 and reducing the border while ensuring the display quality.

[0134] For example, referring to Figures 1B, 2, and 3B, the output control circuit 1044 further includes a first capacitor C1, a first electrode CE11 of the first capacitor C1 being electrically connected to the second node N2. The display substrate 10 further includes a first power line VGH configured to provide a first voltage to the shift register unit 104, and a second electrode CE12 of the first capacitor C1 being electrically connected to the first power line VGH. For example, the first capacitor C1 is located on a first side of the entire structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the second direction D2. This further reduces the size of the shift register unit 104 in the first direction D1, thereby facilitating a narrower bezel.

[0135] For example, the first capacitor C1 and the input transistor T1, the first control transistor T2, the second control transistor T3, the first noise reduction transistor T6, and the second noise reduction transistor T7 are all located on the same side of the whole formed by the first output semiconductor part A11 and the second output semiconductor part A12 in the second direction D2, so that the first capacitor C1 is close to the first noise reduction transistor T6, thereby facilitating electrical connection between the first electrode CE11 of the first capacitor C1 and the gate G6 of the first noise reduction transistor T6. While reducing the width of the frame, a reasonable circuit structure layout can be achieved in a limited space, meeting the requirements of the circuit structure, shortening the connection lines between the various components as much as possible, and ensuring the display quality of the display substrate 10.

[0136] For example, referring to Figures 2 and 3A-3B, the first capacitor C1 is located between the active layer A6 of the first noise reduction transistor T6 and the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12. This allows the first electrode CE11 of the first capacitor C1 to be electrically connected to the gate G6 of the first noise reduction transistor T6. This reduces the width of the bezel while enabling a reasonable circuit layout within a limited space. For example, the first electrode CE11 of the first capacitor C1 is electrically connected to the gate G6 of the first noise reduction transistor T6 and the gate G4 of the output control transistor T4, forming a continuous, integrated structure. This simplifies the structure of the display substrate 10 and facilitates the arrangement of multiple components, such as transistors and capacitors, within the limited bezel space, thereby reducing the bezel of the display substrate 10. Furthermore, this integrated structure can be formed through a single patterning process, reducing the manufacturing difficulty of the display substrate 10.

[0137] For example, referring to Figures 2 and 3B, the electrode E1 at which the gate G4 of the output control transistor T4 is located extends from the first electrode CE11 of the first capacitor C1 along the second direction D2 toward the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12, and the orthographic projection of the gate G4 of the output control transistor T4 on the substrate 1 at least partially overlaps with the orthographic projection of the first output semiconductor portion A11 on the substrate 1, and at least partially overlaps with the orthographic projection of the second output semiconductor portion A12 on the substrate 1; the electrode E2 at which the gate G6 of the first noise reduction transistor T6 is located extends from the first electrode CE11 of the first capacitor C1 along the second direction D2 toward the active layer A6 of the first noise reduction transistor T6, and the orthographic projection of the gate G4 of the output control transistor T4 on the substrate 1 at least partially overlaps with the orthographic projection of the active layer A6 of the first noise reduction transistor T6 on the substrate 1.

[0138] For example, referring to Figures 2 and 3E, the first power line VGH extends along the second direction D2 as a whole. The first power line VGH is located on the first side of the first direction D1 of the whole composed of the active layer A1 of the input transistor T1, the active layer A2 of the first control transistor T2, the second control transistor T3 and the active layer A7 of the second noise reduction transistor T7. The first side is the side close to the display area 102, so that the first power line VGH passes through the position corresponding to the first capacitor C1, thereby facilitating the first power line VGH to pass through and be electrically connected to the second electrode CE12 of the first capacitor C1.

[0139] For example, referring to Figures 2 and 4 , the orthographic projection of the first power line VGH on the substrate 1 overlaps with the orthographic projection of the second electrode CE12 of the first capacitor C1 on the substrate 1, and the first power line VGH is electrically connected to the second electrode CE12 of the first capacitor C1 through a first via V1. For example, the first power line VGH is electrically connected to the second electrode CE12 of the first capacitor C1 through multiple first vias V1. For example, the first power line VGH and the first electrode of the output control transistor T4 form a continuous, integrated structure. The orthographic projection of the first power line VGH on the substrate 1 overlaps with the orthographic projection of the first output semiconductor portion A11 and the orthographic projection of the second output semiconductor portion A12 on the substrate 1, and the first power line VGH is electrically connected to the first output semiconductor portion A11 and the second output semiconductor portion A12 through a second via V2. As a result, the first power line VGH can serve as the first electrode of the output control transistor T4, and a relatively small border area is effectively utilized to layout the interconnected first power line VGH, the output control transistor T4, the first capacitor C1, and the first noise reduction transistor T6.

[0140] For example, referring to Figures 2 and 3E, the first power line VGH has an outer edge OE that is away from the input transistor T1 in the first direction D1 and extends along the second direction D2; the first power line VGH covers the edge of the first output semiconductor portion A11 extending along the second direction D2 and the edge of the second output semiconductor portion A12 extending along the second direction D2, and the outer edge OE of the first power line VGH is located on the side of the whole formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 that is away from the input transistor T1 in the first direction D1, that is, the first power line VGH covers the edge of the first output semiconductor portion A11 extending along the second direction D2 and exceeds the edge, and covers the edge of the second output semiconductor portion A12 extending along the second direction D2 and exceeds the edge.

[0141] Alternatively, in other embodiments, such as the embodiment shown in FIG. 10 below, the outer edge of the first power line VGH is aligned with the edge of the first output semiconductor portion A11 extending along the second direction D2, and is aligned with the edge of the second output semiconductor portion A12 extending along the second direction D2, so as to avoid the first power line VGH from occupying additional space in the first direction D1, thereby further reducing the border size of the display substrate.

[0142] For example, as described above, with reference to FIG1B , the output circuit 1043 further includes a second capacitor C2. A first electrode CE21 of the second capacitor C2 is connected to the control terminal of the output circuit 1043, and a second electrode of the second capacitor C2 is connected to the output terminal GOUT. For example, with reference to FIG2 , the second capacitor C2 is located on one side of the entirety of the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1. For example, in the embodiment shown in FIG2 , the second capacitor C2 is located on one side of the entirety of the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1 away from the display area 102. Since the second capacitor C2 needs to be electrically connected to the output control transistor T4 and the output transistor T5, when one side in the second direction is already used to set the input transistor T1, the first control transistor T2, the second control transistor T3, the first noise reduction transistor T6 and the second noise reduction transistor T7, the position of the second capacitor C2 is set in this way so that the second capacitor C2 is close to the output control transistor T4 and the output transistor T5, which facilitates the electrical connection of the second capacitor C2 with the output control transistor T4 and the output transistor T5, thereby saving space and helping to reduce the border width of the display substrate 10.

[0143] For example, the second capacitor C2, the first output semiconductor portion A11, and the second output semiconductor portion A12 are formed so as to be adjacent to each other in the first direction D1. For example, the second capacitor C2 is adjacent to the output transistor T5, so that the structure in the first direction D1 is compact, which helps to reduce the width of the frame of the display substrate 10. "Adjacent" here means that there is no other electronic component (such as a transistor, capacitor, etc.) between the two adjacent components.

[0144] For example, the length of the second capacitor C2 in the second direction D2 is greater than the length of the second capacitor C2 in the first direction D1. Thus, the space in the second direction is fully utilized to increase the area of ​​the capacitor plate of the second capacitor C2, thereby ensuring the display effect and avoiding the second capacitor C2 occupying too much space in the first direction D1, which is conducive to reducing the border width of the display substrate 10.

[0145] For example, referring to Figures 2 and 3A-3B, the orthographic projection of the active layer A3 of the second control transistor T3 on a plane parallel to the first direction D1 at least partially overlaps with the orthographic projection of the active layer A1 of the input transistor T1 on a plane parallel to the first direction D1, and at least partially overlaps with the orthographic projection of the second capacitor C2 on a plane parallel to the first direction D1. That is, the active layer A3 of the second control transistor T3 overlaps with the active layer A1 of the input transistor T1 in the second direction D1, or there are portions that are directly opposite to each other in the second direction D1. The active layer A3 of the second control transistor T3 overlaps with the second capacitor C2 in the second direction D1, or there are portions that are directly opposite to each other in the second direction D1, so as to reduce the width of the shift register unit in the first direction D1, which is conducive to reducing the border width of the display substrate 10.

[0146] For example, referring to Figure 3A , the active layer A1 of input transistor T1, the active layer A6 of first noise reduction transistor T6, and the active layer A7 of second noise reduction transistor T7 are arranged in a first direction D1. The active layer A1 of input transistor T1, the active layer A2 of first control transistor T2, and the active layer A3 of second control transistor T3 are arranged in a second direction D2. This effectively utilizes the space on the first side of the second direction of the entire structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12, avoids excessive space occupation in the first direction, and facilitates connections between the interconnected transistors. For example, the active layer A6 of the first noise reduction transistor T6 and the active layer A7 of the second noise reduction transistor T7 form a continuous, integrated structure, simplifying the structure and manufacturing process of the display substrate.

[0147] For example, the integrated structure formed by the active layer A1 of the input transistor T1, the active layer A6 of the first noise reduction transistor T6, and the active layer A7 of the second noise reduction transistor T7, as well as the active layer A2 of the first control transistor T2 and the active layer A3 of the second control transistor T3, all have an overall strip shape extending along the first direction D1. For example, the integrated structure formed by the active layer A1 of the input transistor T1, the active layer A6 of the first noise reduction transistor T6, and the active layer A7 of the second noise reduction transistor T7 are substantially arranged along the same straight line in the first direction D1. In this way, the active layers of the multiple transistors are neatly arranged for easier manufacturing, improving the manufacturing yield of the display substrate, and making the entire shift register unit 104 compact, which helps reduce the frame size of the display substrate.

[0148] For example, referring to Figure 3A, in the first direction D1, there is a gap SP between the active layer A1 of the input transistor T1 and the active layer A7 of the second noise reduction transistor T7, and the active layer A2 of the first control transistor T2 at least partially overlaps with the gap SP in the second direction D2, so that the connection electrode is set by utilizing the gap to achieve the connection between the input transistor T1, the first control transistor T2, the first noise reduction transistor T6 and the second noise reduction transistor T7.

[0149] For example, referring to Figures 2 and 3E , the first electrode of the input transistor T1 and the first electrode of the second noise reduction transistor T7 are both connected to the first node N1. The first electrode of the input transistor T1 and the first electrode of the second noise reduction transistor T7 form a continuous, integrated first connection electrode L1. The first connection electrode L1 is at least partially located within the gap SP. The electrode L11 (i.e., the first auxiliary connection electrode L11) where the gate G2 of the first control transistor T2 is located extends through the gap SP to be electrically connected to the first connection electrode L1. For example, referring to Figures 2 and 3D , the first end of the first auxiliary connection electrode L11 is electrically connected to the first connection electrode L1 through a via V4.

[0150] For example, referring to Figures 2, 3A, and 3E, the active layer A1 of the input transistor T1, the active layer A7 of the second noise reduction transistor T7, and the first connection electrode L1 are all generally strip-shaped, extending along a first direction D1. The first connection electrode L1 has two ends in the first direction D1 that electrically connect the active layer A1 of the input transistor T1 and two ends of the active layer A7 of the second noise reduction transistor T7 that are opposite to each other in the first direction D1. For example, referring to Figures 2 and 3D, a first end of the first connection electrode L1 in the first direction D1 is electrically connected to the active layer A1 of the input transistor T1 via a via V02, and a second end of the first connection electrode L1 in the first direction D1 is electrically connected to the active layer A7 of the second noise reduction transistor T7 via a via V03.

[0151] For example, as described above, with reference to FIG1B , the shift register unit 104 further includes a voltage stabilizing circuit 1046 connected to the first node N1 and the third node N3 and configured to stabilize the voltage level of the third node N3. The control terminal of the output circuit 1043 is connected to the third node N3, and the output circuit 1043 is configured to output an output signal to the output terminal GOUT under the control of the voltage level of the third node N3. The voltage stabilizing circuit 1046 includes a voltage stabilizing transistor T8. With reference to FIG2 and FIG3A , the active layer A8 and the second capacitor C2 of the voltage stabilizing transistor T8 are both located on a first side of the entire structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1, for example, on a side away from the display area. Of course, in other embodiments, the side may also be closer to the display area, and this can be changed according to actual needs. Moreover, for example, the orthographic projections of the active layer A8 and the second capacitor C2 of the voltage-stabilizing transistor T8 on a plane parallel to the second direction D2 at least partially overlap with the orthographic projections of the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 on a plane parallel to the second direction D2, that is, the active layer A8 and the second capacitor C2 of the voltage-stabilizing transistor T8 overlap with the entirety formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction, or have portions that are directly opposite to each other, so as to make full use of the limited space and avoid the shift register unit occupying too much space.

[0152] For example, the active layer A8 of the voltage-stabilizing transistor T8 is located on a side of the second capacitor C2 in the second direction D2 that is close to the input transistor T1. That is, the active layer A8 of the voltage-stabilizing transistor T8 is located between the second capacitor C2 and the input transistor T1. This facilitates electrical connection of the voltage-stabilizing transistor T8 to the second capacitor C2 and the input transistor T1, respectively, reducing the length of the connecting wires and the difficulty of wiring, and rationally utilizing space for layout. Furthermore, for example, the orthographic projection of the active layer A8 of the voltage-stabilizing transistor T8 on a plane parallel to the first direction D1 at least partially overlaps with the orthographic projection of the second capacitor C2 on a plane parallel to the first direction D1. That is, the active layer A8 of the voltage-stabilizing transistor T8 and the second capacitor C2 overlap or have portions that are directly opposite each other in the second direction. This reduces the space occupied by the second capacitor C2 and the voltage-stabilizing transistor T8 in the first direction D1, thereby facilitating a reduction in the border width of the display substrate 10.

[0153] For example, the voltage-stabilizing transistor T8 is located on a side of the first control transistor T2 in the second direction D2 that is close to the second capacitor C2, and the first electrode of the voltage-stabilizing transistor T8 is electrically connected to the first electrode CE21 of the second capacitor C2. The orthographic projection of the voltage-stabilizing transistor T8 on a plane parallel to the first direction D1 does not overlap with the orthographic projection of the first control transistor T2 on a plane parallel to the first direction D1, and overlaps with the orthographic projection of the second control transistor T3 on a plane parallel to the first direction D1, so as to facilitate the electrical connection between the voltage-stabilizing transistor T8 and the second capacitor C2. The voltage-stabilizing transistor T8 is staggered from the first control transistor T2, thereby reducing the frame while ensuring that the first control transistor T2 can be electrically connected to the input transistor T1, the second noise reduction transistor T7, and the voltage-stabilizing transistor T8 at the same time, and reducing the space occupied by the voltage-stabilizing transistor T8 and the second control transistor T3 in the first direction D1.

[0154] 2 and 3 , the shift register unit 104 further includes a third connection electrode L3 and a fourth connection electrode L4. For example, the first electrode of the voltage-stabilizing transistor T8 is electrically connected to the first electrode CE21 of the second capacitor C2 via the fourth connection electrode L4. Referring to FIG. 2 and 3D , a first end of the fourth connection electrode L4 is electrically connected to the first electrode CE21 of the second capacitor C2 via a via O4, and a second end of the fourth connection electrode L4 is electrically connected to the first electrode of the voltage-stabilizing transistor T8 via a via O5. For example, the first end of the first auxiliary connection electrode L11 is electrically connected to the first connection electrode L1 through the via V4, the second end of the first auxiliary connection electrode L11 is electrically connected to the third connection electrode L3 through the via V3, and the third connection electrode L3 is electrically connected to the active layer A8 of the voltage-stabilizing transistor T8 through the via 07. Thus, the first connection electrode L1 is electrically connected to the active layer A8 of the voltage-stabilizing transistor T8 through the first auxiliary connection electrode L11 and the third connection electrode L3 in sequence, thereby achieving the electrical connection of the gate G2 of the first control transistor T2, the second electrode of the voltage-stabilizing transistor T8, the first electrode of the second noise reduction transistor T7 and the first electrode of the input transistor T1 to the first node N1.

[0155] For example, referring to Figures 2 and 3B, the electrode where the gate G2 of the first control transistor T2 is located (i.e., the first auxiliary connection electrode L11) includes an inclined portion a, and the extension direction of the inclined portion a intersects both the first direction D1 and the second direction D2. The end of the inclined portion a close to the voltage-stabilizing transistor T8 in the second direction D2 is electrically connected to the third connection electrode L3 through the third via hole (i.e., the above-mentioned via hole V3). The third connection electrode L3 serves as the second pole of the voltage-stabilizing transistor T8, thereby realizing the electrical connection between the gate G2 of the first control transistor T2 and the second pole of the voltage-stabilizing transistor T8.

[0156] For example, the electrode on which the gate G2 of the first control transistor T2 is located (i.e., the first auxiliary connection electrode L11) further includes a vertical portion b connected to the inclined portion a and extending along the second direction D2. The vertical portion b extends through the space SP, and an end of the vertical portion b in the second direction D2, distal from the inclined portion a, is electrically connected to the first connection electrode L1 via a fourth via (i.e., via V4). Because the first control transistor T2 and the voltage-regulating transistor T8 are offset in the first direction, the bridge connection of the inclined portion a in the first and second directions D1 and the bridge connection of the vertical portion b in the second direction D2 coordinates, effectively utilizing limited space to connect the gate G2 of the first control transistor T2, the second electrode of the voltage-regulating transistor T8, the first electrode of the second noise reduction transistor T7, and the first electrode of the input transistor T1 to the first node N1.

[0157] For example, the gate G7 of the second noise reduction transistor T7 and the first electrode of the output transistor T5 are both electrically connected to the second clock signal terminal CB to receive the second clock signal. Referring to Figures 2, 3B, and 3D-3E, the electrode (i.e., the second auxiliary connection electrode L12) where the gate G7 of the second noise reduction transistor T7 is located is in a bar shape extending along the second direction D2, and the first electrode of the output transistor T5 includes the second connection electrode L2. For example, the gate G7 of the second noise reduction transistor T7 is located on the first conductive layer 320, and the second connection electrode L2 is located on the third conductive layer 340. An end of the electrode (i.e., the second auxiliary connection electrode L12) where the gate G7 of the second noise reduction transistor T7 is located, which is proximal to the output transistor T5 in the second direction D2, is electrically connected to the second connection electrode L2 via a fifth via V5. The second connection electrode L2 is electrically connected to the second clock signal line GCB and thus to the second clock signal terminal CB, thereby electrically connecting the gate G7 of the second noise reduction transistor T7 and the first electrode of the output transistor T5 to the second clock signal terminal CB.

[0158] For example, referring to Figures 2 and 3E , the second connection electrode L2 includes a first strip-shaped portion L21 extending along the first direction D1. An end of the electrode (i.e., the second auxiliary connection electrode L12) where the gate G7 of the second noise reduction transistor T7 is located, proximate to the output transistor T5 in the second direction D2, is electrically connected to the first end of the first strip-shaped portion L21 in the first direction D1 via a fifth via V5. The clock signal end of the second connection electrode L2 is also electrically connected. For example, the shift register unit 104 further includes a third connection electrode L3. The second connection electrode L2 is electrically connected to the second clock signal line GCB via the third connection electrode L3. Furthermore, the third connection electrode L3 and the second connection electrode L2 are disposed on different layers to reduce the wiring density of the conductive layers on which they are located, thereby ensuring display quality. This also reduces the space occupied by each conductive layer and the wiring difficulty, thereby reducing the bezel size of the display substrate 10. For example, the third connection electrode L3 and the second auxiliary connection electrode L12 are disposed on the same layer, for example, both located on the first conductive layer 320. The second connection electrode L2 and the second clock signal line GCB are disposed on the same layer, for example, both located on the third conductive layer 340. The second end of the first strip portion L21 of the second connection electrode L2 in the first direction D1 is electrically connected to the first end of the third conductive layer 340 in the first direction D1 via a via V06. The second end of the third connection electrode L3 in the first direction D1 is electrically connected to the second clock signal line GCB via a via V08. For example, the second end of the third conductive layer 340 in the first direction D1 is electrically connected to the second clock signal line GCB via multiple vias V08 to ensure reliable electrical connection with the second clock signal line GCB. Furthermore, sufficient space is provided at the connection point, allowing for the provision of multiple vias V08.

[0159] Referring to Figures 2 and 3E, the second connection electrode L2 also includes a plurality of second strip portions L22 extending along the second direction D2 and arranged in the first direction D1. The plurality of second strip portions L22 are connected to the first strip portion L21 and overlap with the first output semiconductor portion A11 and the second output semiconductor portion A12, respectively. Each second strip portion L22 is electrically connected to the first output semiconductor portion A11 through a via V18 and to the second output semiconductor portion A12 through a via V19 to form the first electrode of the output transistor T5. In this way, the first electrode of the output transistor T5 is electrically connected to the second clock signal line CGB through the first strip portion L21 and the third connection electrode L3 in sequence to realize the electrical connection between the first electrode of the output transistor T5 and the second clock signal terminal CB.

[0160] For example, the first clock signal line GCK and the second power line VGL are both located on the side of the second clock signal line GCB close to the shift register unit 104, that is, on the side of the second clock signal line GCB close to the display area 102, so that the first clock signal line GCK and the second power line VGL are electrically connected to the transistors in the shift register unit 104, and the third conductive layer 340 crosses the first clock signal line GCK and the second power line VGL along the first direction D1 and is electrically connected to the second clock signal line GCB, and in order to facilitate the production of each signal line, the first clock signal line GCK, the second power line VGL and the second clock signal line GCB are all arranged on the same layer. Therefore, the third conductive layer 340 set at a different layer from the second connecting electrode L2 is used for switching, which can avoid the first clock signal line GCK and the second power line VGL. Of course, the arrangement order of the first clock signal line GCK, the second power line VGL and the second clock signal line GCB in the first direction D1 is not limited to this case. No matter in which order they are arranged, among these signal lines, the signal lines arranged in the first direction farther away from the shift register unit 104 are electrically connected to the transistors in the shift register unit 104 through the switching electrodes (similar to the third connection electrode L3) arranged in a different layer from these signal lines. The switching electrodes cross the signal lines closer to the shift register unit 104 to take into account both reducing the border and ensuring the display quality.

[0161] For example, referring to Figure 2, in the first direction D1, the second power line VGL is located on the side of the first clock signal line GCK and the second clock signal line GCB close to the shift register unit 104, and in the first direction D2, the second power line VGL is adjacent to both the second control transistor T3 and the voltage-stabilizing transistor T8, for example, the active layer A3 of the second control transistor T3 and the active layer A8 of the voltage-stabilizing transistor T8, that is, in the first direction D2, there are no other transistors or capacitors between the second power line VGL and the second control transistor T3, so that the second power line VGL is electrically connected to the second electrode of the second control transistor T3 and the second power line VGL is electrically connected to the gate G8 of the voltage-stabilizing transistor T8.

[0162] For example, referring to Figures 2 and 3D-3E, the shift register unit 104 further includes a sixth connection electrode L6, which is electrically connected to the second power line VGL and protrudes from the second power line VGL along the first direction D1. For example, the sixth connection electrode L6 and the second power line VGL form a continuous, integrated structure. For example, the sixth connection electrode L6 is located in the third conductive layer 340 and is connected to the active layer A3 of the second control transistor T3 through a via V12, thereby electrically connecting the second electrode of the second control transistor T3 to the second power line VGL to receive the second voltage. In this way, the second control transistor T3 can be connected to the second power line VGL using the shorter sixth connection electrode, effectively utilizing the limited space for arranging the second control transistor T3 and the second power line VGL, and thus reducing the bezel width of the display substrate.

[0163] For example, referring to Figures 2, 3A, and 3D-3E, the shift register unit 104 further includes a seventh connection electrode L7, which includes a first horizontal portion L71 and a second horizontal portion L72 extending along the first direction D1, respectively, and a vertical portion L73 extending along the second direction D2 and connecting the first horizontal portion L71 and the second horizontal portion L72; the first horizontal portion L71 and the second horizontal portion L72 are arranged in the second direction, and the orthographic projection of the first horizontal portion L71 on the main surface of the substrate 1 is substantially aligned with the orthographic projection of the active layer A2 of the first control transistor T2 on the main surface of the substrate 1 in the first direction D1. The first end of the first horizontal portion L71 in the first direction D1 is electrically connected to the active layer A2 of the first control transistor T2 through the via hole V13, and the second end of the first horizontal portion L71 in the first direction D1 is electrically connected to the first electrode CE11 of the first capacitor C2 through the via hole V14; the second horizontal portion L72 is on the main surface of the substrate 1. The orthographic projection of the second horizontal portion L72 is substantially aligned with the orthographic projection of the active layer A3 of the second control transistor T3 on the main surface of the base substrate 1 in the first direction D1. The first end of the second horizontal portion L72 in the first direction D1 is electrically connected to the active layer A3 of the second control transistor T3 through the via V15. Thus, because the gate of the output control transistor T4, the first electrode CE11 of the first capacitor C2, and the gate of the first noise reduction transistor T6 form an integrated structure, the first electrode of the first control transistor T2, the first electrode of the second control transistor T3, the gate of the output control transistor T4, the first electrode CE11 of the first capacitor C2, and the gate of the first noise reduction transistor T6 are all electrically connected to the second node N2. Simultaneously, the layout of the seventh connection electrode L7 rationally utilizes space, resulting in a compact structure that facilitates reducing the bezel. Furthermore, the overall routing formed by the seventh connection electrode L7, the active layer A2 of the first control transistor T2, and the active layer A3 of the second control transistor T3 is regular, thereby improving the manufacturing yield of the display substrate.

[0164] For example, referring to FIG2 and FIG3B , the gate G1 of the input transistor T1 and the gate G3 of the second control transistor T3 form a continuous integrated structure. For example, the input transistor T1 has a dual-gate structure. For example, the integrated structure formed by the gate G1 of the input transistor T1 and the gate G3 of the second control transistor T3 includes a first directional strip portion L13 extending along the first direction D1, and a first portion connected to the first directional strip portion L13 and extending toward a first side of the first directional strip portion L13 in the second direction D2, and a second portion extending toward a second side of the first directional strip portion L13 in the second direction D2. The first portion includes the gate G1 of the input transistor T1, and the second portion includes the gate G1 of the second control transistor T3. G3; the first end of the first-direction strip portion L13 in the first direction D1 away from the display area is electrically connected to the first clock signal line GCK through the via V09; for example, the shift register unit 104 also includes a fourth connection electrode L4, for example, the fourth connection electrode L4 is located, and the second end of the first-direction strip portion L13 in the first direction D1 close to the display area is electrically connected to the fourth connection structure L4 through the via V10, and the fourth connection structure L4 is electrically connected to the active layer A2 of the first control transistor T2 through the via V11, thereby realizing that the gate G1 of the input transistor T1, the gate G3 of the second control transistor T3 and the second electrode of the first control transistor T2 are all connected to the first clock signal terminal CK to receive the first clock signal.

[0165] For example, referring to Figures 2 and 3B, the display substrate 10 also includes an output signal line OL electrically connected to the output terminal GOUT. For example, the output signal line OL and the gate G5 of the output transistor T5 are arranged on the same layer, and both are located in the first conductive layer 320, so that after the output signal line OL enters the display area 102, it is electrically connected to the gate of the transistor of the pixel circuit in the display area 102 located in the first conductive layer. The portion of the output signal line OL located in the non-display area 102B includes a first direction portion OL1 and a second direction portion OL2; referring to Figure 3E, the fifth connection electrode L5 is located in the third conductive layer 340, and the first direction portion OL1 of the output signal line OL extends along the first direction D1. The end of the first direction portion OL1 away from the display area 102 in the first direction D1 is electrically connected to the electrode where the second pole of the output transistor T5 is located (i.e., the fifth connection electrode L5) through the first output via V001 so that the second pole of the output transistor T5 is electrically connected to the output end GOUT. The second direction portion OL2 of the output signal line OL is connected to the first direction portion OL1, and is located on the side of the first direction portion OL1 close to the display area 102 and extends as a whole along the second direction D2 and then enters the display area 102.

[0166] For example, referring to Figures 2, 3B, and 3E, the electrode at which the second pole of the output transistor T5 is located (i.e., the fifth connection electrode L5) further includes a plurality of strip-shaped extension portions L52 connected to the strip-shaped main portion L51 and located on a first side of the strip-shaped main portion L51 in the second direction D2, spaced from each other, and extending along the second direction D2, and a protrusion L53 located on a first side of the strip-shaped main portion L51 in the second direction D2, the protrusion L53 protruding from the strip-shaped main portion L51 in the second direction D2; the orthographic projections of the plurality of strip-shaped extension portions L52 on the substrate 1 are aligned with the orthographic projections of the first output semiconductor portion A11 on the substrate 1 and the second output semiconductor portion A12. Their orthographic projections on the base substrate 1 at least partially overlap. The protrusion L53 is located on a first side of the overall structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the second direction D2. The first-direction portion OL1 of the output signal line OL is located on a second side of the overall structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12 in the second direction D2. The end of the first-direction portion OL1, located away from the display area 102 in the first direction D1, is connected to the protrusion L53 via a first output via V001. The second-direction portion OL1, located on a side of the first-direction portion D1 closer to the display area 102, extends overall along the second direction D2. For example, the output signal line OL surrounds the corner of the second output semiconductor portion A12 to optimize routing, save space, and minimize the width of the bezel of the display substrate 10.

[0167] For example, in the embodiment shown in FIG2 , the end portion of the main body L51 of the fifth connection electrode L5 close to the second capacitor C2 is electrically connected to the second electrode CE22 of the second capacitor C2 through the via V01, so that the second electrode of the output transistor T5 and the second electrode CE22 of the second capacitor C2 are both electrically connected to the output terminal GOUT.

[0168] For example, in the embodiment shown in FIG2 , the first power line VGH is located on a side of the second electrode of the output transistor T5 close to the display area 102 in the first direction D1, and the orthographic projection of the first power line VGH on the base substrate 1 overlaps with the orthographic projection of the output signal line OL on the base substrate 1, so as to avoid the first power line from occupying too much extra space in the first direction D1, thereby reducing the border width of the display substrate 10.

[0169] For example, referring to FIG3B , the electrode where the gate G5 of the output transistor T5 is located and the first electrode CE21 of the second capacitor C2 form a continuous integrated structure, thereby achieving electrical connection between the gate G5 of the output transistor T5 and the first electrode CE21 of the second capacitor C2 and simplifying the structure and manufacturing process of the display substrate.

[0170] For example, in the embodiment shown in FIG2 , among the first power line VGH, the second power line VGL, the trigger signal line GSTV, the first clock signal line GCK, and the second clock signal line GCB, only the first power line VGH overlaps with the shift register unit 104 in a direction perpendicular to the substrate 1. For example, the first power line VGH overlaps at least with the output control transistor T4. For example, referring to FIG3E , the first power line VGH, the second power line VGL, the trigger signal line GSTV, the first clock signal line GCK, and the second clock signal line GCB are all arranged in the same layer as the second electrode of the second control transistor T3. This allows the same patterning process to be performed on the same film layer to form a structure arranged in the same layer, thereby simplifying the manufacturing process.

[0171] Furthermore, in other embodiments, other signal lines may also overlap with the shift register unit 104 in a direction perpendicular to the substrate 1, for example, overlapping with structures such as transistors and capacitors in the shift register unit 104. For example, while the first power line VGH overlaps with the shift register unit 104 in a direction perpendicular to the substrate 1, at least one of the second power line VGL, the trigger signal line GSTV, the first clock signal line GCK, and the second clock signal line GCB overlaps with the shift register unit 104 in a direction perpendicular to the substrate 1. In this case, for example, the signal line overlapping with the shift register unit 104 in a direction perpendicular to the substrate 1 is provided in a layer different from the second electrode of the second control transistor T3, so that the signal line is electrically connected to an underlying layer (e.g., the semiconductor layer 310) via a connection pad provided in the same layer as the second electrode of the second control transistor T3, thereby avoiding structures in other conductive layers that do not need to be electrically connected to the signal line.

[0172] For example, Figure 5A is a schematic layout diagram of a portion of another display substrate including a shift register unit, provided in at least one embodiment of the present disclosure; Figure 6A is a schematic cross-sectional view taken along line B1-B2 in Figure 5A; and Figure 6B is a schematic cross-sectional view taken along line C1-C2 in Figure 5A. In the embodiment shown in Figure 5A, the display substrate 10 still includes the aforementioned semiconductor layer 310, first conductive layer 320, second conductive layer 330, third conductive layer 340, and fourth conductive layer 350, arranged in a direction perpendicular to the main surface of the base substrate 1. As described above, the display substrate 10 includes a second power line VGL and a trigger signal line GSTV. The second power line VGL is configured to provide a second voltage to the shift register unit 104. The first electrode of the second control transistor T3 is connected to the second node N2, and the second electrode of the second control transistor T3 is connected to the second power line to receive the second voltage. The display substrate includes a plurality of cascaded shift register units 104. The first electrode of the input transistor T1 in the first stage of the shift register unit 104 is connected to the input terminal, and the input terminal is configured to be connected to the trigger signal line to receive a trigger signal from the trigger signal line as an input signal. The first clock signal line GCK is configured to provide a first clock signal to the shift register unit 104. The second clock signal line GCB is configured to provide a second clock signal to the shift register unit 104. The display substrate shown in FIG5A differs from the display substrate shown in FIG2 in the following ways.

[0173] For example, referring to Figures 5A and 6A, the second power line VGL overlaps the shift register unit 104 in a direction perpendicular to the substrate 1 and is disposed on the second polarization layer of the second control transistor T3. For example, the second power line VGL overlaps the second control transistor T3 of the shift register unit 104. For example, referring to Figures 5A and 6A, the second power line VGL extends as a whole along the second direction D2, meaning that the portion of the second power line located in the non-display area 102B where the shift register unit is disposed extends along the second direction D2. The same applies to other signal lines, such as the first power line VGH, the first clock signal line GCK, the second clock signal line GCB, and the trigger signal line GSTV. The second power line VGL at least partially overlaps with the electrode where the gate G3 of the second control transistor T3 is located in a direction perpendicular to the substrate, and at least partially overlaps with the second electrode of the second control transistor T3 in a direction perpendicular to the substrate 1; the second power line VGL and the second electrode of the second control transistor T3 are arranged in a different layer; in a direction perpendicular to the main surface of the substrate 1, the second electrode of the second control transistor T3 is located between the second power line VGL and the electrode where the gate G3 of the second control transistor T3 is located, the second electrode of the second control transistor T3 includes a portion that does not overlap with the electrode where the gate G3 of the second control transistor T3 is located in a direction perpendicular to the main surface of the substrate 1, the second power line VGL is electrically connected to the second electrode of the second control transistor T3 through the first power via VP1, and the second electrode of the second control transistor T3 is electrically connected to the active layer A3 of the second control transistor T3 through the first auxiliary via VA1.

[0174] For example, as shown in FIG. 5B-5D , the structures of the third conductive layer 340 , the third insulating layer ILD3 , and the fourth conductive layer 350 are different from those of the corresponding layers in the embodiment shown in FIG. 2 .

[0175] 5A , 5B-5D , and 6A , the shift register unit 104 includes a first connection pad AP1, which serves as the second electrode of the second control transistor T3. For example, the first connection pad AP1 is located on the third conductive layer 340, and the second power line VGL is located on the fourth conductive layer 350. The second power line VGL is electrically connected to the first connection pad AP1 via a first power via VP1 that penetrates the fourth insulating layer IDL4. The first connection pad AP1 is electrically connected to the active layer A3 of the second control transistor T3 via a first auxiliary via VA1 that penetrates the first insulating layer IDL1, the second insulating layer IDL2, and the third insulating layer IDL3.

[0176] As described above, the shift register unit 104 also includes a voltage stabilizing circuit 1046, which is connected to the first node N1 and the third node N3 and is configured to stabilize the level of the third node N3; the control end of the output circuit 1043 is connected to the third node N3, and the output circuit 1043 is configured to output the output signal to the output end GOUT under the control of the level of the third node N3; the voltage stabilizing circuit 1046 includes a voltage stabilizing transistor T8, and the active layer A8 and the second capacitor C2 of the voltage stabilizing transistor T8 are both located on the first side of the first direction D1 of the whole formed by the first output semiconductor part A11 and the second output semiconductor part A12. In the embodiment shown in Figure 5A, the first side is the side away from the display area 102. For example, referring to Figures 5A and 6B, the second power line VGL at least partially overlaps with the voltage-stabilizing transistor T8 in a direction perpendicular to the base substrate 1; for example, the second power line VGL at least partially overlaps with the electrode where the gate G8 of the voltage-stabilizing transistor T8 is located in a direction perpendicular to the base substrate 1, and the second power line VGL is electrically connected to the electrode where the gate G8 of the voltage-stabilizing transistor T8 is located through the second power via VP2.

[0177] For example, in combination with Figures 5A, 5B-5D and Figure 6B, the shift register unit 104 includes a second connection pad AP2, the second connection pad AP2 is located in the third conductive layer 340, the second power line VGL is located in the fourth conductive layer 350, the second power line VGL is electrically connected to the second connection pad AP2 through a second power via VP2 passing through the fourth insulating layer IDL4, and the second connection pad AP2 is electrically connected to the electrode where the gate G8 of the voltage regulator transistor T8 is located through a second auxiliary via VA2 passing through the first insulating layer IDL1, the second insulating layer IDL2 and the third insulating layer IDL3.

[0178] For example, referring to Figure 5A, the second power line VGL also at least partially overlaps with the input transistor T1 and the second capacitor C2 in a direction perpendicular to the main surface of the substrate 1, that is, the input transistor T1, the second control transistor T3, the voltage regulator transistor T8 and the second capacitor C2 at least partially overlap in the second direction D2 to reduce the width of the shift register unit 104 in the first direction D1.

[0179] For example, in the embodiment shown in Figure 5A, the trigger signal line GSTV, the first power line VGH and the second power line VGL all overlap with the shift register unit 104 in a direction perpendicular to the main surface of the base substrate 1, so as to further avoid these signal lines occupying space outside the shift register unit 104, which is conducive to reducing the border width.

[0180] For example, in the embodiment shown in FIG5A , the aspect ratio of a shift register unit is approximately 1.1:1; for example, the height of a shift register unit in the second direction D2 is 100.8 μm, and the length in the first direction D1 is 108 μm. This further reduces the aspect ratio of the shift register unit compared to the embodiment shown in FIG2 , thereby achieving a narrower bezel.

[0181] 5A , the trigger signal line GSTV extends entirely along the second direction D2 and is located between the first power line VGH and the second power line VGL. For example, the trigger signal line GSTV overlaps the input transistor T1 and the output transistor T5.

[0182] For example, in the first-stage shift register unit, the trigger signal line GSTV at least partially overlaps with the first electrode of the input transistor T1 of the first-stage shift register unit 104 in a direction perpendicular to the main surface of the substrate 1, and the trigger signal line GSTV is electrically connected to the first electrode of the input transistor T1 of the first-stage shift register unit 104 through a trigger via to provide a trigger signal to the input transistor T1 of the first-stage shift register unit 104.

[0183] For example, in some embodiments, in the non-first-stage shift register unit 104 , the trigger signal line GSTV may overlap with any structure of the shift register unit 104 and does not need to be electrically connected to other structures through vias.

[0184] For structures in other figures of the embodiment shown in FIG. 5A that are the same as those in the embodiment shown in FIG. 2 , reference may be made to the description of the embodiment shown in FIG. 2 , which will not be repeated here.

[0185] FIG7 is a schematic layout diagram of a portion of another display substrate including a shift register unit provided in at least one embodiment of the present disclosure, and FIG8A-8G are schematic structural plan views of each layer of the shift register unit of the display substrate shown in FIG7 . FIG9A is a schematic cross-sectional view along the line D1-D2 in FIG7 ; and FIG9B is a schematic cross-sectional view along the line E1-E2 in FIG7 . In the embodiment shown in FIG7 , the display substrate 10 still includes the above-mentioned semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the third conductive layer 340, and the fourth conductive layer 350 arranged in sequence in a direction perpendicular to the main surface of the base substrate 1. The display substrate shown in FIG7 has the following differences from the display substrate shown in FIG2 .

[0186] For example, referring to Figures 7, 8B, 8F-8G, and 9A, the first clock signal line GCK extends along the second direction D2 and at least partially overlaps with the shift register unit 104 in a direction perpendicular to the main surface of the substrate 1. For example, the first clock signal line GCK at least partially overlaps with the electrodes at which the gate G1 of the input transistor T1 and the gate G3 of the second control transistor T3 are located in a direction perpendicular to the main surface of the substrate 1. For example, the gate G1 of the input transistor T1 and the gate G3 of the second control transistor T3 are a continuous, integrated structure. The first clock signal line GCK is electrically connected to the electrodes at which the gate G1 of the input transistor T1 and the gate G3 of the second control transistor T3 of the first-stage shift register unit 104 are located via a first clock via VC1 that penetrates the fourth insulating layer IDL4. In this way, while the first clock signal line GCK is prevented from occupying space outside the shift register unit 104, thereby further reducing the border width of the display substrate, the shift register unit is ensured to perform its normal driving function.

[0187] For example, in the embodiment shown in FIG7 , the aspect ratio of a shift register unit is approximately 1:1; for example, the height of a shift register unit in the second direction D2 is 100.8 μm, and the length in the first direction D1 is 97 μm. This further reduces the aspect ratio of the shift register unit compared to the embodiment shown in FIG5A , thereby achieving a narrower bezel.

[0188] Referring to Figure 9A, the first clock signal line GCK is located in the fourth conductive layer 350, and is electrically connected to the fourth connection electrode L4 located in the third conductive layer 340 through the first clock via VC1 penetrating the fourth insulating layer IDL4; the fourth connection electrode L4 is electrically connected to the electrode where the gate G1 of the input transistor T1 and the gate G3 of the second control transistor T3 are located through the via V10 penetrating the first insulating layer IDL1 and the second insulating layer IDL2; and, one end of the fourth connection electrode L4 away from the first clock signal line GCK in the first direction D1 is electrically connected to the active layer A2 of the first control transistor T2 through the via V10 penetrating the first insulating layer IDL1, the second insulating layer IDL2 and the third insulating layer IDL3, so that the gate G1 of the input transistor T1, the gate G3 of the second control transistor T3 and the second electrode of the first control transistor T2 are all electrically connected to the first clock signal line GCK, and thus are all connected to the first clock signal terminal CK to receive the first clock signal.

[0189] For example, the first clock signal line GCK also overlaps with the voltage regulator transistor T8 and the second capacitor C2.

[0190] For example, referring to Figures 7, 8B, 8F-8G, and 9B, the second clock signal line GCB extends along a second direction D2 and at least partially overlaps with the shift register unit 104 in a direction perpendicular to the main surface of the base substrate 1. For example, the second clock signal line GCB at least partially overlaps with the electrode at which the first electrode of the output transistor T5 is located in a direction perpendicular to the base substrate 1, and the second clock signal line GCB is electrically connected to the electrode at which the first electrode of the output transistor T5 is located via a second clock via VC2 that penetrates the fourth insulating layer IDL4. In this way, while preventing the second clock signal line GCB from occupying space outside the shift register unit 104, thereby further reducing the border width of the display substrate, the shift register unit is ensured to perform its normal driving function.

[0191] For example, referring to FIG8B, FIG8E and FIG9B, the electrode where the gate G7 of the second noise reduction transistor T7 is located is in a strip shape extending along the second direction D2, the first electrode of the output transistor T5 includes a second connection electrode L2, the second connection electrode L2 includes a first strip portion L21 extending along the first direction D1, the second connection electrode L2 is located on the third conductive layer 340, and the second clock signal line GCB is located on the fourth conductive layer 350; the end of the electrode where the gate G7 of the second noise reduction transistor T7 is located, which is close to the output transistor T5 in the second direction D2, passes through the second The fifth via V5 of the insulating layer IDL2 and the third insulating layer IDL3 is electrically connected to the first strip portion L21, the second clock signal line GCB at least partially overlaps with a strip portion L21 of the second connection electrode L2 in a direction perpendicular to the base substrate 1, and the second clock signal line GCB is electrically connected to the first strip portion L21 of the second connection electrode L2 through the second clock via VC2 passing through the fourth insulating layer IDL4, thereby achieving the connection between the gate G7 of the second noise reduction transistor T7 and the first electrode of the output transistor T5 and the second clock signal terminal CB.

[0192] For example, an end of the electrode where the gate G7 of the second noise reduction transistor T7 is located close to the output transistor T5 in the second direction D2 is electrically connected to the first end of the first strip portion L21 in the first direction D1 through the fifth via V5;

[0193] For example, the second clock signal line GCB also overlaps with the first control transistor T2 and the output transistor T5; for example, the second clock signal line GCB overlaps with the first output semiconductor portion A11 and the second output semiconductor portion A12.

[0194] For example, the active layer A8 of the voltage-stabilizing transistor T8 and the second capacitor C2 are both located on the first side of the first output semiconductor portion A11 and the second output semiconductor portion A12 in the first direction D1. In the embodiment shown in FIG. 7 , the first side is the side close to the display area 102 .

[0195] For example, in the embodiment shown in FIG7 , the second capacitor C2 is located on a side of the entire structure formed by the first output semiconductor portion A11 and the second output semiconductor portion A12, near the display area 102 in the first direction D1. The display substrate 10 also includes an output signal line OL, which is electrically connected to the second electrode CE22 of the second capacitor C2. The second electrode CE22 of the second capacitor C2 is electrically connected to the electrode where the second electrode of the output transistor T5 is located via a second output via V002, thereby electrically connecting the second electrode of the output transistor T5 to the output terminal GOUT. For example, the output signal line OL and the second electrode CE22 of the second capacitor C2 are arranged on the same layer and form an integral structure. In this way, there is no need to electrically connect the second electrode CE22 of the second capacitor C2 or the second electrode of the output transistor T5 to the output signal line through a separate via to achieve signal output, thereby simplifying the structure and manufacturing process of the shift register unit.

[0196] For the structures that are the same as those in the embodiment shown in FIG. 2 that can be seen in other figures of the embodiment shown in FIG. 7 , reference can be made to the description of the embodiment shown in FIG. 2 . The connection relationship of the other structures is the same as that in FIG. 2 . The positions of the other structures change accordingly according to the change in the positions of the active layer A8 of the voltage-regulating transistor T8 and the second capacitor C2 in the first direction D1, and are not repeated here.

[0197] FIG10 is a schematic diagram illustrating the layout of a portion of another display substrate including a shift register unit, according to at least one embodiment of the present disclosure. Referring to FIG10 , for example, the first clock signal line GCK, the second clock signal line GCB, the trigger signal line GSTV, the first power line VGH, and the second power line VGL all overlap with the shift register unit 104 in a direction perpendicular to the main surface of the base substrate 1. This further prevents these signal lines from occupying space outside the shift register unit 104, thereby reducing the width of the border.

[0198] For example, in the embodiment shown in FIG10 , the aspect ratio of a shift register unit is approximately 0.75:1. For example, the height of a shift register unit in the second direction D2 is 100.8 μm, and the length in the first direction D1 is 75 μm. This further reduces the aspect ratio of the shift register unit compared to the embodiment shown in FIG7 , thereby achieving a narrower bezel.

[0199] For example, the first clock signal line GCK, the second clock signal line GCB, the trigger signal line GSTV, the first power line VGH and the second power line VGL are arranged on the same layer and are all arranged on a different layer from the first pole of the output transistor T1, so that within the spatial range overlapping with the shift register unit 104, sufficient space is provided for the wiring of the first clock signal line GCK, the second clock signal line GCB, the trigger signal line GSTV, the first power line VGH and the second power line VGL, so as to maintain sufficient spacing between the same-layer traces to avoid adhesion and short circuit, and, in this way, in the embodiment shown in Figure 2, there can be enough space so that the first clock signal line GCK, the second clock signal line GCB, the trigger signal line GSTV, the first power line VGH and the second power line VGL basically avoid overlapping with the traces of other layers as much as possible, thereby avoiding interference caused by mutual coupling caused by the overlapping of traces of different layers.

[0200] For example, referring to FIG10 , in the non-first-stage shift register unit 104, the trigger signal line GSTV extends along the second direction D2 and at least partially overlaps with the active layer of the first noise reduction transistor T6 and the active layer of the second noise reduction transistor T7. Because no other signal lines extending along the second direction D2 that need to be electrically connected to other structures through vias are located at the locations of the active layers of the first noise reduction transistor T6 and the second noise reduction transistor T7, the trigger signal line GSTV can be disposed in this vacant space. This ensures that the trigger signal line GSTV does not occupy additional space outside the shift register unit 104, thereby reducing the border width. Furthermore, the overlapping arrangement of the trigger signal line GSTV and the shift register unit 104 does not affect the arrangement of other structures in the shift register unit 104, thereby ensuring the display quality of the display substrate.

[0201] Of course, the position of the trigger signal line GSTV may also be the same as that in the embodiment shown in FIG. 5A .

[0202] For example, the switching modes of the first clock signal line GCK, the second clock signal line GCB, the first power line VGH, and the second power line VGL are the same as those in the previous embodiments, and reference may be made to the corresponding descriptions above.

[0203] At least one embodiment of the present disclosure further provides a display device. FIG11 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. Referring to FIG11 , a display device 100 provided by at least one embodiment of the present disclosure includes any one of the display substrates 10 provided by the embodiments of the present disclosure.

[0204] For example, the display device 100 further includes a plurality of pixel units located in the display area 102 and arranged in an array. At least some of the plurality of pixel units include light-emitting devices. For example, except for dummy pixels that do not perform a display function, each pixel unit includes a light-emitting device. The output signal output by the output circuit 1043 of the shift register unit 104 serves as a gate scan signal to drive the light-emitting devices of the plurality of pixel units to emit light.

[0205] For example, the display device 100 may be an OLED panel, an OLED TV, a QLED panel, a QLED TV, or any product or component with a display function, such as a mobile phone, a tablet computer, a laptop computer, a digital photo frame, or a navigation system. The display device 100 may also include other components, such as a data driver circuit and a timing controller, which are not limited in the embodiments of the present disclosure.

[0206] It should be noted that for the sake of clarity and brevity, the embodiments of this disclosure do not provide all components of the display device. To implement the substrate function of the display device, those skilled in the art may provide and configure other structures not shown according to specific needs, and the embodiments of this disclosure do not limit this.

[0207] Regarding the technical effects of the display device 2 provided in the above embodiment, reference may be made to the technical effects of the display substrate 1 provided in the embodiments of the present disclosure, which will not be repeated here.

[0208] There are a few points to note:

[0209] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0210] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0211] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the scope defined in the claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a non-display area at least partially surrounding the display area; A shift register unit is arranged on the base substrate and located in the non-display area, wherein: The shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit; The input circuit is configured to input an input signal to the first node in response to a first clock signal; The output circuit is configured to output an output signal to an output terminal; The first control circuit is configured to control the level of the second node in response to the level of the first node and the first clock signal; The output control circuit is configured to control the level of the output terminal under the control of the level of the second node; The output control circuit includes an output control transistor, the output circuit includes an output transistor, a direction parallel to the direction from the non-display area to the display area is a first direction, the shift register unit includes a first output semiconductor part and a second output semiconductor part arranged at intervals from each other in a second direction, the second direction intersects with the first direction, and the first output semiconductor part and the second output semiconductor part constitute a whole including an active layer of the output control transistor and an active layer of the output transistor; wherein the length direction of the channel of the output control transistor and the length direction of the channel of the output transistor are both along the first direction.

2. The display substrate according to claim 1, wherein: The input circuit includes an input transistor, the first control circuit includes a first control transistor and a second control transistor, The active layer of the input transistor, the active layer of the first control transistor, and the active layer of the second control transistor are all located on a first side of the entirety of the first output semiconductor portion and the second output semiconductor portion in the second direction.

3. The display substrate according to claim 2, wherein: The shift register unit further includes a second control circuit, the second control circuit being connected to the first node and the second node and configured to control the level of the first node under the control of the level of the second node and a second clock signal; The second control circuit includes a first noise reduction transistor and a second noise reduction transistor. The active layer of the noise reduction transistor and the active layer of the second noise reduction transistor are both located on a first side in the second direction of an entirety constituted by the first output semiconductor portion and the second output semiconductor portion.

4. The display substrate according to any one of claims 1 to 3, wherein: The active layer of the output control transistor and the active layer of the output transistor respectively include a plurality of sub-channel regions, and the output control transistor and the output transistor respectively include at least one first sub-channel region and at least one second sub-channel region; At least one first sub-channel region of the output control transistor and at least one first sub-channel region of the output transistor are located in the first output semiconductor part and arranged along the first direction, and at least one second sub-channel region of the output control transistor and at least one second sub-channel region of the output transistor are located in the second output semiconductor part and arranged along the first direction.

5. The display substrate according to claim 4, wherein: a length of the first output semiconductor portion in the first direction being greater than a length of the first output semiconductor portion in the second direction; A length of the second output semiconductor portion in the first direction is greater than a length of the second output semiconductor portion in the second direction.

6. The display substrate according to claim 3, wherein: The output control circuit further includes a first capacitor, a first electrode of the first capacitor is electrically connected to the second node; the display substrate further includes a first power line, the first power line is configured to provide a first voltage to the shift register unit, and a second electrode of the first capacitor is electrically connected to the first power line; The first capacitor is located on a first side of a whole composed of the first output semiconductor portion and the second output semiconductor portion in the second direction.

7. The display substrate according to claim 6, wherein: In the second direction, the first capacitor is located between the active layer of the first noise reduction transistor and the entirety of the first output semiconductor portion and the second output semiconductor portion; The first electrode of the first capacitor is electrically connected to the gate of the first noise reduction transistor and the gate of the output control transistor to form a continuous integrated structure; The electrode at which the gate of the output control transistor is located extends from the first electrode of the first capacitor along the second direction toward the entirety of the first output semiconductor portion and the second output semiconductor portion. The gate of the output control transistor is extended, and the orthographic projection of the gate of the output control transistor on the substrate at least partially overlaps with the orthographic projection of the first output semiconductor part on the substrate, and at least partially overlaps with the orthographic projection of the second output semiconductor part on the substrate; The electrode where the gate of the first noise reduction transistor is located extends from the first electrode of the first capacitor along the second direction toward the active layer of the first noise reduction transistor, and the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the first noise reduction transistor on the substrate.

8. The display substrate according to claim 6 or 7, wherein: The first power line extends in the second direction as a whole, and is located on a first side of the active layer of the input transistor, the active layer of the first control transistor, the second control transistor, and the active layer of the second noise reduction transistor in the first direction; The orthographic projection of the first power line on the base substrate overlaps with the orthographic projection of the second electrode of the first capacitor on the base substrate, and the first power line is electrically connected to the second electrode of the first capacitor through a first via hole; and, The first power line and the first electrode of the output control transistor form an integrated structure, the orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the first output semiconductor part on the substrate and the orthographic projection of the second output semiconductor part on the substrate, and the first power line is electrically connected to the first output semiconductor part and the second output semiconductor part through a second via.

9. The display substrate according to claim 8, wherein: The first power supply line covers at least a portion of an edge of the first output semiconductor portion extending in the second direction and at least a portion of an edge of the second output semiconductor portion extending in the second direction.

10. The display substrate according to any one of claims 3 and 6-9, wherein: The output circuit further includes a second capacitor, a first electrode of the second capacitor is connected to the control end of the output circuit, and a second electrode of the second capacitor is connected to the output end; The second capacitor is located on one side of a whole composed of the first output semiconductor portion and the second output semiconductor portion in the first direction.

11. The display substrate according to claim 10, wherein: A length of the second capacitor in the second direction is greater than a length of the second capacitor in the first direction.

12. The display substrate according to claim 10 or 11, wherein: The orthographic projection of the active layer of the second control transistor on the plane parallel to the first direction at least partially overlaps with the orthographic projection of the active layer of the input transistor on the plane parallel to the first direction, and at least partially overlaps with the orthographic projection of the second capacitor on the plane parallel to the first direction.

13. The display substrate according to any one of claims 10 to 12, wherein: The active layer of the input transistor, the active layer of the first noise reduction transistor and the active layer of the second noise reduction transistor are arranged in the first direction, and the active layer of the input transistor, the active layer of the first control transistor and the active layer of the second control transistor are arranged in the second direction.

14. The display substrate according to claim 13, wherein: In the first direction, there is a gap between the active layer of the input transistor and the active layer of the second noise reduction transistor, and the active layer of the first control transistor at least partially overlaps with the gap in the second direction; The first electrode of the input transistor and the first electrode of the second noise reduction transistor are both connected to the first node, and the first electrode of the input transistor and the first electrode of the second noise reduction transistor constitute a continuous and integrated first connecting electrode, the first connecting electrode is at least partially located in the gap, and the electrode where the gate of the first control transistor is located extends through the gap to be electrically connected to the first connecting electrode.

15. The display substrate according to claim 14, wherein: The active layer of the input transistor, the active layer of the second noise reduction transistor and the first connection electrode are respectively in the shape of strips extending along the first direction; Both ends of the first connection electrode in the first direction electrically connect the active layer of the input transistor and the active layer of the second noise reduction transistor, which are opposite to each other in the first direction, respectively.

16. The display substrate according to claim 14 or 15, wherein: The shift register unit further includes a voltage stabilizing circuit, which is connected to the first node and the third node and is configured to stabilize the level of the third node; the control end of the output circuit is connected to the third node, and the output circuit is configured to output the output signal to the output end under the control of the level of the third node; The voltage stabilizing circuit includes a voltage stabilizing transistor, an active layer of the voltage stabilizing transistor and the second capacitor are both located on a first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the first direction, and the active layer of the voltage stabilizing transistor and the second capacitor are both located on a first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the first direction. The orthographic projections of the capacitor on the plane parallel to the second direction at least partially overlap with the orthographic projections of the whole formed by the first output semiconductor part and the second output semiconductor part on the plane parallel to the second direction; The active layer of the voltage-stabilizing transistor is located on a side of the second capacitor in the second direction close to the input transistor, and an orthographic projection of the active layer of the voltage-stabilizing transistor on a plane parallel to the first direction at least partially overlaps with an orthographic projection of the second capacitor on a plane parallel to the first direction.

17. The display substrate according to any one of claims 14 to 16, wherein: The voltage stabilizing transistor is located at a side of the first control transistor close to the second capacitor in the second direction, and a first electrode of the voltage stabilizing transistor is electrically connected to a first electrode of the second capacitor; An orthographic projection of the voltage regulating transistor on a plane parallel to the first direction does not overlap with an orthographic projection of the first control transistor on a plane parallel to the first direction, and overlaps with an orthographic projection of the second control transistor on a plane parallel to the first direction.

18. The display substrate according to claim 17, wherein: The electrode where the gate of the first control transistor is located includes an inclined portion, the extension direction of the inclined portion intersects both the first direction and the second direction, and the end of the inclined portion close to the voltage stabilizing transistor in the second direction is electrically connected to the second electrode of the voltage stabilizing transistor through a third via.

19. The display substrate according to claim 18, wherein: The electrode where the gate of the first control transistor is located also includes a vertical portion connected to the inclined portion and extending along the second direction, the vertical portion extends through the gap, and an end of the vertical portion away from the inclined portion in the second direction is electrically connected to the first connection electrode through a fourth via hole.

20. The display substrate according to claim 19, wherein: The gate of the second noise reduction transistor and the first electrode of the output transistor are both connected to the second clock signal terminal to receive the second clock signal; The electrode where the gate of the second noise reduction transistor is located is in the shape of a strip extending along the second direction, the first pole of the output transistor includes a second connecting electrode, the second connecting electrode includes a first strip portion extending along the first direction, an end of the electrode where the gate of the second noise reduction transistor is located close to the output transistor in the second direction is electrically connected to the first end of the first strip portion in the first direction through a fifth via hole, and the second connecting electrode is electrically connected to the second clock signal end.

21. The display substrate according to any one of claims 6 to 9, wherein: The display substrate further comprises an output signal line electrically connected to the output terminal, and a portion of the output signal line located in the non-display area comprises a first direction portion and a second direction portion; The first direction portion of the output signal line extends along the first direction, and one end of the first direction portion away from the display area in the first direction is electrically connected to the electrode where the second pole of the output transistor is located through a first output via hole so that the second pole of the output transistor is electrically connected to the output end. The second direction portion of the output signal line is connected to the first direction portion, is located on a side of the first direction portion close to the display area, and extends along the second direction as a whole to enter the display area.

22. The display substrate according to claim 21, wherein: The electrode where the second pole of the output transistor is located comprises: a strip-shaped main body extending along the first direction, a plurality of strip-shaped extensions connected to the strip-shaped main body and located on a first side of the strip-shaped main body in the second direction and extending along the second direction, and a protrusion protruding from the strip-shaped main body in the second direction toward away from the plurality of strip-shaped extensions; The orthographic projections of the plurality of strip-shaped extensions on the substrate at least partially overlap with the orthographic projections of the first output semiconductor portion on the substrate and the orthographic projections of the second output semiconductor portion on the substrate, and the protrusion is located on a second side of the whole formed by the first output semiconductor portion and the second output semiconductor portion in the second direction, which is opposite to the first side thereof; The first direction portion of the output signal line is located on the second side of the whole formed by the first output semiconductor portion and the second output semiconductor portion in the second direction, and one end of the first direction portion in the first direction away from the display area is connected to the protrusion through the first output via hole, and the second direction portion is connected to the first direction portion, is located on a side of the first direction portion close to the display area, and extends along the second direction as a whole.

23. The display substrate according to claim 21 or 22, wherein: The first power line is located on a side of the second electrode of the output transistor close to the display area in the first direction, and an orthographic projection of the first power line on the base substrate overlaps with an orthographic projection of the output signal line on the base substrate.

24. The display substrate according to claim 23, wherein: The display substrate further comprises: a second power line configured to provide a second voltage to the shift register unit, wherein a first electrode of the second control transistor is connected to the second node, and a second electrode of the second control transistor is connected to the second power line to receive the second voltage; a trigger signal line, wherein the display substrate comprises a plurality of the shift register units connected in cascade, a first electrode of the input transistor in a first stage of the shift register unit is connected to the input terminal, and the input terminal is configured to be connected to the trigger signal line to receive a trigger signal from the trigger signal line as an input signal; a first clock signal line configured to provide the first clock signal to the shift register unit; and The second clock signal line is configured to provide the second clock signal to the shift register unit, wherein: The second power line, the trigger signal line, the first clock signal line, the second clock signal line, and the first power line are all arranged at the same layer as the second electrode of the second control transistor.

25. The display substrate according to any one of claims 10 to 20, wherein: The second capacitor is located at one side of the whole formed by the first output semiconductor part and the second output semiconductor part and close to the display area in the first direction; The display substrate also includes an output signal line, which is electrically connected to the second electrode of the second capacitor. The second electrode of the second capacitor is electrically connected to the electrode where the second electrode of the output transistor is located through a second output via hole so that the second electrode of the output transistor is electrically connected to the output end.

26. The display substrate according to any one of claims 3, 6-23 and 25, wherein: The display substrate further comprises: a second power line configured to provide a second voltage to the shift register unit, wherein a first electrode of the second control transistor is connected to the second node, and a second electrode of the second control transistor is connected to the second power line to receive the second voltage; The display substrate includes a plurality of shift register units connected in cascade, the first electrode of the input transistor in the first stage of the shift register unit is connected to the input terminal, and the input terminal is configured to be connected to the trigger signal line to receive a trigger signal from the trigger signal line. Signal as input signal; a first clock signal line configured to provide the first clock signal to the shift register unit; and The second clock signal line is configured to provide the second clock signal to the shift register unit, wherein: At least one of the second power line, the trigger signal line, the first clock signal line and the second clock signal line overlaps with the shift register unit in a direction perpendicular to the base substrate and is arranged with the second pole different layer of the second control transistor.

27. The display substrate according to claim 26, wherein: The second power line extends as a whole along the second direction, at least partially overlaps with the electrode where the gate of the second control transistor is located in a direction perpendicular to the substrate, and at least partially overlaps with the second electrode of the second control transistor in a direction perpendicular to the substrate; The second power line and the second pole of the second control transistor are arranged in different layers, the second pole of the second control transistor is located between the second power line and the electrode where the gate of the second control transistor is located, the second pole of the second control transistor includes a portion that does not overlap with the electrode where the gate of the second control transistor is located in a direction perpendicular to the substrate, the second power line is electrically connected to the second pole of the second control transistor through a first power via, and the second pole of the second control transistor is electrically connected to the active layer of the second control transistor through a first auxiliary via.

28. The display substrate according to claim 26 or 27, wherein: The shift register unit further includes a voltage stabilizing circuit, which is connected to the first node and the third node and is configured to stabilize the level of the third node; the control end of the output circuit is connected to the third node, and the output circuit is configured to output the output signal to the output end under the control of the level of the third node; the voltage stabilizing circuit includes a voltage stabilizing transistor, the active layer of the voltage stabilizing transistor and the second capacitor are both located on the first side of the whole formed by the first output semiconductor part and the second output semiconductor part in the first direction, The second power line at least partially overlaps with the electrode where the gate of the voltage stabilizing transistor is located in a direction perpendicular to the substrate, and the second power line is electrically connected to the electrode where the gate of the voltage stabilizing transistor is located through a second power via.

29. The display substrate according to claim 27, wherein: The second power line also at least partially overlaps the input transistor and the second capacitor in a direction perpendicular to the substrate.

30. The display substrate according to any one of claims 26 to 29, wherein: The trigger signal line extends along the second direction and at least partially overlaps with the first electrode of the input transistor of the first-stage shift register unit in a direction perpendicular to the substrate, and the trigger signal line is electrically connected to the first electrode of the input transistor of the first-stage shift register unit through a trigger via.

31. The display substrate according to any one of claims 26 to 30, wherein: The first clock signal line extends as a whole along the second direction and at least partially overlaps with the electrodes where the gate of the input transistor and the gate of the second control transistor are located in a direction perpendicular to the substrate. The first clock signal line is electrically connected to the electrodes where the gate of the input transistor and the gate of the second control transistor of the first-stage shift register unit are located through a first clock via.

32. The display substrate according to any one of claims 26 to 31, wherein: The second clock signal line extends along the second direction and at least partially overlaps with the electrode where the first pole of the output transistor is located in a direction perpendicular to the substrate, and the second clock signal line is electrically connected to the electrode where the first pole of the output transistor is located through a second clock via.

33. The display substrate according to claim 32, wherein: In the case where the electrode where the gate of the second noise reduction transistor is located is in a strip shape extending along the second direction, the first electrode of the output transistor includes a second connection electrode, the second connection electrode includes a first strip portion extending along the first direction, an end of the electrode where the gate of the second noise reduction transistor is located close to the output transistor in the second direction is electrically connected to a first end of the first strip portion in the first direction through a fifth via hole, and the second connection electrode is electrically connected to the second clock signal end. The second clock signal line at least partially overlaps with the first strip portion in a direction perpendicular to the base substrate, and the second clock signal line is electrically connected to the first strip portion through the second clock via, so that the gate of the second noise reduction transistor and the first electrode of the output transistor are both connected to the second clock signal end.

34. The display substrate according to any one of claims 26 to 33, wherein: The second power line, the trigger signal line, the first clock signal line and the second clock signal line all overlap with the shift register unit in a direction perpendicular to the base substrate; The second power supply line, the trigger signal line, the first clock signal line and the second clock signal line are arranged on the same layer, and are all arranged on a different layer from the first pole of the output transistor.

35. A display device comprising the display substrate according to any one of claims 1-34.

36. The display device according to claim 35, wherein: The display device also includes a plurality of pixel units located in the display area and arranged in an array, at least some of the plurality of pixel units include light-emitting devices, and the output signal output by the output circuit of the shift register unit is used as a gate scanning signal to drive the light-emitting devices of the plurality of pixel units to emit light.

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