Triggering error detector at rising and falling edges of clock signal and thereby generating error signal

Abstract

One or more examples involve triggering a single error detector at rising and falling edges of a clock signal and thereby generating an error signal. A method can include receiving a first clock signal and a second clock signal. The method can include generating an error signal representative of a phase difference between the first clock signal and the second clock signal via a single error detector triggered at least in part in response to similar respective edges of the first clock signal and the second clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 367,581, filed on July 1, 2022, entitled “DUAL EDGEPFD CIRCUIT, AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME,” under 35 U.S.C. §119(e), the contents and disclosure of which are hereby incorporated herein by this reference in their entirety. Technical Field

[0003] One or more examples generally relate to error detection, including phase error detection and frequency error detection. One or more examples generally relate to triggering an error detector at rising and falling edges of a clock signal. One or more examples generally relate to clock tracking using an error detector triggered at rising and falling edges of a clock signal. Background Art

[0004] Clock tracking circuits, such as phase-locked loops and delay-locked loops, are circuits used to track clocks and other oscillating signals. The output signal of the clock tracking circuit is locked to the phase and frequency of a reference signal. Clock tracking circuits are used in a variety of operating contexts, including situations where two signals with a known relationship are used to transmit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram depicting a double edge error detection circuit according to one or more examples.

[0007] Figure 2 The present invention is a method for generating a control signal and controlling a first multiplexer and a second multiplexer for generating a control signal and controlling a first multiplexer and a second multiplexer according to one or more examples. Figure 1 Block diagram of the logic circuit for double-edge triggering at the double-edge error detection circuit.

[0008] Figure 3 is a description of one or more examples Figure 1 A timing diagram of a process in a non-limiting example operation of a double edge error detection circuit.

[0009] Figure 4 is a flow chart depicting a process for generating an error signal representing a phase difference between a first clock signal and a second clock signal according to one or more examples.

[0010] Figure 5 is a diagram illustrating a method for controlling a Figure 1 A flow chart of a process for selecting input terminals of a first multiplexer and a second multiplexer of a double edge error detection circuit.

[0011] Figure 6 is a block diagram depicting an apparatus for tracking a clock according to one or more examples.

[0012] Figure 7 are block diagrams of circuits that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0014] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0015] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary", "by way of example", and "for example" means that the relevant description is illustrative, and while the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the examples of the present disclosure to the specified components, steps, features, functions, etc.

[0016] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0017] In addition, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0018] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0019] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0020] Examples can be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operable actions as continuous processes, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes can correspond to methods, threads, functions, procedures, subroutines, subprograms, without limitation. In addition, the methods disclosed herein can be implemented by hardware, software, or both. If implemented in software, functions can be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that are conducive to transferring a computer program from one location to another.

[0021] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0022] As used herein, the term "substantially" in reference to a given parameter, property, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, property, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. For example, depending on the particular parameter, property, or condition being substantially satisfied, the parameter, property, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0023] As used herein, any relative terms (such as "above", "below", "on", "below", "upper", "lower", but not limited to) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0024] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless otherwise expressly indicated or the context would indicate otherwise to one of ordinary skill in the art.

[0025] A clock signal, or just "clock," is a signal that oscillates between a high state and a low state in a reliably predictable manner. One or more circuits may respond to the rising or falling edge of the clock to coordinate the actions of the one or more circuits. The change of the clock signal from a low state to a high state is referred to herein as a "rising edge," and the change of the clock signal from a high state to a low state is referred to herein as a "falling edge."

[0026] An error detector is a circuit (digital or analog) that compares the phase of two input signals and generates an output signal that is proportional to the phase difference between the two input signals. A phase-frequency detector (PFD) is an error detector that generates an output signal that is proportional to the phase difference between the two input signals and derivatively proportional to the frequency difference between the two input signals. Here, "derivatively proportional" means that information about the frequency difference can be derived from the information about the phase difference in the error signal. The magnitude and direction of the output signal of the PFD are proportional to the phase difference between the two input signals, and derivatively proportional to the frequency difference between the two input signals. In applications where phase and frequency differences are not required, the output signal is often referred to as an "error signal".

[0027] A typical PFD is either rising edge triggered or falling edge triggered, but not both. To utilize both the rising and falling edges of the input clock signal, two PFDs are typically utilized: one triggered by the rising edge and the other by the falling edge. Alternatively, both PFDs may be either rising edge triggered or falling edge triggered, and one of the PFDs receives a non-inverted version of the input clock signal and the other of the PFDs receives an inverted version of the input clock signal. In either case, two PFDs are utilized.

[0028] Ideally, the two PFDs are perfectly matched with respect to at least: rise time and fall time, input to output delay (also referred to as "response time"), layout, output loading, and non-idealities (e.g., non-idealities resulting from the manufacturing process, but not limited to). In practice, the inventors of the present disclosure have recognized that the two PFDs will not match, which degrades the performance of the PFDs and, more specifically, the usefulness of the output signals they generate. Depending on the operating context, the reduced performance may result in various disadvantages. As a non-limiting example, a PFD is utilized in a clock tracking circuit to generate an error signal that represents the phase difference and frequency difference between a reference clock signal and an output clock signal generated by the clock tracking circuit to track the reference clock signal. The reduced performance of phase-frequency detection due to the mismatch between the rising edge triggered PFD and the falling edge triggered PFD may result in degradation of the jitter and spur performance of the output clock.

[0029] Additional circuitry may be included to correct for the effects of mismatched PFDs, but this adds complexity and cost.

[0030] As used herein, the phrase "phase difference or frequency difference" means "phase difference or phase difference and frequency difference", unless explicitly stated otherwise.

[0031] The inventors of the present disclosure recognized that error detection based on the rising and falling edges of an input clock signal, such as phase-frequency detection (but not limited to such), is desirable without the degraded performance exhibited by the mismatch exhibited by the rising edge triggered PFD and the falling edge triggered PFD used to perform the error detection.

[0032] Figure 1 is a block diagram depicting an apparatus 100 according to one or more examples. Figure 1 is a non-limiting example of a double edge error detector and may also be referred to herein as “double edge error detector 100 ” or “double edge error detection circuit 100 ”.

[0033] The apparatus 100 includes a first multiplexer 102, a second multiplexer 104, and an error detector 106. The first multiplexer 102 ("MUX 1") includes a non-inverting input 108, an inverting input 110, an output 130, and a select input 124. The second multiplexer 104 ("MUX2") includes a non-inverting input 112, an inverting input 114, an output 132, and a select input 126. The error detector 106 includes a first input 120, a second input 122, and an output 142.

[0034] The first multiplexer 102 / the second multiplexer 104 selects one of the signals at the non-inverting input terminal 108 / the non-inverting input terminal 112 or the signals at the inverting input terminal 110 / the inverting input terminal 114, respectively, at least in part in response to a selection signal (here, a control signal 128) received at the selection input terminal 124 / the selection input terminal 126, and provides the selected signal at the output terminal 130 / the output terminal 132, which are respectively coupled to the input terminal 120 / the input terminal 122 of the error detector 106.

[0035] The error detector 106 generates an error signal 134, which is proportional to the phase difference between the two input selection signals provided at the output 130 of the first multiplexer 102 and the output 132 of the second multiplexer 104, and is derived proportional to the frequency difference between the two input selection signals. Here, "derivatively proportional" means that information about the frequency difference can be derived from information about the phase difference. Here, the phase difference is represented by the error signal 134, so that information about the frequency difference between the two input selection signals can be derived at least in part based on the error signal 134. The magnitude and direction of the error signal 134 are proportional to the phase difference between the two input selection signals (and derived proportional to the frequency difference)-here, the two input selection signals are versions (i.e., inverted or non-inverted, as the case may be) of the first clock signal 116 and the second clock signal 118 received at the input 120 / input 122. As a non-limiting example, the error detector 106 may include or may be a phase detector or a time-to-digital converter.

[0036] In one or more examples, the output of the error detector 106 can be provided to the input of a bang-bang phase detector that generates an increment (INC) signal and a decrement (DEC) signal that indicate information about the phase difference, but not the frequency difference, between two input selection signals.

[0037] In one or more examples, if the respective phases of the two input selection signals are substantially the same, the magnitude and direction of the error signal 134 generated by the error detector 106 will be zero, indicating that the phases and frequencies of the two input selection signals are the same. In one or more examples, if the respective phases of the two input selection signals are different, the magnitude and direction of the error signal 134 generated by the error detector 106 will be non-zero and proportional to such difference.

[0038] The error detector 106 is edge-triggered and resets upon detecting similar corresponding edges of the two input selection signals. In various examples, the error detector 106 can be rising edge-triggered or falling edge-triggered—that is, triggered by corresponding rising edges or corresponding falling edges of the two input selection signals: the selected first clock signal 138 and the selected second clock signal 140. In various examples, the device 100 can be rising edge-triggered or falling edge-triggered—that is, triggered by corresponding rising edges or corresponding falling edges of the first clock signal 116 and the second clock signal 118. As non-limiting examples, the error signal 134 generated by the error detector 106 can be a voltage signal, a current signal, or two binary signals.

[0039] In the case of a voltage signal or a current signal, a positive value of the error signal 134 indicates that the phase of one of the input selection signals leads the other input selection signal (in terms of time), and a negative value of the error signal 134 indicates that the phase of one of the input signals lags the other input signal (in terms of time). The magnitude (e.g., amplitude, but not limited thereto) of the error signal 134 indicates the amount of phase difference between the signal received at the first input terminal 120 and the signal received at the second input terminal 122. A larger magnitude error signal indicates a larger phase difference between the two input selection signals, and a smaller magnitude error signal indicates a smaller phase difference.

[0040] In the case of two binary signals, the error signal 134 may include two signals, namely an UP signal and a DOWN signal. The error detector 106 generates the UP signal and the DOWN signal as a series of pulses, wherein the pulses on the corresponding ones of the UP signal and the DOWN signal indicate the magnitude and direction of the error signal 134. The one of the UP signal and the DOWN signal that first presents a pulse indicates which of the two input selection signals leads the other; and conversely, which of the two input selection signals lags behind the other. The magnitude of the error signal 134 is represented by the pulse width of the pulse generated in the UP signal or the DOWN signal. A larger pulse width indicates a larger phase difference between the two input signals, and a smaller pulse width indicates a smaller phase difference. One of the inputs of the error detector 106 is preset as a reference input of leading, lagging or locking, and the other of the inputs of the error detector 106 is preset as a feedback (or "controlled") input of leading, lagging or locking. As a non-limiting example, in a clock tracking circuit, a reference signal is provided to a reference input, and an output signal is provided to a feedback input.

[0041] The first multiplexer 102 receives the first clock signal 116 at its non-inverting input 108 and inverting input 110 and receives the control signal 128 at its select input 124. The first multiplexer 102 selects one of the non-inverting input 108 and the inverting input 110 at least in part in response to the control signal 128 and provides one of the inverted version or the non-inverted version of the first clock signal 116 as the selected first clock signal 138 at its output 130 at least in part in response to the control signal 128.

[0042] The second multiplexer 104 receives the second clock signal 118 at its non-inverting input 112 and inverting input 114, and receives the control signal 128 at its select input 126. The first multiplexer 102 selects one of the non-inverting input 112 or the inverting input 114 at least in part in response to the control signal 128, and provides one of the inverted version or the non-inverted version of the second clock signal 118 as the selected second clock signal 140 at its output 132 at least in part in response to the control signal 128. In one or more examples, the first clock signal 116 and the second clock signal 118 are different clock signals.

[0043] An output 130 of the first multiplexer 102 is coupled to a first input 120 of the error detector 106, and an output 132 of the second multiplexer 104 is coupled to a second input 122 of the error detector 106. The error detector 106 generates an error signal 134 to represent a phase difference and a frequency difference between a selected first clock signal 138 and a selected second clock signal 140.

[0044] As discussed above, the error detector 106 can be rising edge triggered or falling edge triggered. If rising edge triggered, the error detector 106 ignores falling edges. If falling edge triggered, the error detector 106 ignores rising edges.

[0045] As will be described below, in one or more examples, the first multiplexer 102 and the second multiplexer 104 are controlled via the control signal 128 to provide inverted or non-inverted versions of the first clock signal 116 and the second clock signal 118 as the selected first clock signal 138 and the selected second clock signal 140, respectively.

[0046] As a non-limiting example, after the error detector 106 is triggered by the rising edge of the non-inverted version of the first clock signal 116 and the rising edge of the non-inverted version of the second clock signal 118, the first multiplexer 102 and the second multiplexer 104 are controlled via the control signal 128 to select their respective inverting inputs 110 / 114. When the inverting inputs of the first multiplexer 102 and the second multiplexer 104 are selected, the first multiplexer provides the inverted version of the first clock signal 116 as the selected first clock signal 138 to the first input 120 of the error detector 106, and the second multiplexer provides the inverted version of the second clock signal 118 as the selected second clock signal 140 to the second input 122 of the error detector 106.

[0047] The error detector 106 is reset upon detecting the same corresponding edge of the signals at the first input 120 and the second input 122 (here, the selected first clock signal 138 and the selected second clock signal 140), and asserting the reset signal 136. After being reset, the error detector 106 is triggered at the rising edge of the selected first clock signal 138 (the inverted version of the first clock signal 116) and the rising edge of the selected second clock signal 140 (the inverted version of the second clock signal 118). By alternately providing the inverted version and the non-inverted version of the first clock signal 116 and the second clock signal 118 to the error detector 106 as the selected first clock signal 138 and the selected second clock signal 140, respectively, the double edge error detector 100 reuses the error detector 106 for both the rising and falling edges of the clock signals, and the device 100 operates as a double edge triggered error detector and more specifically as a double edge triggered phase-frequency detector, as discussed in more detail below.

[0048] Figure 2 is a method for generating a Figure 1 A block diagram of a device 200 for using a control signal 128 of the logic circuit 202 and controlling the first multiplexer 102 and the second multiplexer 104 for double edge triggering of the device 100. The device 200 includes a logic circuit 202.

[0049] The logic circuit 202 receives the reset signal 136 from the error detector 106 and generates the control signal 128 at least partially in response to the reset signal 136. In one or more examples, the error detector 106 de-asserts the reset signal 136 to indicate that the error detector 106 has been edge triggered and will be triggered on the next set of edges of the input signal. The logic circuit 202 alternately asserts and de-asserts the control signal 128 in response to one of the de-assertion or assertion of the reset signal 136. Whether the logic circuit 202 asserts or de-asserts the control signal 128 in response to the de-assertion or assertion of the reset signal 136 is an implementation-specific decision, and either may be utilized without exceeding the scope of the present disclosure.

[0050] In one or more examples, the first multiplexer 102 can select the non-inverting input 108 when the control signal 128 is asserted and select the inverting input 110 when the control signal 128 is de-asserted, and the second multiplexer 104 can select the inverting input 114 when the control signal 128 is asserted and select the non-inverting input 112 when the control signal 128 is de-asserted. The association of the inputs of the first multiplexer 102 and the second multiplexer 104 with the assertion or de-assertion of the control signal 128 is an implementation-specific decision, and any suitable association can be utilized without exceeding the scope of the present disclosure.

[0051] Figure 3 is a signal timing diagram depicting a process 300 according to a non-limiting example operation of the apparatus 100 according to one or more examples. The x-axis of the signal timing diagram represents time, increasing from the left side of the page to the right side. The y-axis of the signal timing diagram represents voltage level, which increases from the bottom to the top of the page. Figure 3 In the particular example operations depicted, time is expressed in nanoseconds (ns).

[0052] Process 300 includes Figure 1 and Figure 2 The first clock signal 116, the second clock signal 118, the control signal 128, the error signal 134 and the reset signal 136.

[0053] exist Figure 3 In the particular non-limiting example depicted, the error signal 134 includes two signals, an UP signal ("up") and a DOWN signal ("down"), as discussed above. Figure 3In the particular non-limiting example depicted, the DOWN signal is asserted to indicate the timing of the occurrence of an edge of the first clock signal 116, and is de-asserted to indicate the timing of the occurrence of a similar edge of the second clock signal 118 (e.g., before or after the occurrence of the edge of the first clock signal 116). If the similar edge of the second clock signal 118 occurs before the edge of the first clock signal 116, the DOWN signal is de-asserted after the DOWN signal is temporarily (e.g., for a predetermined duration, where the duration indicates the order of occurrence, but is not limited thereto) maintained in a high state. If the similar edge of the second clock signal 118 occurs after the edge of the first clock signal 116, the DOWN signal remains in a high state until it is de-asserted in response to the occurrence of the similar edge of the second clock signal 118.

[0054] exist Figure 3 In the particular non-limiting example depicted, the UP signal is asserted to indicate the timing of the occurrence of an edge of the second clock signal 118, and is de-asserted to indicate the timing of the occurrence of a similar edge of the first clock signal 116. If the similar edge of the first clock signal 116 occurs before the edge of the second clock signal 118, the UP signal is de-asserted after temporarily (e.g., for a predetermined duration, where the duration indicates the order of occurrence, but is not limited thereto) maintaining the UP signal in a high state. If the similar edge of the first clock signal 116 occurs after the edge of the first clock signal 116, the UP signal remains in a high state until it is de-asserted in response to the occurrence of a similar edge of the second clock signal 118. When the two input signals are in phase, neither the UP signal nor the DOWN signal is asserted (i.e., the UP signal and the DOWN signal remain in a low state).

[0055] The error detector 106 generates pulses at the DOWN signal of the error signal 134 to indicate the timing of the edge of the first clock signal 116 and the similar edge relative to the second clock signal 118, and generates pulses at the UP signal of the error signal 134 to indicate the timing of the edge of the second clock signal 118 and the similar edge relative to the first clock signal 116. The larger pulse width indicates which edge is leading, and the smaller pulse width indicates which edge is lagging. The width of the larger pulse is determined by the time difference between the edges. The width of the smaller pulse is set to a predetermined duration.

[0056] It is worth noting that the UP signal or DOWN signal of the error signal 134 is related to the first clock signal 116 or the second clock signal 118 (or Figure 1The association of the DOWN signal with the edge of the first clock signal 116 and the UP signal with the edge of the second clock signal 118, or the DOWN signal with the edge of the second clock signal 118 and the UP signal with the edge of the first clock signal 116, without exceeding the scope of the present disclosure, and their relative timing are a matter of design choice (e.g., based on operating conditions, but not limited thereto) and are not limiting of the present disclosure in any way. As non-limiting examples, without exceeding the scope of the present disclosure, the DOWN signal may be associated with an edge of the first clock signal 116 and the UP signal may be associated with an edge of the second clock signal 118, or the DOWN signal may be associated with an edge of the second clock signal 118 and the UP signal may be associated with an edge of the first clock signal 116.

[0057] Steering Figure 3 , at time T1, the error detector 106 asserts the DOWN signal to indicate an edge (here, a rising edge) of the first clock signal 116, while the second clock signal 118 remains low. The control signal 128 is de-asserted until time T1. At time T2, the error detector 106 de-asserts the DOWN signal and temporarily asserts the UP signal to indicate an edge (here, a rising edge) of the second clock signal 118.

[0058] At time T2, the error detector 106 temporarily asserts the reset signal 136 (here, the reset signal 136 is asserted to be active low) to indicate that the error detector 106 has been edge triggered, i.e., rising edges have been detected for both the first clock signal 116 and the second clock signal 118, and the error detector 106 is ready to trigger at the next set of edges of the input signal. At time T2, the device 200 asserts the control signal 128 in response to the temporary assertion of the reset signal 136. As discussed above, the outputs of the first multiplexer 102 and the second multiplexer 104 are switched to provide the selected first clock signal 138 and the selected second clock signal 140 as the other of the inverted version or the non-inverted version of the first clock signal 116 and the second clock signal 118 in response to the assertion of the control signal 128.

[0059] At time T3, the error detector 106 asserts the DOWN signal to indicate an edge (here, a falling edge) of the first clock signal 116, while the second clock signal 118 remains high. At T4, the error detector 106 deasserts the DOWN signal and temporarily asserts the UP signal to indicate an edge (here, a falling edge) of the second clock signal 118.

[0060] At time T4, the error detector 106 temporarily asserts the reset signal 136 to indicate that the error detector 106 has been edge triggered, i.e., a falling edge has been detected for both the first clock signal 116 and the second clock signal 118, and the error detector 106 is ready to trigger at the next set of edges of the input signal. At time T4, the device 200 de-asserts the control signal 128 in response to the temporary assertion of the reset signal 136.

[0061] exist Figure 3 In the particular non-limiting example operation depicted, the DOWN and UP signals of the error signal 134 and the control signal 128 are described as being active high (i.e., being in a high state when asserted and being in a low state when de-asserted), and the reset signal 136 is described as being active low (i.e., being in a low state when asserted and being in a high state when de-asserted). Whether to use active high or active low is a matter of design choice (e.g., based on operating conditions, but not limited thereto) and does not limit the present disclosure in any way. As non-limiting examples, one or more of the DOWN and UP signals of the error signal 134, the control signal 128, or the reset signal 136 may be set to be active high or to be active low.

[0062] Figure 4 4 is a flowchart depicting a process 400 for generating an error signal representing a phase difference between a first clock signal and a second clock signal according to one or more examples. In one or more examples, some or all of the operations of process 400 can be performed by Figure 1 The double edge error detection circuit 100 is used to perform.

[0063] Although the example process 400 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 400. In other examples, different components of an example device or system implementing the process 400 may perform functions substantially simultaneously or in a particular order.

[0064] In one or more examples, process 400 includes receiving a first clock signal and a second clock signal at operation 402. The first clock signal is different from the second clock signal (eg, generated by a different source, provided via a different signal path, or both, but is not limited thereto).

[0065] In one or more examples, one of the first clock signal and the second clock signal may be a reference clock signal and the other may be an output clock signal (or a clock signal indicative of the output clock signal, such as a feedback clock signal) generated by a clock tracking circuit to track the reference clock signal.

[0066] In one or more examples, the process 400 includes generating an error signal representing a phase difference between the first clock signal and the second clock signal via a single error detector (e.g., error detector 106, but not limited thereto) triggered at least in part in response to similar corresponding edges of the first clock signal and the second clock signal at operation 404. To be triggered at least in part in response to similar corresponding edges of the first clock signal and the second clock signal, in the case of the device 100, the single error detector is alternately provided with a selected one of a non-inverted version and an inverted version of the first clock signal and the second clock signal, and is alternately triggered by a selected one of a non-inverted version and an inverted version of the first clock signal and the second clock signal, but not limited thereto. In one or more examples, the single error detector is triggered by all of the similar corresponding edges of the first clock signal and the second clock signal, which in the case of clock signals means that the single error detector is triggered by corresponding rising edges of the first clock signal and the second clock signal, and is triggered by corresponding falling edges of the first clock signal and the second clock signal.

[0067] In order to trigger a single error detector (e.g., error detector 106, but not limited thereto) in response to rising and falling edges of the first clock signal and the second clock signal, in one or more examples, a multiplexer (e.g., multiplexers 102 and 104, but not limited thereto) may be used to alternately select a non-inverted version or an inverted version of the first clock signal and the second clock signal, and provide a corresponding input selection signal to a corresponding one of a first input terminal and a second input terminal of the single error detector. A logic circuit (e.g., logic circuit 202, but not limited thereto) may control the selection of the inverted version or the non-inverted version of the first clock signal and the second clock signal at the multiplexer and the timing thereof via one or more control signals.

[0068] Figure 5 is a flow chart depicting a process 500 for controlling selection of an inverted version or a non-inverted version of a first clock signal and a second clock signal according to one or more examples. More specifically, Figure 5 A process 500 is depicted for controlling the select inputs 124, 126 of the first multiplexer 102 and the second multiplexer 104 of the device 100, respectively, via the control signal 128. In one or more examples, some or all of the operations of the process 300 may be performed by Figure 2 The device 200, Figure 1 The multiplexers 102 and 104 or a combination thereof are implemented.

[0069] Although the example process 500 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 500. In other examples, different components of the example device or system implementing the process 500 may perform functions substantially simultaneously or in a particular order.

[0070] In one or more examples, process 500 includes selecting a non-inverting input of a first multiplexer having an output coupled to a first input of the error detector at least in part in response to a first assertion of a reset signal of the error detector at operation 502 .

[0071] In one or more examples, process 500 includes selecting a non-inverting input of a second multiplexer having an output coupled to a second input of the error detector at least in part in response to a first assertion of a reset signal of the error detector at operation 504 .

[0072] In one or more examples, process 500 includes selecting an inverting input of a first multiplexer having an output coupled to a first input of the error detector at least in part in response to a second assertion of a reset signal of the error detector at operation 506 .

[0073] In one or more examples, process 500 includes selecting an inverting input of a second multiplexer having an output coupled to a second input of the error detector at least in part in response to a second assertion of a reset signal of the error detector at operation 508 .

[0074] In one or more examples of process 500, one of the first multiplexer and the second multiplexer may be receiving the first clock signal at its non-inverting input and inverting input, and the other of the first multiplexer and the second multiplexer may be receiving the other of the first clock signal and the second clock signal at its non-inverting input and inverting input.

[0075] In one or more examples, "selection" in process 500 should be understood to include, but is not limited to: selecting the inverting input or the non-inverting input at the multiplexer as appropriate, generating a control signal configured to select the inverting input or the non-inverting input at the multiplexer as appropriate, combinations thereof, and their legal equivalents.

[0076] Figure 66 is a block diagram depicting an apparatus 600 for tracking a clock (and may also be referred to herein as a "clock tracking circuit 600") according to one or more examples. As non-limiting examples, the clock tracking circuit 600 may be a hybrid phase-locked loop (PLL), an analog PLL, a digital PLL, a delay-locked loop (DLL), an injection-locked loop (ILL), or a frequency synthesizer.

[0077] The apparatus 600 includes a double edge error detector 602, a controller 604, and a controlled oscillator 606. The apparatus 600 generally operates to generate an output clock signal 608 that is phase-locked and frequency-locked to a reference clock signal 614.

[0078] The double edge error detector 602 is Figure 1 6. A double edge error detector 602 is a non-limiting example of a double edge error detector 100. The double edge error detector 602 receives a reference clock signal 614 and a feedback clock signal 616. Generally, the double edge error detector 602 is edge triggered and resets upon detecting similar edges of the reference clock signal 614 and the feedback clock signal 616. The double edge error detector 602 does not distinguish between rising or falling edges. The double edge error detector 602 reuses a single error detector to detect similar edges (rising and falling) of the reference clock signal 614 and the output clock signal 608. The double edge error detector 602 generates an error signal 612 that is proportional to the phase difference and frequency difference between the reference clock signal 614 and the feedback clock signal 616.

[0079] The reference clock signal 614 may be generated by any suitable clock source for a given operating context. The feedback clock signal 616 may be the same as the output clock signal 608 (e.g., the output clock signal 608 is provided directly to the input of the double edge error detector 602, but is not limited thereto), or may be a clock signal that indicates the phase, frequency, pulse width, and duty cycle of the output clock signal 608. For example, the phase, frequency, pulse width, and duty cycle of the feedback clock signal 616 may be the same as or different from the output clock signal 608, but in either case, can be related to the phase, frequency, pulse width, and duty cycle of the output clock signal 608. In one or more examples, the feedback clock signal 616 may be a divided version of the output clock signal 608 (e.g., via a divider or buffer, but is not limited thereto).

[0080] The controlled oscillator 606 is an electronic oscillator for generating an output clock signal 608 at least partially in response to a control signal 610, which control signal 610 may be a digital control signal (i.e., in the case of a digitally controlled oscillator (DCO)), a voltage control signal (i.e., in the case of a voltage controlled oscillator (VCO)), a current control signal (i.e., in the case of a current controlled oscillator (CCO)), or a combination thereof (i.e., a hybrid controlled oscillator (e.g., any combination of digital control, voltage control, or current control, but not limited to such)).

[0081] exist Figure 6 In the particular non-limiting example depicted, the apparatus 600 includes a controller 604 that provides a control signal 610 to a controlled oscillator 606 to adjust an output clock signal 608. The controller 604 generates the control signal 610 at least in part in response to an error signal 612. In one or more examples, the controller 604 may include circuitry (analog, digital, or both) to provide proportional and integral control of the controlled oscillator 606. The controller 604 may include a proportional control path for instantaneous correction of a phase difference between a feedback clock signal 616 and a reference clock signal 614 indicated by the error signal 612. The controller 604 may include an integral control path to urge an average frequency of the controlled oscillator 606 toward a target frequency (e.g., the frequency of the reference clock signal 614 or a multiple thereof, but not limited thereto) in response to a phase difference or frequency difference between the feedback clock signal 616 and the reference clock signal 614 indicated by the error signal 612.

[0082] Since the double edge error detector 602 determines the phase difference and frequency difference between the rising edge and the falling edge of the reference clock signal 614 and the feedback clock signal 616, the device 600 can achieve double edge lock. In other words, the device 600 achieves lock in response to the phase difference between the reference clock signal 614 and the feedback clock signal 616 being sufficiently small (e.g., within a predetermined threshold difference, but not limited thereto), and the determined phase difference and frequency difference are at least partially based on the rising edge and the falling edge of the reference clock signal 614 and the feedback clock signal 616. When the phase difference between the reference clock signal 614 and the feedback clock signal 616 is too large (e.g., outside a predetermined threshold difference, but not limited thereto), the device 600 can be considered to be out of lock. Furthermore, utilizing the dual edge error detector 602 in the clock tracking circuit 600 increases the proportional gain of the clock tracking circuit 600 because twice as much error detection is achieved in a given clock cycle as a single edge error detector (e.g., detecting errors with respect to each of the corresponding edges of the reference clock signal), and twice as much phase correction and frequency correction can be achieved as a single edge error detector (e.g., correcting errors with respect to each edge of the reference clock signal, but not limited thereto). Furthermore, the dual edge error detector 602 does not have to address the mismatches between the multiple error detectors discussed above, such as in a circuit utilizing two separate and distinct error detectors to separately detect rising and falling edges of an input signal. Furthermore, the dual edge error detector 602 avoids the complexity associated with accommodating mismatched error detectors in a circuit utilizing two error detectors.

[0083] Those skilled in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Figure 7 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated.In some examples, some or all parts of the functional elements disclosed herein may be performed by hardware specifically for executing the functional elements.

[0084] Figure 7700 is a block diagram of a circuit 700 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. The circuit 700 includes one or more processors 702 (sometimes referred to herein as "processors 702") operably coupled to one or more data storage devices 706 (sometimes referred to herein as "storage devices 706"). The storage devices 706 include machine executable code 708 stored thereon, and the processor 702 includes logic circuits 704. The machine executable code 708 includes information describing functional elements that can be implemented (e.g., executed) by the logic circuits 704. The logic circuits 704 are adapted to implement (e.g., execute) the functional elements described by the machine executable code 708. When executing the functional elements described by the machine executable code 708, the circuit 700 should be regarded as dedicated hardware for executing the functional elements disclosed herein. In some examples, the processor 702 can execute the functional elements described by the machine executable code 708 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0085] When implemented by the logic circuit 704 of the processor 702, the machine executable code 708 adapts the processor 702 to perform the operations of the examples disclosed herein. As a non-limiting example, the machine executable code 708 adapts the processor 702 to perform some or all of the operations of one or more of the processes 300, 400, or 500.

[0086] Also as non-limiting examples, the machine executable code 708 may adapt the processor 702 to perform some or all of the features, functions, or operations disclosed herein for one or more of: device 100, including a first multiplexer 102, a second multiplexer 104, an error detector 106; device 200, including logic circuit 202; or device 600, including a double-edge error detector 602, a controller 604, and a controlled oscillator 606.

[0087] The processor 702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer executes or is configured to execute functional elements corresponding to the machine executable code 708 (e.g., software code, firmware code, hardware description) associated with the examples of the present disclosure. It should be noted that the general-purpose processor (also referred to as a host processor or simply a host in this article) can be a microprocessor, but in an alternative, the processor 702 may include any conventional processor, controller, microcontroller or state machine. The processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0088] In some examples, the storage device 706 includes a volatile data storage device (e.g., a random access memory (RAM)), a non-volatile data storage device (e.g., a flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, the processor 702 and the storage device 706 may be implemented as a single device (e.g., a semiconductor device product, a system on a chip (SOC), but not limited thereto). In some examples, the processor 702 and the storage device 706 may be implemented as independent devices.

[0089] In some examples, machine executable code 708 may include computer readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer readable instructions may be stored by storage device 706, directly accessed by processor 702, and executed by processor 702 using at least logic circuitry 704. Also by way of non-limiting example, the computer readable instructions may be stored on storage device 706, transferred to a memory device (not shown) for execution, and executed by processor 702 using at least logic circuitry 704. Thus, in some examples, logic circuitry 704 includes electrically configurable logic circuitry 704.

[0090] In some examples, machine executable code 708 may describe hardware (e.g., circuitry) to be implemented in logic circuit 704 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). As a non-limiting example, a SYSTEMVERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0091] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 704 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic, discrete hardware components, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 708 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0092] In examples where the machine executable code 708 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 706) may implement the hardware description described by the machine executable code 708. As a non-limiting example, the processor 702 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 704 may be electrically controlled to implement circuits corresponding to the hardware description into the logic circuit 704. Also as a non-limiting example, the logic circuit 704 may include hard-wired logic manufactured by a manufacturing system (not shown, but including the storage device 706) according to the hardware description of the machine executable code 708.

[0093] Regardless of whether the machine executable code 708 includes computer readable instructions or a hardware description, the logic circuit 704 is adapted to perform the functional elements described by the machine executable code 708 when implementing the functional elements of the machine executable code 708. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0094] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that performs the actions of a module or component and / or a software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0095] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0096] The terms used in this disclosure and in particular in the appended claims (e.g., the body of the appended claims, but not limited thereto) are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," but not limited thereto). As used herein, the term "each" means some or all. As used herein, the terms "each and every" mean all.

[0097] Additionally, if a specific number of introduced claim statements is intended, such intent will be expressly recited in the claim, and in the absence of such a statement, no such intent is present. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that a claim statement introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "a kind" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more", but not limited to such); the same is true when a claim statement is introduced using a definite article.

[0098] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted as intending at least the recited number (e.g., the unmodified recitation "two recitations" without other modifying elements intends at least two recitations, or two or more recitations, but not limited thereto). Moreover, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited thereto.

[0099] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0100] Additional non-limiting examples include:

[0101] Embodiment 1: A device, comprising: an error detector; a first multiplexer, the first multiplexer comprising: an output end, the output end coupled to the first input end of the error detector; a non-inverting input end and an inverting input end, the non-inverting input end and the inverting input end are respectively used to receive a first clock signal; and a selection input end, the selection input end is used to receive a control signal; and a second multiplexer, the second multiplexer comprising: an output end, the output end coupled to the second input end of the error detector; a non-inverting input end and an inverting input end, the non-inverting input end and the inverting input end are respectively used to receive a second clock signal; and a selection input end, the selection input end is used to receive the control signal.

[0102] Embodiment 2: The apparatus according to embodiment 1 comprises: a logic circuit, the logic circuit being configured to receive a reset signal of the error detector and to generate the control signal at least partially in response to the reset signal of the error detector.

[0103] Embodiment 3: An apparatus according to one or more of embodiments 1 and 2, wherein the logic circuit is used to generate the control signal to alternately select the corresponding non-inverting input terminals or the corresponding inverting input terminals of the first multiplexer and the second multiplexer at least partially in response to the assertion of the reset signal.

[0104] Embodiment 4: The apparatus of one or more of Embodiments 1 to 3, wherein the error detector is configured to assert the reset signal at least in part in response to similar corresponding edges of the first clock signal and the second clock signal.

[0105] Embodiment 5: The apparatus of one or more of embodiments 1 to 4, wherein the first clock signal is different from the second clock signal.

[0106] Embodiment 6: The apparatus of one or more of embodiments 1 to 5, wherein the error detector is a single error detector.

[0107] Embodiment 7: A system comprising: a controlled oscillator for generating an output clock signal; a double edge error detection circuit for indicating a difference between a reference clock signal and the output clock signal, wherein the double edge error detection circuit reuses an error detector to detect rising and falling edges of the reference clock signal and the output clock signal; and a controller for generating a control signal to reduce the difference between the reference clock signal and the output clock signal indicated by the double edge error detector.

[0108] Embodiment 8: The system according to embodiment 7, wherein the double edge error detection circuit comprises: an error detector; a first multiplexer, the first multiplexer comprising: a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal are respectively coupled to receive a reference clock signal; an output terminal, the output terminal is coupled to the first input terminal of the phase frequency detector; and a selection input terminal, the selection input terminal is coupled to receive a control signal; and a second multiplexer, the second multiplexer comprising: a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal are respectively coupled to receive a feedback clock signal generated by the clock tracking circuit to track the reference clock signal; an output terminal, the output terminal is coupled to the second input terminal of the error detector; and a selection input terminal, the selection input terminal is coupled to receive the control signal. The error detector is a single error detector.

[0109] Embodiment 9: A system according to embodiment 7 or 8, wherein one of the first input terminal or the second input terminal of the error detection circuit is a reference input terminal, and the other of the first input terminal or the second input terminal of the error detection circuit is a feedback input terminal.

[0110] Embodiment 10: A system according to one or more of embodiments 7 to 9, wherein the output of the error detection circuit is coupled to the input of a controller of the clock tracking circuit, and the controller is used to control a controlled oscillator of the clock tracking circuit.

[0111] Embodiment 11: A method comprising: receiving a first clock signal and a second clock signal; and generating an error signal representing a phase difference between the first clock signal and the second clock signal via a single error detector triggered at least partially in response to similar corresponding edges of the first clock signal and the second clock signal.

[0112] Embodiment 12: A method according to embodiment 11, the method comprising: selecting a non-inverting input of a first multiplexer at least partially in response to a first assertion of a reset signal of the error detector, the first multiplexer having an output coupled to a first input of the error detector; selecting a non-inverting input of a second multiplexer at least partially in response to the first assertion of the reset signal of the error detector, the second multiplexer having an output coupled to a second input of the error detector; selecting an inverting input of the first multiplexer at least partially in response to a second assertion of the reset signal of the error detector, the first multiplexer having the output coupled to the first input of the error detector; and selecting an inverting input of the second multiplexer at least partially in response to the second assertion of the reset signal of the error detector, the second multiplexer having the output coupled to the second input of the error detector.

[0113] Embodiment 13: The method according to embodiment 11 or 12, wherein the similar corresponding edges of the first clock signal and the second clock signal are corresponding rising edges or falling edges of the first clock signal and the second clock signal.

[0114] Embodiment 14: The method according to one or more of embodiments 11 to 13, wherein generating the error signal comprises: generating an UP signal and a DOWN signal representing the phase difference between the first clock signal and the second clock signal.

[0115] Embodiment 15: A method according to one or more of embodiments 11 to 14, wherein one of the first clock signal or the second clock signal is a reference clock signal, and the other of the first clock signal or the second clock signal is a feedback clock signal generated by a clock tracking circuit to track the reference clock signal.

[0116] Embodiment 16: A method according to one or more of Embodiments 11 to 15, wherein the single error detector is triggered at least partially in response to similar corresponding edges of the first clock signal and the second clock signal, including: the single error detector is triggered at least partially in response to all of the similar corresponding edges of the first clock signal and the second clock signal.

[0117] Embodiment 17: The method according to one or more of embodiments 11 to 16, wherein the single error detector is a single error detector.

[0118] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: Error detector; A first multiplexer, the first multiplexer comprising: an output terminal coupled to the first input terminal of the error detector; a non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal and the inverting input terminal are respectively used to receive a first clock signal; and a selection input terminal, the selection input terminal being used to receive a control signal, and A second multiplexer, the second multiplexer comprising: an output terminal coupled to a second input terminal of the error detector; a non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal and the inverting input terminal are respectively used to receive a second clock signal; and A selection input terminal is used to receive the control signal.

2. The device according to claim 1, comprising: A logic circuit is configured to receive a reset signal of the error detector and generate the control signal at least partially in response to the reset signal of the error detector.

3. The apparatus of claim 2, wherein the logic circuit is to generate the control signal to alternately select the respective non-inverting input terminals or the respective inverting input terminals of the first multiplexer and the second multiplexer in response, at least in part, to assertion of the reset signal. 4 . The apparatus of claim 2 , wherein the error detector asserts the reset signal at least in part in response to similar corresponding edges of the first clock signal and the second clock signal. The apparatus of claim 1 , wherein the first clock signal is different from the second clock signal. The apparatus of claim 1 , wherein the error detector is a single error detector.

7. A system, comprising: a controlled oscillator for generating an output clock signal; a double edge error detection circuit for indicating a difference between a reference clock signal and the output clock signal, wherein the double edge error detection circuit reuses an error detector to detect rising and falling edges of the reference clock signal and the output clock signal; and A controller is provided for generating a control signal to reduce the difference between the reference clock signal and the output clock signal indicated by the double edge error detector.

8. The system of claim 7, wherein the double edge error detection circuit comprises: the error detector; A first multiplexer, the first multiplexer comprising: a non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal and the inverting input terminal are respectively coupled to receive a reference clock signal; an output terminal coupled to a first input terminal of a phase frequency detector; and a select input terminal coupled to receive a control signal, and A second multiplexer, the second multiplexer comprising: a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal being respectively coupled to receive a feedback clock signal generated by the clock tracking circuit to track the reference clock signal; an output terminal coupled to a second input terminal of the error detector; and A selection input terminal is coupled to receive the control signal.

9. The system of claim 8, wherein one of the first input terminal or the second input terminal of the error detection circuit is a reference input terminal, and the other of the first input terminal or the second input terminal of the error detection circuit is a feedback input terminal.

10. The system of claim 7, wherein the controller includes integral control and proportional control.

11. A method comprising: receiving a first clock signal and a second clock signal; as well as An error signal representative of a phase difference between the first clock signal and the second clock signal is generated via a single error detector triggered at least in part in response to similar corresponding edges of the first clock signal and the second clock signal.

12. The method according to claim 10, comprising: selecting a non-inverting input of a first multiplexer having an output coupled to a first input of the error detector in response at least in part to a first assertion of a reset signal of the error detector; selecting a non-inverting input of a second multiplexer having an output coupled to a second input of the error detector in response at least in part to the first assertion of the reset signal of the error detector; selecting an inverting input of the first multiplexer having the output coupled to the first input of the error detector in response at least in part to a second assertion of the reset signal of the error detector; and selecting an inverting input of a second multiplexer having the output coupled to the second input of the error detector in response at least in part to the second assertion of the reset signal of the error detector. 13 . The method of claim 10 , wherein the similar corresponding edges of the first clock signal and the second clock signal are corresponding rising edges or falling edges of the first clock signal and the second clock signal.

14. The method of claim 10, wherein generating the error signal comprises: An UP signal and a DOWN signal are generated that represent the phase difference between the first clock signal and the second clock signal.

15. The method of claim 10, wherein one of the first clock signal or the second clock signal is a reference clock signal, and the other of the first clock signal or the second clock signal is a feedback clock signal generated by a clock tracking circuit to track the reference clock signal.

16. The method of claim 10, wherein the single error detector is triggered at least in part in response to similar corresponding edges of the first clock signal and the second clock signal comprising: A single error detector is triggered at least in part in response to all of the like corresponding edges of the first clock signal and the second clock signal.

17. The method of claim 10, wherein the single error detector is a single error detector.

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